Re: [Mesa-dev] [PATCH v2 2/3] glapi/glx: call __glEmptyImage if USE_XCB, not memcpy directly
On Fri, Jul 20, 2012 at 11:09:19 +0200, Julien Cristau wrote: From: Julien Cristau julien.cris...@logilab.fr We were stomping on the caller's buffer by ignoring their alignment requests and other pixel store modes. This patch makes the USE_XCB path match the older one more closely. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=52059 Signed-off-by: Julien Cristau julien.cris...@logilab.fr --- v2: add explicit bugzilla reference to commit message, drop unused assignment src/mapi/glapi/gen/glX_proto_send.py | 35 - 1 files changed, 25 insertions(+), 10 deletions(-) Ping? Cheers, Julien ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 41152] [glsl] Shader backend in Regnum Online does not work
https://bugs.freedesktop.org/show_bug.cgi?id=41152 Rafael Castillo jrch2...@gmail.com changed: What|Removed |Added Platform|Other |x86-64 (AMD64) OS/Version|All |Linux (All) Severity|normal |major Priority|medium |high AssignedTo|mesa-dev@lists.freedesktop. |i...@freedesktop.org |org | Component|Mesa core |glsl-compiler --- Comment #10 from Rafael Castillo jrch2...@gmail.com 2012-07-28 18:02:35 PDT --- the shader problem are glGetError(glGetUniformLocationARB) = GL_INVALID_OPERATION error: linking with uncompiled shader glGetError(glUniform4fARB) = GL_INVALID_OPERATION taken from apitrace 3.0 [i can put my apitrace online if needed] happens with r600g TGSI and LLVM shaders -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 52595] WebGL conformance tests failures on cubemap tests (Sandybridge Mobible)
https://bugs.freedesktop.org/show_bug.cgi?id=52595 --- Comment #1 from Kenneth Graunke kenn...@whitecape.org 2012-07-28 19:45:01 PDT --- I can't seem to reproduce this. I ran the tests at the link you provided on my Sandybridge GT2 mobile using the latest nightly build of Firefox. With Mesa master, everything passes. With 8.0.3, only one multisampling test fails; everything else passes. I could not get any cubemap tests to fail. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] some radeon/r200 cleanup/fixes
I have applied these 5 Roland's patches for the r200 driver : http://lists.freedesktop.org/archives/mesa-dev/2012-July/024753.html with my radeon 9000 ( rv250 ) it seems Ok, no problems, but I don't have a good protocol for testing, how I must proceed ? currently I play some 3D games to check mesa libs, like nexuiz : http://www.nexuiz.com/ but maybe there is a better option like unit tests especially written for mesa ? Le 27/07/2012 23:52, Brian Paul a écrit : See the mail list archive at http://lists.freedesktop.org/mailman/listinfo/mesa-dev Roland's patches start here: http://lists.freedesktop.org/archives/mesa-dev/2012-July/024753.html This is the patch I posted: http://lists.freedesktop.org/archives/mesa-dev/2012-July/024780.html -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/5] i965/gen6+: Add support for edge flags.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40707
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/brw_draw_upload.c | 50 ---
src/mesa/drivers/dri/i965/brw_vs.c |6 ++--
3 files changed, 51 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 73ade0a..3605c18 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1008,6 +1008,7 @@ enum brw_message_target {
# define BRW_VE0_FORMAT_SHIFT 16
# define BRW_VE0_VALID (1 26)
# define GEN6_VE0_VALID(1 25)
+# define GEN6_VE0_EDGE_FLAG_ENABLE (1 15)
# define BRW_VE0_SRC_OFFSET_SHIFT 0
# define BRW_VE1_COMPONENT_NOSTORE 0
# define BRW_VE1_COMPONENT_STORE_SRC 1
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index b606de2..9c41c53 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -366,6 +366,18 @@ static void brw_prepare_vertices(struct brw_context *brw)
struct brw_vertex_element *upload[VERT_ATTRIB_MAX];
GLuint nr_uploads = 0;
+ /* _NEW_POLYGON
+*
+* On gen6+, edge flags don't end up in the VUE (either in or out of the
+* VS). Instead, they're uploaded as the last vertex element, and the data
+* is passed sideband through the fixed function units. So, we need to
+* prepare the vertex buffer for it, but it's not present in inputs_read.
+*/
+ if (intel-gen = 6 (ctx-Polygon.FrontMode != GL_FILL ||
+ ctx-Polygon.BackMode != GL_FILL)) {
+ vs_inputs |= VERT_BIT_EDGEFLAG;
+ }
+
/* First build an array of pointers to ve's in vb.inputs_read
*/
if (0)
@@ -707,6 +719,8 @@ static void brw_emit_vertices(struct brw_context *brw)
assert(nr_elements = 18);
}
+ struct brw_vertex_element *gen6_edgeflag_input = NULL;
+
BEGIN_BATCH(1 + nr_elements * 2);
OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS 16) | (2 * nr_elements - 1));
for (i = 0; i brw-vb.nr_enabled; i++) {
@@ -727,9 +741,19 @@ static void brw_emit_vertices(struct brw_context *brw)
* glEdgeFlagPointer, on the other hand, gives us an unnormalized
* integer ubyte. Just rewrite that to convert to a float.
*/
- if (input-attrib == VERT_ATTRIB_EDGEFLAG
- format == BRW_SURFACEFORMAT_R8_UINT)
- format = BRW_SURFACEFORMAT_R8_SSCALED;
+ if (input-attrib == VERT_ATTRIB_EDGEFLAG) {
+ /* Gen6+ passes edgeflag as sideband along with the vertex, instead
+ * of in the VUE. We have to upload it sideband as the last vertex
+ * element according to the B-Spec.
+ */
+ if (intel-gen = 6) {
+gen6_edgeflag_input = input;
+continue;
+ }
+
+ if (format == BRW_SURFACEFORMAT_R8_UINT)
+format = BRW_SURFACEFORMAT_R8_SSCALED;
+ }
switch (input-glarray-Size) {
case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
@@ -765,6 +789,24 @@ static void brw_emit_vertices(struct brw_context *brw)
((i * 4) BRW_VE1_DST_OFFSET_SHIFT));
}
+ if (intel-gen = 6 gen6_edgeflag_input) {
+ uint32_t format = get_surface_type(gen6_edgeflag_input-glarray-Type,
+ gen6_edgeflag_input-glarray-Size,
+ gen6_edgeflag_input-glarray-Format,
+
gen6_edgeflag_input-glarray-Normalized,
+
gen6_edgeflag_input-glarray-Integer);
+
+ OUT_BATCH((gen6_edgeflag_input-buffer GEN6_VE0_INDEX_SHIFT) |
+GEN6_VE0_VALID |
+GEN6_VE0_EDGE_FLAG_ENABLE |
+(format BRW_VE0_FORMAT_SHIFT) |
+(gen6_edgeflag_input-offset BRW_VE0_SRC_OFFSET_SHIFT));
+ OUT_BATCH((BRW_VE1_COMPONENT_STORE_SRC BRW_VE1_COMPONENT_0_SHIFT) |
+(BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_1_SHIFT) |
+(BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_2_SHIFT) |
+(BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_3_SHIFT));
+ }
+
if (brw-vs.prog_data-uses_vertexid) {
uint32_t dw0 = 0, dw1 = 0;
@@ -793,7 +835,7 @@ static void brw_emit_vertices(struct brw_context *brw)
const struct brw_tracked_state brw_vertices = {
.dirty = {
- .mesa = 0,
+ .mesa = _NEW_POLYGON,
.brw = BRW_NEW_BATCH | BRW_NEW_VERTICES,
.cache = CACHE_NEW_VS_PROG,
},
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index c4d6db4..88a073c 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -321,8 +321,10 @@ static void brw_upload_vs_prog(struct brw_context *brw)
}
/*
[Mesa-dev] [PATCH 2/5] i965/vs: Add support for copying user edge flags.
Fixes the glsl skinning demo regression since changing to the new GLSL compiler, and is part of fixing piglit gl-2.0-edgeflag. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50079 NOTE: This is a candidate for the 8.0 branch. --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 13 +++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index c77dc91..de7dfce 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -2193,6 +2193,17 @@ vec4_visitor::emit_urb_slot(int mrf, int vert_result) emit_clip_distances(hw_reg, (vert_result - VERT_RESULT_CLIP_DIST0) * 4); } break; + case VERT_RESULT_EDGE: + /* This is present when doing unfilled polygons. We're supposed to copy + * the edge flag from the user-provided vertex array + * (glEdgeFlagPointer), or otherwise we'll copy from the current value + * of that attribute (starts as 1.0f). This is then used in clipping to + * determine which edges should be drawn as wireframe. + */ + current_annotation = edge flag; + emit(MOV(reg, src_reg(dst_reg(ATTR, VERT_ATTRIB_EDGEFLAG, +glsl_type::float_type, WRITEMASK_XYZW; + break; case BRW_VERT_RESULT_PAD: /* No need to write to this slot */ break; @@ -2249,8 +2260,6 @@ vec4_visitor::emit_urb_writes() */ assert ((max_usable_mrf - base_mrf) % 2 == 0); - /* FINISHME: edgeflag */ - /* First mrf is the g0-based message header containing URB handles and such, * which is implied in VS_OPCODE_URB_WRITE. */ -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/5] i965/fs: Fix the FS inputs setup when some SF outputs aren't used in the FS.
From: Olivier Galibert galib...@pobox.com
If there was an edge flag or a two-side-color pair present, we'd end up
mismatched and read values from earlier in the VUE for later FS inputs.
v2: Fix regression in gles2conform shaders generating point size. (change by
anholt)
Signed-off-by: Olivier Galibert galib...@pobox.com
Reviewed-by: Eric Anholt e...@anholt.net
NOTE: This is a candidate for the 8.0 branch.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 13 -
src/mesa/drivers/dri/i965/brw_wm_pass2.c | 14 +-
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d06858e..0fd5799 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -954,11 +954,22 @@ fs_visitor::calculate_urb_setup()
} else {
/* FINISHME: The sf doesn't map VS-FS inputs for us very well. */
for (unsigned int i = 0; i VERT_RESULT_MAX; i++) {
+ /* Point size is packed into the header, not as a general attribute */
+ if (i == VERT_RESULT_PSIZ)
+continue;
+
if (c-key.vp_outputs_written BITFIELD64_BIT(i)) {
int fp_index = _mesa_vert_result_to_frag_attrib((gl_vert_result) i);
+ /* The back color slot is skipped when the front color is
+* also written to. In addition, some slots can be
+* written in the vertex shader and not read in the
+* fragment shader. So the register number must always be
+* incremented, mapped or not.
+*/
if (fp_index = 0)
- urb_setup[fp_index] = urb_next++;
+ urb_setup[fp_index] = urb_next;
+urb_next++;
}
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 27c0a94..562a189 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -93,12 +93,24 @@ static void init_registers( struct brw_wm_compile *c )
}
} else {
for (j = 0; j VERT_RESULT_MAX; j++) {
+ /* Point size is packed into the header, not as a general attribute */
+ if (j == VERT_RESULT_PSIZ)
+continue;
+
if (c-key.vp_outputs_written BITFIELD64_BIT(j)) {
int fp_index = _mesa_vert_result_to_frag_attrib(j);
nr_interp_regs++;
+
+ /* The back color slot is skipped when the front color is
+* also written to. In addition, some slots can be
+* written in the vertex shader and not read in the
+* fragment shader. So the register number must always be
+* incremented, mapped or not.
+*/
if (fp_index = 0)
- prealloc_reg(c, c-payload.input_interp[fp_index], i++);
+ prealloc_reg(c, c-payload.input_interp[fp_index], i);
+i++;
}
}
assert(nr_interp_regs = 1);
--
1.7.10.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/5] i965/vs: Convert EdgeFlagPointer values appropriately for the VS on gen4.
Fixes piglit gl-2.0/edgeflag.
NOTE: This is a candidate for the 8.0 branch.
---
src/mesa/drivers/dri/i965/brw_draw_upload.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 82dd81d..b606de2 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -721,6 +721,16 @@ static void brw_emit_vertices(struct brw_context *brw)
uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
uint32_t comp3 = BRW_VE1_COMPONENT_STORE_SRC;
+ /* The gen4 driver expects edgeflag to come in as a float, and passes
+ * that float on to the tests in the clipper. Mesa's current vertex
+ * attribute value for EdgeFlag is stored as a float, which works out.
+ * glEdgeFlagPointer, on the other hand, gives us an unnormalized
+ * integer ubyte. Just rewrite that to convert to a float.
+ */
+ if (input-attrib == VERT_ATTRIB_EDGEFLAG
+ format == BRW_SURFACEFORMAT_R8_UINT)
+ format = BRW_SURFACEFORMAT_R8_SSCALED;
+
switch (input-glarray-Size) {
case 0: comp0 = BRW_VE1_COMPONENT_STORE_0;
case 1: comp1 = BRW_VE1_COMPONENT_STORE_0;
--
1.7.10.4
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] i965/fs: Don't set the saturate bit on gen4 math send instructions.
The saturate bit gets communicated as part of the message descriptor, and setting it in the instruction somehow trashes the results. Fixes piglit general/fog-modes and ext_fog_coord-modes. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=48628 NOTE: This is a candidate for the 8.0 branch. --- src/mesa/drivers/dri/i965/brw_fs_emit.cpp |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp index dc5f3e1..9658d91 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp @@ -237,6 +237,8 @@ fs_visitor::generate_math_gen4(fs_inst *inst, assert(inst-mlen = 1); + brw_set_saturate(p, false); + brw_set_compression_control(p, BRW_COMPRESSION_NONE); brw_math(p, dst, op, -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
