Re: [Mesa-dev] [PATCH 4/4] mesa: remove MALLOC, CALLOC, FREE macros
On Thu, Aug 30, 2012 at 7:17 PM, Brian Paul brian.e.p...@gmail.com wrote:
From: Brian Paul bri...@vmware.com
These macros go way back to the early days of Mesa before there was
valgrind, etc. for debugging memory errors. I used to use the macros
to plug in my own debugging routines. We've been using regular malloc,
calloc, free for a while so let's be consistent.
We'll keep the MALLOC_STRUCT and CALLOC_STRUCT macros since those are
still pretty helpful.
---
src/mesa/main/imports.h |6 --
1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/src/mesa/main/imports.h b/src/mesa/main/imports.h
index 2635ce5..d8f0d76 100644
--- a/src/mesa/main/imports.h
+++ b/src/mesa/main/imports.h
@@ -49,16 +49,10 @@ extern C {
/** Memory macros */
/*@{*/
-/** Allocate \p BYTES bytes */
-#define MALLOC(BYTES) malloc(BYTES)
-/** Allocate and zero \p BYTES bytes */
-#define CALLOC(BYTES) calloc(1, BYTES)
/** Allocate a structure of type \p T */
#define MALLOC_STRUCT(T) (struct T *) malloc(sizeof(struct T))
/** Allocate and zero a structure of type \p T */
#define CALLOC_STRUCT(T) (struct T *) calloc(1, sizeof(struct T))
-/** Free memory */
-#define FREE(PTR) free(PTR)
/*@}*/
--
1.7.4.1
Series is: Reviewed-by: Matt Turner matts...@gmail.com
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[Mesa-dev] [PATCH] i965: Fix primitive restart on Haswell.
Haswell moved the Cut Index Enable bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0x.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 36 +++
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
5 files changed, 43 insertions(+), 1 deletion(-)
I could have sworn I sent this out, but I can't find it in my inbox, so I
guess I must not have been connected to the internet at the time...oops.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3605c18..6dc4707 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1037,6 +1037,9 @@ enum brw_message_target {
# define GEN6_URB_GS_ENTRIES_SHIFT 8
# define GEN6_URB_GS_SIZE_SHIFT0
+#define _3DSTATE_VF 0x780c /* GEN7.5+ */
+#define HSW_CUT_INDEX_ENABLE(1 8)
+
#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
#define _3DSTATE_URB_HS 0x7831 /* GEN7+ */
#define _3DSTATE_URB_DS 0x7832 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e40c7d5..33cce8f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -930,7 +930,7 @@ static void brw_emit_index_buffer(struct brw_context *brw)
if (index_buffer == NULL)
return;
- if (brw-prim_restart.enable_cut_index) {
+ if (brw-prim_restart.enable_cut_index !intel-is_haswell) {
cut_index_setting = BRW_CUT_INDEX_ENABLE;
} else {
cut_index_setting = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 02deba4..38b5243 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -29,8 +29,11 @@
#include main/bufferobj.h
#include brw_context.h
+#include brw_defines.h
#include brw_draw.h
+#include intel_batchbuffer.h
+
/**
* Check if the hardware's cut index support can handle the primitive
* restart index value.
@@ -39,6 +42,12 @@ static bool
can_cut_index_handle_restart_index(struct gl_context *ctx,
const struct _mesa_index_buffer *ib)
{
+ struct intel_context *intel = intel_context(ctx);
+
+ /* Haswell supports an arbitrary cut index. */
+ if (intel-is_haswell)
+ return true;
+
bool cut_index_will_work;
switch (ib-type) {
@@ -176,3 +185,30 @@ brw_handle_primitive_restart(struct gl_context *ctx,
return GL_TRUE;
}
+static void
+haswell_upload_cut_index(struct brw_context *brw)
+{
+ struct intel_context *intel = brw-intel;
+ struct gl_context *ctx = intel-ctx;
+
+ /* Don't trigger on Ivybridge */
+ if (!intel-is_haswell)
+ return;
+
+ const unsigned cut_index_setting =
+ ctx-Array.PrimitiveRestart ? HSW_CUT_INDEX_ENABLE : 0;
+
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_VF 16 | cut_index_setting | (2 - 2));
+ OUT_BATCH(ctx-Array.RestartIndex);
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state haswell_cut_index = {
+ .dirty = {
+ .mesa = _NEW_TRANSFORM,
+ .brw = 0,
+ .cache = 0,
+ },
+ .emit = haswell_upload_cut_index,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index a80ee86..99fa088 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -133,6 +133,7 @@ extern const struct brw_tracked_state gen7_wm_constants;
extern const struct brw_tracked_state gen7_wm_constant_surface;
extern const struct brw_tracked_state gen7_wm_state;
extern const struct brw_tracked_state gen7_wm_surfaces;
+extern const struct brw_tracked_state haswell_cut_index;
/* brw_misc_state.c */
uint32_t
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 7291988..ec0f765 100644
---
[Mesa-dev] [PATCH] i965/fs: Don't use brw-fragment_program in calculate_urb_setup().
Reading brw-fragment_program is nonsensical in compiler code: it contains the currently active program (if any), not the one currently being compiled. Attempting to access it may either lead to crashes (null pointer dereference if no program is active) or wrong results. Fixes piglit regressions since 9ef710575b914ddfc8e9a162d98ad554c1c217f7 on pre-Sandybridge hardware. The actual bug was created in commit 7b1fbc688999fd568e65211d79d7678562061594. NOTE: This is a candidate for the 9.0 and 8.0 branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54183 Cc: Rico Tzschichholz ric...@t-online.de Signed-off-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) As I suspected: the precompile just exposed a bug that'd been lurking for a while (February 2012 to be precise). diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a8d55ff..167ea08 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -979,7 +979,7 @@ fs_visitor::calculate_urb_setup() * * See compile_sf_prog() for more info. */ - if (brw-fragment_program-Base.InputsRead BITFIELD64_BIT(FRAG_ATTRIB_PNTC)) + if (fp-Base.InputsRead BITFIELD64_BIT(FRAG_ATTRIB_PNTC)) urb_setup[FRAG_ATTRIB_PNTC] = urb_next++; } -- 1.7.11.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] radeonsi: first successful piglit run
On 30.08.2012 22:31, Tom Stellard wrote: On Thu, Aug 30, 2012 at 07:00:44PM +0200, Christian König wrote: Hi everybody, with the following patchset the radeonsi driver finally completes a run of nearly all tests in Piglits quick-driver profile without an GPU hang or X server crash. Which kernel tree are you using? Davids drm-next + some additional changes to aid my debugging attempts. But none of the additional changes where bugfixes, so I'm pretty sure that it should work even with older kernels. On the other hand I'm currently changing to Alex drm-next-3.7-wip branch and retesting with that one. Christian. -Tom The only exceptions are: 1. glx/glx-tfp Results in a reproducible X server crash in the GLAMOR code. 2. glean/makeCurrent Also crashes the X server, but this time it isn't reproducible and the backtrace doesn't show a GLAMOR relation. 3. texturing/texsubimage I have now idea why, but this test results in a hardlock of the whole system, going to investigate that one closer next week. The patchset mostly disable features or adds gracefully handling for not implement features, so I'm not completely sure if I should commit them or instead try to fix all the features in question. Anyway I looks like we finally have something for regression testing now. Cheers, Christian. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 6/6] winsys/radeon: create only one winsys for each fd
On 30.08.2012 20:06, Marek Olšák wrote:
Reviewed-by: Marek Olšák mar...@gmail.com
Shouldn't accesses to fd_tab be guarded by a mutex?
Yes probably, but I'm still not sure if this solution to the problem is
a good idea or not.
That both GLAMOR and GLX end up creating a separate winsys with the same
fd inside one X-Server looks like a bug itself.
It's just not more than a big ugly hack for a problem that should
probably be solved in an upper layer.
Christian.
Marek
On Thu, Aug 30, 2012 at 7:00 PM, Christian König
deathsim...@vodafone.de wrote:
Fixing problems with GLAMOR.
Signed-off-by: Christian König deathsim...@vodafone.de
---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 38 +++--
src/gallium/winsys/radeon/drm/radeon_winsys.h |5 +++
2 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index c03dd04..33451ab 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -37,6 +37,7 @@
#include pipebuffer/pb_bufmgr.h
#include util/u_memory.h
+#include util/u_hash_table.h
#include xf86drm.h
#include stdio.h
@@ -89,6 +90,7 @@
#define RADEON_INFO_TIMESTAMP 0x11
#endif
+static struct util_hash_table *fd_tab = NULL;
/* Enable/disable feature access for one command stream.
* If enable == TRUE, return TRUE on success.
@@ -318,6 +320,10 @@ static void radeon_winsys_destroy(struct radeon_winsys
*rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
+if (!pipe_reference(ws-base.reference, NULL)) {
+return;
+}
+
pipe_mutex_destroy(ws-hyperz_owner_mutex);
pipe_mutex_destroy(ws-cmask_owner_mutex);
@@ -326,6 +332,9 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws)
if (ws-gen = R600) {
radeon_surface_manager_free(ws-surf_man);
}
+if (fd_tab) {
+util_hash_table_remove(fd_tab, intptr_to_pointer(ws-fd));
+}
FREE(rws);
}
@@ -395,14 +404,36 @@ static uint64_t radeon_query_timestamp(struct
radeon_winsys *rws)
return ts;
}
+static unsigned hash_fd(void *key)
+{
+return pointer_to_intptr(key);
+}
+
+static int compare_fd(void *key1, void *key2)
+{
+return pointer_to_intptr(key1) != pointer_to_intptr(key2);
+}
+
struct radeon_winsys *radeon_drm_winsys_create(int fd)
{
-struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
+struct radeon_drm_winsys *ws;
+
+if (!fd_tab) {
+fd_tab = util_hash_table_create(hash_fd, compare_fd);
+}
+
+ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
+if (ws) {
+pipe_reference(NULL, ws-base.reference);
+return ws-base;
+}
+
+ws = CALLOC_STRUCT(radeon_drm_winsys);
if (!ws) {
return NULL;
}
-
ws-fd = fd;
+util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
if (!do_winsys_init(ws))
goto fail;
@@ -421,6 +452,9 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd)
goto fail;
}
+/* init reference */
+pipe_reference_init(ws-base.reference, 1);
+
/* Set functions. */
ws-base.destroy = radeon_winsys_destroy;
ws-base.query_info = radeon_query_info;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 4eb57fb..8e4693b 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -108,6 +108,11 @@ enum radeon_feature_id {
struct radeon_winsys {
/**
+ * Reference counting
+ */
+struct pipe_reference reference;
+
+/**
* Destroy this winsys.
*
* \param wsThe winsys this function is called from.
--
1.7.9.5
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[Mesa-dev] [PATCH] r600g: adjust QUANT_MODE for higher precision
Use 1/256 for R6xx/7xx, 1/4096 for evergreen, instead of default 1/16.
Helps to pass some piglit tests (fbo, multisample).
Signed-off-by: Vadim Girlin vadimgir...@gmail.com
---
src/gallium/drivers/r600/evergreen_state.c | 3 ++-
src/gallium/drivers/r600/evergreend.h | 11 +++
src/gallium/drivers/r600/r600_state.c | 3 ++-
src/gallium/drivers/r600/r600d.h | 9 +
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 28a83f2..bda8ed5 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -920,7 +920,8 @@ static void *evergreen_create_rs_state(struct pipe_context
*ctx,
S_028C08_PIX_CENTER_HALF(state-gl_rasterization_rules));
} else {
r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
-
S_028C08_PIX_CENTER_HALF(state-gl_rasterization_rules));
+
S_028C08_PIX_CENTER_HALF(state-gl_rasterization_rules) |
+
S_028C08_QUANT_MODE(V_028C08_X_1_4096TH));
}
r600_pipe_state_add_reg(rstate, R_028B7C_PA_SU_POLY_OFFSET_CLAMP,
fui(state-offset_clamp));
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 91d78f8..e4d72f5 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1955,6 +1955,17 @@
#define S_028C08_PIX_CENTER_HALF(x) (((x) 0x1) 0)
#define G_028C08_PIX_CENTER_HALF(x) (((x) 0) 0x1)
#define C_028C08_PIX_CENTER_HALF 0xFFFE
+#define S_028C08_QUANT_MODE(x) (((x) 0x7) 3)
+#define G_028C08_QUANT_MODE(x) (((x) 3) 0x7)
+#define C_028C08_QUANT_MODE 0xFFC7
+#define V_028C08_X_1_16TH 0x00
+#define V_028C08_X_1_8TH 0x01
+#define V_028C08_X_1_4TH 0x02
+#define V_028C08_X_1_2 0x03
+#define V_028C08_X_1 0x04
+#define V_028C08_X_1_256TH 0x05
+#define V_028C08_X_1_1024TH0x06
+#define V_028C08_X_1_4096TH0x07
#define R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x00028C0C
#define R_028C10_PA_CL_GB_VERT_DISC_ADJ 0x00028C10
#define R_028C14_PA_CL_GB_HORZ_CLIP_ADJ 0x00028C14
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 26db24b..53bbdd9 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -948,7 +948,8 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
-
S_028C08_PIX_CENTER_HALF(state-gl_rasterization_rules));
+
S_028C08_PIX_CENTER_HALF(state-gl_rasterization_rules) |
+ S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP,
fui(state-offset_clamp));
r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index a6da0a2..28423e1 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -2194,6 +2194,15 @@
#define S_028C08_PIX_CENTER_HALF(x) (((x) 0x1) 0)
#define G_028C08_PIX_CENTER_HALF(x) (((x) 0) 0x1)
#define C_028C08_PIX_CENTER_HALF 0xFFFE
+#define S_028C08_QUANT_MODE(x) (((x) 0x7) 3)
+#define G_028C08_QUANT_MODE(x) (((x) 3) 0x7)
+#define C_028C08_QUANT_MODE 0xFFC7
+#define V_028C08_X_1_16TH 0x00
+#define V_028C08_X_1_8TH 0x01
+#define V_028C08_X_1_4TH 0x02
+#define V_028C08_X_1_2 0x03
+#define V_028C08_X_1 0x04
+#define V_028C08_X_1_256TH 0x05
#define R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX 0x028C1C
#define R_028C48_PA_SC_AA_MASK 0x028C48
#define R_028810_PA_CL_CLIP_CNTL 0x028810
--
1.7.11.4
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Re: [Mesa-dev] radeonsi: first successful piglit run
On 31.08.2012 06:55, Michel Dänzer wrote: On Don, 2012-08-30 at 13:30 -0400, Alex Deucher wrote: On Thu, Aug 30, 2012 at 1:14 PM, Tom Stellard t...@stellard.net wrote: On Thu, Aug 30, 2012 at 07:00:44PM +0200, Christian König wrote: Hi everybody, with the following patchset the radeonsi driver finally completes a run of nearly all tests in Piglits quick-driver profile without an GPU hang or X server crash. The only exceptions are: 1. glx/glx-tfp Results in a reproducible X server crash in the GLAMOR code. 2. glean/makeCurrent Also crashes the X server, but this time it isn't reproducible and the backtrace doesn't show a GLAMOR relation. 3. texturing/texsubimage I have now idea why, but this test results in a hardlock of the whole system, going to investigate that one closer next week. The patchset mostly disable features or adds gracefully handling for not implement features, so I'm not completely sure if I should commit them or instead try to fix all the features in question. I'm in favor of committing these. It will really help to be able to run through a full piglit run, and it'd be nice not to have to manually apply these patches to every feature branch. I agree. We can re-enable as features are fixed/implemented. Agreed. I do agree for patch 1,2,3 and 5. For patch 4 what Tom has send me for LLVM already solves halve of the problem, so I think I'm just going to solve the other half today or on Monday and if that takes longer than expected just commit the workaround. And I'm REALLY unhappy with patch 6. As I already wrote Marek it's just a workaround for GLAMOR and GLX not playing nicely together inside the X-Server. Maybe I get a good idea over the weekend how to solve that in a better way, but I don't really think so. Christian. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 39846] can't compile mesa ‘__u64’problem.
https://bugs.freedesktop.org/show_bug.cgi?id=39846 --- Comment #5 from Jerome St-Louis jerstlo...@gmail.com 2012-08-31 11:03:55 UTC --- I've ran accross the same issue, and commenting out the: // #if defined(__GNUC__) !defined(__STRICT_ANSI__) line around __u64 definition in /usr/include/asm/types.h fixed it (CentOS 5.5 getting seriously hacked to get OpenGL working in VirtualBox) Regards, Jerome -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeon/llvm: Convert to Automake
On Thu, Aug 30, 2012 at 02:11:22PM -0700, Matt Turner wrote: On Thu, Aug 30, 2012 at 1:19 PM, Tom Stellard t...@stellard.net wrote: On Thu, Aug 30, 2012 at 10:47:55AM -0700, Matt Turner wrote: On Thu, Aug 30, 2012 at 9:55 AM, tstel...@gmail.com wrote: From: Tom Stellard thomas.stell...@amd.com --- Hi Matt, This patch applies to your automake-gallium branch. Thanks a bunch! configure.ac|5 ++ src/gallium/drivers/radeon/.gitignore |1 + src/gallium/drivers/radeon/Makefile | 76 --- src/gallium/drivers/radeon/Makefile.am | 87 +++ src/gallium/drivers/radeon/Makefile.sources | 32 ++- 5 files changed, 124 insertions(+), 77 deletions(-) delete mode 100644 src/gallium/drivers/radeon/Makefile create mode 100644 src/gallium/drivers/radeon/Makefile.am + $(LLVM_CFLAGS) + +CXXFLAGS+= $(LLVM_CXXFLAGS) Do we really need this? We already have LLVM_CXXFLAGS in AM_CXXFLAGS. Probably not. + +tablegen = $(LLVM_BINDIR)/llvm-tblgen -I $(LLVM_INCLUDEDIR) $1 $2 -o $3 + +libradeon_la_SOURCES = \ + $(GENERATED_SOURCES) \ + $(CXX_SOURCES) \ + $(C_SOURCES) + +CLEANFILES = $(GENERATED_SOURCES) We should probably set BUILT_SOURCES here. OK + +SIRegisterInfo.td: SIGenRegisterInfo.pl + $(PERL) $^ $@ + +SIRegisterGetHWRegNum.inc: SIGenRegisterInfo.pl + $(PERL) $^ $@ /dev/null + +R600Intrinsics.td: R600IntrinsicsNoOpenCL.td R600IntrinsicsOpenCL.td +if HAVE_R600_LLVM_INTRINSICS + cp R600IntrinsicsNoOpenCL.td R600Intrinsics.td +else + cp R600IntrinsicsOpenCL.td R600Intrinsics.td +endif + +R600RegisterInfo.td: R600GenRegisterInfo.pl + $(PERL) $^ $@ It's nice to put $(AM_V_GEN) before generator calls. You mean like: $(AM_V_GEN) $(PERL) $^ $@ Yeah, exactly. + +AMDGPUGenRegisterInfo.inc: $(TD_FILES) + $(call tablegen, -gen-register-info, AMDGPU.td, $@) + +AMDGPUGenInstrInfo.inc: $(TD_FILES) + $(call tablegen, -gen-instr-info, AMDGPU.td, $@) + +AMDGPUGenAsmWriter.inc: $(TD_FILES) + $(call tablegen, -gen-asm-writer, AMDGPU.td, $@) + +AMDGPUGenDAGISel.inc: $(TD_FILES) + $(call tablegen, -gen-dag-isel, AMDGPU.td, $@) + +AMDGPUGenCallingConv.inc: $(TD_FILES) + $(call tablegen, -gen-callingconv, AMDGPU.td, $@) + +AMDGPUGenSubtargetInfo.inc: $(TD_FILES) + $(call tablegen, -gen-subtarget, AMDGPU.td, $@) + +AMDGPUGenEDInfo.inc: $(TD_FILES) + $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@) + +AMDGPUGenIntrinsics.inc: $(TD_FILES) + $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@) + +AMDGPUGenCodeEmitter.inc: $(TD_FILES) + $(call tablegen, -gen-emitter, AMDGPU.td, $@) + +AMDGPUGenMCCodeEmitter.inc: $(TD_FILES) + $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@) + +AMDGPUGenDFAPacketizer.inc: $(TD_FILES) + $(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@) + +noinst_PROGRAMS = loader + +loader_SOURCES = loader.cpp + +loader_LDADD = libradeon.la $(LLVM_LIBS) +loader_LDFLAGS = \ + $(LLVM_LDFLAGS) \ + $(LD_FLAGS) + +#XXX: Delete this when all targets that rely on radeon are converted to +# automake. +all-local: libradeon.la + ln -f $(builddir)/.libs/libradeon.a $(builddir)/libradeon.a + +CLEANFILES += libradeon.a diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 687acb3..d8df295 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -1,4 +1,34 @@ +TD_FILES := \ + AMDGPU.td \ + AMDGPUInstrInfo.td \ + AMDGPUInstructions.td \ + AMDGPUIntrinsics.td \ + AMDGPURegisterInfo.td \ + AMDILBase.td\ + AMDILInstrInfo.td \ + AMDILIntrinsics.td \ + AMDILRegisterInfo.td\ + Processors.td \ + R600InstrInfo.td\ + R600Instructions.td \ + R600Intrinsics.td \ + R600Intrinsics.td \ + R600IntrinsicsNoOpenCL.td \ + R600IntrinsicsOpenCL.td \ + R600OpenCLIntrinsics.td \ + R600RegisterInfo.td \ + R600RegisterInfo.td \ + R600Schedule.td \ + SIInstrFormats.td \ + SIInstrInfo.td \ + SIInstructions.td \ + SIIntrinsics.td \ + SIRegisterInfo.td \ + SIRegisterInfo.td \ + SISchedule.td + + GENERATED_SOURCES := \ R600Intrinsics.td
Re: [Mesa-dev] [PATCH 1/4] mesa: s/MALLOC/malloc/
On 08/31/2012 01:44 AM, Kenneth Graunke wrote:
For the series:
Reviewed-by: Kenneth Graunkekenn...@whitecape.org
Thanks (and Matt). But I found some more instances of this macro down
in the src/mesa/dri/common/ code that I missed before (by grepping
with 'MALLOC(' while the code reads 'MALLOC (', ugh).
I'll post v2 patches.
I'd also go ahead and cherry-pick these to 9.0, as it ought to make
later cherry-picking easier...and the branch is still really young anyway.
Yeah, I'd like to do that too.
-Brian
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[Mesa-dev] [PATCH 1/3] mesa: s/MALLOC/malloc/
From: Brian Paul bri...@vmware.com
v2: replace instances in dri/common/ dirs
---
src/gallium/state_trackers/glx/xlib/glx_usefont.c |2 +-
src/gallium/state_trackers/glx/xlib/xm_api.c |4 ++--
src/mesa/drivers/dri/common/xmlconfig.c | 14 +++---
src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c |2 +-
src/mesa/drivers/x11/xfonts.c |2 +-
src/mesa/drivers/x11/xm_api.c |4 ++--
src/mesa/drivers/x11/xm_buffer.c |2 +-
src/mesa/main/attrib.c|2 +-
src/mesa/main/errors.c|2 +-
src/mesa/main/eval.c | 16
src/mesa/main/teximage.c |2 +-
src/mesa/program/nvfragparse.c|2 +-
src/mesa/program/nvvertparse.c|2 +-
src/mesa/swrast/s_context.c |2 +-
src/mesa/swrast/s_texcombine.c|2 +-
src/mesa/tnl/t_vb_fog.c |2 +-
src/mesa/tnl/t_vb_light.c |2 +-
src/mesa/tnl/t_vb_texgen.c|4 ++--
src/mesa/vbo/vbo_save_api.c |2 +-
19 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/src/gallium/state_trackers/glx/xlib/glx_usefont.c
b/src/gallium/state_trackers/glx/xlib/glx_usefont.c
index fa5c93a..5dac7a7 100644
--- a/src/gallium/state_trackers/glx/xlib/glx_usefont.c
+++ b/src/gallium/state_trackers/glx/xlib/glx_usefont.c
@@ -241,7 +241,7 @@ glXUseXFont(Font font, int first, int count, int listbase)
max_bm_width = (max_width + 7) / 8;
max_bm_height = max_height;
- bm = (GLubyte *) MALLOC((max_bm_width * max_bm_height) * sizeof(GLubyte));
+ bm = (GLubyte *) malloc((max_bm_width * max_bm_height) * sizeof(GLubyte));
if (!bm) {
XFreeFontInfo(NULL, fs, 1);
_mesa_error(NULL, GL_OUT_OF_MEMORY,
diff --git a/src/gallium/state_trackers/glx/xlib/xm_api.c
b/src/gallium/state_trackers/glx/xlib/xm_api.c
index 8f90704..ef275b2 100644
--- a/src/gallium/state_trackers/glx/xlib/xm_api.c
+++ b/src/gallium/state_trackers/glx/xlib/xm_api.c
@@ -220,7 +220,7 @@ bits_per_pixel( XMesaVisual xmv )
/* Create a temporary XImage */
img = XCreateImage( dpy, visinfo-visual, visinfo-depth,
ZPixmap, 0, /*format, offset*/
- (char*) MALLOC(8),/*data*/
+ (char*) malloc(8),/*data*/
1, 1, /*width, height*/
32, /*bitmap_pad*/
0 /*bytes_per_line*/
@@ -706,7 +706,7 @@ XMesaVisual XMesaCreateVisual( Display *display,
* the struct but we may need some of the information contained in it
* at a later time.
*/
- v-visinfo = (XVisualInfo *) MALLOC(sizeof(*visinfo));
+ v-visinfo = (XVisualInfo *) malloc(sizeof(*visinfo));
if (!v-visinfo) {
free(v);
return NULL;
diff --git a/src/mesa/drivers/dri/common/xmlconfig.c
b/src/mesa/drivers/dri/common/xmlconfig.c
index 6d1d5ec..bbd62f7 100644
--- a/src/mesa/drivers/dri/common/xmlconfig.c
+++ b/src/mesa/drivers/dri/common/xmlconfig.c
@@ -142,10 +142,10 @@ static GLuint countOptions (const driOptionCache *cache) {
return count;
}
-/** \brief Like strdup but using MALLOC and with error checking. */
+/** \brief Like strdup but using malloc and with error checking. */
#define XSTRDUP(dest,source) do { \
GLuint len = strlen (source); \
-if (!(dest = MALLOC (len+1))) { \
+if (!(dest = malloc(len+1))) { \
fprintf (stderr, %s: %d: out of memory.\n, __FILE__, __LINE__); \
abort(); \
} \
@@ -347,7 +347,7 @@ static GLboolean parseRanges (driOptionInfo *info, const
XML_Char *string) {
if (*range == ',')
++nRanges;
-if ((ranges = MALLOC (nRanges*sizeof(driOptionRange))) == NULL) {
+if ((ranges = malloc(nRanges*sizeof(driOptionRange))) == NULL) {
fprintf (stderr, %s: %d: out of memory.\n, __FILE__, __LINE__);
abort();
}
@@ -702,8 +702,8 @@ void driParseOptionInfo (driOptionCache *info,
GLuint size, log2size;
for (size = 1, log2size = 0; size minSize; size = 1, ++log2size);
info-tableSize = log2size;
-info-info = CALLOC (size * sizeof (driOptionInfo));
-info-values = CALLOC (size * sizeof (driOptionValue));
+info-info = calloc(size, sizeof (driOptionInfo));
+info-values = calloc(size, sizeof (driOptionValue));
if (info-info == NULL || info-values == NULL) {
fprintf (stderr, %s: %d: out of memory.\n, __FILE__, __LINE__);
abort();
@@ -895,7 +895,7 @@ static void optConfEndElem (void *userData, const XML_Char
*name) {
static void initOptionCache (driOptionCache *cache, const driOptionCache
*info) {
cache-info = info-info;
cache-tableSize = info-tableSize;
[Mesa-dev] [PATCH 2/3] mesa: s/CALLOC/calloc/
From: Brian Paul bri...@vmware.com
v2: replace instances in dri/common/ dirs
---
src/mesa/drivers/dri/intel/intel_screen.c | 10 +-
src/mesa/drivers/dri/r200/r200_context.c|2 +-
src/mesa/drivers/dri/r200/r200_state_init.c |4 ++--
src/mesa/drivers/dri/radeon/radeon_context.c|2 +-
src/mesa/drivers/dri/radeon/radeon_queryobj.h |2 +-
src/mesa/drivers/dri/radeon/radeon_screen.c |8
src/mesa/drivers/dri/radeon/radeon_state_init.c |4 ++--
src/mesa/drivers/dri/radeon/radeon_texture.c|2 +-
src/mesa/main/api_arrayelt.c|2 +-
src/mesa/main/matrix.c |2 +-
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |6 --
src/mesa/swrast/s_context.c |2 +-
src/mesa/swrast/s_zoom.c|2 +-
src/mesa/swrast_setup/ss_context.c |2 +-
src/mesa/tnl/t_context.c|2 +-
src/mesa/tnl/t_vb_program.c |2 +-
src/mesa/tnl/t_vb_texgen.c |2 +-
src/mesa/tnl/t_vb_texmat.c |2 +-
src/mesa/tnl/t_vb_vertex.c |2 +-
19 files changed, 31 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 55cebac..c09c1eb 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -195,7 +195,7 @@ intel_allocate_image(int dri_format, void *loaderPrivate)
{
__DRIimage *image;
-image = CALLOC(sizeof *image);
+image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;
@@ -280,7 +280,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
}
irb = intel_renderbuffer(rb);
- image = CALLOC(sizeof *image);
+ image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;
@@ -382,7 +382,7 @@ intel_dup_image(__DRIimage *orig_image, void *loaderPrivate)
{
__DRIimage *image;
- image = CALLOC(sizeof *image);
+ image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;
@@ -942,7 +942,7 @@ __DRIconfig **intelInitScreen2(__DRIscreen *psp)
}
/* Allocate the private area */
- intelScreen = CALLOC(sizeof *intelScreen);
+ intelScreen = calloc(1, sizeof *intelScreen);
if (!intelScreen) {
fprintf(stderr, \nERROR! Allocating private area failed\n);
return false;
@@ -1024,7 +1024,7 @@ intelAllocateBuffer(__DRIscreen *screen,
assert(attachment == __DRI_BUFFER_FRONT_LEFT ||
attachment == __DRI_BUFFER_BACK_LEFT);
- intelBuffer = CALLOC(sizeof *intelBuffer);
+ intelBuffer = calloc(1, sizeof *intelBuffer);
if (intelBuffer == NULL)
return NULL;
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 5a5520b..523a89d 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -235,7 +235,7 @@ GLboolean r200CreateContext( gl_api api,
assert(screen);
/* Allocate the R200 context */
- rmesa = (r200ContextPtr) CALLOC( sizeof(*rmesa) );
+ rmesa = (r200ContextPtr) calloc(1, sizeof(*rmesa));
if ( !rmesa ) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
diff --git a/src/mesa/drivers/dri/r200/r200_state_init.c
b/src/mesa/drivers/dri/r200/r200_state_init.c
index a19e858..06e8242 100644
--- a/src/mesa/drivers/dri/r200/r200_state_init.c
+++ b/src/mesa/drivers/dri/r200/r200_state_init.c
@@ -627,8 +627,8 @@ void r200InitState( r200ContextPtr rmesa )
#define ALLOC_STATE( ATOM, CHK, SZ, NM, IDX ) \
do {\
rmesa-hw.ATOM.cmd_size = SZ;\
- rmesa-hw.ATOM.cmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
- rmesa-hw.ATOM.lastcmd = (GLuint *)CALLOC(SZ * sizeof(int)); \
+ rmesa-hw.ATOM.cmd = (GLuint *) calloc(SZ, sizeof(int)); \
+ rmesa-hw.ATOM.lastcmd = (GLuint *) calloc(SZ, sizeof(int)); \
rmesa-hw.ATOM.name = NM;\
rmesa-hw.ATOM.idx = IDX;\
if (check_##CHK != check_never) {\
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
b/src/mesa/drivers/dri/radeon/radeon_context.c
index e17c786..ebc0c69 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -201,7 +201,7 @@ r100CreateContext( gl_api api,
assert(screen);
/* Allocate the Radeon context */
- rmesa = (r100ContextPtr) CALLOC( sizeof(*rmesa) );
+ rmesa = (r100ContextPtr) calloc(1, sizeof(*rmesa));
if ( !rmesa ) {
*error = __DRI_CTX_ERROR_NO_MEMORY;
return GL_FALSE;
diff --git a/src/mesa/drivers/dri/radeon/radeon_queryobj.h
[Mesa-dev] [PATCH 3/3] mesa: s/FREE/free/
From: Brian Paul bri...@vmware.com
v2: replace instances in dri/common/ dirs
---
.../state_trackers/dri/common/dri_context.c|6 +-
src/gallium/state_trackers/dri/common/dri_screen.c | 10 ++--
src/gallium/state_trackers/glx/xlib/glx_usefont.c |2 +-
src/gallium/state_trackers/glx/xlib/xm_api.c |6 +-
src/gallium/state_trackers/glx/xlib/xm_st.c|8 ++--
src/mesa/drivers/dri/common/drisw_util.c | 12 +++---
src/mesa/drivers/dri/common/xmlconfig.c| 14 +++---
src/mesa/drivers/dri/i915/i830_context.c |2 +-
src/mesa/drivers/dri/i915/i915_context.c |6 +-
src/mesa/drivers/dri/i965/brw_context.c|2 +-
src/mesa/drivers/dri/i965/brw_state_cache.c|2 +-
src/mesa/drivers/dri/intel/intel_screen.c | 16
src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c |6 +-
src/mesa/drivers/dri/nouveau/nouveau_fbo.c |2 +-
src/mesa/drivers/dri/nouveau/nouveau_screen.c |2 +-
src/mesa/drivers/dri/nouveau/nv04_context.c|2 +-
src/mesa/drivers/dri/nouveau/nv10_context.c|2 +-
src/mesa/drivers/dri/nouveau/nv20_context.c|2 +-
src/mesa/drivers/dri/r200/r200_context.c |2 +-
.../drivers/dri/radeon/radeon_common_context.c |6 +-
src/mesa/drivers/dri/radeon/radeon_context.c |2 +-
src/mesa/drivers/dri/radeon/radeon_dma.c | 16
src/mesa/drivers/dri/radeon/radeon_screen.c| 10 ++--
src/mesa/drivers/dri/swrast/swrast.c |4 +-
src/mesa/drivers/x11/xfonts.c |2 +-
src/mesa/main/api_arrayelt.c |2 +-
src/mesa/main/attrib.c |8 ++--
src/mesa/main/errors.c |4 +-
src/mesa/main/eval.c | 44 ++--
src/mesa/main/matrix.c |2 +-
src/mesa/main/samplerobj.c |2 +-
src/mesa/program/nvfragparse.c |2 +-
src/mesa/state_tracker/st_cb_syncobj.c |2 +-
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 ++--
src/mesa/state_tracker/st_manager.c|2 +-
src/mesa/state_tracker/st_mesa_to_tgsi.c |8 ++--
src/mesa/state_tracker/st_program.c| 12 +++---
src/mesa/swrast/s_context.c| 10 ++--
src/mesa/swrast_setup/ss_context.c |2 +-
src/mesa/tnl/t_context.c |2 +-
src/mesa/tnl/t_vb_fog.c|2 +-
src/mesa/tnl/t_vb_light.c |2 +-
src/mesa/tnl/t_vb_program.c|2 +-
src/mesa/tnl/t_vb_texgen.c |6 +-
src/mesa/tnl/t_vb_texmat.c |2 +-
src/mesa/tnl/t_vb_vertex.c |2 +-
src/mesa/tnl/t_vertex.c|4 +-
src/mesa/vbo/vbo_context.c |2 +-
src/mesa/vbo/vbo_save.c|4 +-
src/mesa/vbo/vbo_save_api.c|6 +-
50 files changed, 144 insertions(+), 144 deletions(-)
diff --git a/src/gallium/state_trackers/dri/common/dri_context.c
b/src/gallium/state_trackers/dri/common/dri_context.c
index 0403826..b91303d 100644
--- a/src/gallium/state_trackers/dri/common/dri_context.c
+++ b/src/gallium/state_trackers/dri/common/dri_context.c
@@ -159,7 +159,7 @@ dri_create_context(gl_api api, const struct gl_config *
visual,
if (ctx ctx-st)
ctx-st-destroy(ctx-st);
- FREE(ctx);
+ free(ctx);
return GL_FALSE;
}
@@ -172,7 +172,7 @@ dri_destroy_context(__DRIcontext * cPriv)
* driParseConfigFiles allocated values only - the rest
* is owned by screen optionCache.
*/
- FREE(ctx-optionCache.values);
+ free(ctx-optionCache.values);
/* No particular reason to wait for command completion before
* destroying a context, but we flush the context here
@@ -184,7 +184,7 @@ dri_destroy_context(__DRIcontext * cPriv)
if (ctx-pp) pp_free(ctx-pp);
- FREE(ctx);
+ free(ctx);
}
GLboolean
diff --git a/src/gallium/state_trackers/dri/common/dri_screen.c
b/src/gallium/state_trackers/dri/common/dri_screen.c
index 102a132..b76cb9a 100644
--- a/src/gallium/state_trackers/dri/common/dri_screen.c
+++ b/src/gallium/state_trackers/dri/common/dri_screen.c
@@ -355,13 +355,13 @@ dri_destroy_option_cache(struct dri_screen * screen)
if (screen-optionCache.info) {
for (i = 0; i (1 screen-optionCache.tableSize); ++i) {
- FREE(screen-optionCache.info[i].name);
- FREE(screen-optionCache.info[i].ranges);
+ free(screen-optionCache.info[i].name);
+ free(screen-optionCache.info[i].ranges);
}
- FREE(screen-optionCache.info);
+ free(screen-optionCache.info);
}
-
[Mesa-dev] [Bug 54325] New: Account request
https://bugs.freedesktop.org/show_bug.cgi?id=54325 Bug #: 54325 Summary: Account request Classification: Unclassified Product: Mesa Version: unspecified Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Other AssignedTo: mesa-dev@lists.freedesktop.org ReportedBy: andreas.boll@gmail.com I'm requesting an account with write access to mesa git repository. Name: Andreas Boll Email: andreas.boll.dev at gmail.com Preferred account name: ab -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54325] Account request
https://bugs.freedesktop.org/show_bug.cgi?id=54325 --- Comment #1 from Andreas Boll andreas.boll@gmail.com 2012-08-31 14:22:13 UTC --- Created attachment 66407 -- https://bugs.freedesktop.org/attachment.cgi?id=66407 ssh public key -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54325] Account request
https://bugs.freedesktop.org/show_bug.cgi?id=54325 --- Comment #2 from Andreas Boll andreas.boll@gmail.com 2012-08-31 14:23:36 UTC --- Created attachment 66408 -- https://bugs.freedesktop.org/attachment.cgi?id=66408 gpg public key -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54293] Undefined symbol sqrt firt referenced in file build/sunos-debug/glsl/libglsl.a(so_pp.os)
https://bugs.freedesktop.org/show_bug.cgi?id=54293 Brian Paul brian.e.p...@gmail.com changed: What|Removed |Added Status|NEW |RESOLVED Resolution||FIXED --- Comment #4 from Brian Paul brian.e.p...@gmail.com 2012-08-31 14:26:07 UTC --- Your patch looks good to me. Committed to master as c57fb034b19156e06e2ec25d9b06a0e174d861c9 Committed to 9.0 branch as 7b676fd738691dba283fb17626026774b790cc0d -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54325] Account request
https://bugs.freedesktop.org/show_bug.cgi?id=54325 Brian Paul brian.e.p...@gmail.com changed: What|Removed |Added AssignedTo|mesa-dev@lists.freedesktop. |sitewranglers@lists.freedes |org |ktop.org Product|Mesa|freedesktop.org Component|Other |New Accounts --- Comment #3 from Brian Paul brian.e.p...@gmail.com 2012-08-31 14:34:19 UTC --- Reassigning to the admins. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54326] New: When building 32 bit on 64 bit, build ends saying it can't find 32 bit libkms.so
https://bugs.freedesktop.org/show_bug.cgi?id=54326 Bug #: 54326 Summary: When building 32 bit on 64 bit, build ends saying it can't find 32 bit libkms.so Classification: Unclassified Product: Mesa Version: unspecified Platform: Other OS/Version: All Status: NEW Severity: normal Priority: medium Component: Mesa core AssignedTo: mesa-dev@lists.freedesktop.org ReportedBy: alexandre.f.dem...@gmail.com Yesterday, after bug 54234 was fixed, I tried building mesa 32 bit on 64 bit (as I do at least twice a week). The build aborted after complaining about libkms.so being wrong (wrong architecture). Indeed, it had stopped after checking in my 64 bit lib folder, not in my 32 bit folder. Could this be related to all the Automake patches landing in repo? I'll have to double check, but I'm pretty sure libdrm wasn't changed so it shouldn't come from that side. I'll be adding the exact error message tonight. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: also bump version in Makefile.am and configure.ac to 9.0
--- Makefile.am |2 +- configure.ac |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index e8c7b59..36bcf1f 100644 --- a/Makefile.am +++ b/Makefile.am @@ -52,7 +52,7 @@ distclean-local: # Rules for making release tarballs -PACKAGE_VERSION=8.1-devel +PACKAGE_VERSION=9.0-devel PACKAGE_DIR = Mesa-$(PACKAGE_VERSION) PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION) diff --git a/configure.ac b/configure.ac index 3355488..12a9a74 100644 --- a/configure.ac +++ b/configure.ac @@ -6,7 +6,7 @@ dnl Tell the user about autoconf.html in the --help output m4_divert_once([HELP_END], [ See docs/autoconf.html for more details on the options for Mesa.]) -AC_INIT([Mesa], [8.1.0], +AC_INIT([Mesa], [9.0.0], [https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa]) AC_CONFIG_AUX_DIR([bin]) AC_CANONICAL_HOST -- 1.7.4.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] intel: Support new dri image interface v2
On Fri, 31 Aug 2012 15:22:04 +0200
Jakob Bornecrantz ja...@vmware.com wrote:
Follow up to the previous patch, kept seperate for easier viewing,
will be merged with previous patch before commiting.
v2: Should fix YUV pitch/stride == 0.
Signed-off-by: Jakob Bornecrantz ja...@vmware.com
---
src/mesa/drivers/dri/intel/intel_regions.h | 26 ++
src/mesa/drivers/dri/intel/intel_screen.c | 135
++--
2 files changed, 153 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h
b/src/mesa/drivers/dri/intel/intel_regions.h
index 4ff0efe..c0fdc95 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.h
+++ b/src/mesa/drivers/dri/intel/intel_regions.h
@@ -141,12 +141,38 @@ uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
uint32_t y);
+/**
+ * Used with images created with image_from_names
+ * to help support planar images.
+ */
+typedef struct intel_image_format {
+ int fourcc;
+ int components;
+ int nplanes;
+ struct {
+ int buffer_index;
+ int width_shift;
+ int height_shift;
+ uint32_t dri_format;
+ int cpp;
+ } planes[3];
+} intel_image_format_t;
+
struct __DRIimageRec {
struct intel_region *region;
GLenum internal_format;
uint32_t dri_format;
GLuint format;
uint32_t offset;
+
+ /*
+* Need to save these here between calls to
+* image_from_names and calls to image_from_planar.
+*/
+ uint32_t strides[3];
+ uint32_t offsets[3];
+ struct intel_image_format *planar_format;
+
void *data;
};
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 55cebac..f20b072 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -190,6 +190,59 @@ static const struct __DRI2flushExtensionRec
intelFlushExtension = {
dri2InvalidateDrawable,
};
+intel_image_format_t intel_image_formats[] = {
+ { __DRI_IMAGE_FOURCC_ARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_XRGB, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB, 4 }, } },
+
+ { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+
+ { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+
+ /* For YUYV buffers, we set up two overlapping DRI images and treat
+* them as planar buffers in the compositors. Plane 0 is GR88 and
+* samples YU or YV pairs and places Y into the R component, while
+* plane 1 is ARGB and samples YUYV clusters and places pairs and
+* places U into the G component and V into A. This lets the
+* texture sampler interpolate the Y components correctly when
+* sampling from plane 0, and interpolate U and V correctly when
+* sampling from plane 1. */
+ { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
+ { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } }
+};
+
static __DRIimage *
intel_allocate_image(int dri_format, void *loaderPrivate)
{
@@ -249,7 +302,7 @@ intel_create_image_from_name(__DRIscreen *screen,
image = intel_allocate_image(format, loaderPrivate);
if (image-format == MESA_FORMAT_NONE)
- cpp = 0;
+ cpp = 1;
else
cpp = _mesa_get_format_bytes(image-format);
image-region = intel_region_alloc_for_handle(intelScreen,
@@ -372,6 +425,11 @@ intel_query_image(__DRIimage *image, int attrib, int
*value)
[Mesa-dev] [PATCH] docs: update relnotes-9.0
---
docs/relnotes-9.0.html | 16 +---
1 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/docs/relnotes-9.0.html b/docs/relnotes-9.0.html
index 164c8e9..1e3a11b 100644
--- a/docs/relnotes-9.0.html
+++ b/docs/relnotes-9.0.html
@@ -37,10 +37,14 @@ Note: some of the new features are only available with
certain drivers.
/p
ul
+liAdded new Gallium3D - nv30 driver/li
+liAdded new Gallium3D - radeonsi driver/li
+liAdded OpenCL state tracker Clover/li
+liCompleted VDPAU state tracker (video decoding support is currently limited
to MPEG1 and MPEG2)/li
liGL_ARB_base_instance/li
liGL_ARB_blend_func_extended/li
liGL_ARB_debug_output/li
-liGL_ARB_invalidate_subdate - Currently a no-op implementation. This
+liGL_ARB_invalidate_subdata - Currently a no-op implementation. This
extension is always enabled in all drivers./li
liGL_ARB_shader_bit_encoding/li
liGL_ARB_texture_buffer_object/li
@@ -52,6 +56,7 @@ extension is always enabled in all drivers./li
liGL_EXT_read_format_bgra for ES 1.1 and 2.0/li
liGL_EXT_texture_rg for ES 2.x/li
liGL_NV_read_buffer for ES 2.0/li
+liGLX_ARB_create_context_robustness/li
liEGL_KHR_create_context/li
liEGL_KHR_surfaceless_context - This replaces the
EGL_KHR_surfaceless_{gles1,gles2,opengl} extensions that were never approved
@@ -67,10 +72,15 @@ by Khronos./li
h2Changes/h2
-p
+ul
+li
The legacy/static Makefile system (ex: 'make linux-dri') has been removed.
+br
The two supported build methods are now autoconf/automake and SCons.
-/p
+/li
+liRemoved support for GL_ARB_shadow_ambient extension/li
+liRemoved Gallium3D - nvfx driver (use nv30 instead)/li
+/ul
/body
--
1.7.4.1
___
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[Mesa-dev] [Bug 52996] Read out of bounds in swizzle_for_size() (MesaLib/src/mesa/program/ir_to_mesa.cpp)
https://bugs.freedesktop.org/show_bug.cgi?id=52996 --- Comment #3 from Alexander Potapenko gli...@google.com 2012-08-31 15:03:18 UTC --- I've managed to reproduce this locally. Inserting fprintf() calls into third_party/mesa/MesaLib/src/mesa/program/ir_to_mesa.cpp shows that swizzle_for_size(0) is really called for some ir type named Nesting2: ir-type-name: Nesting2 swizzle_for_size(0) = ==5641== ERROR: AddressSanitizer global-buffer-overflow on address 0x7fcd7760bc7c at pc 0x7fcd771ed9b3 bp 0x7fff035d6e10 sp 0x7fff035d6e08 READ of size 4 at 0x7fcd7760bc7c thread T0 #0 0x7fcd771ed9b2 in swizzle_for_size(int) /usr/local/google/chrome-asan/src/out/Release/../../third_party/mesa/MesaLib/src/mesa/program/ir_to_mesa.cpp:319 #1 0x7fcd771ed701 in ir_to_mesa_visitor::visit(ir_dereference_record*) /usr/local/google/chrome-asan/src/out/Release/../../third_party/mesa/MesaLib/src/mesa/program/ir_to_mesa.cpp:1547 #2 0x7fcd771edadd in ir_to_mesa_visitor::visit(ir_assignment*) /usr/local/google/chrome-asan/src/out/Release/../../third_party/mesa/MesaLib/src/mesa/program/ir_to_mesa.cpp:1591 #3 0x7fcd771dca42 in ir_to_mesa_visitor::visit(ir_function*) /usr/local/google/chrome-asan/src/out/Release/../../third_party/mesa/MesaLib/src/mesa/program/ir_to_mesa.cpp:1020 #4 0x7fcd77412d29 in visit_exec_list(exec_list*, ir_visitor*) /usr/local/google/chrome-asan/src/out/Release/../../third_party/mesa/MesaLib/src/glsl/ir.cpp:1200 ... Please let me know how else I can help. -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: also bump version in Makefile.am and configure.ac to 9.0
On 08/31/2012 08:43 AM, Andreas Boll wrote: --- Makefile.am |2 +- configure.ac |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Makefile.am b/Makefile.am index e8c7b59..36bcf1f 100644 --- a/Makefile.am +++ b/Makefile.am @@ -52,7 +52,7 @@ distclean-local: # Rules for making release tarballs -PACKAGE_VERSION=8.1-devel +PACKAGE_VERSION=9.0-devel PACKAGE_DIR = Mesa-$(PACKAGE_VERSION) PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION) diff --git a/configure.ac b/configure.ac index 3355488..12a9a74 100644 --- a/configure.ac +++ b/configure.ac @@ -6,7 +6,7 @@ dnl Tell the user about autoconf.html in the --help output m4_divert_once([HELP_END], [ See docs/autoconf.html for more details on the options for Mesa.]) -AC_INIT([Mesa], [8.1.0], +AC_INIT([Mesa], [9.0.0], [https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa]) AC_CONFIG_AUX_DIR([bin]) AC_CANONICAL_HOST This patch and the other one LGTM. I'll commit them (I see that you just applied for a fd.o account). -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] intel: Support new dri image interface v2
On Fri, Aug 31, 2012 at 9:22 AM, Jakob Bornecrantz ja...@vmware.com wrote:
Follow up to the previous patch, kept seperate for easier viewing,
will be merged with previous patch before commiting.
v2: Should fix YUV pitch/stride == 0.
Signed-off-by: Jakob Bornecrantz ja...@vmware.com
Works here too:
Tested-by: Kristian Høgsberg k...@bitplanet.net
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
thanks,
Kristian
---
src/mesa/drivers/dri/intel/intel_regions.h | 26 ++
src/mesa/drivers/dri/intel/intel_screen.c | 135
++--
2 files changed, 153 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.h
b/src/mesa/drivers/dri/intel/intel_regions.h
index 4ff0efe..c0fdc95 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.h
+++ b/src/mesa/drivers/dri/intel/intel_regions.h
@@ -141,12 +141,38 @@ uint32_t
intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,
uint32_t y);
+/**
+ * Used with images created with image_from_names
+ * to help support planar images.
+ */
+typedef struct intel_image_format {
+ int fourcc;
+ int components;
+ int nplanes;
+ struct {
+ int buffer_index;
+ int width_shift;
+ int height_shift;
+ uint32_t dri_format;
+ int cpp;
+ } planes[3];
+} intel_image_format_t;
+
struct __DRIimageRec {
struct intel_region *region;
GLenum internal_format;
uint32_t dri_format;
GLuint format;
uint32_t offset;
+
+ /*
+* Need to save these here between calls to
+* image_from_names and calls to image_from_planar.
+*/
+ uint32_t strides[3];
+ uint32_t offsets[3];
+ struct intel_image_format *planar_format;
+
void *data;
};
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 55cebac..f20b072 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -190,6 +190,59 @@ static const struct __DRI2flushExtensionRec
intelFlushExtension = {
dri2InvalidateDrawable,
};
+intel_image_format_t intel_image_formats[] = {
+ { __DRI_IMAGE_FOURCC_ARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } },
+
+ { __DRI_IMAGE_FOURCC_XRGB, __DRI_IMAGE_COMPONENTS_RGB, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB, 4 }, } },
+
+ { __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV411, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 2, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV420, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 1, 1, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV422, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 1, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_YUV444, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 2, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 } } },
+
+ { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+
+ { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
+ { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } },
+
+ /* For YUYV buffers, we set up two overlapping DRI images and treat
+* them as planar buffers in the compositors. Plane 0 is GR88 and
+* samples YU or YV pairs and places Y into the R component, while
+* plane 1 is ARGB and samples YUYV clusters and places pairs and
+* places U into the G component and V into A. This lets the
+* texture sampler interpolate the Y components correctly when
+* sampling from plane 0, and interpolate U and V correctly when
+* sampling from plane 1. */
+ { __DRI_IMAGE_FOURCC_YUYV, __DRI_IMAGE_COMPONENTS_Y_XUXV, 2,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 },
+ { 0, 1, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } }
+};
+
static __DRIimage *
intel_allocate_image(int dri_format, void *loaderPrivate)
{
@@ -249,7 +302,7 @@ intel_create_image_from_name(__DRIscreen *screen,
image = intel_allocate_image(format, loaderPrivate);
if (image-format == MESA_FORMAT_NONE)
- cpp = 0;
+ cpp = 1;
else
cpp = _mesa_get_format_bytes(image-format);
image-region =
[Mesa-dev] r600: performance reading from staging texture
Hi, In my application, I need to read pixels back to system memory for every rendered frame. My approach is to create a chain of textures with PIPE_USAGE_STAGING flag, and copy the render target to the staging textures before reading them to avoid pipeline stall. Now I found out as in the patch below, there's a line of code checking whether the texture volume has more than 1024 pixels and will use a staging texture if so. However the texture I am mapping is already staging and can be surely mapped directly regardless of its volume. This checking does not make any sense for me and is causing significant performance penalty. I have tried removing it and nothing is broken, performance can go up 10-20% in my case. Please point it out if I missed anything here, otherwise I suggest this two lines of code should be removed. Thanks in advanced. Vic diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 6de3d6a..536f88f 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -622,9 +622,6 @@ struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx, use_staging_texture = TRUE; } - if ((usage PIPE_TRANSFER_READ) u_box_volume(box) 1024) - use_staging_texture = TRUE; - /* Use a staging texture for uploads if the underlying BO is busy. */ if (!(usage PIPE_TRANSFER_READ) (rctx-ws-cs_is_buffer_referenced(rctx-cs, rtex-resource.cs_buf, RADEON_USAGE_READWRITE) || Vic ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] intel: Support new dri image interface v2
On Fri, Aug 31, 2012 at 10:39 AM, Kristian Høgsberg k...@bitplanet.netwrote: On Fri, Aug 31, 2012 at 9:22 AM, Jakob Bornecrantz ja...@vmware.com wrote: Follow up to the previous patch, kept seperate for easier viewing, will be merged with previous patch before commiting. v2: Should fix YUV pitch/stride == 0. Signed-off-by: Jakob Bornecrantz ja...@vmware.com Also works here. Tested-by: Scott Moreau ore...@gmail.com Scott ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Disable write masking when setting up texturing m0.
On 30 August 2012 11:07, Eric Anholt e...@anholt.net wrote:
I don't know of any hangs/rendering failures that this fixes, but it sure
looks necessary.
Good catch! This definitely seems like the kind of thing that could lead
to rare/unpredictable problems.
It looks like there is similar code in brw_vec4_emit.cpp that needs fixing
(vec4_visitor::generate_tex()).
With the vec4 code also fixed, this patch is:
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_fs_emit.cpp |1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 5900c0e..cc038dd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -389,6 +389,7 @@ fs_visitor::generate_tex(fs_inst *inst, struct brw_reg
dst, struct brw_reg src)
*/
if (inst-texture_offset) {
brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
/* Explicitly set up the message header by copying g0 to the MRF. */
brw_MOV(p, retype(brw_message_reg(inst-base_mrf),
BRW_REGISTER_TYPE_UD),
--
1.7.10.4
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[Mesa-dev] [PATCH 2/8] dri: Reuse dri_test.c for stub glapi symbols for unit testing.
This file was previously used to provide stubs for the link test. Now
that the link test wasn't used any more, there's no more purpose for
this file. However, these will be nice for linking unit tests against
the whole contents of a dri driver.
---
src/mesa/drivers/dri/common/Makefile.am |8 +++-
src/mesa/drivers/dri/common/dri_test.c |2 ++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/common/Makefile.am
b/src/mesa/drivers/dri/common/Makefile.am
index d81bc0e..6e9d738 100644
--- a/src/mesa/drivers/dri/common/Makefile.am
+++ b/src/mesa/drivers/dri/common/Makefile.am
@@ -28,11 +28,17 @@ AM_CFLAGS = \
$(API_DEFINES) \
$(LIBDRM_CFLAGS)
-noinst_LTLIBRARIES = libdricommon.la
+noinst_LTLIBRARIES = \
+ libdricommon.la \
+ libdri_test_stubs.la
libdricommon_la_SOURCES = \
utils.c \
dri_util.c \
xmlconfig.c
+libdri_test_stubs_la_SOURCES = \
+ dri_test.c
+libdri_test_stubs_la_CFLAGS = $(AM_CFLAGS) -DNO_MAIN
+
sysconf_DATA = drirc
diff --git a/src/mesa/drivers/dri/common/dri_test.c
b/src/mesa/drivers/dri/common/dri_test.c
index 793f0c3..3573285 100644
--- a/src/mesa/drivers/dri/common/dri_test.c
+++ b/src/mesa/drivers/dri/common/dri_test.c
@@ -82,8 +82,10 @@ _glthread_GetID(void)
return 0;
}
+#ifndef NO_MAIN
int main(int argc, char** argv)
{
void* p = __driDriverExtensions;
return (int)(unsigned long)p;
}
+#endif
--
1.7.10.4
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[Mesa-dev] [PATCH 3/8] i965: Make a linkable library for the contents of i965_dri.so.
To do unit testing of i965, we want to be able to link against the driver's symbols and prod them. If we don't have a separate lib from our loadable module, libtool gets super whiny. --- src/mesa/drivers/dri/i965/.gitignore |1 + src/mesa/drivers/dri/i965/Makefile.am | 17 - 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/.gitignore b/src/mesa/drivers/dri/i965/.gitignore index 09cb4ff..fe4578e 100644 --- a/src/mesa/drivers/dri/i965/.gitignore +++ b/src/mesa/drivers/dri/i965/.gitignore @@ -1,2 +1,3 @@ Makefile i965_symbols_test +libi965_dri.la diff --git a/src/mesa/drivers/dri/i965/Makefile.am b/src/mesa/drivers/dri/i965/Makefile.am index c1526ae..0ac3de7 100644 --- a/src/mesa/drivers/dri/i965/Makefile.am +++ b/src/mesa/drivers/dri/i965/Makefile.am @@ -23,6 +23,8 @@ include Makefile.sources +if HAVE_I965_DRI + # Hack to make some of the non-automake variables work. TOP=$(top_builddir) @@ -42,22 +44,27 @@ AM_CXXFLAGS = $(AM_CFLAGS) dridir = $(DRI_DRIVER_INSTALL_DIR) -if HAVE_I965_DRI +noinst_LTLIBRARIES = libi965_dri.la dri_LTLIBRARIES = i965_dri.la -endif -i965_dri_la_SOURCES = \ +libi965_dri_la_SOURCES = \ $(i965_C_FILES) \ $(i965_CXX_FILES) -i965_dri_la_LDFLAGS = -module -avoid-version -shared -i965_dri_la_LIBADD = \ +COMMON_LIBS = \ + libi965_dri.la \ $(DRI_LIB_DEPS) \ $(INTEL_LIBS) \ ../common/libdricommon.la +i965_dri_la_SOURCES = +i965_dri_la_LIBADD = $(COMMON_LIBS) +i965_dri_la_LDFLAGS = -module -avoid-version -shared + # Provide compatibility with scripts for the old Mesa build system for # a while by putting a link to the driver into /lib of the build tree. all-local: i965_dri.la $(MKDIR_P) $(top_builddir)/$(LIB_DIR); ln -f .libs/i965_dri.so $(top_builddir)/$(LIB_DIR)/i965_dri.so; + +endif -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 1/8] i965: Clear brw_compile on setup.
I noticed in valgrind that p-single_program_flow was used while
uninitialized. Everything else zeroed out brw_compile, but this is better
API.
---
src/mesa/drivers/dri/i965/brw_eu.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index acbf7c0..89091db 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -173,6 +173,8 @@ void brw_pop_insn_state( struct brw_compile *p )
void
brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
{
+ memset(p, 0, sizeof(*p));
+
p-brw = brw;
/*
* Set the initial instruction store array size to 1024, if found that
--
1.7.10.4
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[Mesa-dev] [PATCH 5/8] i965: Prepare the uip/jip setting for compacted instructions in the program.
The first cut at instruction compaction won't compact things that
would change control flow jump distances, but we do need to still be
able to walk the instruction stream, which involves jumping by 8 or 16
bytes between instructions.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 57 +++
1 file changed, 43 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 4d7b76d..c36742a 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2476,12 +2476,24 @@ void brw_urb_WRITE(struct brw_compile *p,
}
static int
+next_ip(struct brw_compile *p, int ip)
+{
+ struct brw_instruction *insn = (void *)p-store + ip;
+
+ if (insn-header.cmpt_control)
+ return ip + 8;
+ else
+ return ip + 16;
+}
+
+static int
brw_find_next_block_end(struct brw_compile *p, int start)
{
int ip;
+ void *store = p-store;
- for (ip = start + 1; ip p-nr_insn; ip++) {
- struct brw_instruction *insn = p-store[ip];
+ for (ip = next_ip(p, start); ip p-next_insn_offset; ip = next_ip(p, ip))
{
+ struct brw_instruction *insn = store + ip;
switch (insn-header.opcode) {
case BRW_OPCODE_ENDIF:
@@ -2503,20 +2515,24 @@ brw_find_loop_end(struct brw_compile *p, int start)
{
struct intel_context *intel = p-brw-intel;
int ip;
- int br = 2;
+ int scale = 8;
+ void *store = p-store;
- for (ip = start + 1; ip p-nr_insn; ip++) {
- struct brw_instruction *insn = p-store[ip];
+ /* Always start after the instruction (such as a WHILE) we're trying to fix
+* up.
+*/
+ for (ip = next_ip(p, start); ip p-next_insn_offset; ip = next_ip(p, ip))
{
+ struct brw_instruction *insn = store + ip;
if (insn-header.opcode == BRW_OPCODE_WHILE) {
int jip = intel-gen == 6 ? insn-bits1.branch_gen6.jump_count
: insn-bits3.break_cont.jip;
-if (ip + jip / br = start)
+if (ip + jip * scale = start)
return ip;
}
}
assert(!not reached);
- return start + 1;
+ return start;
}
/* After program generation, go back and update the UIP and JIP of
@@ -2527,24 +2543,37 @@ brw_set_uip_jip(struct brw_compile *p)
{
struct intel_context *intel = p-brw-intel;
int ip;
- int br = 2;
+ int scale = 8;
+ void *store = p-store;
if (intel-gen 6)
return;
- for (ip = 0; ip p-nr_insn; ip++) {
- struct brw_instruction *insn = p-store[ip];
+ for (ip = 0; ip p-next_insn_offset; ip = next_ip(p, ip)) {
+ struct brw_instruction *insn = store + ip;
+
+ if (insn-header.cmpt_control) {
+/* Fixups for compacted BREAK/CONTINUE not supported yet. */
+assert(insn-header.opcode != BRW_OPCODE_BREAK
+ insn-header.opcode != BRW_OPCODE_CONTINUE
+ insn-header.opcode != BRW_OPCODE_HALT);
+continue;
+ }
switch (insn-header.opcode) {
case BRW_OPCODE_BREAK:
-insn-bits3.break_cont.jip = br * (brw_find_next_block_end(p, ip) -
ip);
+insn-bits3.break_cont.jip =
+(brw_find_next_block_end(p, ip) - ip) / scale;
/* Gen7 UIP points to WHILE; Gen6 points just after it */
insn-bits3.break_cont.uip =
- br * (brw_find_loop_end(p, ip) - ip + (intel-gen == 6 ? 1 : 0));
+ (brw_find_loop_end(p, ip) - ip +
+ (intel-gen == 6 ? 16 : 0)) / scale;
break;
case BRW_OPCODE_CONTINUE:
-insn-bits3.break_cont.jip = br * (brw_find_next_block_end(p, ip) -
ip);
-insn-bits3.break_cont.uip = br * (brw_find_loop_end(p, ip) - ip);
+insn-bits3.break_cont.jip =
+(brw_find_next_block_end(p, ip) - ip) / scale;
+insn-bits3.break_cont.uip =
+(brw_find_loop_end(p, ip) - ip) / scale;
assert(insn-bits3.break_cont.uip != 0);
assert(insn-bits3.break_cont.jip != 0);
--
1.7.10.4
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[Mesa-dev] [PATCH 8/8] i965: Add support for instruction compression on Gen7.
From: Kenneth Graunke kenn...@whitecape.org
Reduces l4d2 program size from 1195kb to 919kb.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu.c |2 +
src/mesa/drivers/dri/i965/brw_eu.h |1 +
src/mesa/drivers/dri/i965/brw_eu_compact.c | 208 +---
3 files changed, 192 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index c2515eb..a59b83f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -206,6 +206,8 @@ brw_init_compile(struct brw_context *brw, struct
brw_compile *p, void *mem_ctx)
p-loop_stack_array_size = 16;
p-loop_stack = rzalloc_array(mem_ctx, int, p-loop_stack_array_size);
p-if_depth_in_loop = rzalloc_array(mem_ctx, int, p-loop_stack_array_size);
+
+ brw_init_compaction_tables(brw-intel);
}
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 01b8d08..b64611e 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -1108,6 +1108,7 @@ void brw_set_uip_jip(struct brw_compile *p);
uint32_t brw_swap_cmod(uint32_t cmod);
/* brw_eu_compact.c */
+void brw_init_compaction_tables(struct intel_context *intel);
void brw_compact_instructions(struct brw_compile *c);
void brw_uncompact_instruction(struct intel_context *intel,
struct brw_instruction *dst,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index dd661f5..009c961 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -180,6 +180,151 @@ static const uint32_t gen6_src_index_table[32] = {
0b00110101,
};
+static const uint32_t gen7_control_index_table[32] = {
+ 0b010,
+ 0b100,
+ 0b101,
+ 0b110,
+ 0b111,
+ 0b1000100,
+ 0b1000101,
+ 0b1000111,
+ 0b1001000,
+ 0b1001001,
+ 0b1001101,
+ 0b110,
+ 0b111,
+ 0b1100010,
+ 0b1100011,
+ 0b1100100,
+ 0b1100101,
+ 0b1100111,
+ 0b1101001,
+ 0b1101101,
+ 0b111,
+ 0b111,
+ 0b0001000,
+ 0b0001010,
+ 0b0001100,
+ 0b0001001,
+ 0b0010110,
+ 0b0010111,
+ 0b0011000,
+ 0b0011001,
+ 0b0101000,
+ 0b0101001
+};
+
+static const uint32_t gen7_datatype_table[32] = {
+ 0b001001,
+ 0b001010,
+ 0b001011,
+ 0b001111,
+ 0b0010001001,
+ 0b0010101101,
+ 0b0010111011,
+ 0b00101110100101,
+ 0b0010111001,
+ 0b001111,
+ 0b0010001110,
+ 0b0010001111,
+ 0b001001010010100101,
+ 0b001001110010100100,
+ 0b001001110010100101,
+ 0b0000111001,
+ 0b0000011101,
+ 0b000000,
+ 0b000001,
+ 0b001000,
+ 0b101100,
+ 0b001001,
+ 0b00100010100101,
+ 0b001110,
+ 0b001001010010100100,
+ 0b00100111001100,
+ 0b00101001011001,
+ 0b0011011001,
+ 0b001001,
+ 0b00100110101100,
+ 0b001010010100101000,
+ 0b001010110100101000
+};
+
+static const uint32_t gen7_subreg_table[32] = {
+ 0b000,
+ 0b001,
+ 0b0001000,
+ 0b000,
+ 0b001,
+ 0b0001000,
+ 0b001,
+ 0b0011000,
+ 0b010,
+ 0b011,
+ 0b101,
+ 0b001,
+ 0b0010001,
+ 0b0011001,
+ 0b0011010,
+ 0b0011011,
+ 0b0011100,
+ 0b0011111,
+ 0b00110001000,
+ 0b00110001110,
+ 0b0011000,
+ 0b00100011000,
+ 0b00100001000,
+ 0b010,
+ 0b0111000,
+ 0b011,
+ 0b0001111,
+ 0b100,
+ 0b101,
+ 0b110,
+ 0b111,
+ 0b11100011100
+};
+
+static const uint32_t gen7_src_index_table[32] = {
+ 0b,
+ 0b0010,
+ 0b0001,
+ 0b00010010,
+ 0b00011000,
+ 0b0010,
+ 0b00101000,
+ 0b01001000,
+ 0b0101,
+ 0b0111,
+ 0b0000,
+ 0b0011,
+ 0b00110010,
+ 0b00111000,
+ 0b00110001,
+ 0b001100010010,
+ 0b00110010,
+ 0b001100101000,
+ 0b001100111000,
+ 0b00110100,
+ 0b00110110,
+ 0b001101001000,
+ 0b00110101,
+ 0b00110110,
+ 0b001101101000,
+
[Mesa-dev] [PATCH 7/8] i965: Support instruction compaction between control flow.
---
src/mesa/drivers/dri/i965/brw_eu_compact.c | 111 ++--
1 file changed, 87 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c
b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 2c15c85..dd661f5 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -324,6 +324,19 @@ brw_try_compact_instruction(struct brw_compile *c,
return false; /* FINISHME: What else needs handling? */
}
+
+ if (src-header.opcode == BRW_OPCODE_IF ||
+ src-header.opcode == BRW_OPCODE_ELSE ||
+ src-header.opcode == BRW_OPCODE_ENDIF ||
+ src-header.opcode == BRW_OPCODE_DO ||
+ src-header.opcode == BRW_OPCODE_HALT ||
+ src-header.opcode == BRW_OPCODE_WHILE) {
+ /* FINISHME: The fixup code below, and brw_set_uip_jip and friends, needs
+ * to be able to handle flow control.
+ */
+ return false;
+ }
+
/* FINISHME: immediates */
if (src-bits1.da1.src0_reg_file == BRW_IMMEDIATE_VALUE ||
src-bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE)
@@ -476,12 +489,40 @@ void brw_debug_compact_uncompact(struct intel_context
*intel,
}
}
+static int
+compressed_between(int old_ip, int old_target_ip, int *compressed_counts)
+{
+ int this_compressed_count = compressed_counts[old_ip];
+ int target_compressed_count = compressed_counts[old_target_ip];
+ return target_compressed_count - this_compressed_count;
+}
+
+static void
+update_uip_jip(struct brw_instruction *insn, int this_old_ip,
+ int *compressed_counts)
+{
+ int target_old_ip;
+
+ target_old_ip = this_old_ip + insn-bits3.break_cont.jip;
+ insn-bits3.break_cont.jip -= compressed_between(this_old_ip,
+ target_old_ip,
+ compressed_counts);
+
+ target_old_ip = this_old_ip + insn-bits3.break_cont.uip;
+ insn-bits3.break_cont.uip -= compressed_between(this_old_ip,
+ target_old_ip,
+ compressed_counts);
+}
+
void
brw_compact_instructions(struct brw_compile *p)
{
struct brw_context *brw = p-brw;
struct intel_context *intel = brw-intel;
void *store = p-store;
+ /* Control flow fixup information */
+ int compressed_counts[p-next_insn_offset / 8];
+ int old_ip[p-next_insn_offset / 8];
assert(gen6_control_index_table[ARRAY_SIZE(gen6_control_index_table) - 1]
!= 0);
assert(gen6_datatype_table[ARRAY_SIZE(gen6_datatype_table) - 1] != 0);
@@ -491,36 +532,21 @@ brw_compact_instructions(struct brw_compile *p)
if (intel-gen != 6)
return;
- /* FINISHME: If we are going to compress instructions between flow control,
-* we have to do fixups to flow control offsets to represent the new
-* distances, since flow control uses (virtual address distance)/2, not a
-* logical instruction count.
-*/
- bool continue_compressing = true;
- for (int i = 0; i p-nr_insn; i++) {
- if (p-store[i].header.opcode == BRW_OPCODE_WHILE)
-return;
- }
-
int src_offset;
int offset = 0;
+ int compressed_count = 0;
for (src_offset = 0; src_offset p-nr_insn * 16;) {
struct brw_instruction *src = store + src_offset;
void *dst = store + offset;
- switch (src-header.opcode) {
- case BRW_OPCODE_IF:
- case BRW_OPCODE_HALT:
- case BRW_OPCODE_JMPI:
-continue_compressing = false;
-break;
- }
+ old_ip[offset / 8] = src_offset / 8;
+ compressed_counts[src_offset / 8] = compressed_count;
struct brw_instruction saved = *src;
- if (continue_compressing
- !src-header.cmpt_control
+ if (!src-header.cmpt_control
brw_try_compact_instruction(p, dst, src)) {
+compressed_count++;
/* debug */
struct brw_instruction uncompacted;
@@ -544,6 +570,7 @@ brw_compact_instructions(struct brw_compile *p)
align-dw0.opcode = BRW_OPCODE_NOP;
align-dw0.cmpt_ctrl = 1;
offset += 8;
+ old_ip[offset / 8] = src_offset / 8;
dst = store + offset;
}
@@ -558,20 +585,56 @@ brw_compact_instructions(struct brw_compile *p)
}
}
+ /* Fix up control flow offsets. */
+ p-next_insn_offset = offset;
+ for (offset = 0; offset p-next_insn_offset;) {
+ struct brw_instruction *insn = store + offset;
+ int this_old_ip = old_ip[offset / 8];
+ int this_compressed_count = compressed_counts[this_old_ip];
+ int target_old_ip, target_compressed_count;
+
+ switch (insn-header.opcode) {
+ case BRW_OPCODE_BREAK:
+ case BRW_OPCODE_CONTINUE:
+ case BRW_OPCODE_HALT:
+update_uip_jip(insn, this_old_ip, compressed_counts);
+break;
+
+ case BRW_OPCODE_IF:
+ case BRW_OPCODE_ELSE:
+ case BRW_OPCODE_ENDIF:
+
[Mesa-dev] [PATCH 6/8] i965: Add support for instruction compaction.
This reduces program size by using some smaller encodings for common bit
patterns in the Gen ISA, with the hope of making programs fit in the
instruction cache better. Unfortunately, we don't have any evidence for any
particular program being measurably helped.
---
src/mesa/drivers/dri/i965/.gitignore|1 +
src/mesa/drivers/dri/i965/Makefile.am | 12 +
src/mesa/drivers/dri/i965/Makefile.sources |1 +
src/mesa/drivers/dri/i965/brw_eu.c | 38 +-
src/mesa/drivers/dri/i965/brw_eu.h | 13 +
src/mesa/drivers/dri/i965/brw_eu_compact.c | 594 +++
src/mesa/drivers/dri/i965/brw_eu_debug.c|1 +
src/mesa/drivers/dri/i965/brw_fs.cpp|6 +
src/mesa/drivers/dri/i965/brw_structs.h | 24 ++
src/mesa/drivers/dri/i965/test_eu_compact.c | 265
10 files changed, 947 insertions(+), 8 deletions(-)
create mode 100644 src/mesa/drivers/dri/i965/brw_eu_compact.c
create mode 100644 src/mesa/drivers/dri/i965/test_eu_compact.c
diff --git a/src/mesa/drivers/dri/i965/.gitignore
b/src/mesa/drivers/dri/i965/.gitignore
index fe4578e..c6ea403 100644
--- a/src/mesa/drivers/dri/i965/.gitignore
+++ b/src/mesa/drivers/dri/i965/.gitignore
@@ -1,3 +1,4 @@
Makefile
i965_symbols_test
libi965_dri.la
+test_eu_compact
diff --git a/src/mesa/drivers/dri/i965/Makefile.am
b/src/mesa/drivers/dri/i965/Makefile.am
index 0ac3de7..be1523d 100644
--- a/src/mesa/drivers/dri/i965/Makefile.am
+++ b/src/mesa/drivers/dri/i965/Makefile.am
@@ -51,16 +51,28 @@ libi965_dri_la_SOURCES = \
$(i965_C_FILES) \
$(i965_CXX_FILES)
+# list of libs to be linked against by i965_dri.so and i965 test programs.
COMMON_LIBS = \
libi965_dri.la \
$(DRI_LIB_DEPS) \
$(INTEL_LIBS) \
../common/libdricommon.la
+TEST_LIBS = \
+ $(COMMON_LIBS) \
+ ../common/libdri_test_stubs.la
+
i965_dri_la_SOURCES =
i965_dri_la_LIBADD = $(COMMON_LIBS)
i965_dri_la_LDFLAGS = -module -avoid-version -shared
+TESTS = test_eu_compact
+check_PROGRAMS = test_eu_compact
+
+test_eu_compact_SOURCES = \
+ test_eu_compact.c
+test_eu_compact_LDADD = $(TEST_LIBS)
+
# Provide compatibility with scripts for the old Mesa build system for
# a while by putting a link to the driver into /lib of the build tree.
all-local: i965_dri.la
diff --git a/src/mesa/drivers/dri/i965/Makefile.sources
b/src/mesa/drivers/dri/i965/Makefile.sources
index d6d189a..3715b0f 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -44,6 +44,7 @@ i965_C_FILES = \
brw_draw.c \
brw_draw_upload.c \
brw_eu.c \
+ brw_eu_compact.c \
brw_eu_debug.c \
brw_eu_emit.c \
brw_eu_util.c \
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index d5080c3..c2515eb 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -214,6 +214,11 @@ const GLuint *brw_get_program( struct brw_compile *p,
{
GLuint i;
+ brw_compact_instructions(p);
+
+ /* We emit a cacheline (8 instructions) of NOPs at the end of the program to
+* make sure that instruction prefetch doesn't wander off into some other
BO.
+*/
for (i = 0; i 8; i++)
brw_NOP(p);
@@ -224,19 +229,36 @@ const GLuint *brw_get_program( struct brw_compile *p,
void
brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
{
+ struct brw_context *brw = p-brw;
+ struct intel_context *intel = brw-intel;
void *store = p-store;
+ bool dump_hex = false;
- for (int offset = start; offset end; offset += 16) {
+ for (int offset = start; offset end;) {
struct brw_instruction *insn = store + offset;
-
+ struct brw_instruction uncompacted;
printf(0x%08x: , offset);
- if (0) {
-printf(0x%08x 0x%08x 0x%08x 0x%08x ,
- ((uint32_t *)insn)[3],
- ((uint32_t *)insn)[2],
- ((uint32_t *)insn)[1],
- ((uint32_t *)insn)[0]);
+ if (insn-header.cmpt_control) {
+struct brw_compact_instruction *compacted = (void *)insn;
+if (dump_hex) {
+ printf(0x%08x 0x%08x ,
+ ((uint32_t *)insn)[1],
+ ((uint32_t *)insn)[0]);
+}
+
+brw_uncompact_instruction(intel, uncompacted, compacted);
+insn = uncompacted;
+offset += 8;
+ } else {
+if (dump_hex) {
+ printf(0x%08x 0x%08x 0x%08x 0x%08x ,
+ ((uint32_t *)insn)[3],
+ ((uint32_t *)insn)[2],
+ ((uint32_t *)insn)[1],
+ ((uint32_t *)insn)[0]);
+}
+offset += 16;
}
brw_disasm(stdout, insn, p-brw-intel.gen);
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 2fa84df..01b8d08 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++
[Mesa-dev] [PATCH 1/2] mesa: add context version routines
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
Based on the discussion July 26-27 in the thread
[PATCH 1/4] mesa: Add a Version field to the context
with VersionMajor*10+VersionMinor.
src/mesa/main/version.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 94a9855..6e13c6c 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -27,6 +27,11 @@
#ifndef VERSION_H
#define VERSION_H
+#include mtypes.h
+
+#ifdef __cplusplus
+extern C {
+#endif
struct gl_context;
@@ -48,4 +53,53 @@ _mesa_compute_version(struct gl_context *ctx);
extern void
_mesa_override_glsl_version(struct gl_context *ctx);
+/**
+ * Merge major/minor into a comparable uint
+ */
+static inline GLuint
+_mesa_uint_version(int major, int minor)
+{
+return major * 10 + minor;
+}
+
+/**
+ * Return the GL major version of the context
+ */
+static inline GLuint
+_mesa_get_version_major(struct gl_context *ctx)
+{
+return ctx-Version / 10;
+}
+
+/**
+ * Return the GL minor version of the context
+ */
+static inline GLuint
+_mesa_get_version_minor(struct gl_context *ctx)
+{
+return ctx-Version % 10;
+}
+
+/**
+ * Sets the context version to major.minor
+ */
+static inline void
+_mesa_set_version(struct gl_context *ctx, int major, int minor)
+{
+ctx-Version = _mesa_uint_version(major, minor);
+}
+
+/**
+ * Checks if the context version is greater than or equal to major.minor
+ */
+static inline GLboolean
+_mesa_have_version(const struct gl_context *ctx, int major, int minor)
+{
+return ctx-Version = _mesa_uint_version(major, minor);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* VERSION_H */
--
1.7.9.5
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[Mesa-dev] [PATCH 2/2] mesa: utilize context version routines
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/nouveau/nouveau_context.c |2 +-
src/mesa/main/context.h|3 ++-
src/mesa/main/enable.c |4 ++--
src/mesa/main/fbobject.c | 28
src/mesa/main/get.c| 11 +-
src/mesa/main/glformats.c |8 +++
src/mesa/main/points.c |2 +-
src/mesa/main/readpix.c|2 +-
src/mesa/main/texformat.c |4 ++--
src/mesa/main/teximage.c | 14 ++--
src/mesa/main/texparam.c |4 ++--
src/mesa/main/varray.c |8 +++
src/mesa/main/version.c| 14 ++--
src/mesa/state_tracker/st_manager.c|2 +-
14 files changed, 53 insertions(+), 53 deletions(-)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c
b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index 4409eae..8cad41e 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -97,7 +97,7 @@ nouveau_context_create(gl_api api,
dri_ctx-driverPrivate = ctx;
_mesa_compute_version(ctx);
- if (ctx-Version major_version * 10 + minor_version) {
+ if (!_mesa_have_version(ctx, major_version, minor_version)) {
nouveau_context_destroy(dri_ctx);
*error = __DRI_CTX_ERROR_BAD_VERSION;
return GL_FALSE;
diff --git a/src/mesa/main/context.h b/src/mesa/main/context.h
index e238752..7c2261a 100644
--- a/src/mesa/main/context.h
+++ b/src/mesa/main/context.h
@@ -51,6 +51,7 @@
#include imports.h
#include mtypes.h
+#include version.h
#ifdef __cplusplus
@@ -316,7 +317,7 @@ _mesa_is_gles(const struct gl_context *ctx)
static inline GLboolean
_mesa_is_gles3(const struct gl_context *ctx)
{
- return ctx-API == API_OPENGLES2 ctx-Version = 30;
+ return ctx-API == API_OPENGLES2 _mesa_have_version(ctx, 3, 0);
}
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index b713f5f..00852ad 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1041,7 +1041,7 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
* GL_PRIMITIVE_RESTART_NV (which is client state).
*/
case GL_PRIMITIVE_RESTART:
- if (!_mesa_is_desktop_gl(ctx) || ctx-Version 31) {
+ if (!_mesa_is_desktop_gl(ctx) || !_mesa_have_version(ctx, 3, 1)) {
goto invalid_enum_error;
}
if (ctx-Array.PrimitiveRestart != state) {
@@ -1711,7 +1711,7 @@ _mesa_IsEnabled( GLenum cap )
/* GL 3.1 primitive restart */
case GL_PRIMITIVE_RESTART:
- if (!_mesa_is_desktop_gl(ctx) || ctx-Version 31) {
+ if (!_mesa_is_desktop_gl(ctx) || !_mesa_have_version(ctx, 3,1)) {
goto invalid_enum_error;
}
return ctx-Array.PrimitiveRestart;
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 59a5ec3..1f34f49 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -1148,11 +1148,11 @@ _mesa_base_fbo_format(struct gl_context *ctx, GLenum
internalFormat)
return ctx-Extensions.EXT_packed_depth_stencil
? GL_DEPTH_STENCIL_EXT : 0;
case GL_DEPTH_COMPONENT32F:
- return ctx-Version = 30
+ return _mesa_have_version(ctx, 3, 0)
|| (ctx-API == API_OPENGL ctx-Extensions.ARB_depth_buffer_float)
? GL_DEPTH_COMPONENT : 0;
case GL_DEPTH32F_STENCIL8:
- return ctx-Version = 30
+ return _mesa_have_version(ctx, 3, 0)
|| (ctx-API == API_OPENGL ctx-Extensions.ARB_depth_buffer_float)
? GL_DEPTH_STENCIL : 0;
case GL_RED:
@@ -1171,7 +1171,7 @@ _mesa_base_fbo_format(struct gl_context *ctx, GLenum
internalFormat)
? GL_RG : 0;
/* signed normalized texture formats */
case GL_R8_SNORM:
- return ctx-Version = 30
+ return _mesa_have_version(ctx, 3, 0)
|| (ctx-API == API_OPENGL ctx-Extensions.EXT_texture_snorm)
? GL_RED : 0;
case GL_RED_SNORM:
@@ -1179,7 +1179,7 @@ _mesa_base_fbo_format(struct gl_context *ctx, GLenum
internalFormat)
return _mesa_is_desktop_gl(ctx) ctx-Extensions.EXT_texture_snorm
? GL_RED : 0;
case GL_RG8_SNORM:
- return ctx-Version = 30
+ return _mesa_have_version(ctx, 3, 0)
|| (ctx-API == API_OPENGL ctx-Extensions.EXT_texture_snorm)
? GL_RG : 0;
case GL_RG_SNORM:
@@ -1187,7 +1187,7 @@ _mesa_base_fbo_format(struct gl_context *ctx, GLenum
internalFormat)
return _mesa_is_desktop_gl(ctx) ctx-Extensions.EXT_texture_snorm
? GL_RG : 0;
case GL_RGB8_SNORM:
- return ctx-Version = 30
+ return _mesa_have_version(ctx, 3, 0)
|| (ctx-API == API_OPENGL
Re: [Mesa-dev] [PATCH 1/2] mesa: add context version routines
On Fri, Aug 31, 2012 at 11:52 AM, Jordan Justen
jordan.l.jus...@intel.com wrote:
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
Based on the discussion July 26-27 in the thread
[PATCH 1/4] mesa: Add a Version field to the context
with VersionMajor*10+VersionMinor.
src/mesa/main/version.h | 54
+++
1 file changed, 54 insertions(+)
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 94a9855..6e13c6c 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -27,6 +27,11 @@
#ifndef VERSION_H
#define VERSION_H
+#include mtypes.h
+
+#ifdef __cplusplus
+extern C {
+#endif
struct gl_context;
@@ -48,4 +53,53 @@ _mesa_compute_version(struct gl_context *ctx);
extern void
_mesa_override_glsl_version(struct gl_context *ctx);
+/**
+ * Merge major/minor into a comparable uint
+ */
+static inline GLuint
+_mesa_uint_version(int major, int minor)
+{
+return major * 10 + minor;
+}
+
+/**
+ * Return the GL major version of the context
+ */
+static inline GLuint
+_mesa_get_version_major(struct gl_context *ctx)
+{
+return ctx-Version / 10;
+}
+
+/**
+ * Return the GL minor version of the context
+ */
+static inline GLuint
+_mesa_get_version_minor(struct gl_context *ctx)
+{
+return ctx-Version % 10;
+}
+
+/**
+ * Sets the context version to major.minor
+ */
+static inline void
+_mesa_set_version(struct gl_context *ctx, int major, int minor)
+{
+ctx-Version = _mesa_uint_version(major, minor);
+}
+
+/**
+ * Checks if the context version is greater than or equal to major.minor
+ */
+static inline GLboolean
+_mesa_have_version(const struct gl_context *ctx, int major, int minor)
+{
+return ctx-Version = _mesa_uint_version(major, minor);
+}
Brian, you sent _mesa_have_version to the list on July 27. Can I add
your Signed-off-by to the patch?
Thanks,
-Jordan
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* VERSION_H */
--
1.7.9.5
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Re: [Mesa-dev] [PATCH] i965: Fix primitive restart on Haswell.
On 31 August 2012 00:22, Kenneth Graunke kenn...@whitecape.org wrote:
Haswell moved the Cut Index Enable bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0x.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 36
+++
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
5 files changed, 43 insertions(+), 1 deletion(-)
I could have sworn I sent this out, but I can't find it in my inbox, so I
guess I must not have been connected to the internet at the time...oops.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3605c18..6dc4707 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1037,6 +1037,9 @@ enum brw_message_target {
# define GEN6_URB_GS_ENTRIES_SHIFT 8
# define GEN6_URB_GS_SIZE_SHIFT0
+#define _3DSTATE_VF 0x780c /* GEN7.5+ */
+#define HSW_CUT_INDEX_ENABLE(1 8)
+
#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
#define _3DSTATE_URB_HS 0x7831 /* GEN7+ */
#define _3DSTATE_URB_DS 0x7832 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e40c7d5..33cce8f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -930,7 +930,7 @@ static void brw_emit_index_buffer(struct brw_context
*brw)
if (index_buffer == NULL)
return;
- if (brw-prim_restart.enable_cut_index) {
+ if (brw-prim_restart.enable_cut_index !intel-is_haswell) {
I'm worried that we may have a pre-existing bug here.
brw-prim_restart.enable_cut_index depends not only on primitive restart
settings (tracked under _NEW_TRANSFORM) but also on whether we are doing
primitive restart in hardware or software; pre-Haswell that depends on the
type of primitive (BRW_NEW_PRIMITIVE) and whether we are counting
primitives (_NEW_DEPTH I think, ugh). But brw_emit_index_buffer is only
emitted when BRW_NEW_BATCH or BRW_NEW_INDEX_BUFFER is flagged.
I suspect we could come up with a state change that would cause
brw-prim_restart.enable_cut_index to flip from false to true without
setting BRW_NEW_BATCH or BRW_NEW_INDEX_BUFFER; if that happens, then
brw_emit_index_buffer() won't get called, so hardware primitive restart
won't get switched on when it needs to be.
Possible solutions:
1. Update brw_index_buffer so that it will also be triggered by
_NEW_TRANSFORM, and change the condition to if
(ctx-Array.PrimitiveRestart !intel-is_haswell). As a side effect,
this will enable hardware primitive restart whenever software primitive
restart is in use, but I think that should be harmless (since software
primitive restart should prevent the cut index from getting sent into the
pipeline).
2. Update brw_index_buffer so that it will also be triggered by
_NEW_TRANSFORM, BRW_NEW_PRIMITIVE, and _NEW_DEPTH.
3. Define a new BRW bit that will be flagged when
brw-prim_restart.enable_cut_index is changed, and update brw_index_buffer
so that it will be triggered by that bit.
I'm leaning toward #1. What do you think?
cut_index_setting = BRW_CUT_INDEX_ENABLE;
} else {
cut_index_setting = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 02deba4..38b5243 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -29,8 +29,11 @@
#include main/bufferobj.h
#include brw_context.h
+#include brw_defines.h
#include brw_draw.h
+#include intel_batchbuffer.h
+
/**
* Check if the hardware's cut index support can handle the primitive
* restart index value.
@@ -39,6 +42,12 @@ static bool
can_cut_index_handle_restart_index(struct gl_context *ctx,
const struct _mesa_index_buffer *ib)
{
+ struct
[Mesa-dev] [PATCH] i965: Stop putting 8 NOPs after each prorgam.
As far as I can see, the intention of the requirement that we do so is to
prevent instruction prefetch from wandering out into either unmapped memory or
memory with a different caching type, and hanging the chip. The kernel makes
sure that the page after your BO has a valid page of the same caching type,
which meets this requirement, so there's no need to waste space between our
programs (and in instruction cache) on this.
Saves another 9kb instructions in l4d2 shaders.
---
src/mesa/drivers/dri/i965/brw_eu.c |8
1 file changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 130d801..c60b16c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -214,16 +214,8 @@ brw_init_compile(struct brw_context *brw, struct
brw_compile *p, void *mem_ctx)
const GLuint *brw_get_program( struct brw_compile *p,
GLuint *sz )
{
- GLuint i;
-
brw_compact_instructions(p);
- /* We emit a cacheline (8 instructions) of NOPs at the end of the program to
-* make sure that instruction prefetch doesn't wander off into some other
BO.
-*/
- for (i = 0; i 8; i++)
- brw_NOP(p);
-
*sz = p-next_insn_offset;
return (const GLuint *)p-store;
}
--
1.7.10.4
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Re: [Mesa-dev] [PATCH] i965/fs: Don't use brw-fragment_program in calculate_urb_setup().
On 31 August 2012 01:00, Kenneth Graunke kenn...@whitecape.org wrote: Reading brw-fragment_program is nonsensical in compiler code: it contains the currently active program (if any), not the one currently being compiled. Attempting to access it may either lead to crashes (null pointer dereference if no program is active) or wrong results. Fixes piglit regressions since 9ef710575b914ddfc8e9a162d98ad554c1c217f7 on pre-Sandybridge hardware. The actual bug was created in commit 7b1fbc688999fd568e65211d79d7678562061594. NOTE: This is a candidate for the 9.0 and 8.0 branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54183 Cc: Rico Tzschichholz ric...@t-online.de Signed-off-by: Kenneth Graunke kenn...@whitecape.org Good catch! It looks like a similar mistake exists in brw_wm_pass2.c's init_registers() function (if (brw-fragment_program-Base.InputsRead BITFIELD64_BIT(j))). Incidentally, this gives me an idea for a structural change to the compiler back-end that would prevent bugs like this from happening in the future. Rather than passing brw around inside the compiler functions, let's make a new data structure that contains just those parts of brw that make sense for the compiler to access (things like brw-intel.gen, brw-needs_unlit_centroid_workaround, brw-has_pln, etc.). And pass around that data structure inside the compiler functions instead of brw. In addition to preventing bugs like this one, it would prevent bugs where we forget to include important state in the program key, since the compiler functions wouldn't be able to just consult the state directly anymore. I think I might experiment with that as a back-burner project in my copious free time :) --- src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) As I suspected: the precompile just exposed a bug that'd been lurking for a while (February 2012 to be precise). diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index a8d55ff..167ea08 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -979,7 +979,7 @@ fs_visitor::calculate_urb_setup() * * See compile_sf_prog() for more info. */ - if (brw-fragment_program-Base.InputsRead BITFIELD64_BIT(FRAG_ATTRIB_PNTC)) + if (fp-Base.InputsRead BITFIELD64_BIT(FRAG_ATTRIB_PNTC)) urb_setup[FRAG_ATTRIB_PNTC] = urb_next++; } -- 1.7.11.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Fix primitive restart on Haswell.
On Fri, Aug 31, 2012 at 12:08 PM, Paul Berry stereotype...@gmail.com wrote:
On 31 August 2012 00:22, Kenneth Graunke kenn...@whitecape.org wrote:
Haswell moved the Cut Index Enable bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0x.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 36
+++
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
5 files changed, 43 insertions(+), 1 deletion(-)
I could have sworn I sent this out, but I can't find it in my inbox, so I
guess I must not have been connected to the internet at the time...oops.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3605c18..6dc4707 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1037,6 +1037,9 @@ enum brw_message_target {
# define GEN6_URB_GS_ENTRIES_SHIFT 8
# define GEN6_URB_GS_SIZE_SHIFT0
+#define _3DSTATE_VF 0x780c /* GEN7.5+ */
+#define HSW_CUT_INDEX_ENABLE(1 8)
+
#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
#define _3DSTATE_URB_HS 0x7831 /* GEN7+ */
#define _3DSTATE_URB_DS 0x7832 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e40c7d5..33cce8f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -930,7 +930,7 @@ static void brw_emit_index_buffer(struct brw_context
*brw)
if (index_buffer == NULL)
return;
- if (brw-prim_restart.enable_cut_index) {
+ if (brw-prim_restart.enable_cut_index !intel-is_haswell) {
I'm worried that we may have a pre-existing bug here.
brw-prim_restart.enable_cut_index depends not only on primitive restart
settings (tracked under _NEW_TRANSFORM) but also on whether we are doing
primitive restart in hardware or software; pre-Haswell that depends on the
type of primitive (BRW_NEW_PRIMITIVE) and whether we are counting primitives
(_NEW_DEPTH I think, ugh). But brw_emit_index_buffer is only emitted when
BRW_NEW_BATCH or BRW_NEW_INDEX_BUFFER is flagged.
I suspect we could come up with a state change that would cause
brw-prim_restart.enable_cut_index to flip from false to true without
setting BRW_NEW_BATCH or BRW_NEW_INDEX_BUFFER; if that happens, then
brw_emit_index_buffer() won't get called, so hardware primitive restart
won't get switched on when it needs to be.
Possible solutions:
1. Update brw_index_buffer so that it will also be triggered by
_NEW_TRANSFORM, and change the condition to if (ctx-Array.PrimitiveRestart
!intel-is_haswell). As a side effect, this will enable hardware
primitive restart whenever software primitive restart is in use, but I think
that should be harmless (since software primitive restart should prevent the
cut index from getting sent into the pipeline).
2. Update brw_index_buffer so that it will also be triggered by
_NEW_TRANSFORM, BRW_NEW_PRIMITIVE, and _NEW_DEPTH.
3. Define a new BRW bit that will be flagged when
brw-prim_restart.enable_cut_index is changed, and update brw_index_buffer
so that it will be triggered by that bit.
I'm leaning toward #1. What do you think?
Since this is a pre-existing bug, we should probably address it
separately, right?
cut_index_setting = BRW_CUT_INDEX_ENABLE;
} else {
cut_index_setting = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 02deba4..38b5243 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -29,8 +29,11 @@
#include main/bufferobj.h
#include brw_context.h
+#include brw_defines.h
#include brw_draw.h
+#include intel_batchbuffer.h
+
/**
* Check if the hardware's cut index support can handle the primitive
* restart index value.
@@
Re: [Mesa-dev] [PATCH] i965: Fix primitive restart on Haswell.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
2 minor questions below...
On Fri, Aug 31, 2012 at 12:22 AM, Kenneth Graunke kenn...@whitecape.org wrote:
Haswell moved the Cut Index Enable bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0x.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 36
+++
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
5 files changed, 43 insertions(+), 1 deletion(-)
I could have sworn I sent this out, but I can't find it in my inbox, so I
guess I must not have been connected to the internet at the time...oops.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3605c18..6dc4707 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1037,6 +1037,9 @@ enum brw_message_target {
# define GEN6_URB_GS_ENTRIES_SHIFT 8
# define GEN6_URB_GS_SIZE_SHIFT0
+#define _3DSTATE_VF 0x780c /* GEN7.5+ */
+#define HSW_CUT_INDEX_ENABLE(1 8)
+
#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
#define _3DSTATE_URB_HS 0x7831 /* GEN7+ */
#define _3DSTATE_URB_DS 0x7832 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e40c7d5..33cce8f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -930,7 +930,7 @@ static void brw_emit_index_buffer(struct brw_context *brw)
if (index_buffer == NULL)
return;
- if (brw-prim_restart.enable_cut_index) {
+ if (brw-prim_restart.enable_cut_index !intel-is_haswell) {
cut_index_setting = BRW_CUT_INDEX_ENABLE;
} else {
cut_index_setting = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 02deba4..38b5243 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -29,8 +29,11 @@
#include main/bufferobj.h
#include brw_context.h
+#include brw_defines.h
#include brw_draw.h
+#include intel_batchbuffer.h
+
/**
* Check if the hardware's cut index support can handle the primitive
* restart index value.
@@ -39,6 +42,12 @@ static bool
can_cut_index_handle_restart_index(struct gl_context *ctx,
const struct _mesa_index_buffer *ib)
{
+ struct intel_context *intel = intel_context(ctx);
+
+ /* Haswell supports an arbitrary cut index. */
+ if (intel-is_haswell)
+ return true;
+
bool cut_index_will_work;
switch (ib-type) {
@@ -176,3 +185,30 @@ brw_handle_primitive_restart(struct gl_context *ctx,
return GL_TRUE;
}
+static void
+haswell_upload_cut_index(struct brw_context *brw)
I see hsw above. Should we use hsw similar to brw?
+{
+ struct intel_context *intel = brw-intel;
+ struct gl_context *ctx = intel-ctx;
+
+ /* Don't trigger on Ivybridge */
Should this say 'Don't trigger for previous generations'?
+ if (!intel-is_haswell)
+ return;
+
+ const unsigned cut_index_setting =
+ ctx-Array.PrimitiveRestart ? HSW_CUT_INDEX_ENABLE : 0;
+
+ BEGIN_BATCH(2);
+ OUT_BATCH(_3DSTATE_VF 16 | cut_index_setting | (2 - 2));
+ OUT_BATCH(ctx-Array.RestartIndex);
+ ADVANCE_BATCH();
+}
+
+const struct brw_tracked_state haswell_cut_index = {
+ .dirty = {
+ .mesa = _NEW_TRANSFORM,
+ .brw = 0,
+ .cache = 0,
+ },
+ .emit = haswell_upload_cut_index,
+};
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index a80ee86..99fa088 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -133,6 +133,7 @@ extern const struct brw_tracked_state gen7_wm_constants;
extern const struct brw_tracked_state
Re: [Mesa-dev] [PATCH] i965: Fix primitive restart on Haswell.
On 31 August 2012 12:52, Jordan Justen jljus...@gmail.com wrote:
On Fri, Aug 31, 2012 at 12:08 PM, Paul Berry stereotype...@gmail.com
wrote:
On 31 August 2012 00:22, Kenneth Graunke kenn...@whitecape.org wrote:
Haswell moved the Cut Index Enable bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us
to specify the cut index rather than assuming it's 0x.
This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.
Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 ++
src/mesa/drivers/dri/i965/brw_draw_upload.c | 2 +-
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 36
+++
src/mesa/drivers/dri/i965/brw_state.h | 1 +
src/mesa/drivers/dri/i965/brw_state_upload.c | 2 ++
5 files changed, 43 insertions(+), 1 deletion(-)
I could have sworn I sent this out, but I can't find it in my inbox, so
I
guess I must not have been connected to the internet at the time...oops.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3605c18..6dc4707 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1037,6 +1037,9 @@ enum brw_message_target {
# define GEN6_URB_GS_ENTRIES_SHIFT 8
# define GEN6_URB_GS_SIZE_SHIFT0
+#define _3DSTATE_VF 0x780c /* GEN7.5+ */
+#define HSW_CUT_INDEX_ENABLE(1 8)
+
#define _3DSTATE_URB_VS 0x7830 /* GEN7+ */
#define _3DSTATE_URB_HS 0x7831 /* GEN7+ */
#define _3DSTATE_URB_DS 0x7832 /* GEN7+ */
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e40c7d5..33cce8f 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -930,7 +930,7 @@ static void brw_emit_index_buffer(struct brw_context
*brw)
if (index_buffer == NULL)
return;
- if (brw-prim_restart.enable_cut_index) {
+ if (brw-prim_restart.enable_cut_index !intel-is_haswell) {
I'm worried that we may have a pre-existing bug here.
brw-prim_restart.enable_cut_index depends not only on primitive restart
settings (tracked under _NEW_TRANSFORM) but also on whether we are doing
primitive restart in hardware or software; pre-Haswell that depends on
the
type of primitive (BRW_NEW_PRIMITIVE) and whether we are counting
primitives
(_NEW_DEPTH I think, ugh). But brw_emit_index_buffer is only emitted
when
BRW_NEW_BATCH or BRW_NEW_INDEX_BUFFER is flagged.
I suspect we could come up with a state change that would cause
brw-prim_restart.enable_cut_index to flip from false to true without
setting BRW_NEW_BATCH or BRW_NEW_INDEX_BUFFER; if that happens, then
brw_emit_index_buffer() won't get called, so hardware primitive restart
won't get switched on when it needs to be.
Possible solutions:
1. Update brw_index_buffer so that it will also be triggered by
_NEW_TRANSFORM, and change the condition to if
(ctx-Array.PrimitiveRestart
!intel-is_haswell). As a side effect, this will enable hardware
primitive restart whenever software primitive restart is in use, but I
think
that should be harmless (since software primitive restart should prevent
the
cut index from getting sent into the pipeline).
2. Update brw_index_buffer so that it will also be triggered by
_NEW_TRANSFORM, BRW_NEW_PRIMITIVE, and _NEW_DEPTH.
3. Define a new BRW bit that will be flagged when
brw-prim_restart.enable_cut_index is changed, and update
brw_index_buffer
so that it will be triggered by that bit.
I'm leaning toward #1. What do you think?
Since this is a pre-existing bug, we should probably address it
separately, right?
Yeah, good point. I'd be ok with that. Keeping in mind, of course, that
after this patch lands, the bug will be in two places rather than one :)
It also occurs to me that another state change we should worry about is if
the client program switches between glDrawArrays() and glDrawElements(). I
don't know if BRW_NEW_INDEX_BUFFER gets flagged when that happens. If not,
that might cause a problem for my proposal #2 above.
Re: [Mesa-dev] [PATCH 2/2] mesa: utilize context version routines
On Fri, Aug 31, 2012 at 11:52 AM, Jordan Justen
jordan.l.jus...@intel.com wrote:
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
diff --git a/src/mesa/main/enable.c b/src/mesa/main/enable.c
index b713f5f..00852ad 100644
--- a/src/mesa/main/enable.c
+++ b/src/mesa/main/enable.c
@@ -1041,7 +1041,7 @@ _mesa_set_enable(struct gl_context *ctx, GLenum cap,
GLboolean state)
* GL_PRIMITIVE_RESTART_NV (which is client state).
*/
case GL_PRIMITIVE_RESTART:
- if (!_mesa_is_desktop_gl(ctx) || ctx-Version 31) {
+ if (!_mesa_is_desktop_gl(ctx) || !_mesa_have_version(ctx, 3, 1)) {
goto invalid_enum_error;
}
if (ctx-Array.PrimitiveRestart != state) {
@@ -1711,7 +1711,7 @@ _mesa_IsEnabled( GLenum cap )
/* GL 3.1 primitive restart */
case GL_PRIMITIVE_RESTART:
- if (!_mesa_is_desktop_gl(ctx) || ctx-Version 31) {
+ if (!_mesa_is_desktop_gl(ctx) || !_mesa_have_version(ctx, 3,1)) {
Missing a space between the 3, and 1.
goto invalid_enum_error;
}
return ctx-Array.PrimitiveRestart;
--
There are some more too --
src/mesa/drivers/dri/i915/i915_context.c:183 - could use _mesa_uint_version
src/mesa/drivers/dri/i965/brw_context.c:101,119 - could use _mesa_uint_version
src/mesa/drivers/dri/nouveau/nouveau_context.c:100 - could use
_mesa_have_version
With those fixed, the series is
Reviewed-by: Matt Turner matts...@gmail.com
Thanks,
Matt
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Re: [Mesa-dev] [PATCH] radeon/llvm: Convert to Automake
On Fri, Aug 31, 2012 at 6:04 AM, Tom Stellard t...@stellard.net wrote: On Thu, Aug 30, 2012 at 02:11:22PM -0700, Matt Turner wrote: On Thu, Aug 30, 2012 at 1:19 PM, Tom Stellard t...@stellard.net wrote: On Thu, Aug 30, 2012 at 10:47:55AM -0700, Matt Turner wrote: On Thu, Aug 30, 2012 at 9:55 AM, tstel...@gmail.com wrote: From: Tom Stellard thomas.stell...@amd.com --- Hi Matt, This patch applies to your automake-gallium branch. Thanks a bunch! configure.ac|5 ++ src/gallium/drivers/radeon/.gitignore |1 + src/gallium/drivers/radeon/Makefile | 76 --- src/gallium/drivers/radeon/Makefile.am | 87 +++ src/gallium/drivers/radeon/Makefile.sources | 32 ++- 5 files changed, 124 insertions(+), 77 deletions(-) delete mode 100644 src/gallium/drivers/radeon/Makefile create mode 100644 src/gallium/drivers/radeon/Makefile.am + $(LLVM_CFLAGS) + +CXXFLAGS+= $(LLVM_CXXFLAGS) Do we really need this? We already have LLVM_CXXFLAGS in AM_CXXFLAGS. Probably not. + +tablegen = $(LLVM_BINDIR)/llvm-tblgen -I $(LLVM_INCLUDEDIR) $1 $2 -o $3 + +libradeon_la_SOURCES = \ + $(GENERATED_SOURCES) \ + $(CXX_SOURCES) \ + $(C_SOURCES) + +CLEANFILES = $(GENERATED_SOURCES) We should probably set BUILT_SOURCES here. OK + +SIRegisterInfo.td: SIGenRegisterInfo.pl + $(PERL) $^ $@ + +SIRegisterGetHWRegNum.inc: SIGenRegisterInfo.pl + $(PERL) $^ $@ /dev/null + +R600Intrinsics.td: R600IntrinsicsNoOpenCL.td R600IntrinsicsOpenCL.td +if HAVE_R600_LLVM_INTRINSICS + cp R600IntrinsicsNoOpenCL.td R600Intrinsics.td +else + cp R600IntrinsicsOpenCL.td R600Intrinsics.td +endif + +R600RegisterInfo.td: R600GenRegisterInfo.pl + $(PERL) $^ $@ It's nice to put $(AM_V_GEN) before generator calls. You mean like: $(AM_V_GEN) $(PERL) $^ $@ Yeah, exactly. + +AMDGPUGenRegisterInfo.inc: $(TD_FILES) + $(call tablegen, -gen-register-info, AMDGPU.td, $@) + +AMDGPUGenInstrInfo.inc: $(TD_FILES) + $(call tablegen, -gen-instr-info, AMDGPU.td, $@) + +AMDGPUGenAsmWriter.inc: $(TD_FILES) + $(call tablegen, -gen-asm-writer, AMDGPU.td, $@) + +AMDGPUGenDAGISel.inc: $(TD_FILES) + $(call tablegen, -gen-dag-isel, AMDGPU.td, $@) + +AMDGPUGenCallingConv.inc: $(TD_FILES) + $(call tablegen, -gen-callingconv, AMDGPU.td, $@) + +AMDGPUGenSubtargetInfo.inc: $(TD_FILES) + $(call tablegen, -gen-subtarget, AMDGPU.td, $@) + +AMDGPUGenEDInfo.inc: $(TD_FILES) + $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@) + +AMDGPUGenIntrinsics.inc: $(TD_FILES) + $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@) + +AMDGPUGenCodeEmitter.inc: $(TD_FILES) + $(call tablegen, -gen-emitter, AMDGPU.td, $@) + +AMDGPUGenMCCodeEmitter.inc: $(TD_FILES) + $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@) + +AMDGPUGenDFAPacketizer.inc: $(TD_FILES) + $(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@) + +noinst_PROGRAMS = loader + +loader_SOURCES = loader.cpp + +loader_LDADD = libradeon.la $(LLVM_LIBS) +loader_LDFLAGS = \ + $(LLVM_LDFLAGS) \ + $(LD_FLAGS) + +#XXX: Delete this when all targets that rely on radeon are converted to +# automake. +all-local: libradeon.la + ln -f $(builddir)/.libs/libradeon.a $(builddir)/libradeon.a + +CLEANFILES += libradeon.a diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 687acb3..d8df295 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -1,4 +1,34 @@ +TD_FILES := \ + AMDGPU.td \ + AMDGPUInstrInfo.td \ + AMDGPUInstructions.td \ + AMDGPUIntrinsics.td \ + AMDGPURegisterInfo.td \ + AMDILBase.td\ + AMDILInstrInfo.td \ + AMDILIntrinsics.td \ + AMDILRegisterInfo.td\ + Processors.td \ + R600InstrInfo.td\ + R600Instructions.td \ + R600Intrinsics.td \ + R600Intrinsics.td \ + R600IntrinsicsNoOpenCL.td \ + R600IntrinsicsOpenCL.td \ + R600OpenCLIntrinsics.td \ + R600RegisterInfo.td \ + R600RegisterInfo.td \ + R600Schedule.td \ + SIInstrFormats.td \ + SIInstrInfo.td \ + SIInstructions.td \ + SIIntrinsics.td \ + SIRegisterInfo.td \ + SIRegisterInfo.td \ +
[Mesa-dev] [PATCH] mesa: don't wait in _mesa_ClientWaitSync if timeout is 0
From ARB_sync spec:
If the value of timeout is zero, then ClientWaitSync does not
block, but simply tests the current state of sync. TIMEOUT_EXPIRED
will be returned in this case if sync is not signaled, even though
no actual wait was performed.
Fixes random fails of the arb_sync-timeout-zero piglit test on r600g.
Signed-off-by: Vadim Girlin vadimgir...@gmail.com
---
src/mesa/main/syncobj.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/syncobj.c b/src/mesa/main/syncobj.c
index e1a5c6c..9f5a27e 100644
--- a/src/mesa/main/syncobj.c
+++ b/src/mesa/main/syncobj.c
@@ -326,9 +326,13 @@ _mesa_ClientWaitSync(GLsync sync, GLbitfield flags,
GLuint64 timeout)
if (syncObj-StatusFlag) {
ret = GL_ALREADY_SIGNALED;
} else {
- ctx-Driver.ClientWaitSync(ctx, syncObj, flags, timeout);
+ if (timeout == 0) {
+ ret = GL_TIMEOUT_EXPIRED;
+ } else {
+ ctx-Driver.ClientWaitSync(ctx, syncObj, flags, timeout);
- ret = syncObj-StatusFlag ? GL_CONDITION_SATISFIED : GL_TIMEOUT_EXPIRED;
+ ret = syncObj-StatusFlag ? GL_CONDITION_SATISFIED :
GL_TIMEOUT_EXPIRED;
+ }
}
_mesa_unref_sync_object(ctx, syncObj);
--
1.7.11.4
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Re: [Mesa-dev] [PATCH] radeon/llvm: Convert to Automake
On Fri, Aug 31, 2012 at 01:26:33PM -0700, Matt Turner wrote: On Fri, Aug 31, 2012 at 6:04 AM, Tom Stellard t...@stellard.net wrote: On Thu, Aug 30, 2012 at 02:11:22PM -0700, Matt Turner wrote: On Thu, Aug 30, 2012 at 1:19 PM, Tom Stellard t...@stellard.net wrote: On Thu, Aug 30, 2012 at 10:47:55AM -0700, Matt Turner wrote: On Thu, Aug 30, 2012 at 9:55 AM, tstel...@gmail.com wrote: From: Tom Stellard thomas.stell...@amd.com --- Hi Matt, This patch applies to your automake-gallium branch. Thanks a bunch! configure.ac|5 ++ src/gallium/drivers/radeon/.gitignore |1 + src/gallium/drivers/radeon/Makefile | 76 --- src/gallium/drivers/radeon/Makefile.am | 87 +++ src/gallium/drivers/radeon/Makefile.sources | 32 ++- 5 files changed, 124 insertions(+), 77 deletions(-) delete mode 100644 src/gallium/drivers/radeon/Makefile create mode 100644 src/gallium/drivers/radeon/Makefile.am + $(LLVM_CFLAGS) + +CXXFLAGS+= $(LLVM_CXXFLAGS) Do we really need this? We already have LLVM_CXXFLAGS in AM_CXXFLAGS. Probably not. + +tablegen = $(LLVM_BINDIR)/llvm-tblgen -I $(LLVM_INCLUDEDIR) $1 $2 -o $3 + +libradeon_la_SOURCES = \ + $(GENERATED_SOURCES) \ + $(CXX_SOURCES) \ + $(C_SOURCES) + +CLEANFILES = $(GENERATED_SOURCES) We should probably set BUILT_SOURCES here. OK + +SIRegisterInfo.td: SIGenRegisterInfo.pl + $(PERL) $^ $@ + +SIRegisterGetHWRegNum.inc: SIGenRegisterInfo.pl + $(PERL) $^ $@ /dev/null + +R600Intrinsics.td: R600IntrinsicsNoOpenCL.td R600IntrinsicsOpenCL.td +if HAVE_R600_LLVM_INTRINSICS + cp R600IntrinsicsNoOpenCL.td R600Intrinsics.td +else + cp R600IntrinsicsOpenCL.td R600Intrinsics.td +endif + +R600RegisterInfo.td: R600GenRegisterInfo.pl + $(PERL) $^ $@ It's nice to put $(AM_V_GEN) before generator calls. You mean like: $(AM_V_GEN) $(PERL) $^ $@ Yeah, exactly. + +AMDGPUGenRegisterInfo.inc: $(TD_FILES) + $(call tablegen, -gen-register-info, AMDGPU.td, $@) + +AMDGPUGenInstrInfo.inc: $(TD_FILES) + $(call tablegen, -gen-instr-info, AMDGPU.td, $@) + +AMDGPUGenAsmWriter.inc: $(TD_FILES) + $(call tablegen, -gen-asm-writer, AMDGPU.td, $@) + +AMDGPUGenDAGISel.inc: $(TD_FILES) + $(call tablegen, -gen-dag-isel, AMDGPU.td, $@) + +AMDGPUGenCallingConv.inc: $(TD_FILES) + $(call tablegen, -gen-callingconv, AMDGPU.td, $@) + +AMDGPUGenSubtargetInfo.inc: $(TD_FILES) + $(call tablegen, -gen-subtarget, AMDGPU.td, $@) + +AMDGPUGenEDInfo.inc: $(TD_FILES) + $(call tablegen, -gen-enhanced-disassembly-info, AMDGPU.td, $@) + +AMDGPUGenIntrinsics.inc: $(TD_FILES) + $(call tablegen, -gen-tgt-intrinsic, AMDGPU.td, $@) + +AMDGPUGenCodeEmitter.inc: $(TD_FILES) + $(call tablegen, -gen-emitter, AMDGPU.td, $@) + +AMDGPUGenMCCodeEmitter.inc: $(TD_FILES) + $(call tablegen, -mc-emitter -gen-emitter, AMDGPU.td, $@) + +AMDGPUGenDFAPacketizer.inc: $(TD_FILES) + $(call tablegen, -gen-dfa-packetizer, AMDGPU.td, $@) + +noinst_PROGRAMS = loader + +loader_SOURCES = loader.cpp + +loader_LDADD = libradeon.la $(LLVM_LIBS) +loader_LDFLAGS = \ + $(LLVM_LDFLAGS) \ + $(LD_FLAGS) + +#XXX: Delete this when all targets that rely on radeon are converted to +# automake. +all-local: libradeon.la + ln -f $(builddir)/.libs/libradeon.a $(builddir)/libradeon.a + +CLEANFILES += libradeon.a diff --git a/src/gallium/drivers/radeon/Makefile.sources b/src/gallium/drivers/radeon/Makefile.sources index 687acb3..d8df295 100644 --- a/src/gallium/drivers/radeon/Makefile.sources +++ b/src/gallium/drivers/radeon/Makefile.sources @@ -1,4 +1,34 @@ +TD_FILES := \ + AMDGPU.td \ + AMDGPUInstrInfo.td \ + AMDGPUInstructions.td \ + AMDGPUIntrinsics.td \ + AMDGPURegisterInfo.td \ + AMDILBase.td\ + AMDILInstrInfo.td \ + AMDILIntrinsics.td \ + AMDILRegisterInfo.td\ + Processors.td \ + R600InstrInfo.td\ + R600Instructions.td \ + R600Intrinsics.td \ + R600Intrinsics.td \ + R600IntrinsicsNoOpenCL.td \ + R600IntrinsicsOpenCL.td \ + R600OpenCLIntrinsics.td \ + R600RegisterInfo.td \ + R600RegisterInfo.td \ + R600Schedule.td \ +
Re: [Mesa-dev] [PATCH] i965: Fix primitive restart on Haswell.
On 31 August 2012 13:16, Paul Berry stereotype...@gmail.com wrote: Yeah, good point. I'd be ok with that. Keeping in mind, of course, that after this patch lands, the bug will be in two places rather than one :) Scratch that. Ken's patch implements my suggestion #1 for Haswell, so the bug only needs to be addressed for previous chip generations. Sorry for the confusion. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965/fs: Don't use brw-fragment_program in calculate_urb_setup().
Kenneth Graunke kenn...@whitecape.org writes: Reading brw-fragment_program is nonsensical in compiler code: it contains the currently active program (if any), not the one currently being compiled. Attempting to access it may either lead to crashes (null pointer dereference if no program is active) or wrong results. Fixes piglit regressions since 9ef710575b914ddfc8e9a162d98ad554c1c217f7 on pre-Sandybridge hardware. The actual bug was created in commit 7b1fbc688999fd568e65211d79d7678562061594. NOTE: This is a candidate for the 9.0 and 8.0 branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54183 Cc: Rico Tzschichholz ric...@t-online.de Signed-off-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Eric Anholt e...@anholt.net pgpdQxpZfP3RH.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: don't wait in _mesa_ClientWaitSync if timeout is 0
Vadim Girlin vadimgir...@gmail.com writes: From ARB_sync spec: If the value of timeout is zero, then ClientWaitSync does not block, but simply tests the current state of sync. TIMEOUT_EXPIRED will be returned in this case if sync is not signaled, even though no actual wait was performed. Fixes random fails of the arb_sync-timeout-zero piglit test on r600g. We had similar failures. Thanks! Reviewed-by: Eric Anholt e...@anholt.net pgpkLK7STHsOn.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: don't wait in _mesa_ClientWaitSync if timeout is 0
On 08/31/2012 02:53 PM, Eric Anholt wrote: Vadim Girlinvadimgir...@gmail.com writes: From ARB_sync spec: If the value oftimeout is zero, then ClientWaitSync does not block, but simply tests the current state ofsync. TIMEOUT_EXPIRED will be returned in this case ifsync is not signaled, even though no actual wait was performed. Fixes random fails of the arb_sync-timeout-zero piglit test on r600g. We had similar failures. Thanks! Reviewed-by: Eric Anholte...@anholt.net Candidate for the 9.0 (and 8.0?) branches? -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] mesa: add context version routines
On 08/31/2012 12:52 PM, Jordan Justen wrote:
Signed-off-by: Jordan Justenjordan.l.jus...@intel.com
---
Based on the discussion July 26-27 in the thread
[PATCH 1/4] mesa: Add a Version field to the context
with VersionMajor*10+VersionMinor.
src/mesa/main/version.h | 54 +++
1 file changed, 54 insertions(+)
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 94a9855..6e13c6c 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -27,6 +27,11 @@
#ifndef VERSION_H
#define VERSION_H
+#include mtypes.h
+
+#ifdef __cplusplus
+extern C {
+#endif
struct gl_context;
@@ -48,4 +53,53 @@ _mesa_compute_version(struct gl_context *ctx);
extern void
_mesa_override_glsl_version(struct gl_context *ctx);
+/**
+ * Merge major/minor into a comparable uint
+ */
+static inline GLuint
+_mesa_uint_version(int major, int minor)
+{
+return major * 10 + minor;
+}
+
+/**
+ * Return the GL major version of the context
+ */
+static inline GLuint
+_mesa_get_version_major(struct gl_context *ctx)
+{
+return ctx-Version / 10;
+}
+
+/**
+ * Return the GL minor version of the context
+ */
+static inline GLuint
+_mesa_get_version_minor(struct gl_context *ctx)
+{
+return ctx-Version % 10;
+}
+
+/**
+ * Sets the context version to major.minor
+ */
+static inline void
+_mesa_set_version(struct gl_context *ctx, int major, int minor)
+{
+ctx-Version = _mesa_uint_version(major, minor);
+}
+
+/**
+ * Checks if the context version is greater than or equal to major.minor
+ */
+static inline GLboolean
+_mesa_have_version(const struct gl_context *ctx, int major, int minor)
+{
+return ctx-Version= _mesa_uint_version(major, minor);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* VERSION_H */
--
1.7.9.5
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Looks OK to me.
Signed-off-by: Brian Paul bri...@vmware.com
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[Mesa-dev] [PATCH] i965: Don't leave dangling pointer to brw context on failure
From: Ian Romanick ian.d.roman...@intel.com
Otherwise intelDestroyContext would try to dereference the pointer to
freed memory.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 4e5aed6..ab485c3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -149,6 +149,7 @@ brwCreateContext(int api,
sharedContextPrivate, functions )) {
printf(%s: failed to init intel context\n, __FUNCTION__);
FREE(brw);
+ driContextPriv-driverPrivate = NULL;
*error = __DRI_CTX_ERROR_NO_MEMORY;
return false;
}
--
1.7.11.4
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[Mesa-dev] [PATCH 3/4] i965: Make the param pointer arrays for the WM dynamically sized.
Saves 26.5MB of wasted memory allocation in the l4d2 demo.
v2: Rebase on compare func change, fix comments.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com (v1)
---
src/mesa/drivers/dri/i965/brw_context.h |7 --
src/mesa/drivers/dri/i965/brw_fs.cpp|2 --
src/mesa/drivers/dri/i965/brw_state_cache.c |5
src/mesa/drivers/dri/i965/brw_wm.c | 35 +++
src/mesa/drivers/dri/i965/brw_wm.h |1 +
5 files changed, 46 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 6cc567c..7261c9d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -322,8 +322,8 @@ struct brw_wm_prog_data {
* These must be the last fields of the struct (see
* brw_wm_prog_data_compare()).
*/
- const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
- const float *pull_param[MAX_UNIFORMS * 4];
+ const float **param;
+ const float **pull_param;
};
/**
@@ -631,6 +631,7 @@ struct brw_cache_item {
typedef bool (*cache_aux_compare_func)(void *a, void *b, int aux_size,
void *key);
+typedef void (*cache_aux_free_func)(const void *aux);
struct brw_cache {
struct brw_context *brw;
@@ -648,6 +649,8 @@ struct brw_cache {
* outside of the prog_data). If NULL, a plain memcmp is done.
*/
cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
+ /** Optional functions for freeing other pointers attached to a prog_data.
*/
+ cache_aux_free_func aux_free[BRW_MAX_CACHE];
};
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a8d55ff..fa4c64b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -528,8 +528,6 @@ fs_visitor::setup_uniform_values(int loc, const glsl_type
*type)
for (unsigned int i = 0; i type-vector_elements; i++) {
unsigned int param = c-prog_data.nr_params++;
-assert(param ARRAY_SIZE(c-prog_data.param));
-
this-param_index[param] = loc;
this-param_offset[param] = i;
}
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 354d94b..894142b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -341,6 +341,7 @@ brw_init_caches(struct brw_context *brw)
cache-aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
cache-aux_compare[BRW_WM_PROG] = brw_wm_prog_data_compare;
+ cache-aux_free[BRW_WM_PROG] = brw_wm_prog_data_free;
}
static void
@@ -355,6 +356,10 @@ brw_clear_cache(struct brw_context *brw, struct brw_cache
*cache)
for (i = 0; i cache-size; i++) {
for (c = cache-items[i]; c; c = next) {
next = c-next;
+ if (cache-aux_free[c-cache_id]) {
+const void *item_aux = c-key + c-key_size;
+cache-aux_free[c-cache_id](item_aux);
+ }
free((void *)c-key);
free(c);
}
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c
b/src/mesa/drivers/dri/i965/brw_wm.c
index f16bed6..87e793e 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -272,6 +272,15 @@ brw_wm_prog_data_compare(void *in_a, void *in_b, int
aux_size, void *in_key)
return true;
}
+void
+brw_wm_prog_data_free(const void *in_prog_data)
+{
+ const struct brw_wm_prog_data *prog_data = in_prog_data;
+
+ ralloc_free((void *)prog_data-param);
+ ralloc_free((void *)prog_data-pull_param);
+}
+
/**
* All Mesa program - GPU code generation goes through this function.
* Depending on the instructions used (i.e. flow control instructions)
@@ -285,8 +294,12 @@ bool do_wm_prog(struct brw_context *brw,
struct intel_context *intel = brw-intel;
struct brw_wm_compile *c;
const GLuint *program;
+ struct gl_shader *fs = NULL;
GLuint program_size;
+ if (prog)
+ fs = prog-_LinkedShaders[MESA_SHADER_FRAGMENT];
+
c = brw-wm.compile_data;
if (c == NULL) {
brw-wm.compile_data = rzalloc(NULL, struct brw_wm_compile);
@@ -309,6 +322,28 @@ bool do_wm_prog(struct brw_context *brw,
c-vreg = vreg;
c-refs = refs;
}
+
+ /* Allocate the references to the uniforms that will end up in the
+* prog_data associated with the compiled program, and which will be freed
+* by the state cache.
+*/
+ if (fs) {
+ int param_count = fs-num_uniform_components;
+ /* The backend also sometimes adds params for texture size. */
+ param_count += 2 * BRW_MAX_TEX_UNIT;
+
+ c-prog_data.param = rzalloc_array(c, const float *, param_count);
+ c-prog_data.pull_param = rzalloc_array(c, const float *, param_count);
+ } else {
+ /* brw_wm_pass0.c will also add references to 0.0 and 1.0 which are
+ * uploaded as push parameters.
+
[Mesa-dev] [PATCH 4/4] i965: Make the param pointer arrays for the VS dynamically sized.
Saves 96MB of wasted memory in the l4d2 demo.
v2: Rebase on compare func change, change brace style.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |4 ++--
src/mesa/drivers/dri/i965/brw_state_cache.c |2 ++
src/mesa/drivers/dri/i965/brw_vs.c | 33 +++
src/mesa/drivers/dri/i965/brw_vs.h |1 +
4 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 7261c9d..feb23aa 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -459,8 +459,8 @@ struct brw_vs_prog_data {
int num_surfaces;
/* These pointers must appear last. See brw_vs_prog_data_compare(). */
- const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
- const float *pull_param[MAX_UNIFORMS * 4];
+ const float **param;
+ const float **pull_param;
};
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 894142b..faff94e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -49,6 +49,7 @@
#include brw_state.h
#include brw_vs.h
#include brw_wm.h
+#include brw_vs.h
#define FILE_DEBUG_FLAG DEBUG_STATE
@@ -341,6 +342,7 @@ brw_init_caches(struct brw_context *brw)
cache-aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
cache-aux_compare[BRW_WM_PROG] = brw_wm_prog_data_compare;
+ cache-aux_free[BRW_VS_PROG] = brw_vs_prog_data_free;
cache-aux_free[BRW_WM_PROG] = brw_wm_prog_data_free;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index a54999d..aa383c3 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -219,6 +219,10 @@ do_vs_prog(struct brw_context *brw,
void *mem_ctx;
int aux_size;
int i;
+ struct gl_shader *vs = NULL;
+
+ if (prog)
+ vs = prog-_LinkedShaders[MESA_SHADER_VERTEX];
memset(c, 0, sizeof(c));
memcpy(c.key, key, sizeof(*key));
@@ -228,6 +232,26 @@ do_vs_prog(struct brw_context *brw,
brw_init_compile(brw, c.func, mem_ctx);
c.vp = vp;
+ /* Allocate the references to the uniforms that will end up in the
+* prog_data associated with the compiled program, and which will be freed
+* by the state cache.
+*/
+ int param_count;
+ if (vs) {
+ /* We add padding around uniform values below vec4 size, with the worst
+ * case being a float value that gets blown up to a vec4, so be
+ * conservative here.
+ */
+ param_count = vs-num_uniform_components * 4;
+
+ /* We also upload clip plane data as uniforms */
+ param_count += MAX_CLIP_PLANES * 4;
+ } else {
+ param_count = vp-program.Base.Parameters-NumParameters * 4;
+ }
+ c.prog_data.param = rzalloc_array(NULL, const float *, param_count);
+ c.prog_data.pull_param = rzalloc_array(NULL, const float *, param_count);
+
c.prog_data.outputs_written = vp-program.Base.OutputsWritten;
c.prog_data.inputs_read = vp-program.Base.InputsRead;
@@ -511,3 +535,12 @@ brw_vs_precompile(struct gl_context *ctx, struct
gl_shader_program *prog)
return success;
}
+
+void
+brw_vs_prog_data_free(const void *in_prog_data)
+{
+ const struct brw_vs_prog_data *prog_data = in_prog_data;
+
+ ralloc_free((void *)prog_data-param);
+ ralloc_free((void *)prog_data-pull_param);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h
b/src/mesa/drivers/dri/i965/brw_vs.h
index 8fcdbb3..ee7621d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -124,5 +124,6 @@ void brw_vs_debug_recompile(struct brw_context *brw,
struct gl_shader_program *prog,
const struct brw_vs_prog_key *key);
bool brw_vs_prog_data_compare(void *a, void *b, int aux_size, void *key);
+void brw_vs_prog_data_free(const void *in_prog_data);
#endif
--
1.7.10.4
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[Mesa-dev] [PATCH 1/4] glsl: Count builtin uniforms against uniform component limits.
We don't fully process the builtin uniforms, but at least
num_uniform_components reflects reality now.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/link_uniforms.cpp |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
index eef9025..aa8a8b3 100644
--- a/src/glsl/link_uniforms.cpp
+++ b/src/glsl/link_uniforms.cpp
@@ -572,8 +572,11 @@ link_assign_uniform_locations(struct gl_shader_program
*prog)
/* FINISHME: Update code to process built-in uniforms!
*/
-if (strncmp(gl_, var-name, 3) == 0)
+if (strncmp(gl_, var-name, 3) == 0) {
+ uniform_size.num_shader_uniform_components +=
+ var-type-component_slots();
continue;
+}
uniform_size.process(var);
}
--
1.7.10.4
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[Mesa-dev] [PATCH 2/4] i965: Add functions for comparing two brw_wm/vs_prog_data structs.
Currently, this just avoids comparing all unused parts of param[] and
pull_param[], but it's a step toward getting rid of those giant statically
sized arrays.
---
src/mesa/drivers/dri/i965/brw_context.h | 29 ++-
src/mesa/drivers/dri/i965/brw_state_cache.c | 10 -
src/mesa/drivers/dri/i965/brw_vs.c | 18 +
src/mesa/drivers/dri/i965/brw_vs.h |1 +
src/mesa/drivers/dri/i965/brw_wm.c | 19 ++
src/mesa/drivers/dri/i965/brw_wm.h |1 +
6 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 71cd0f4..6cc567c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -288,7 +288,10 @@ struct brw_shader_program {
/* Data about a particular attempt to compile a program. Note that
* there can be many of these, each in a different GL state
* corresponding to a different brw_wm_prog_key struct, with different
- * compiled programs:
+ * compiled programs.
+ *
+ * Note: brw_wm_prog_data_compare() must be updated when adding fields to this
+ * struct!
*/
struct brw_wm_prog_data {
GLuint curb_read_length;
@@ -313,8 +316,11 @@ struct brw_wm_prog_data {
*/
uint32_t barycentric_interp_modes;
- /* Pointer to tracked values (only valid once
+ /* Pointers to tracked values (only valid once
* _mesa_load_state_parameters has been called at runtime).
+*
+* These must be the last fields of the struct (see
+* brw_wm_prog_data_compare()).
*/
const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
const float *pull_param[MAX_UNIFORMS * 4];
@@ -426,6 +432,9 @@ struct brw_gs_prog_data {
unsigned svbi_postincrement_value;
};
+/* Note: brw_vs_prog_data_compare() must be updated when adding fields to this
+ * struct!
+ */
struct brw_vs_prog_data {
struct brw_vue_map vue_map;
@@ -443,14 +452,15 @@ struct brw_vs_prog_data {
*/
GLuint urb_entry_size;
- const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
- const float *pull_param[MAX_UNIFORMS * 4];
-
bool uses_new_param_layout;
bool uses_vertexid;
bool userclip;
int num_surfaces;
+
+ /* These pointers must appear last. See brw_vs_prog_data_compare(). */
+ const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
+ const float *pull_param[MAX_UNIFORMS * 4];
};
@@ -619,6 +629,8 @@ struct brw_cache_item {
};
+typedef bool (*cache_aux_compare_func)(void *a, void *b, int aux_size,
+ void *key);
struct brw_cache {
struct brw_context *brw;
@@ -629,6 +641,13 @@ struct brw_cache {
uint32_t next_offset;
bool bo_used_by_gpu;
+
+ /**
+* Optional functions used in determining whether the prog_data for a new
+* cache item matches an existing cache item (in case there's relevant data
+* outside of the prog_data). If NULL, a plain memcmp is done.
+*/
+ cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
};
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 8823b22..354d94b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -47,6 +47,8 @@
#include main/imports.h
#include intel_batchbuffer.h
#include brw_state.h
+#include brw_vs.h
+#include brw_wm.h
#define FILE_DEBUG_FLAG DEBUG_STATE
@@ -211,7 +213,10 @@ brw_try_upload_using_copy(struct brw_cache *cache,
continue;
}
-if (memcmp(item_aux, aux, item-aux_size) != 0) {
+ if (cache-aux_compare[result_item-cache_id]) {
+if (!cache-aux_compare[result_item-cache_id])
+ continue;
+ } else if (memcmp(item_aux, aux, item-aux_size) != 0) {
continue;
}
@@ -333,6 +338,9 @@ brw_init_caches(struct brw_context *brw)
cache-bo = drm_intel_bo_alloc(intel-bufmgr,
program cache,
4096, 64);
+
+ cache-aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
+ cache-aux_compare[BRW_WM_PROG] = brw_wm_prog_data_compare;
}
static void
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 710ffe8..a54999d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -186,6 +186,24 @@ gl_clip_plane *brw_select_clip_planes(struct gl_context
*ctx)
}
}
+bool
+brw_vs_prog_data_compare(void *in_a, void *in_b, int aux_size, void *in_key)
+{
+ struct brw_vs_prog_data *a = in_a;
+ struct brw_vs_prog_data *b = in_b;
+
+ /* Compare all the struct up to the pointers. */
+ if (memcmp(a, b, offsetof(struct brw_vs_prog_data, param)))
+ return false;
+
+ if (memcmp(a-param, b-param, a-nr_params * sizeof(void *)))
+
[Mesa-dev] [PATCH] meta: Don't save and restore fog state when there is no fog state
From: Ian Romanick ian.d.roman...@intel.com
I wonder if the better solution is to have _mesa_meta_GenerateMipmap not
use MESA_META_ALL for the GLSL path. Even on compatibility profiles
there is no reason to save and restore fog on this path.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54295
---
src/mesa/drivers/common/meta.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 4b448fe..98fa847 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -538,7 +538,9 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
_mesa_set_enable(ctx, GL_DEPTH_TEST, GL_FALSE);
}
- if (state MESA_META_FOG) {
+ if ((state MESA_META_FOG)
+ctx-API != API_OPENGL_CORE
+ctx-API != API_OPENGLES2) {
save-Fog = ctx-Fog.Enabled;
if (ctx-Fog.Enabled)
_mesa_set_enable(ctx, GL_FOG, GL_FALSE);
@@ -856,7 +858,9 @@ _mesa_meta_end(struct gl_context *ctx)
_mesa_DepthMask(save-Depth.Mask);
}
- if (state MESA_META_FOG) {
+ if (state MESA_META_FOG
+ctx-API != API_OPENGL_CORE
+ctx-API != API_OPENGLES2) {
_mesa_set_enable(ctx, GL_FOG, save-Fog);
}
--
1.7.11.4
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Re: [Mesa-dev] [PATCH] meta: Don't save and restore fog state when there is no fog state
On 08/31/2012 04:31 PM, Ian Romanick wrote:
From: Ian Romanickian.d.roman...@intel.com
I wonder if the better solution is to have _mesa_meta_GenerateMipmap not
use MESA_META_ALL for the GLSL path. Even on compatibility profiles
there is no reason to save and restore fog on this path.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Ian Romanickian.d.roman...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54295
---
src/mesa/drivers/common/meta.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 4b448fe..98fa847 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -538,7 +538,9 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
_mesa_set_enable(ctx, GL_DEPTH_TEST, GL_FALSE);
}
- if (state MESA_META_FOG) {
+ if ((state MESA_META_FOG)
+ ctx-API != API_OPENGL_CORE
+ ctx-API != API_OPENGLES2) {
save-Fog = ctx-Fog.Enabled;
if (ctx-Fog.Enabled)
_mesa_set_enable(ctx, GL_FOG, GL_FALSE);
@@ -856,7 +858,9 @@ _mesa_meta_end(struct gl_context *ctx)
_mesa_DepthMask(save-Depth.Mask);
}
- if (state MESA_META_FOG) {
+ if (state MESA_META_FOG
Need parens around (state MESA_META_FOG), as above.
+ ctx-API != API_OPENGL_CORE
+ ctx-API != API_OPENGLES2) {
_mesa_set_enable(ctx, GL_FOG, save-Fog);
}
Reviewed-by: Brian Paul bri...@vmware.com
Probably quite a bit of fixed-function texture and transformation
state could be left untouched too (esp. when using shaders).
-Brian
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Re: [Mesa-dev] [PATCH] mesa: don't wait in _mesa_ClientWaitSync if timeout is 0
On Fri, 2012-08-31 at 15:50 -0600, Brian Paul wrote: On 08/31/2012 02:53 PM, Eric Anholt wrote: Vadim Girlinvadimgir...@gmail.com writes: From ARB_sync spec: If the value oftimeout is zero, then ClientWaitSync does not block, but simply tests the current state ofsync. TIMEOUT_EXPIRED will be returned in this case ifsync is not signaled, even though no actual wait was performed. Fixes random fails of the arb_sync-timeout-zero piglit test on r600g. We had similar failures. Thanks! Reviewed-by: Eric Anholte...@anholt.net Candidate for the 9.0 (and 8.0?) branches? Probably yes, but I forget to mention it in the commit message. On the other hand, I think it doesn't fix anything besides that test. Vadim -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] glsl: Generate compile errors for explicit blend indices 0 or 1.
According to the GLSL 4.30 specification, this is a compile time error.
Earlier specifications don't specify a behavior, but since 0 and 1 are
the only valid indices for dual source blending, it makes sense to
generate the error.
Fixes (the fixed version of) piglit's layout-12.frag.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/ast_to_hir.cpp | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 02fe66b..becf6f9 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2086,9 +2086,22 @@ apply_type_qualifier_to_variable(const struct
ast_type_qualifier *qual,
} else {
var-location = qual-location;
}
+
if (qual-flags.q.explicit_index) {
- var-explicit_index = true;
- var-index = qual-index;
+/* From the GLSL 4.30 specification: It is also a compile-time
+ * error if a fragment shader sets a layout index to less than 0
+ * or greater than 1.
+ *
+ * Older specifications don't mandate a behavior; we take this
+ * as a clarification and always generate the error.
+ */
+if (qual-index 0 || qual-index 1) {
+ _mesa_glsl_error(loc, state,
+explicit index may only be 0 or 1\n);
+} else {
+ var-explicit_index = true;
+ var-index = qual-index;
+}
}
}
} else if (qual-flags.q.explicit_index) {
--
1.7.11.4
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Re: [Mesa-dev] [PATCH] mesa: don't wait in _mesa_ClientWaitSync if timeout is 0
On 08/31/2012 01:37 PM, Vadim Girlin wrote: From ARB_sync spec: If the value of timeout is zero, then ClientWaitSync does not block, but simply tests the current state of sync. TIMEOUT_EXPIRED will be returned in this case if sync is not signaled, even though no actual wait was performed. Fixes random fails of the arb_sync-timeout-zero piglit test on r600g. Signed-off-by: Vadim Girlin vadimgir...@gmail.com --- src/mesa/main/syncobj.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) Hooray! I kept meaning to look into this, but never got to it. Thanks for fixing it. Reviewed-by: Kenneth Graunke kenn...@whitecape.org ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/4] i965: Add functions for comparing two brw_wm/vs_prog_data structs.
On 08/31/2012 03:05 PM, Eric Anholt wrote:
Currently, this just avoids comparing all unused parts of param[] and
pull_param[], but it's a step toward getting rid of those giant statically
sized arrays.
---
src/mesa/drivers/dri/i965/brw_context.h | 29
++-
src/mesa/drivers/dri/i965/brw_state_cache.c | 10 -
src/mesa/drivers/dri/i965/brw_vs.c | 18 +
src/mesa/drivers/dri/i965/brw_vs.h |1 +
src/mesa/drivers/dri/i965/brw_wm.c | 19 ++
src/mesa/drivers/dri/i965/brw_wm.h |1 +
6 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 71cd0f4..6cc567c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -288,7 +288,10 @@ struct brw_shader_program {
/* Data about a particular attempt to compile a program. Note that
* there can be many of these, each in a different GL state
* corresponding to a different brw_wm_prog_key struct, with different
- * compiled programs:
+ * compiled programs.
+ *
+ * Note: brw_wm_prog_data_compare() must be updated when adding fields to
this
+ * struct!
*/
struct brw_wm_prog_data {
GLuint curb_read_length;
@@ -313,8 +316,11 @@ struct brw_wm_prog_data {
*/
uint32_t barycentric_interp_modes;
- /* Pointer to tracked values (only valid once
+ /* Pointers to tracked values (only valid once
* _mesa_load_state_parameters has been called at runtime).
+*
+* These must be the last fields of the struct (see
+* brw_wm_prog_data_compare()).
*/
const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
const float *pull_param[MAX_UNIFORMS * 4];
@@ -426,6 +432,9 @@ struct brw_gs_prog_data {
unsigned svbi_postincrement_value;
};
+/* Note: brw_vs_prog_data_compare() must be updated when adding fields to
this
+ * struct!
+ */
struct brw_vs_prog_data {
struct brw_vue_map vue_map;
@@ -443,14 +452,15 @@ struct brw_vs_prog_data {
*/
GLuint urb_entry_size;
- const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
- const float *pull_param[MAX_UNIFORMS * 4];
-
bool uses_new_param_layout;
bool uses_vertexid;
bool userclip;
int num_surfaces;
+
+ /* These pointers must appear last. See brw_vs_prog_data_compare(). */
+ const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
+ const float *pull_param[MAX_UNIFORMS * 4];
};
@@ -619,6 +629,8 @@ struct brw_cache_item {
};
+typedef bool (*cache_aux_compare_func)(void *a, void *b, int aux_size,
+ void *key);
struct brw_cache {
struct brw_context *brw;
@@ -629,6 +641,13 @@ struct brw_cache {
uint32_t next_offset;
bool bo_used_by_gpu;
+
+ /**
+* Optional functions used in determining whether the prog_data for a new
+* cache item matches an existing cache item (in case there's relevant
data
+* outside of the prog_data). If NULL, a plain memcmp is done.
+*/
+ cache_aux_compare_func aux_compare[BRW_MAX_CACHE];
};
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 8823b22..354d94b 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -47,6 +47,8 @@
#include main/imports.h
#include intel_batchbuffer.h
#include brw_state.h
+#include brw_vs.h
+#include brw_wm.h
#define FILE_DEBUG_FLAG DEBUG_STATE
@@ -211,7 +213,10 @@ brw_try_upload_using_copy(struct brw_cache *cache,
continue;
}
- if (memcmp(item_aux, aux, item-aux_size) != 0) {
+ if (cache-aux_compare[result_item-cache_id]) {
+if (!cache-aux_compare[result_item-cache_id])
+ continue;
It sure doesn't look like you're calling the function...just checking
if (function_pointer) {
if (!function_pointer)
continue;
}
which is really not what you want :)
Otherwise this looks good.
+ } else if (memcmp(item_aux, aux, item-aux_size) != 0) {
continue;
}
@@ -333,6 +338,9 @@ brw_init_caches(struct brw_context *brw)
cache-bo = drm_intel_bo_alloc(intel-bufmgr,
program cache,
4096, 64);
+
+ cache-aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
+ cache-aux_compare[BRW_WM_PROG] = brw_wm_prog_data_compare;
}
static void
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index 710ffe8..a54999d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -186,6 +186,24 @@ gl_clip_plane *brw_select_clip_planes(struct gl_context
*ctx)
}
}
[Mesa-dev] [Bug 54326] When building 32 bit on 64 bit, build ends saying it can't find 32 bit libkms.so
https://bugs.freedesktop.org/show_bug.cgi?id=54326 --- Comment #1 from Alexandre Demers alexandre.f.dem...@gmail.com 2012-09-01 04:08:24 UTC --- Making all in gbm make[2]: Entering directory `/home/dema1701/projects/display/mesa/src/gbm' CCLD libgbm.la /usr/bin/ld: skipping incompatible /usr/lib/x86_64-linux-gnu/libudev.so when searching for -ludev /usr/bin/ld: skipping incompatible /usr/lib/x86_64-linux-gnu/libudev.a when searching for -ludev /usr/bin/ld: skipping incompatible /usr/lib/x86_64-linux-gnu/librt.so when searching for -lrt /usr/bin/ld: skipping incompatible /usr/lib/x86_64-linux-gnu/librt.a when searching for -lrt /usr/lib/x86_64-linux-gnu/libkms.so: could not read symbols: File in wrong format collect2: error: ld returned 1 exit status make[2]: *** [libgbm.la] Error 1 -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 54326] When building 32 bit on 64 bit, build ends saying it can't find 32 bit libkms.so
https://bugs.freedesktop.org/show_bug.cgi?id=54326 --- Comment #2 from Alexandre Demers alexandre.f.dem...@gmail.com 2012-09-01 04:11:50 UTC --- Pretty sure the culprit commit is a669a5055eadae85ffa000cea19a2241d0699348: gbm: Use libkms to replace DRI cursor images Author Jakob Bornecrantzja...@vmware.com Author date 8/13/12 9:55 AM Parent i965: Don't set iz_lookup the FS precompile's program key... Child dri: Remove image write function Branch master (build: Remove left over echo from GLU removal) Branch origin/master (build: Remove left over echo from GLU removal) Follows snb-magic (graw: Add struct pipe_surface forward declaration.) gbm: Use libkms to replace DRI cursor images -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] i965: Make the param pointer arrays for the VS dynamically sized.
On 08/31/2012 03:05 PM, Eric Anholt wrote:
Saves 96MB of wasted memory in the l4d2 demo.
v2: Rebase on compare func change, change brace style.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |4 ++--
src/mesa/drivers/dri/i965/brw_state_cache.c |2 ++
src/mesa/drivers/dri/i965/brw_vs.c | 33
+++
src/mesa/drivers/dri/i965/brw_vs.h |1 +
4 files changed, 38 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 7261c9d..feb23aa 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -459,8 +459,8 @@ struct brw_vs_prog_data {
int num_surfaces;
/* These pointers must appear last. See brw_vs_prog_data_compare(). */
- const float *param[MAX_UNIFORMS * 4]; /* should be: BRW_MAX_CURBE */
- const float *pull_param[MAX_UNIFORMS * 4];
+ const float **param;
+ const float **pull_param;
};
diff --git a/src/mesa/drivers/dri/i965/brw_state_cache.c
b/src/mesa/drivers/dri/i965/brw_state_cache.c
index 894142b..faff94e 100644
--- a/src/mesa/drivers/dri/i965/brw_state_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_state_cache.c
@@ -49,6 +49,7 @@
#include brw_state.h
#include brw_vs.h
#include brw_wm.h
+#include brw_vs.h
#define FILE_DEBUG_FLAG DEBUG_STATE
@@ -341,6 +342,7 @@ brw_init_caches(struct brw_context *brw)
cache-aux_compare[BRW_VS_PROG] = brw_vs_prog_data_compare;
cache-aux_compare[BRW_WM_PROG] = brw_wm_prog_data_compare;
+ cache-aux_free[BRW_VS_PROG] = brw_vs_prog_data_free;
cache-aux_free[BRW_WM_PROG] = brw_wm_prog_data_free;
}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.c
b/src/mesa/drivers/dri/i965/brw_vs.c
index a54999d..aa383c3 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -219,6 +219,10 @@ do_vs_prog(struct brw_context *brw,
void *mem_ctx;
int aux_size;
int i;
+ struct gl_shader *vs = NULL;
+
+ if (prog)
+ vs = prog-_LinkedShaders[MESA_SHADER_VERTEX];
memset(c, 0, sizeof(c));
memcpy(c.key, key, sizeof(*key));
@@ -228,6 +232,26 @@ do_vs_prog(struct brw_context *brw,
brw_init_compile(brw, c.func, mem_ctx);
c.vp = vp;
+ /* Allocate the references to the uniforms that will end up in the
+* prog_data associated with the compiled program, and which will be freed
+* by the state cache.
+*/
+ int param_count;
+ if (vs) {
+ /* We add padding around uniform values below vec4 size, with the worst
+ * case being a float value that gets blown up to a vec4, so be
+ * conservative here.
+ */
+ param_count = vs-num_uniform_components * 4;
+
+ /* We also upload clip plane data as uniforms */
+ param_count += MAX_CLIP_PLANES * 4;
+ } else {
+ param_count = vp-program.Base.Parameters-NumParameters * 4;
+ }
+ c.prog_data.param = rzalloc_array(NULL, const float *, param_count);
+ c.prog_data.pull_param = rzalloc_array(NULL, const float *, param_count);
I'm surprised to see these be the same. Maybe we can do better later.
This is definitely a great start though!
For the series (assuming you fix patch 2 to actually call the function):
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
c.prog_data.outputs_written = vp-program.Base.OutputsWritten;
c.prog_data.inputs_read = vp-program.Base.InputsRead;
@@ -511,3 +535,12 @@ brw_vs_precompile(struct gl_context *ctx, struct
gl_shader_program *prog)
return success;
}
+
+void
+brw_vs_prog_data_free(const void *in_prog_data)
+{
+ const struct brw_vs_prog_data *prog_data = in_prog_data;
+
+ ralloc_free((void *)prog_data-param);
+ ralloc_free((void *)prog_data-pull_param);
+}
diff --git a/src/mesa/drivers/dri/i965/brw_vs.h
b/src/mesa/drivers/dri/i965/brw_vs.h
index 8fcdbb3..ee7621d 100644
--- a/src/mesa/drivers/dri/i965/brw_vs.h
+++ b/src/mesa/drivers/dri/i965/brw_vs.h
@@ -124,5 +124,6 @@ void brw_vs_debug_recompile(struct brw_context *brw,
struct gl_shader_program *prog,
const struct brw_vs_prog_key *key);
bool brw_vs_prog_data_compare(void *a, void *b, int aux_size, void *key);
+void brw_vs_prog_data_free(const void *in_prog_data);
#endif
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[Mesa-dev] [Bug 54326] When building 32 bit on 64 bit, build ends at libgbm saying it can't find 32 bit libkms.so
https://bugs.freedesktop.org/show_bug.cgi?id=54326 Alexandre Demers alexandre.f.dem...@gmail.com changed: What|Removed |Added Summary|When building 32 bit on 64 |When building 32 bit on 64 |bit, build ends saying it |bit, build ends at libgbm |can't find 32 bit libkms.so |saying it can't find 32 bit ||libkms.so -- Configure bugmail: https://bugs.freedesktop.org/userprefs.cgi?tab=email --- You are receiving this mail because: --- You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Don't leave dangling pointer to brw context on failure
On 08/31/2012 03:03 PM, Ian Romanick wrote:
From: Ian Romanick ian.d.roman...@intel.com
Otherwise intelDestroyContext would try to dereference the pointer to
freed memory.
NOTE: This is a candidate for the 9.0 branch.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54301
---
src/mesa/drivers/dri/i965/brw_context.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 4e5aed6..ab485c3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -149,6 +149,7 @@ brwCreateContext(int api,
sharedContextPrivate, functions )) {
printf(%s: failed to init intel context\n, __FUNCTION__);
FREE(brw);
+ driContextPriv-driverPrivate = NULL;
*error = __DRI_CTX_ERROR_NO_MEMORY;
return false;
}
I had a little bit of a hard time figuring out where the NULL check is.
It looks like glXDestroyContext() checks.
I doubt it can hurt, anyway.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
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Re: [Mesa-dev] [PATCH 2/2] mesa: utilize context version routines
I'm really ambivalent about these patches. 1. I'm not a huge fan of the name have_version...it sounds like it would return whether a driver supports a given version, not whether the current context's version is a certain value. 2. Personally I think ctx-Version = XY is clearer than !_mesa_have_version(ctx, X, Y + 1). With the two-digit notation, you can just do whatever comparison you like, rather than having to negate = and possibly increment the minor version being compared. 3. _mesa_have_version(ctx, 3, 1) is longer than ctx-Version = 31 3. I really don't see the major * 10 + minor notation needing to be changed in the future. Even if Khronos did offer (say) a GL 4.3.1 release, the likelihood of it making incompatible changes over 4.3 that require special checks is infinitesimal. It would just be clarifications... Normally, I'm all for encapsulation, but I guess I just don't see much point. That said, I won't object too strongly if people prefer this approach. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Stop putting 8 NOPs after each prorgam.
On 08/31/2012 12:19 PM, Eric Anholt wrote:
As far as I can see, the intention of the requirement that we do so is to
prevent instruction prefetch from wandering out into either unmapped memory or
memory with a different caching type, and hanging the chip. The kernel makes
sure that the page after your BO has a valid page of the same caching type,
which meets this requirement, so there's no need to waste space between our
programs (and in instruction cache) on this.
Saves another 9kb instructions in l4d2 shaders.
That makes sense. The kernel needs to protect us against this for the
sake of robustness against lame userspace anyway. We may as well take
advantage of it and not waste the space.
Acked-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_eu.c |8
1 file changed, 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 130d801..c60b16c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -214,16 +214,8 @@ brw_init_compile(struct brw_context *brw, struct
brw_compile *p, void *mem_ctx)
const GLuint *brw_get_program( struct brw_compile *p,
GLuint *sz )
{
- GLuint i;
-
brw_compact_instructions(p);
- /* We emit a cacheline (8 instructions) of NOPs at the end of the program
to
-* make sure that instruction prefetch doesn't wander off into some other
BO.
-*/
- for (i = 0; i 8; i++)
- brw_NOP(p);
-
*sz = p-next_insn_offset;
return (const GLuint *)p-store;
}
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Re: [Mesa-dev] [PATCH 1/2] mesa: add context version routines
On 08/31/2012 11:52 AM, Jordan Justen wrote:
Signed-off-by: Jordan Justen jordan.l.jus...@intel.com
---
Based on the discussion July 26-27 in the thread
[PATCH 1/4] mesa: Add a Version field to the context
with VersionMajor*10+VersionMinor.
src/mesa/main/version.h | 54
+++
1 file changed, 54 insertions(+)
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 94a9855..6e13c6c 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -27,6 +27,11 @@
#ifndef VERSION_H
#define VERSION_H
+#include mtypes.h
+
+#ifdef __cplusplus
+extern C {
+#endif
struct gl_context;
@@ -48,4 +53,53 @@ _mesa_compute_version(struct gl_context *ctx);
extern void
_mesa_override_glsl_version(struct gl_context *ctx);
+/**
+ * Merge major/minor into a comparable uint
+ */
+static inline GLuint
+_mesa_uint_version(int major, int minor)
+{
+return major * 10 + minor;
+}
+
+/**
+ * Return the GL major version of the context
+ */
+static inline GLuint
+_mesa_get_version_major(struct gl_context *ctx)
+{
+return ctx-Version / 10;
+}
+
+/**
+ * Return the GL minor version of the context
+ */
+static inline GLuint
+_mesa_get_version_minor(struct gl_context *ctx)
+{
+return ctx-Version % 10;
+}
+
+/**
+ * Sets the context version to major.minor
+ */
+static inline void
+_mesa_set_version(struct gl_context *ctx, int major, int minor)
+{
+ctx-Version = _mesa_uint_version(major, minor);
+}
+
+/**
+ * Checks if the context version is greater than or equal to major.minor
+ */
+static inline GLboolean
+_mesa_have_version(const struct gl_context *ctx, int major, int minor)
+{
+return ctx-Version = _mesa_uint_version(major, minor);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
#endif /* VERSION_H */
--
1.7.9.5
Whitespace errors on all of these functions. Mesa is 3-space indent, not 4.
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[Mesa-dev] [PATCH] i965: Don't use brw-fragment_program in the old brw_wm_pass2.c.
Reading brw-fragment_program is nonsensical in compiler code: it
contains the currently active program (if any), not the one currently
being compiled. Attempting to access it may either lead to crashes
(null pointer dereference if no program is active) or wrong results.
Not known to fix anything, but that's probably just due to a lack of
testing.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reported-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_wm_pass2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 562a189..f20e0b7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -86,7 +86,7 @@ static void init_registers( struct brw_wm_compile *c )
if (intel-gen = 6) {
for (unsigned int j = 0; j FRAG_ATTRIB_MAX; j++) {
-if (brw-fragment_program-Base.InputsRead BITFIELD64_BIT(j)) {
+if (c-fp-program.Base.InputsRead BITFIELD64_BIT(j)) {
nr_interp_regs++;
prealloc_reg(c, c-payload.input_interp[j], i++);
}
--
1.7.11.4
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