[Mesa-dev] [PATCH] st/egl: Flush resources before presentation

2013-12-26 Thread Martin Andersson 
Fixes wayland regression on r600g due to fast clear introduced by commit
edbbfac6.
---
 src/gallium/state_trackers/egl/common/native_helper.c   | 15 +++
 src/gallium/state_trackers/egl/common/native_helper.h   |  5 +
 src/gallium/state_trackers/egl/wayland/native_wayland.c |  4 
 3 files changed, 24 insertions(+)

diff --git a/src/gallium/state_trackers/egl/common/native_helper.c 
b/src/gallium/state_trackers/egl/common/native_helper.c
index 4a77a50..856cbb6 100644
--- a/src/gallium/state_trackers/egl/common/native_helper.c
+++ b/src/gallium/state_trackers/egl/common/native_helper.c
@@ -341,6 +341,21 @@ resource_surface_throttle(struct resource_surface *rsurf)
 }
 
 boolean
+resource_surface_flush_resource(struct resource_surface *rsurf,
+struct native_display *ndpy,
+enum native_attachment which)
+{
+   struct pipe_context *pipe = ndpy_get_copy_context(ndpy);
+
+   if (!pipe)
+  return FALSE;
+
+   pipe-flush_resource(pipe, rsurf-resources[which]);
+
+   return TRUE;
+}
+
+boolean
 resource_surface_flush(struct resource_surface *rsurf,
   struct native_display *ndpy)
 {
diff --git a/src/gallium/state_trackers/egl/common/native_helper.h 
b/src/gallium/state_trackers/egl/common/native_helper.h
index 4c369a7..0b53b28 100644
--- a/src/gallium/state_trackers/egl/common/native_helper.h
+++ b/src/gallium/state_trackers/egl/common/native_helper.h
@@ -91,6 +91,11 @@ resource_surface_copy_swap(struct resource_surface *rsurf,
 boolean
 resource_surface_throttle(struct resource_surface *rsurf);
 
+boolean
+resource_surface_flush_resource(struct resource_surface *rsurf,
+struct native_display *ndpy,
+enum native_attachment which);
+
 /**
  * Flush pending rendering using the copy context. This function saves a
  * marker for upcoming throttles.
diff --git a/src/gallium/state_trackers/egl/wayland/native_wayland.c 
b/src/gallium/state_trackers/egl/wayland/native_wayland.c
index cfdf4f8..0ab4be6 100644
--- a/src/gallium/state_trackers/egl/wayland/native_wayland.c
+++ b/src/gallium/state_trackers/egl/wayland/native_wayland.c
@@ -259,6 +259,10 @@ wayland_surface_swap_buffers(struct native_surface *nsurf)
if (ret == -1)
   return EGL_FALSE;
 
+   (void) resource_surface_flush_resource(surface-rsurf, display-base,
+  NATIVE_ATTACHMENT_BACK_LEFT);
+   (void) resource_surface_flush(surface-rsurf, display-base);
+
surface-frame_callback = wl_surface_frame(surface-win-surface);
wl_callback_add_listener(surface-frame_callback, frame_listener, surface);
wl_proxy_set_queue((struct wl_proxy *) surface-frame_callback,
-- 
1.8.5.1

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Re: [Mesa-dev] [PATCH] st/egl: Flush resources before presentation

2013-12-26 Thread Marek Olšák 
Reviewed-by: Marek Olšák marek.ol...@amd.com

Marek

On Thu, Dec 26, 2013 at 10:33 AM, Martin Andersson g02ma...@gmail.com wrote:
 Fixes wayland regression on r600g due to fast clear introduced by commit
 edbbfac6.
 ---
  src/gallium/state_trackers/egl/common/native_helper.c   | 15 +++
  src/gallium/state_trackers/egl/common/native_helper.h   |  5 +
  src/gallium/state_trackers/egl/wayland/native_wayland.c |  4 
  3 files changed, 24 insertions(+)

 diff --git a/src/gallium/state_trackers/egl/common/native_helper.c 
 b/src/gallium/state_trackers/egl/common/native_helper.c
 index 4a77a50..856cbb6 100644
 --- a/src/gallium/state_trackers/egl/common/native_helper.c
 +++ b/src/gallium/state_trackers/egl/common/native_helper.c
 @@ -341,6 +341,21 @@ resource_surface_throttle(struct resource_surface *rsurf)
  }

  boolean
 +resource_surface_flush_resource(struct resource_surface *rsurf,
 +struct native_display *ndpy,
 +enum native_attachment which)
 +{
 +   struct pipe_context *pipe = ndpy_get_copy_context(ndpy);
 +
 +   if (!pipe)
 +  return FALSE;
 +
 +   pipe-flush_resource(pipe, rsurf-resources[which]);
 +
 +   return TRUE;
 +}
 +
 +boolean
  resource_surface_flush(struct resource_surface *rsurf,
struct native_display *ndpy)
  {
 diff --git a/src/gallium/state_trackers/egl/common/native_helper.h 
 b/src/gallium/state_trackers/egl/common/native_helper.h
 index 4c369a7..0b53b28 100644
 --- a/src/gallium/state_trackers/egl/common/native_helper.h
 +++ b/src/gallium/state_trackers/egl/common/native_helper.h
 @@ -91,6 +91,11 @@ resource_surface_copy_swap(struct resource_surface *rsurf,
  boolean
  resource_surface_throttle(struct resource_surface *rsurf);

 +boolean
 +resource_surface_flush_resource(struct resource_surface *rsurf,
 +struct native_display *ndpy,
 +enum native_attachment which);
 +
  /**
   * Flush pending rendering using the copy context. This function saves a
   * marker for upcoming throttles.
 diff --git a/src/gallium/state_trackers/egl/wayland/native_wayland.c 
 b/src/gallium/state_trackers/egl/wayland/native_wayland.c
 index cfdf4f8..0ab4be6 100644
 --- a/src/gallium/state_trackers/egl/wayland/native_wayland.c
 +++ b/src/gallium/state_trackers/egl/wayland/native_wayland.c
 @@ -259,6 +259,10 @@ wayland_surface_swap_buffers(struct native_surface 
 *nsurf)
 if (ret == -1)
return EGL_FALSE;

 +   (void) resource_surface_flush_resource(surface-rsurf, display-base,
 +  NATIVE_ATTACHMENT_BACK_LEFT);
 +   (void) resource_surface_flush(surface-rsurf, display-base);
 +
 surface-frame_callback = wl_surface_frame(surface-win-surface);
 wl_callback_add_listener(surface-frame_callback, frame_listener, 
 surface);
 wl_proxy_set_queue((struct wl_proxy *) surface-frame_callback,
 --
 1.8.5.1

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Re: [Mesa-dev] [PATCH 13/16] i965/fs: Add a saturation propagation optimization pass.

2013-12-26 Thread Pohjolainen, Topi 
On Thu, Dec 19, 2013 at 01:40:27PM -0800, Matt Turner wrote:
 Transforms, for example,
 
 mul vgrf3, vgrf2, vgrf1
 mov.sat vgrf4, vgrf3
 
 into
 
 mul.sat vgrf3, vgrf2, vgrf1
 mov vgrf4, vgrf3
 
 which gives register_coalescing an opportunity to remove the MOV
 instruction.
 
 total instructions in shared programs: 1512588 - 1501297 (-0.75%)
 instructions in affected programs: 723097 - 711806 (-1.56%)
 GAINED:0
 LOST:  4
 ---
  src/mesa/drivers/dri/i965/Makefile.sources |   1 +
  src/mesa/drivers/dri/i965/brw_fs.cpp   |   1 +
  src/mesa/drivers/dri/i965/brw_fs.h |   1 +
  .../dri/i965/brw_fs_saturate_propagation.cpp   | 102 
 +
  4 files changed, 105 insertions(+)
  create mode 100644 src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
 
 diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
 b/src/mesa/drivers/dri/i965/Makefile.sources
 index 36d8261..3f901da 100644
 --- a/src/mesa/drivers/dri/i965/Makefile.sources
 +++ b/src/mesa/drivers/dri/i965/Makefile.sources
 @@ -62,6 +62,7 @@ i965_FILES = \
   brw_fs_live_variables.cpp \
   brw_fs_peephole_predicated_break.cpp \
   brw_fs_reg_allocate.cpp \
 + brw_fs_saturate_propagation.cpp \
   brw_fs_sel_peephole.cpp \
   brw_fs_value_numbering.cpp \
   brw_fs_vector_splitting.cpp \
 diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs.cpp
 index 08837da..12b6d4a 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
 +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
 @@ -3304,6 +3304,7 @@ fs_visitor::run()
   progress = opt_peephole_sel() || progress;
   progress = dead_control_flow_eliminate(this) || progress;
   vn_progress = opt_value_numbering();
 + progress = opt_saturate_propagation() || progress;
   progress = register_coalesce() || progress;
progress = compute_to_mrf() || progress;
  
 diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
 b/src/mesa/drivers/dri/i965/brw_fs.h
 index 75de18e..07360ae 100644
 --- a/src/mesa/drivers/dri/i965/brw_fs.h
 +++ b/src/mesa/drivers/dri/i965/brw_fs.h
 @@ -368,6 +368,7 @@ public:
 void try_replace_with_sel();
 bool opt_peephole_sel();
 bool opt_peephole_predicated_break();
 +   bool opt_saturate_propagation();
 void emit_bool_to_cond_code(ir_rvalue *condition);
 void emit_if_gen6(ir_if *ir);
 void emit_unspill(fs_inst *inst, fs_reg reg, uint32_t spill_offset,
 diff --git a/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp 
 b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
 new file mode 100644
 index 000..91a1338
 --- /dev/null
 +++ b/src/mesa/drivers/dri/i965/brw_fs_saturate_propagation.cpp
 @@ -0,0 +1,102 @@
 +/*
 + * Copyright © 2013 Intel Corporation
 + *
 + * Permission is hereby granted, free of charge, to any person obtaining a
 + * copy of this software and associated documentation files (the Software),
 + * to deal in the Software without restriction, including without limitation
 + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 + * and/or sell copies of the Software, and to permit persons to whom the
 + * Software is furnished to do so, subject to the following conditions:
 + *
 + * The above copyright notice and this permission notice (including the next
 + * paragraph) shall be included in all copies or substantial portions of the
 + * Software.
 + *
 + * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
 DEALINGS
 + * IN THE SOFTWARE.
 + */
 +
 +#include brw_fs.h
 +#include brw_fs_live_variables.h
 +#include brw_cfg.h
 +
 +/** @file brw_fs_saturate_propagation.cpp
 + */
 +
 +static bool
 +opt_saturate_propagation_local(fs_visitor *v, bblock_t *block)
 +{
 +   bool progress = false;
 +   int ip = block-start_ip;
 +
 +   for (fs_inst *inst = (fs_inst *)block-start;
 +inst != block-end-next;
 +inst = (fs_inst *) inst-next) {
 +  ip++;
 +
 +  if (inst-opcode != BRW_OPCODE_MOV ||
 +  inst-dst.file != GRF ||
 +  !inst-saturate)
 + continue;
 +
 +  int src_var = v-live_intervals-var_from_reg(inst-src[0]);
 +  int src_end_ip = v-live_intervals-end[src_var];
 +  if (src_end_ip  ip  !inst-dst.equals(inst-src[0]))
 + continue;
 +
 +  int scan_ip = ip;
 +  bool interfered = false;
 +  for (fs_inst *scan_inst = (fs_inst *) inst-prev;
 +   scan_inst != block-start-prev;
 +   scan_inst = (fs_inst *)

[Mesa-dev] [PATCH] mesa/st: expose ARB_texture_rgb10_a2ui if R10G10B10A2_UINT is supported v2

2013-12-26 Thread Christoph Bumiller 
---
 src/mesa/state_tracker/st_extensions.c | 4 +++-
 src/mesa/state_tracker/st_format.c | 6 +-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 5e4a3b3..8c49e54 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -419,7 +419,9 @@ void st_init_extensions(struct st_context *st)
   PIPE_FORMAT_R16G16B16A16_FLOAT } },
 
   { { o(ARB_texture_rgb10_a2ui) },
-{ PIPE_FORMAT_B10G10R10A2_UINT } },
+{ PIPE_FORMAT_R10G10B10A2_UINT,
+  PIPE_FORMAT_B10G10R10A2_UINT },
+ GL_TRUE }, /* at least one format must be supported */
 
   { { o(EXT_framebuffer_sRGB) },
 { PIPE_FORMAT_A8B8G8R8_SRGB,
diff --git a/src/mesa/state_tracker/st_format.c 
b/src/mesa/state_tracker/st_format.c
index 6acf983..320d3d4 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -359,6 +359,8 @@ st_mesa_format_to_pipe_format(gl_format mesaFormat)
   return PIPE_FORMAT_R11G11B10_FLOAT;
case MESA_FORMAT_ARGB2101010_UINT:
   return PIPE_FORMAT_B10G10R10A2_UINT;
+   case MESA_FORMAT_ABGR2101010_UINT:
+  return PIPE_FORMAT_R10G10B10A2_UINT;
 
case MESA_FORMAT_XRGB_UNORM:
   return PIPE_FORMAT_B4G4R4X4_UNORM;
@@ -712,6 +714,8 @@ st_pipe_format_to_mesa_format(enum pipe_format format)
 
case PIPE_FORMAT_B10G10R10A2_UINT:
   return MESA_FORMAT_ARGB2101010_UINT;
+   case PIPE_FORMAT_R10G10B10A2_UINT:
+  return MESA_FORMAT_ABGR2101010_UINT;
 
case PIPE_FORMAT_B4G4R4X4_UNORM:
   return MESA_FORMAT_XRGB_UNORM;
@@ -1483,7 +1487,7 @@ static const struct format_mapping format_map[] = {
},
{
   { GL_RGB10_A2UI, 0 },
-  { PIPE_FORMAT_B10G10R10A2_UINT, 0 }
+  { PIPE_FORMAT_R10G10B10A2_UINT, PIPE_FORMAT_B10G10R10A2_UINT, 0 }
},
 };
 
-- 
1.8.1.5

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[Mesa-dev] [Bug 70766] Run-time link error in swrast_dri.so

2013-12-26 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=70766

Jan Vesely jano.ves...@gmail.com changed:

   What|Removed |Added

   See Also||http://llvm.org/bugs/show_b
   ||ug.cgi?id=14200

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You are the assignee for the bug.
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Re: [Mesa-dev] [PATCH] i965: Avoid extraneous fast depth clears

2013-12-26 Thread Chad Versace 

On 12/10/2013 09:54 PM, Chia-I Wu wrote:

When the depth buffer is already cleared, skip GEN6_HIZ_OP_DEPTH_CLEAR.  This
is made possible by tracking which slices have been cleared in
struct intel_mipmap_level.  The hiz_cleared flag is unset when the depth
buffer is rendered to or when a HiZ resolve is needed.

For Unigine Tropics, the FPS improvement is 1.32134% +/- 0.161878% (n=13).


The code looks correct to me, and the perf improvement is nice. I have
comments below that should improve the maintainability of the affected
codepaths.


---
  src/mesa/drivers/dri/i965/brw_blorp_blit.cpp  |  1 +
  src/mesa/drivers/dri/i965/brw_clear.c | 58 +--
  src/mesa/drivers/dri/i965/brw_draw.c  | 16 +++-
  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 37 +
  src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 21 ++
  5 files changed, 119 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 51a3bef..d9ec3e9 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -173,6 +173,7 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
 brw_blorp_exec(brw, params);

 intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_layer);
+   intel_miptree_slice_set_hiz_cleared(dst_mt, dst_level, dst_layer, false);


If the miptree slice needs a hiz resolve, then the hiz buffer is not cleared. 
You captured
this invariant by appending ``intel_miptree_slice_set_hiz_cleared(false)`` to 
each occurrence
``intel_miptree_slice_set_needs_hiz_resolve()``.

In effect, this patch introduces the requirement that all calls to 
``intel_miptree_slice_set_needs_hiz_resolve()``
be followed by ``intel_miptree_slice_set_hiz_cleared(false)``. Rather than 
introducing an implicit
requirement, ``intel_miptree_slice_set_needs_hiz_resolve()`` should 
automatically set ``hiz_cleared = false``.


  }

  static void
diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 1cac996..9dfb94a 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -164,34 +164,66 @@ brw_fast_clear_depth(struct gl_context *ctx)
break;
 }

+   unsigned num_layers_cleared = 0;
+   bool clear_all_layers = false;
+
 /* If we're clearing to a new clear value, then we need to resolve any 
clear
  * flags out of the HiZ buffer into the real depth buffer.
  */
 if (mt-depth_clear_value != depth_clear_value) {
intel_miptree_all_slices_resolve_depth(brw, mt);
mt-depth_clear_value = depth_clear_value;
-   }

-   /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
-*
-* If other rendering operations have preceded this clear, a
-*  PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
-*  must be issued before the rectangle primitive used for the depth
-*  buffer clear operation.
-*/
-   intel_batchbuffer_emit_mi_flush(brw);
+  clear_all_layers = true;
+   }

 if (fb-NumLayers  0) {
assert(fb-NumLayers == 
depth_irb-mt-level[depth_irb-mt_level].depth);
for (unsigned layer = 0; layer  fb-NumLayers; layer++) {
- intel_hiz_exec(brw, mt, depth_irb-mt_level, layer,
-GEN6_HIZ_OP_DEPTH_CLEAR);
+ if (clear_all_layers ||
+ !intel_miptree_slice_get_hiz_cleared(mt,
+  depth_irb-mt_level,
+  layer)) {
+/* From the Sandy Bridge PRM, volume 2 part 1, page 313:
+ *
+ * If other rendering operations have preceded this clear, a
+ *  PIPE_CONTROL with write cache flush enabled and Z-inhibit
+ *  disabled must be issued before the rectangle primitive used
+ *  for the depth buffer clear operation.
+ */
+if (!num_layers_cleared)

   
This is an integer, not a boolean, and therefore ``num_layers_cleared == 0`` is 
more
readable.


+   intel_batchbuffer_emit_mi_flush(brw);
+
+intel_hiz_exec(brw, mt, depth_irb-mt_level, layer,
+   GEN6_HIZ_OP_DEPTH_CLEAR);
+
+intel_miptree_slice_set_hiz_cleared(mt,
+depth_irb-mt_level,
+layer,
+true);
+num_layers_cleared++;
+ }
}
 } else {
-  intel_hiz_exec(brw, mt, depth_irb-mt_level, depth_irb-mt_layer,
- GEN6_HIZ_OP_DEPTH_CLEAR);
+  if (clear_all_layers ||
+  !intel_miptree_slice_get_hiz_cleared(mt,
+   depth_irb-mt_level,
+

Re: [Mesa-dev] [PATCH] mesa: rename MESA format names to have the same names as PIPE formats

2013-12-26 Thread Michel Dänzer 
On Mit, 2013-12-25 at 20:35 -0800, Mark Mueller wrote:

 On Wed, Dec 25, 2013 at 7:25 PM, Michel Dänzer mic...@daenzer.net
 wrote:
 On Mit, 2013-12-25 at 15:19 -0800, Mark Mueller wrote:
 
  --Format Base Type P: Packed  --
  MESA_FORMAT_[[component list,bit width][storage
 type*][_]][_][storage
  type**]
   * when type differs between component
   ** when type applies to all components
 
 
  examples:
  MESA_FORMAT_R5G6B5_UNORM  /*  RGGG GGGB 
 */
 
  MESA_FORMAT_B4G4R4X4_UNORM  /*    
 */
 
 This is slightly confusing in that the PIPE_FORMATs use this
 convention
 for naming the components of 'array' formats, packed formats
 use
 BGRX (just like packed MESA_FORMATs do now). Beware that
 not all
 PIPE_FORMATs have been updated yet according to that
 distinction.
 
 Is this what you are suggesting then?
 
 
 --Format Base Type P: Packed  --
 MESA_FORMAT_[[component list][bit width per component]_[storage
 type*]][_][storage type**]
  * when type differs between component
  ** when type applies to all components
 
 
 examples: 
 MESA_FORMAT_RGB565_UNORM  /*  RGGG GGGB  */
 MESA_FORMAT_BGRX_UNORM  /*     */
 MESA_FORMAT_Z32_FLOAT_SX824_UINT
 MESA_FORMAT_RGBA1010102_UINT
 MESA_FORMAT_RGBE9995_FLOAT

That would be more consistent with the current PIPE_FORMAT naming
convention, but some of the component size sequences look a bit weird,
your original proposal actually makes more sense for those...


 I'm afraid there also needs to be a way to encode endianness,
 either
 explicitly or via something like _REV to indicate the inverse
 byte order
 of the host byte order. This would apply to the packed values
 as a whole
 and to any multi-byte components of array formats.
 
 
 I have seen the gallium discussion on this. Since my current focus is
 i965, I'm safely immune from big endian problems and I'm not aware of
 the details around the issue. Is it not sufficient to maintain a flag
 within the individual texture object or image, or a global flag per
 context to indicate host big endianess?

Maybe? Hard to be sure without actually trying it and working out all
the issues.


-- 
Earthling Michel Dänzer|  http://www.amd.com
Libre software enthusiast  |Mesa and X developer

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Re: [Mesa-dev] [PATCH] mesa: rename MESA format names to have the same names as PIPE formats

2013-12-26 Thread Mark Mueller 
On Thu, Dec 26, 2013 at 6:57 PM, Michel Dänzer mic...@daenzer.net wrote:

 On Mit, 2013-12-25 at 20:35 -0800, Mark Mueller wrote:

  On Wed, Dec 25, 2013 at 7:25 PM, Michel Dänzer mic...@daenzer.net
  wrote:
  On Mit, 2013-12-25 at 15:19 -0800, Mark Mueller wrote:
  
   --Format Base Type P: Packed  --
   MESA_FORMAT_[[component list,bit width][storage
  type*][_]][_][storage
   type**]
* when type differs between component
** when type applies to all components
  
  
   examples:
   MESA_FORMAT_R5G6B5_UNORM  /*  RGGG GGGB 
  */
  
   MESA_FORMAT_B4G4R4X4_UNORM  /*    
  */
 
  This is slightly confusing in that the PIPE_FORMATs use this
  convention
  for naming the components of 'array' formats, packed formats
  use
  BGRX (just like packed MESA_FORMATs do now). Beware that
  not all
  PIPE_FORMATs have been updated yet according to that
  distinction.
 
  Is this what you are suggesting then?
 
 
  --Format Base Type P: Packed  --
  MESA_FORMAT_[[component list][bit width per component]_[storage
  type*]][_][storage type**]
   * when type differs between component
   ** when type applies to all components
 
 
  examples:
  MESA_FORMAT_RGB565_UNORM  /*  RGGG GGGB  */
  MESA_FORMAT_BGRX_UNORM  /*     */
  MESA_FORMAT_Z32_FLOAT_SX824_UINT
  MESA_FORMAT_RGBA1010102_UINT
  MESA_FORMAT_RGBE9995_FLOAT

 That would be more consistent with the current PIPE_FORMAT naming
 convention, but some of the component size sequences look a bit weird,
 your original proposal actually makes more sense for those...

 Sorry, I'm not sure which original proposal you are referring to, could
you be more specific? My concern about this latest iteration is that the
delimiter between bit widths per component isn't distinct, though it's
generally intuitive, whereas a component followed by a bit width gives a
clearer association.


  I'm afraid there also needs to be a way to encode endianness,
  either
  explicitly or via something like _REV to indicate the inverse
  byte order
  of the host byte order. This would apply to the packed values
  as a whole
  and to any multi-byte components of array formats.
 
 
  I have seen the gallium discussion on this. Since my current focus is
  i965, I'm safely immune from big endian problems and I'm not aware of
  the details around the issue. Is it not sufficient to maintain a flag
  within the individual texture object or image, or a global flag per
  context to indicate host big endianess?

 Maybe? Hard to be sure without actually trying it and working out all
 the issues.


Since the endianess issue is still in flux, and the format naming work
doesn't offer a silver bullet, my recommendation is to solve the two
problems independently. Thus I can produce a new set of patches based on
the naming spec tomorrow for another round or review.

Mark



 --
 Earthling Michel Dänzer|  http://www.amd.com
 Libre software enthusiast  |Mesa and X developer


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