[Mesa-dev] [PATCH] glsl: Allow explicit binding on atomics again
As of 943b2d52bf5, layout(binding) on an atomic would fail the assertion
here.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
Cc: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/link_uniform_initializers.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/link_uniform_initializers.cpp
b/src/glsl/link_uniform_initializers.cpp
index e60bb64..2100e05 100644
--- a/src/glsl/link_uniform_initializers.cpp
+++ b/src/glsl/link_uniform_initializers.cpp
@@ -296,8 +296,10 @@ link_set_uniform_initializers(struct gl_shader_program
*prog)
linker::set_block_binding(prog, iface_type-name,
var-data.binding);
}
+} else if (type-contains_atomic()) {
+ /* we don't actually need to do anything. */
} else {
- assert(!Explicit binding not on a sampler or UBO.);
+ assert(!Explicit binding not on a sampler, UBO or atomic.);
}
} else if (var-constant_value) {
linker::set_uniform_initializer(mem_ctx, prog, var-name,
--
1.9.2
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Re: [Mesa-dev] [PATCH] winsys/radeon: consolidate hash table lookup
Am 11.04.2014 19:03, schrieb Marek Olšák:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
BTW:
I've always wondered if the custom hash table is the best approach here.
Having a BO active in more than one command submission context at the
same time sounds rather unlikely to me.
Something like storing a pointer to the last used CS and it's index in
the BO and only when a BO is really used in more than one CS context at
the same time fall back to the hashtable and lockup the index from there
sounds like less overhead.
I should have done this long ago.
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 110 +++---
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 7 +-
2 files changed, 49 insertions(+), 68 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index db9fbfa..b55eb80 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -188,41 +188,40 @@ static INLINE void update_reloc(struct
drm_radeon_cs_reloc *reloc,
reloc-flags = MAX2(reloc-flags, priority);
}
-int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo)
+int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo,
+ struct drm_radeon_cs_reloc **out_reloc)
{
-struct drm_radeon_cs_reloc *reloc;
-unsigned i;
+struct drm_radeon_cs_reloc *reloc = NULL;
unsigned hash = bo-handle (sizeof(csc-is_handle_added)-1);
+int i = -1;
if (csc-is_handle_added[hash]) {
i = csc-reloc_indices_hashlist[hash];
reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-return i;
-}
-/* Hash collision, look for the BO in the list of relocs linearly. */
-for (i = csc-crelocs; i != 0;) {
---i;
-reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-/* Put this reloc in the hash list.
- * This will prevent additional hash collisions if there are
- * several consecutive get_reloc calls for the same buffer.
- *
- * Example: Assuming buffers A,B,C collide in the hash list,
- * the following sequence of relocs:
- * AAABB
- * will collide here: ^ and here: ^,
- * meaning that we should get very few collisions in the end.
*/
-csc-reloc_indices_hashlist[hash] = i;
-/*printf(write_reloc collision, hash: %i, handle: %i\n, hash,
bo-handle);*/
-return i;
+if (reloc-handle != bo-handle) {
+/* Hash collision, look for the BO in the list of relocs linearly.
*/
+for (i = csc-crelocs - 1; i = 0; i--) {
+reloc = csc-relocs[i];
+if (reloc-handle == bo-handle) {
+/* Put this reloc in the hash list.
+ * This will prevent additional hash collisions if there
are
+ * several consecutive get_reloc calls for the same buffer.
+ *
+ * Example: Assuming buffers A,B,C collide in the hash
list,
+ * the following sequence of relocs:
+ * AAABB
+ * will collide here: ^ and here: ^,
+ * meaning that we should get very few collisions in the
end. */
+csc-reloc_indices_hashlist[hash] = i;
+break;
+}
}
}
}
-
-return -1;
+if (out_reloc)
+*out_reloc = reloc;
+return i;
}
static unsigned radeon_add_reloc(struct radeon_drm_cs *cs,
@@ -237,45 +236,28 @@ static unsigned radeon_add_reloc(struct radeon_drm_cs *cs,
unsigned hash = bo-handle (sizeof(csc-is_handle_added)-1);
enum radeon_bo_domain rd = usage RADEON_USAGE_READ ? domains : 0;
enum radeon_bo_domain wd = usage RADEON_USAGE_WRITE ? domains : 0;
-bool update_hash = TRUE;
-int i;
+int i = -1;
priority = MIN2(priority, 15);
*added_domains = 0;
-if (csc-is_handle_added[hash]) {
-i = csc-reloc_indices_hashlist[hash];
-reloc = csc-relocs[i];
-
-if (reloc-handle != bo-handle) {
-/* Hash collision, look for the BO in the list of relocs linearly.
*/
-for (i = csc-crelocs - 1; i = 0; i--) {
-reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-/*printf(write_reloc collision, hash: %i, handle: %i\n,
hash, bo-handle);*/
-break;
-}
-}
-}
-
-if (i = 0) {
-update_reloc(reloc, rd, wd, priority,
Re: [Mesa-dev] Mesa build instructions
On Fri, 11 Apr 2014 11:50:50 -0700 Eric Anholt e...@anholt.net wrote: For anyone that's curious about how I work: My scripts setup looks a lot like Matt's. I don't do OOT builds, and instead I just have 6 main trees: ~/src/mesa (normal debug build) ~/src/mesa-release (non-debug build) ~/src/mesa-clean (usually HEAD~1 of ~/src/mesa) ~/src/32/mesa ~/src/32/mesa-release ~/src/32/mesa-clean The debug build also is with -O2 so that I can actually get mostly-representative performance results while developing. REALLY IMPORTANT: Don't forget -fno-omit-frame-pointer on 64-bit, otherwise you won't get backtraces from sysprof and perf (similarly, in your kernel, CONFIG_FRAME_POINTER=y). I think the most important feature of my setup is the clean builds. By having copies of unmodified mesa along with patched mesa, I can use http://anholt.net/compare-perf/ to easily produce stats to test whether my change is actually having the desired effect. Hi Eric, just curious, how have you set up git here? Do you have a .git/ completely separate in each directory, and if so, how do you keep them synced? Or do you use some GIT_DIR env magic to have a single git repo with multiple checkouts? Thanks, pq ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] mesa: Consider gl_VertexID and gl_InstanceID active attribs
Fixes piglit's spec/gl-3.2/get-active-attrib-returns-all-inputs.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/shader_query.cpp | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index c6e7342..2be84f2 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -85,6 +85,15 @@ is_active_attrib(const ir_variable *var) {
case ir_var_shader_in:
return var-data.location != -1;
+ case ir_var_system_value:
+ /* From GL 4.3 core spec, section 11.1.1 (Vertex Attributes):
+ * For GetActiveAttrib, all active vertex shader input variables
+ * are enumerated, including the special built-in inputs gl_VertexID
+ * and gl_InstanceID.
+ */
+ return !strcmp(var-name, gl_VertexID) ||
+ !strcmp(var-name, gl_InstanceID);
+
default:
return false;
}
--
1.9.2
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[Mesa-dev] [PATCH 1/2] mesa: Extract is_active_attrib() in shaderapi
The rules are about to get a bit more complex to account for
gl_InstanceID and gl_VertexID, which are system values.
Extracting this first avoids introducing duplication.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/shader_query.cpp | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index e1afe53..c6e7342 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -76,6 +76,20 @@ _mesa_BindAttribLocation(GLhandleARB program, GLuint index,
*/
}
+static bool
+is_active_attrib(const ir_variable *var) {
+ if (!var)
+ return false;
+
+ switch (var-data.mode) {
+ case ir_var_shader_in:
+ return var-data.location != -1;
+
+ default:
+ return false;
+ }
+}
+
void GLAPIENTRY
_mesa_GetActiveAttrib(GLhandleARB program, GLuint desired_index,
GLsizei maxLength, GLsizei * length, GLint * size,
@@ -105,10 +119,8 @@ _mesa_GetActiveAttrib(GLhandleARB program, GLuint
desired_index,
foreach_list(node, ir) {
const ir_variable *const var = ((ir_instruction *) node)-as_variable();
- if (var == NULL
- || var-data.mode != ir_var_shader_in
- || var-data.location == -1)
-continue;
+ if (!is_active_attrib(var))
+ continue;
if (current_index == desired_index) {
_mesa_copy_string(name, maxLength, length, var-name);
@@ -196,10 +208,8 @@ _mesa_count_active_attribs(struct gl_shader_program
*shProg)
foreach_list(node, ir) {
const ir_variable *const var = ((ir_instruction *) node)-as_variable();
- if (var == NULL
- || var-data.mode != ir_var_shader_in
- || var-data.location == -1)
-continue;
+ if (!is_active_attrib(var))
+ continue;
i++;
}
--
1.9.2
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[Mesa-dev] [PATCH] i965: Add comment to explain the weird-looking shadow compares.
This always looks crazy when I stumble across it, until I remember
what the hardware is doing. Describing it ought to short-circuit
that process next time :)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_state.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_state.c
b/src/mesa/drivers/dri/i965/intel_state.c
index bfc35d8..1597db6 100644
--- a/src/mesa/drivers/dri/i965/intel_state.c
+++ b/src/mesa/drivers/dri/i965/intel_state.c
@@ -40,6 +40,17 @@
int
intel_translate_shadow_compare_func(GLenum func)
{
+ /* GL specifies the result of shadow comparisons as:
+* 1 if ref op texel,
+* 0 otherwise.
+*
+* The hardware does:
+* 0 if texel op ref,
+* 1 otherwise.
+*
+* So, these look a bit strange because there's both a negation
+* and swapping of the arguments involved.
+*/
switch (func) {
case GL_NEVER:
return BRW_COMPAREFUNCTION_ALWAYS;
@@ -50,11 +61,11 @@ intel_translate_shadow_compare_func(GLenum func)
case GL_GREATER:
return BRW_COMPAREFUNCTION_GEQUAL;
case GL_GEQUAL:
- return BRW_COMPAREFUNCTION_GREATER;
+ return BRW_COMPAREFUNCTION_GREATER;
case GL_NOTEQUAL:
- return BRW_COMPAREFUNCTION_EQUAL;
+ return BRW_COMPAREFUNCTION_EQUAL;
case GL_EQUAL:
- return BRW_COMPAREFUNCTION_NOTEQUAL;
+ return BRW_COMPAREFUNCTION_NOTEQUAL;
case GL_ALWAYS:
return BRW_COMPAREFUNCTION_NEVER;
}
--
1.9.2
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Re: [Mesa-dev] [PATCH] winsys/radeon: consolidate hash table lookup
Do you mean having bo-cs and bo-index? That would work, but there
would have to be mutex_lock and mutex_unlock when accessing the
variables. I'm not sure if locking a mutex is more expensive than the
hash table lookup. OpenGL with GLX allows sharing buffers and textures
between contexts, so we must play safe.
Note that if all handles are less than 512, the lookup is always in
O(1), so it's very cheap. We can increase the number to 1024 or 2048
if we find out that apps use too many buffers.
Marek
On Sat, Apr 12, 2014 at 10:35 AM, Christian König
deathsim...@vodafone.de wrote:
Am 11.04.2014 19:03, schrieb Marek Olšák:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
BTW:
I've always wondered if the custom hash table is the best approach here.
Having a BO active in more than one command submission context at the same
time sounds rather unlikely to me.
Something like storing a pointer to the last used CS and it's index in the
BO and only when a BO is really used in more than one CS context at the same
time fall back to the hashtable and lockup the index from there sounds like
less overhead.
I should have done this long ago.
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 110
+++---
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 7 +-
2 files changed, 49 insertions(+), 68 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index db9fbfa..b55eb80 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -188,41 +188,40 @@ static INLINE void update_reloc(struct
drm_radeon_cs_reloc *reloc,
reloc-flags = MAX2(reloc-flags, priority);
}
-int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo
*bo)
+int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo,
+ struct drm_radeon_cs_reloc **out_reloc)
{
-struct drm_radeon_cs_reloc *reloc;
-unsigned i;
+struct drm_radeon_cs_reloc *reloc = NULL;
unsigned hash = bo-handle (sizeof(csc-is_handle_added)-1);
+int i = -1;
if (csc-is_handle_added[hash]) {
i = csc-reloc_indices_hashlist[hash];
reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-return i;
-}
-/* Hash collision, look for the BO in the list of relocs
linearly. */
-for (i = csc-crelocs; i != 0;) {
---i;
-reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-/* Put this reloc in the hash list.
- * This will prevent additional hash collisions if there
are
- * several consecutive get_reloc calls for the same
buffer.
- *
- * Example: Assuming buffers A,B,C collide in the hash
list,
- * the following sequence of relocs:
- * AAABB
- * will collide here: ^ and here: ^,
- * meaning that we should get very few collisions in the
end. */
-csc-reloc_indices_hashlist[hash] = i;
-/*printf(write_reloc collision, hash: %i, handle: %i\n,
hash, bo-handle);*/
-return i;
+if (reloc-handle != bo-handle) {
+/* Hash collision, look for the BO in the list of relocs
linearly. */
+for (i = csc-crelocs - 1; i = 0; i--) {
+reloc = csc-relocs[i];
+if (reloc-handle == bo-handle) {
+/* Put this reloc in the hash list.
+ * This will prevent additional hash collisions if
there are
+ * several consecutive get_reloc calls for the same
buffer.
+ *
+ * Example: Assuming buffers A,B,C collide in the
hash list,
+ * the following sequence of relocs:
+ * AAABB
+ * will collide here: ^ and here: ^,
+ * meaning that we should get very few collisions in
the end. */
+csc-reloc_indices_hashlist[hash] = i;
+break;
+}
}
}
}
-
-return -1;
+if (out_reloc)
+*out_reloc = reloc;
+return i;
}
static unsigned radeon_add_reloc(struct radeon_drm_cs *cs,
@@ -237,45 +236,28 @@ static unsigned radeon_add_reloc(struct
radeon_drm_cs *cs,
unsigned hash = bo-handle (sizeof(csc-is_handle_added)-1);
enum radeon_bo_domain rd = usage RADEON_USAGE_READ ? domains : 0;
enum radeon_bo_domain wd = usage RADEON_USAGE_WRITE ? domains : 0;
-bool update_hash = TRUE;
-int i;
+int i = -1;
priority = MIN2(priority, 15);
Re: [Mesa-dev] [PATCH] winsys/radeon: consolidate hash table lookup
Am 12.04.2014 12:52, schrieb Marek Olšák:
Do you mean having bo-cs and bo-index? That would work, but there
would have to be mutex_lock and mutex_unlock when accessing the
variables. I'm not sure if locking a mutex is more expensive than the
hash table lookup. OpenGL with GLX allows sharing buffers and textures
between contexts, so we must play safe.
Obviously thread safety must be taken care of. Maybe we could squash CS
identifier and index into a 64bit atomic? If we need to lock a mutex for
every access it would indeed take longer than the hashtable handling.
Note that if all handles are less than 512, the lookup is always in
O(1), so it's very cheap. We can increase the number to 1024 or 2048
if we find out that apps use too many buffers.
Didn't knew that there are so many entries in the hashtable, thought
that we rather get a collision every 32 handles or something like this.
If we have O(1) anyway most of the time than changing it would probably
not make much sense.
Christian.
Marek
On Sat, Apr 12, 2014 at 10:35 AM, Christian König
deathsim...@vodafone.de wrote:
Am 11.04.2014 19:03, schrieb Marek Olšák:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Christian König christian.koe...@amd.com
BTW:
I've always wondered if the custom hash table is the best approach here.
Having a BO active in more than one command submission context at the same
time sounds rather unlikely to me.
Something like storing a pointer to the last used CS and it's index in the
BO and only when a BO is really used in more than one CS context at the same
time fall back to the hashtable and lockup the index from there sounds like
less overhead.
I should have done this long ago.
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 110
+++---
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 7 +-
2 files changed, 49 insertions(+), 68 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index db9fbfa..b55eb80 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -188,41 +188,40 @@ static INLINE void update_reloc(struct
drm_radeon_cs_reloc *reloc,
reloc-flags = MAX2(reloc-flags, priority);
}
-int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo
*bo)
+int radeon_get_reloc(struct radeon_cs_context *csc, struct radeon_bo *bo,
+ struct drm_radeon_cs_reloc **out_reloc)
{
-struct drm_radeon_cs_reloc *reloc;
-unsigned i;
+struct drm_radeon_cs_reloc *reloc = NULL;
unsigned hash = bo-handle (sizeof(csc-is_handle_added)-1);
+int i = -1;
if (csc-is_handle_added[hash]) {
i = csc-reloc_indices_hashlist[hash];
reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-return i;
-}
-/* Hash collision, look for the BO in the list of relocs
linearly. */
-for (i = csc-crelocs; i != 0;) {
---i;
-reloc = csc-relocs[i];
-if (reloc-handle == bo-handle) {
-/* Put this reloc in the hash list.
- * This will prevent additional hash collisions if there
are
- * several consecutive get_reloc calls for the same
buffer.
- *
- * Example: Assuming buffers A,B,C collide in the hash
list,
- * the following sequence of relocs:
- * AAABB
- * will collide here: ^ and here: ^,
- * meaning that we should get very few collisions in the
end. */
-csc-reloc_indices_hashlist[hash] = i;
-/*printf(write_reloc collision, hash: %i, handle: %i\n,
hash, bo-handle);*/
-return i;
+if (reloc-handle != bo-handle) {
+/* Hash collision, look for the BO in the list of relocs
linearly. */
+for (i = csc-crelocs - 1; i = 0; i--) {
+reloc = csc-relocs[i];
+if (reloc-handle == bo-handle) {
+/* Put this reloc in the hash list.
+ * This will prevent additional hash collisions if
there are
+ * several consecutive get_reloc calls for the same
buffer.
+ *
+ * Example: Assuming buffers A,B,C collide in the
hash list,
+ * the following sequence of relocs:
+ * AAABB
+ * will collide here: ^ and here: ^,
+ * meaning that we should get very few collisions in
the end. */
+csc-reloc_indices_hashlist[hash] = i;
+break;
+}
}
}
}
-
-return -1;
+if (out_reloc)
+*out_reloc = reloc;
+return i;
}
static unsigned
[Mesa-dev] [PATCH 0/2] Turning swrast into DRI2 drivers
Hi everyone, Some time ago I sent patches to enable the swrast driver on GBM/DRM, and I did them in the dumbest way possible (that is, having GBM implement the dri-swrast interface), to make sure it would work without kernel support. This patch series is a little smarter, in that it creates more than one KMS buffer and has llvmpipe render directly into the KMS buffer, so we don't need to copy from the back to the shadow (before the kernel copies from the shadow to the front). For background, this is necessary to get mutter-wayland running inside VMs such as gnome-continuous, which has a qxl DRM driver. mutter-wayland only has a KMS/EGL rendering backend, and we have no intention to add pixman or fbdev. GNOME bug: https://bugzilla.gnome.org/show_bug.cgi?id=728059 The older patches were http://lists.freedesktop.org/archives/mesa-dev/2014-March/055113.html I can rebase if so is desired. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] Add a new capabilities for drivers that can't share buffers
From: Giovanni Campagna gcampa...@src.gnome.org
The kms-dri swrast driver cannot share buffers using the GEM,
so it must tell the loader to disable extensions relying on
that, without disabling the image DRI extension altogheter
(which would prevent the loader from working at all).
This requires a new gallium capability (which is queried on
the pipe_screen and for swrast drivers it's forwared to the
winsys), and requires a new version of the DRI image extension.
---
include/GL/internal/dri_interface.h| 15 +
src/egl/drivers/dri2/egl_dri2.c| 10 -
src/egl/drivers/dri2/platform_drm.c| 17 +++---
src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
src/gallium/drivers/i915/i915_screen.c | 1 +
src/gallium/drivers/ilo/ilo_screen.c | 2 ++
src/gallium/drivers/llvmpipe/lp_screen.c | 7 ++
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 +
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 ++
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++
src/gallium/drivers/r300/r300_screen.c | 1 +
src/gallium/drivers/r600/r600_pipe.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
src/gallium/drivers/softpipe/sp_screen.c | 7 ++
src/gallium/drivers/svga/svga_screen.c | 2 ++
src/gallium/include/pipe/p_defines.h | 1 +
src/gallium/include/state_tracker/sw_winsys.h | 5 +
src/gallium/state_trackers/dri/common/dri_screen.h | 1 +
src/gallium/state_trackers/dri/drm/dri2.c | 23 +--
src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 26 +++---
20 files changed, 117 insertions(+), 9 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index d028d05..85d4afa 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1133,6 +1133,13 @@ enum __DRIChromaSiting {
#define __DRI_IMAGE_ERROR_BAD_PARAMETER 3
/*@}*/
+/**
+ * \name Capabilities that might be returned by
__DRIimageExtensionRec::getCapabilities
+ */
+/*@{*/
+#define __DRI_IMAGE_CAP_GLOBAL_NAMES 1
+/*@}*/
+
typedef struct __DRIimageRec __DRIimage;
typedef struct __DRIimageExtensionRec __DRIimageExtension;
struct __DRIimageExtensionRec {
@@ -1239,6 +1246,14 @@ struct __DRIimageExtensionRec {
enum __DRIChromaSiting vert_siting,
unsigned *error,
void *loaderPrivate);
+
+ /**
+* Query for general capabilities of the driver that concern
+* buffer sharing and image importing.
+*
+* \since 9
+*/
+ int (*getCapabilities)(__DRIscreen *screen);
};
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index dc541ad..26f9fd4 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -521,7 +521,15 @@ dri2_setup_screen(_EGLDisplay *disp)
}
if (dri2_dpy-image) {
- disp-Extensions.MESA_drm_image = EGL_TRUE;
+ if (dri2_dpy-image-base.version = 9
+ dri2_dpy-image-getCapabilities != NULL) {
+ int capabilities;
+
+ capabilities = dri2_dpy-image-getCapabilities(dri2_dpy-dri_screen);
+ disp-Extensions.MESA_drm_image = (capabilities
__DRI_IMAGE_CAP_GLOBAL_NAMES) != 0;
+ } else
+ disp-Extensions.MESA_drm_image = EGL_TRUE;
+
disp-Extensions.KHR_image_base = EGL_TRUE;
disp-Extensions.KHR_gl_renderbuffer_image = EGL_TRUE;
if (dri2_dpy-image-base.version = 5
diff --git a/src/egl/drivers/dri2/platform_drm.c
b/src/egl/drivers/dri2/platform_drm.c
index 17b93db..2b79612 100644
--- a/src/egl/drivers/dri2/platform_drm.c
+++ b/src/egl/drivers/dri2/platform_drm.c
@@ -266,7 +266,10 @@ back_bo_to_dri_buffer(struct dri2_egl_surface *dri2_surf,
__DRIbuffer *buffer)
bo = (struct gbm_dri_bo *) dri2_surf-back-bo;
- dri2_dpy-image-queryImage(bo-image, __DRI_IMAGE_ATTRIB_NAME, name);
+ if (dri2_surf-base.Resource.Display-Extensions.MESA_drm_image)
+ dri2_dpy-image-queryImage(bo-image, __DRI_IMAGE_ATTRIB_NAME, name);
+ else
+ dri2_dpy-image-queryImage(bo-image, __DRI_IMAGE_ATTRIB_HANDLE, name);
dri2_dpy-image-queryImage(bo-image, __DRI_IMAGE_ATTRIB_STRIDE, pitch);
buffer-attachment = __DRI_BUFFER_BACK_LEFT;
@@ -719,8 +722,16 @@ dri2_initialize_drm(_EGLDriver *drv, _EGLDisplay *disp)
disp-Extensions.EXT_buffer_age = EGL_TRUE;
#ifdef HAVE_WAYLAND_PLATFORM
- if (dri2_dpy-image)
- disp-Extensions.WL_bind_wayland_display = EGL_TRUE;
+ if (dri2_dpy-image) {
+ if (dri2_dpy-image-base.version = 9
+ dri2_dpy-image-getCapabilities != NULL) {
+ int capabilities;
+
+ capabilities =
dri2_dpy-image-getCapabilities(dri2_dpy-dri_screen);
+
[Mesa-dev] [PATCH 1/2] Add a dumb drm/kms winsys for software rendering
From: Giovanni Campagna gcampa...@src.gnome.org Add a new winsys and target that can be used with a dri2 state tracker and loader instead of drisw. This allows to use gbm as a dri2/image loader and avoid the extra copy from the backbuffer to the shadow frontbuffer. --- configure.ac | 4 +- src/gallium/targets/Makefile.am | 2 +- src/gallium/targets/dri-swrast2/Makefile.am | 72 + src/gallium/targets/dri-swrast2/swrast2_drm_api.c | 65 + src/gallium/winsys/Makefile.am| 2 +- src/gallium/winsys/sw/kms-dri/Makefile.am | 33 +++ src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c | 310 ++ src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.h | 37 +++ 8 files changed, 522 insertions(+), 3 deletions(-) create mode 100644 src/gallium/targets/dri-swrast2/Makefile.am create mode 100644 src/gallium/targets/dri-swrast2/swrast2_drm_api.c create mode 100644 src/gallium/winsys/sw/kms-dri/Makefile.am create mode 100644 src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.c create mode 100644 src/gallium/winsys/sw/kms-dri/kms_dri_sw_winsys.h diff --git a/configure.ac b/configure.ac index c71fa26..7179abd 100644 --- a/configure.ac +++ b/configure.ac @@ -1857,7 +1857,7 @@ if test -n $with_gallium_drivers; then fi if test x$enable_dri = xyes; then -GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS dri-swrast +GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS dri-swrast dri-swrast2 fi ;; *) @@ -2073,6 +2073,7 @@ AC_CONFIG_FILES([Makefile src/gallium/targets/dri-ilo/Makefile src/gallium/targets/dri-nouveau/Makefile src/gallium/targets/dri-swrast/Makefile + src/gallium/targets/dri-swrast2/Makefile src/gallium/targets/dri-vmwgfx/Makefile src/gallium/targets/egl-static/Makefile src/gallium/targets/gbm/Makefile @@ -2103,6 +2104,7 @@ AC_CONFIG_FILES([Makefile src/gallium/winsys/nouveau/drm/Makefile src/gallium/winsys/radeon/drm/Makefile src/gallium/winsys/svga/drm/Makefile + src/gallium/winsys/sw/kms-dri/Makefile src/gallium/winsys/sw/dri/Makefile src/gallium/winsys/sw/fbdev/Makefile src/gallium/winsys/sw/null/Makefile diff --git a/src/gallium/targets/Makefile.am b/src/gallium/targets/Makefile.am index 871b31d..475962b 100644 --- a/src/gallium/targets/Makefile.am +++ b/src/gallium/targets/Makefile.am @@ -120,7 +120,7 @@ endif if HAVE_GALLIUM_SOFTPIPE if HAVE_DRI -SUBDIRS += dri-swrast +SUBDIRS += dri-swrast dri-swrast2 endif endif diff --git a/src/gallium/targets/dri-swrast2/Makefile.am b/src/gallium/targets/dri-swrast2/Makefile.am new file mode 100644 index 000..d22ec82 --- /dev/null +++ b/src/gallium/targets/dri-swrast2/Makefile.am @@ -0,0 +1,72 @@ +# Copyright © 2012 Intel Corporation +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, +# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +# NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT +# HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +# DEALINGS IN THE SOFTWARE. + +include $(top_srcdir)/src/gallium/Automake.inc + +AM_CFLAGS = \ + $(GALLIUM_CFLAGS) \ + $(PTHREAD_CFLAGS) \ + $(LIBDRM_CFLAGS) +AM_CPPFLAGS = \ + -I$(top_srcdir)/src/gallium/winsys/sw/kms-dri \ + -I$(top_srcdir)/src/gallium/drivers \ + -I$(top_srcdir)/src/gallium/winsys \ + -I$(top_srcdir)/src/mesa \ + -I$(top_srcdir)/src/mapi \ + -DGALLIUM_RBUG \ + -DGALLIUM_TRACE \ + -DGALLIUM_SOFTPIPE + +dridir = $(DRI_DRIVER_INSTALL_DIR) +dri_LTLIBRARIES = swrast_dri2_dri.la + +swrast_dri2_dri_la_SOURCES = \ + swrast2_drm_api.c \ + $(top_srcdir)/src/mesa/drivers/dri/common/utils.c \ + $(top_srcdir)/src/mesa/drivers/dri/common/dri_util.c \ + $(top_srcdir)/src/mesa/drivers/dri/common/xmlconfig.c + +swrast_dri2_dri_la_LDFLAGS = -module -avoid-version
[Mesa-dev] [PATCH 02/10] r600g: remove redundant r600_flush_from_winsys
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_pipe.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index c037662..6b2fcaf 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -120,13 +120,6 @@ static void r600_flush_gfx_ring(void *ctx, unsigned flags)
r600_flush((struct pipe_context*)ctx, flags);
}
-static void r600_flush_from_winsys(void *ctx, unsigned flags)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
-
- rctx-b.rings.gfx.flush(rctx, flags);
-}
-
static void r600_destroy_context(struct pipe_context *context)
{
struct r600_context *rctx = (struct r600_context *)context;
@@ -244,7 +237,7 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
rctx-b.rings.gfx.cs = rctx-b.ws-cs_create(rctx-b.ws,
RING_GFX, NULL);
}
rctx-b.rings.gfx.flush = r600_flush_gfx_ring;
- rctx-b.ws-cs_set_flush_callback(rctx-b.rings.gfx.cs,
r600_flush_from_winsys, rctx);
+ rctx-b.ws-cs_set_flush_callback(rctx-b.rings.gfx.cs,
r600_flush_gfx_ring, rctx);
rctx-b.rings.gfx.flushing = false;
rctx-allocator_fetch_shader = u_suballocator_create(rctx-b.b, 64 *
1024, 256,
--
1.8.3.2
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[Mesa-dev] [PATCH 09/10] r600g,radeonsi: share r600_flush_from_st
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_pipe.c | 17 -
src/gallium/drivers/radeon/r600_pipe_common.c | 17 +
src/gallium/drivers/radeonsi/si_pipe.c| 17 -
3 files changed, 17 insertions(+), 34 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 983c65a..3797b56b 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -66,22 +66,6 @@ static const struct debug_named_value r600_debug_options[] =
{
* pipe_context
*/
-static void r600_flush_from_st(struct pipe_context *ctx,
- struct pipe_fence_handle **fence,
- unsigned flags)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- unsigned fflags;
-
- fflags = flags PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME :
0;
-
- /* flush gfx dma ring, order does not matter as only one can be live
*/
- if (rctx-b.rings.dma.cs) {
- rctx-b.rings.dma.flush(rctx, fflags, NULL);
- }
- rctx-b.rings.gfx.flush(rctx, fflags, fence);
-}
-
static void r600_destroy_context(struct pipe_context *context)
{
struct r600_context *rctx = (struct r600_context *)context;
@@ -137,7 +121,6 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
rctx-b.b.screen = screen;
rctx-b.b.priv = priv;
rctx-b.b.destroy = r600_destroy_context;
- rctx-b.b.flush = r600_flush_from_st;
if (!r600_common_context_init(rctx-b, rscreen-b))
goto fail;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index bc48388..3a0d981 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -53,6 +53,22 @@ static void r600_memory_barrier(struct pipe_context *ctx,
unsigned flags)
{
}
+static void r600_flush_from_st(struct pipe_context *ctx,
+ struct pipe_fence_handle **fence,
+ unsigned flags)
+{
+ struct r600_common_context *rctx = (struct r600_common_context *)ctx;
+ unsigned rflags = 0;
+
+ if (flags PIPE_FLUSH_END_OF_FRAME)
+ rflags |= RADEON_FLUSH_END_OF_FRAME;
+
+ if (rctx-rings.dma.cs) {
+ rctx-rings.dma.flush(rctx, rflags, NULL);
+ }
+ rctx-rings.gfx.flush(rctx, rflags, fence);
+}
+
static void r600_flush_dma_ring(void *ctx, unsigned flags,
struct pipe_fence_handle **fence)
{
@@ -86,6 +102,7 @@ bool r600_common_context_init(struct r600_common_context
*rctx,
rctx-b.transfer_unmap = u_transfer_unmap_vtbl;
rctx-b.transfer_inline_write = u_default_transfer_inline_write;
rctx-b.memory_barrier = r600_memory_barrier;
+ rctx-b.flush = r600_flush_from_st;
r600_init_context_texture_functions(rctx);
r600_streamout_init(rctx);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 7f3b0c2..a1aea7b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -33,22 +33,6 @@
/*
* pipe_context
*/
-static void si_flush_from_st(struct pipe_context *ctx,
-struct pipe_fence_handle **fence,
-unsigned flags)
-{
- struct si_context *sctx = (struct si_context *)ctx;
- unsigned rflags = 0;
-
- if (flags PIPE_FLUSH_END_OF_FRAME)
- rflags |= RADEON_FLUSH_END_OF_FRAME;
-
- if (sctx-b.rings.dma.cs) {
- sctx-b.rings.dma.flush(sctx, rflags, NULL);
- }
- sctx-b.rings.gfx.flush(sctx, rflags, fence);
-}
-
static void si_destroy_context(struct pipe_context *context)
{
struct si_context *sctx = (struct si_context *)context;
@@ -97,7 +81,6 @@ static struct pipe_context *si_create_context(struct
pipe_screen *screen, void *
sctx-b.b.screen = screen; /* this must be set first */
sctx-b.b.priv = priv;
sctx-b.b.destroy = si_destroy_context;
- sctx-b.b.flush = si_flush_from_st;
sctx-screen = sscreen; /* Easy accessing of screen/winsys. */
if (!r600_common_context_init(sctx-b, sscreen-b))
--
1.8.3.2
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[Mesa-dev] [PATCH 04/10] winsys/radeon: fold cs_set_flush_callback into cs_create
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r300/r300_context.c | 4 +---
src/gallium/drivers/r600/r600_pipe.c | 11 +--
src/gallium/drivers/radeon/r600_pipe_common.c | 5 +++--
src/gallium/drivers/radeon/radeon_uvd.c | 2 +-
src/gallium/drivers/radeon/radeon_vce.c | 3 +--
src/gallium/drivers/radeonsi/si_pipe.c| 5 +++--
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 22 --
src/gallium/winsys/radeon/drm/radeon_winsys.h | 16
8 files changed, 26 insertions(+), 42 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_context.c
b/src/gallium/drivers/r300/r300_context.c
index e28dbfb..0116d6c 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -379,7 +379,7 @@ struct pipe_context* r300_create_context(struct
pipe_screen* screen,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
-r300-cs = rws-cs_create(rws, RING_GFX, NULL);
+r300-cs = rws-cs_create(rws, RING_GFX, r300_flush_callback, r300, NULL);
if (r300-cs == NULL)
goto fail;
@@ -420,8 +420,6 @@ struct pipe_context* r300_create_context(struct
pipe_screen* screen,
goto fail;
r300-blitter-draw_rectangle = r300_blitter_draw_rectangle;
-rws-cs_set_flush_callback(r300-cs, r300_flush_callback, r300);
-
/* The KIL opcode needs the first texture unit to be enabled
* on r3xx-r4xx. In order to calm down the CS checker, we bind this
* dummy texture there. */
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 6b2fcaf..677f414 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -167,6 +167,7 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
{
struct r600_context *rctx = CALLOC_STRUCT(r600_context);
struct r600_screen* rscreen = (struct r600_screen *)screen;
+ struct radeon_winsys *ws = rscreen-b.ws;
if (rctx == NULL)
return NULL;
@@ -231,13 +232,11 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
goto fail;
}
- if (rscreen-b.trace_bo) {
- rctx-b.rings.gfx.cs = rctx-b.ws-cs_create(rctx-b.ws,
RING_GFX, rscreen-b.trace_bo-cs_buf);
- } else {
- rctx-b.rings.gfx.cs = rctx-b.ws-cs_create(rctx-b.ws,
RING_GFX, NULL);
- }
+ rctx-b.rings.gfx.cs = ws-cs_create(ws, RING_GFX,
+r600_flush_gfx_ring, rctx,
+rscreen-b.trace_bo ?
+
rscreen-b.trace_bo-cs_buf : NULL);
rctx-b.rings.gfx.flush = r600_flush_gfx_ring;
- rctx-b.ws-cs_set_flush_callback(rctx-b.rings.gfx.cs,
r600_flush_gfx_ring, rctx);
rctx-b.rings.gfx.flushing = false;
rctx-allocator_fetch_shader = u_suballocator_create(rctx-b.b, 64 *
1024, 256,
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index c5e85f5..efb78cf 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -109,9 +109,10 @@ bool r600_common_context_init(struct r600_common_context
*rctx,
return false;
if (rscreen-info.r600_has_dma !(rscreen-debug_flags
DBG_NO_ASYNC_DMA)) {
- rctx-rings.dma.cs = rctx-ws-cs_create(rctx-ws, RING_DMA,
NULL);
+ rctx-rings.dma.cs = rctx-ws-cs_create(rctx-ws, RING_DMA,
+
r600_flush_dma_from_winsys,
+rctx, NULL);
rctx-rings.dma.flush = r600_flush_dma_ring;
- rctx-ws-cs_set_flush_callback(rctx-rings.dma.cs,
r600_flush_dma_from_winsys, rctx);
}
return true;
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 6c54cee..88573c1 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -806,7 +806,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct
pipe_context *context,
dec-set_dtb = set_dtb;
dec-stream_handle = rvid_alloc_stream_handle();
dec-ws = ws;
- dec-cs = ws-cs_create(ws, RING_UVD, NULL);
+ dec-cs = ws-cs_create(ws, RING_UVD, NULL, NULL, NULL);
if (!dec-cs) {
RVID_ERR(Can't get command submission context.\n);
goto error;
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index a7dfcda..5778dd1 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -308,13 +308,12 @@ struct pipe_video_codec
[Mesa-dev] [PATCH 01/10] winsys/radeon: remove cs_write_reloc, add simpler cs_get_reloc
From: Marek Olšák marek.ol...@amd.com
The only difference is that it doesn't write to the CS and only returns
the index.
---
src/gallium/drivers/r300/r300_cs.h| 3 ++-
src/gallium/drivers/r300/r300_emit.c | 4 ++--
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 26 +-
src/gallium/winsys/radeon/drm/radeon_winsys.h | 19 ++-
4 files changed, 23 insertions(+), 29 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_cs.h
b/src/gallium/drivers/r300/r300_cs.h
index 744e19e..748d6ea 100644
--- a/src/gallium/drivers/r300/r300_cs.h
+++ b/src/gallium/drivers/r300/r300_cs.h
@@ -109,7 +109,8 @@
#define OUT_CS_RELOC(r) do { \
assert((r)); \
assert((r)-cs_buf); \
-cs_winsys-cs_write_reloc(cs_copy, (r)-cs_buf); \
+OUT_CS(0xc0001000); /* PKT3_NOP */ \
+OUT_CS(cs_winsys-cs_get_reloc(cs_copy, (r)-cs_buf) * 4); \
CS_USED_DW(2); \
} while (0)
diff --git a/src/gallium/drivers/r300/r300_emit.c
b/src/gallium/drivers/r300/r300_emit.c
index d99b919..9f16413 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -1043,8 +1043,8 @@ void r300_emit_vertex_arrays_swtcl(struct r300_context
*r300, boolean indexed)
OUT_CS(0);
assert(r300-vbo_cs);
-cs_winsys-cs_write_reloc(cs_copy, r300-vbo_cs);
-CS_USED_DW(2);
+OUT_CS(0xc0001000); /* PKT3_NOP */
+OUT_CS(r300-rws-cs_get_reloc(r300-cs, r300-vbo_cs) * 4);
END_CS;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index b55eb80..4ce1717 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -313,6 +313,14 @@ static unsigned radeon_drm_cs_add_reloc(struct
radeon_winsys_cs *rcs,
return index;
}
+static int radeon_drm_cs_get_reloc(struct radeon_winsys_cs *rcs,
+ struct radeon_winsys_cs_handle *buf)
+{
+struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
+
+return radeon_get_reloc(cs-csc, (struct radeon_bo*)buf, NULL);
+}
+
static boolean radeon_drm_cs_validate(struct radeon_winsys_cs *rcs)
{
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
@@ -359,22 +367,6 @@ static boolean radeon_drm_cs_memory_below_limit(struct
radeon_winsys_cs *rcs, ui
return status;
}
-static void radeon_drm_cs_write_reloc(struct radeon_winsys_cs *rcs,
- struct radeon_winsys_cs_handle *buf)
-{
-struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
-struct radeon_bo *bo = (struct radeon_bo*)buf;
-unsigned index = radeon_get_reloc(cs-csc, bo, NULL);
-
-if (index == -1) {
-fprintf(stderr, radeon: Cannot get a relocation in %s.\n, __func__);
-return;
-}
-
-OUT_CS(cs-base, 0xc0001000);
-OUT_CS(cs-base, index * RELOC_DWORDS);
-}
-
void radeon_drm_cs_emit_ioctl_oneshot(struct radeon_drm_cs *cs, struct
radeon_cs_context *csc)
{
unsigned i;
@@ -650,9 +642,9 @@ void radeon_drm_cs_init_functions(struct radeon_drm_winsys
*ws)
ws-base.cs_create = radeon_drm_cs_create;
ws-base.cs_destroy = radeon_drm_cs_destroy;
ws-base.cs_add_reloc = radeon_drm_cs_add_reloc;
+ws-base.cs_get_reloc = radeon_drm_cs_get_reloc;
ws-base.cs_validate = radeon_drm_cs_validate;
ws-base.cs_memory_below_limit = radeon_drm_cs_memory_below_limit;
-ws-base.cs_write_reloc = radeon_drm_cs_write_reloc;
ws-base.cs_flush = radeon_drm_cs_flush;
ws-base.cs_set_flush_callback = radeon_drm_cs_set_flush;
ws-base.cs_is_buffer_referenced = radeon_bo_is_referenced;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 485e925..320989c 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -450,6 +450,16 @@ struct radeon_winsys {
enum radeon_bo_priority priority);
/**
+ * Return the index of an already-added buffer.
+ *
+ * \param csCommand stream
+ * \param buf Buffer
+ * \return The buffer index, or -1 if the buffer has not been
added.
+ */
+int (*cs_get_reloc)(struct radeon_winsys_cs *cs,
+struct radeon_winsys_cs_handle *buf);
+
+/**
* Return TRUE if there is enough memory in VRAM and GTT for the relocs
* added so far. If the validation fails, all the relocations which have
* been added since the last call of cs_validate will be removed and
@@ -470,15 +480,6 @@ struct radeon_winsys {
boolean (*cs_memory_below_limit)(struct radeon_winsys_cs *cs, uint64_t
vram, uint64_t gtt);
/**
- * Write a relocated dword to a command buffer.
- *
- * \param csA command stream the relocation is written to.
- * \param buf A winsys buffer to write the relocation for.
- */
-void (*cs_write_reloc)(struct
[Mesa-dev] [PATCH 10/10] r600g, radeonsi: share some of gfx flush code
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_hw_context.c| 44 ++---
src/gallium/drivers/radeon/r600_pipe_common.c | 47 +++
src/gallium/drivers/radeon/r600_pipe_common.h | 2 ++
src/gallium/drivers/radeonsi/si_hw_context.c | 44 ++---
4 files changed, 55 insertions(+), 82 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 6d3f799..a860519 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -236,35 +236,12 @@ void r600_context_gfx_flush(void *context, unsigned flags,
struct r600_context *ctx = context;
struct radeon_winsys_cs *cs = ctx-b.rings.gfx.cs;
- if (ctx-b.rings.gfx.cs-cdw == ctx-b.initial_gfx_cs_size)
+ if (cs-cdw == ctx-b.initial_gfx_cs_size)
return;
ctx-b.rings.gfx.flushing = true;
- /* Disable render condition. */
- ctx-b.saved_render_cond = NULL;
- ctx-b.saved_render_cond_cond = FALSE;
- ctx-b.saved_render_cond_mode = 0;
- if (ctx-b.current_render_cond) {
- ctx-b.saved_render_cond = ctx-b.current_render_cond;
- ctx-b.saved_render_cond_cond = ctx-b.current_render_cond_cond;
- ctx-b.saved_render_cond_mode = ctx-b.current_render_cond_mode;
- ctx-b.b.render_condition(ctx-b.b, NULL, FALSE, 0);
- }
-
- ctx-b.nontimer_queries_suspended = false;
- ctx-b.streamout.suspended = false;
-
- /* suspend queries */
- if (ctx-b.num_cs_dw_nontimer_queries_suspend) {
- r600_suspend_nontimer_queries(ctx-b);
- ctx-b.nontimer_queries_suspended = true;
- }
-
- if (ctx-b.streamout.begin_emitted) {
- r600_emit_streamout_end(ctx-b);
- ctx-b.streamout.suspended = true;
- }
+ r600_preflush_suspend_features(ctx-b);
/* flush the framebuffer cache */
ctx-b.flags |= R600_CONTEXT_FLUSH_AND_INV |
@@ -362,22 +339,7 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_sampler_states_dirty(ctx, samplers-states);
}
- if (ctx-b.streamout.suspended) {
- ctx-b.streamout.append_bitmask = ctx-b.streamout.enabled_mask;
- r600_streamout_buffers_dirty(ctx-b);
- }
-
- /* resume queries */
- if (ctx-b.nontimer_queries_suspended) {
- r600_resume_nontimer_queries(ctx-b);
- }
-
- /* Re-enable render condition. */
- if (ctx-b.saved_render_cond) {
- ctx-b.b.render_condition(ctx-b.b, ctx-b.saved_render_cond,
- ctx-b.saved_render_cond_cond,
- ctx-b.saved_render_cond_mode);
- }
+ r600_postflush_resume_features(ctx-b);
/* Re-emit the draw state. */
ctx-last_primitive_type = -1;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 3a0d981..7508865 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -53,6 +53,53 @@ static void r600_memory_barrier(struct pipe_context *ctx,
unsigned flags)
{
}
+void r600_preflush_suspend_features(struct r600_common_context *ctx)
+{
+ /* Disable render condition. */
+ ctx-saved_render_cond = NULL;
+ ctx-saved_render_cond_cond = FALSE;
+ ctx-saved_render_cond_mode = 0;
+ if (ctx-current_render_cond) {
+ ctx-saved_render_cond = ctx-current_render_cond;
+ ctx-saved_render_cond_cond = ctx-current_render_cond_cond;
+ ctx-saved_render_cond_mode = ctx-current_render_cond_mode;
+ ctx-b.render_condition(ctx-b, NULL, FALSE, 0);
+ }
+
+ /* suspend queries */
+ ctx-nontimer_queries_suspended = false;
+ if (ctx-num_cs_dw_nontimer_queries_suspend) {
+ r600_suspend_nontimer_queries(ctx);
+ ctx-nontimer_queries_suspended = true;
+ }
+
+ ctx-streamout.suspended = false;
+ if (ctx-streamout.begin_emitted) {
+ r600_emit_streamout_end(ctx);
+ ctx-streamout.suspended = true;
+ }
+}
+
+void r600_postflush_resume_features(struct r600_common_context *ctx)
+{
+ if (ctx-streamout.suspended) {
+ ctx-streamout.append_bitmask = ctx-streamout.enabled_mask;
+ r600_streamout_buffers_dirty(ctx);
+ }
+
+ /* resume queries */
+ if (ctx-nontimer_queries_suspended) {
+ r600_resume_nontimer_queries(ctx);
+ }
+
+ /* Re-enable render condition. */
+ if (ctx-saved_render_cond) {
+ ctx-b.render_condition(ctx-b, ctx-saved_render_cond,
+ ctx-saved_render_cond_cond,
+
[Mesa-dev] [PATCH 07/10] radeonsi: merge si_flush with si_context_flush
From: Marek Olšák marek.ol...@amd.com
This also removes si_flush_gfx_ring.
---
src/gallium/drivers/radeon/r600_pipe_common.h | 4 +++
src/gallium/drivers/radeonsi/si_hw_context.c | 26 +--
src/gallium/drivers/radeonsi/si_pipe.c| 37 +++
src/gallium/drivers/radeonsi/si_pipe.h| 4 +--
4 files changed, 33 insertions(+), 38 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 36a4fb1..a87efdc 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -352,6 +352,10 @@ struct r600_common_context {
unsignedcurrent_render_cond_mode;
boolean current_render_cond_cond;
boolean predicate_drawing;
+ /* For context flushing. */
+ struct pipe_query *saved_render_cond;
+ boolean saved_render_cond_cond;
+ unsignedsaved_render_cond_mode;
/* Copy one resource to another using async DMA. */
void (*dma_copy)(struct pipe_context *ctx,
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c
b/src/gallium/drivers/radeonsi/si_hw_context.c
index f527781..37ca290 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -77,14 +77,28 @@ void si_need_cs_space(struct si_context *ctx, unsigned
num_dw,
}
}
-void si_context_flush(struct si_context *ctx, unsigned flags,
- struct pipe_fence_handle **fence)
+void si_context_gfx_flush(void *context, unsigned flags,
+ struct pipe_fence_handle **fence)
{
+ struct si_context *ctx = context;
struct radeon_winsys_cs *cs = ctx-b.rings.gfx.cs;
if (cs-cdw == ctx-b.initial_gfx_cs_size)
return;
+ ctx-b.rings.gfx.flushing = true;
+
+ /* Disable render condition. */
+ ctx-b.saved_render_cond = NULL;
+ ctx-b.saved_render_cond_cond = FALSE;
+ ctx-b.saved_render_cond_mode = 0;
+ if (ctx-b.current_render_cond) {
+ ctx-b.saved_render_cond = ctx-b.current_render_cond;
+ ctx-b.saved_render_cond_cond = ctx-b.current_render_cond_cond;
+ ctx-b.saved_render_cond_mode = ctx-b.current_render_cond_mode;
+ ctx-b.b.render_condition(ctx-b.b, NULL, FALSE, 0);
+ }
+
/* suspend queries */
ctx-b.nontimer_queries_suspended = false;
if (ctx-b.num_cs_dw_nontimer_queries_suspend) {
@@ -125,6 +139,7 @@ void si_context_flush(struct si_context *ctx, unsigned
flags,
/* Flush the CS. */
ctx-b.ws-cs_flush(cs, flags, fence, 0);
+ ctx-b.rings.gfx.flushing = false;
#if SI_TRACE_CS
if (ctx-screen-b.trace_bo) {
@@ -177,6 +192,13 @@ void si_begin_new_cs(struct si_context *ctx)
r600_resume_nontimer_queries(ctx-b);
}
+ /* Re-enable render condition. */
+ if (ctx-b.saved_render_cond) {
+ ctx-b.b.render_condition(ctx-b.b, ctx-b.saved_render_cond,
+ ctx-b.saved_render_cond_cond,
+ ctx-b.saved_render_cond_mode);
+ }
+
ctx-framebuffer.atom.dirty = true;
ctx-b.streamout.enable_atom.dirty = true;
si_all_descriptors_begin_new_cs(ctx);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index d434064..7f3b0c2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -33,30 +33,6 @@
/*
* pipe_context
*/
-static void si_flush(struct pipe_context *ctx, unsigned flags,
-struct pipe_fence_handle **fence)
-{
- struct si_context *sctx = (struct si_context *)ctx;
- struct pipe_query *render_cond = NULL;
- boolean render_cond_cond = FALSE;
- unsigned render_cond_mode = 0;
-
- /* Disable render condition. */
- if (sctx-b.current_render_cond) {
- render_cond = sctx-b.current_render_cond;
- render_cond_cond = sctx-b.current_render_cond_cond;
- render_cond_mode = sctx-b.current_render_cond_mode;
- ctx-render_condition(ctx, NULL, FALSE, 0);
- }
-
- si_context_flush(sctx, flags, fence);
-
- /* Re-enable render condition. */
- if (render_cond) {
- ctx-render_condition(ctx, render_cond, render_cond_cond,
render_cond_mode);
- }
-}
-
static void si_flush_from_st(struct pipe_context *ctx,
struct pipe_fence_handle **fence,
unsigned flags)
@@ -70,14 +46,7 @@ static void si_flush_from_st(struct pipe_context *ctx,
if (sctx-b.rings.dma.cs) {
sctx-b.rings.dma.flush(sctx, rflags, NULL);
}
-
-
[Mesa-dev] [PATCH 08/10] r600g: merge r600_flush with r600_context_flush
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_hw_context.c | 31 +++--
src/gallium/drivers/r600/r600_pipe.c | 43 ++
src/gallium/drivers/r600/r600_pipe.h | 4 +--
3 files changed, 33 insertions(+), 45 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 60260ee..6d3f799 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -230,11 +230,28 @@ void r600_flush_emit(struct r600_context *rctx)
rctx-b.flags = 0;
}
-void r600_context_flush(struct r600_context *ctx, unsigned flags,
- struct pipe_fence_handle **fence)
+void r600_context_gfx_flush(void *context, unsigned flags,
+ struct pipe_fence_handle **fence)
{
+ struct r600_context *ctx = context;
struct radeon_winsys_cs *cs = ctx-b.rings.gfx.cs;
+ if (ctx-b.rings.gfx.cs-cdw == ctx-b.initial_gfx_cs_size)
+ return;
+
+ ctx-b.rings.gfx.flushing = true;
+
+ /* Disable render condition. */
+ ctx-b.saved_render_cond = NULL;
+ ctx-b.saved_render_cond_cond = FALSE;
+ ctx-b.saved_render_cond_mode = 0;
+ if (ctx-b.current_render_cond) {
+ ctx-b.saved_render_cond = ctx-b.current_render_cond;
+ ctx-b.saved_render_cond_cond = ctx-b.current_render_cond_cond;
+ ctx-b.saved_render_cond_mode = ctx-b.current_render_cond_mode;
+ ctx-b.b.render_condition(ctx-b.b, NULL, FALSE, 0);
+ }
+
ctx-b.nontimer_queries_suspended = false;
ctx-b.streamout.suspended = false;
@@ -272,6 +289,9 @@ void r600_context_flush(struct r600_context *ctx, unsigned
flags,
/* Flush the CS. */
ctx-b.ws-cs_flush(cs, flags, fence, ctx-screen-b.cs_count++);
+ ctx-b.rings.gfx.flushing = false;
+
+ r600_begin_new_cs(ctx);
}
void r600_begin_new_cs(struct r600_context *ctx)
@@ -352,6 +372,13 @@ void r600_begin_new_cs(struct r600_context *ctx)
r600_resume_nontimer_queries(ctx-b);
}
+ /* Re-enable render condition. */
+ if (ctx-b.saved_render_cond) {
+ ctx-b.b.render_condition(ctx-b.b, ctx-b.saved_render_cond,
+ ctx-b.saved_render_cond_cond,
+ ctx-b.saved_render_cond_mode);
+ }
+
/* Re-emit the draw state. */
ctx-last_primitive_type = -1;
ctx-last_start_instance = -1;
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index ef8883d..983c65a 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -66,38 +66,6 @@ static const struct debug_named_value r600_debug_options[] =
{
* pipe_context
*/
-static void r600_flush(struct pipe_context *ctx, unsigned flags,
- struct pipe_fence_handle **fence)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct pipe_query *render_cond = NULL;
- unsigned render_cond_mode = 0;
- boolean render_cond_cond = FALSE;
-
- if (rctx-b.rings.gfx.cs-cdw == rctx-b.initial_gfx_cs_size)
- return;
-
- rctx-b.rings.gfx.flushing = true;
- /* Disable render condition. */
- if (rctx-b.current_render_cond) {
- render_cond = rctx-b.current_render_cond;
- render_cond_cond = rctx-b.current_render_cond_cond;
- render_cond_mode = rctx-b.current_render_cond_mode;
- ctx-render_condition(ctx, NULL, FALSE, 0);
- }
-
- r600_context_flush(rctx, flags, fence);
- rctx-b.rings.gfx.flushing = false;
- r600_begin_new_cs(rctx);
-
- /* Re-enable render condition. */
- if (render_cond) {
- ctx-render_condition(ctx, render_cond, render_cond_cond,
render_cond_mode);
- }
-
- rctx-b.initial_gfx_cs_size = rctx-b.rings.gfx.cs-cdw;
-}
-
static void r600_flush_from_st(struct pipe_context *ctx,
struct pipe_fence_handle **fence,
unsigned flags)
@@ -114,12 +82,6 @@ static void r600_flush_from_st(struct pipe_context *ctx,
rctx-b.rings.gfx.flush(rctx, fflags, fence);
}
-static void r600_flush_gfx_ring(void *ctx, unsigned flags,
- struct pipe_fence_handle **fence)
-{
- r600_flush((struct pipe_context*)ctx, flags, fence);
-}
-
static void r600_destroy_context(struct pipe_context *context)
{
struct r600_context *rctx = (struct r600_context *)context;
@@ -233,11 +195,10 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
}
rctx-b.rings.gfx.cs = ws-cs_create(ws, RING_GFX,
-r600_flush_gfx_ring, rctx,
+
[Mesa-dev] [PATCH 05/10] r600g: remove redundant r600_flush_dma_from_winsys
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index efb78cf..92f43de 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -67,13 +67,6 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags)
rctx-rings.dma.flushing = false;
}
-static void r600_flush_dma_from_winsys(void *ctx, unsigned flags)
-{
- struct r600_common_context *rctx = (struct r600_common_context *)ctx;
-
- rctx-rings.dma.flush(rctx, flags);
-}
-
bool r600_common_context_init(struct r600_common_context *rctx,
struct r600_common_screen *rscreen)
{
@@ -110,7 +103,7 @@ bool r600_common_context_init(struct r600_common_context
*rctx,
if (rscreen-info.r600_has_dma !(rscreen-debug_flags
DBG_NO_ASYNC_DMA)) {
rctx-rings.dma.cs = rctx-ws-cs_create(rctx-ws, RING_DMA,
-
r600_flush_dma_from_winsys,
+r600_flush_dma_ring,
rctx, NULL);
rctx-rings.dma.flush = r600_flush_dma_ring;
}
--
1.8.3.2
___
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http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/10] radeonsi: cleanup redundant computation of flush flags and rename a function
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_pipe.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 03f73ac..ec03d6c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -66,17 +66,19 @@ static void si_flush_from_st(struct pipe_context *ctx,
unsigned flags)
{
struct si_context *sctx = (struct si_context *)ctx;
+ unsigned rflags = 0;
+
+ if (flags PIPE_FLUSH_END_OF_FRAME)
+ rflags |= RADEON_FLUSH_END_OF_FRAME;
if (sctx-b.rings.dma.cs) {
- sctx-b.rings.dma.flush(sctx,
- flags PIPE_FLUSH_END_OF_FRAME ?
RADEON_FLUSH_END_OF_FRAME : 0);
+ sctx-b.rings.dma.flush(sctx, rflags);
}
- si_flush(ctx, fence,
-flags PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME :
0);
+ si_flush(ctx, fence, rflags);
}
-static void si_flush_from_winsys(void *ctx, unsigned flags)
+static void si_flush_gfx_ring(void *ctx, unsigned flags)
{
si_flush((struct pipe_context*)ctx, NULL, flags);
}
@@ -146,7 +148,8 @@ static struct pipe_context *si_create_context(struct
pipe_screen *screen, void *
}
sctx-b.rings.gfx.cs = sctx-b.ws-cs_create(sctx-b.ws, RING_GFX,
NULL);
- sctx-b.rings.gfx.flush = si_flush_from_winsys;
+ sctx-b.rings.gfx.flush = si_flush_gfx_ring;
+ sctx-b.ws-cs_set_flush_callback(sctx-b.rings.gfx.cs,
si_flush_gfx_ring, sctx);
si_init_all_descriptors(sctx);
@@ -168,8 +171,6 @@ static struct pipe_context *si_create_context(struct
pipe_screen *screen, void *
goto fail;
}
- sctx-b.ws-cs_set_flush_callback(sctx-b.rings.gfx.cs,
si_flush_from_winsys, sctx);
-
sctx-blitter = util_blitter_create(sctx-b.b);
if (sctx-blitter == NULL)
goto fail;
--
1.8.3.2
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Re: [Mesa-dev] Mesa build instructions
Pekka Paalanen ppaala...@gmail.com writes: On Fri, 11 Apr 2014 11:50:50 -0700 Eric Anholt e...@anholt.net wrote: For anyone that's curious about how I work: My scripts setup looks a lot like Matt's. I don't do OOT builds, and instead I just have 6 main trees: ~/src/mesa (normal debug build) ~/src/mesa-release (non-debug build) ~/src/mesa-clean (usually HEAD~1 of ~/src/mesa) ~/src/32/mesa ~/src/32/mesa-release ~/src/32/mesa-clean The debug build also is with -O2 so that I can actually get mostly-representative performance results while developing. REALLY IMPORTANT: Don't forget -fno-omit-frame-pointer on 64-bit, otherwise you won't get backtraces from sysprof and perf (similarly, in your kernel, CONFIG_FRAME_POINTER=y). I think the most important feature of my setup is the clean builds. By having copies of unmodified mesa along with patched mesa, I can use http://anholt.net/compare-perf/ to easily produce stats to test whether my change is actually having the desired effect. Hi Eric, just curious, how have you set up git here? Do you have a .git/ completely separate in each directory, and if so, how do you keep them synced? Or do you use some GIT_DIR env magic to have a single git repo with multiple checkouts? ~/src/mesa is a full checkout, while the other 5 are git clone upstream --references ~/src/mesa. Be careful with --references, of course, because it means that a git gc in ~/src/mesa after deleting a branch, where that branch also existed in the other repo, may result in warnings like: error: refs/remotes/anholt/i965-texture-writemask does not point to a valid object! error: refs/remotes/anholt/sched does not point to a valid object! error: refs/remotes/origin/broadwell does not point to a valid object! (and those warnings also mean you can't gc in those trees) It's not a good solution, but OOT builds drive me up the wall and I've never found anything better. pgpuBTy3wQd3E.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Add comment to explain the weird-looking shadow compares.
On 04/12/2014 03:34 AM, Chris Forbes wrote:
This always looks crazy when I stumble across it, until I remember
what the hardware is doing. Describing it ought to short-circuit
that process next time :)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_state.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_state.c
b/src/mesa/drivers/dri/i965/intel_state.c
index bfc35d8..1597db6 100644
--- a/src/mesa/drivers/dri/i965/intel_state.c
+++ b/src/mesa/drivers/dri/i965/intel_state.c
@@ -40,6 +40,17 @@
int
intel_translate_shadow_compare_func(GLenum func)
{
+ /* GL specifies the result of shadow comparisons as:
+* 1 if ref op texel,
+* 0 otherwise.
+*
+* The hardware does:
+* 0 if texel op ref,
+* 1 otherwise.
+*
+* So, these look a bit strange because there's both a negation
+* and swapping of the arguments involved.
+*/
Thanks for adding this! I've had to do this a few times as well.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
switch (func) {
case GL_NEVER:
return BRW_COMPAREFUNCTION_ALWAYS;
@@ -50,11 +61,11 @@ intel_translate_shadow_compare_func(GLenum func)
case GL_GREATER:
return BRW_COMPAREFUNCTION_GEQUAL;
case GL_GEQUAL:
- return BRW_COMPAREFUNCTION_GREATER;
+ return BRW_COMPAREFUNCTION_GREATER;
Although your patch makes the 6-7 space indent consistent...we really
want to use 2*3=6, not 7. :) If you wouldn't mind switching that before
pushing...
case GL_NOTEQUAL:
- return BRW_COMPAREFUNCTION_EQUAL;
+ return BRW_COMPAREFUNCTION_EQUAL;
case GL_EQUAL:
- return BRW_COMPAREFUNCTION_NOTEQUAL;
+ return BRW_COMPAREFUNCTION_NOTEQUAL;
case GL_ALWAYS:
return BRW_COMPAREFUNCTION_NEVER;
}
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Re: [Mesa-dev] [PATCH] i965: Add comment to explain the weird-looking shadow compares.
Eek -- yes, I'll fix that!
On Sun, Apr 13, 2014 at 8:04 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On 04/12/2014 03:34 AM, Chris Forbes wrote:
This always looks crazy when I stumble across it, until I remember
what the hardware is doing. Describing it ought to short-circuit
that process next time :)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/intel_state.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_state.c
b/src/mesa/drivers/dri/i965/intel_state.c
index bfc35d8..1597db6 100644
--- a/src/mesa/drivers/dri/i965/intel_state.c
+++ b/src/mesa/drivers/dri/i965/intel_state.c
@@ -40,6 +40,17 @@
int
intel_translate_shadow_compare_func(GLenum func)
{
+ /* GL specifies the result of shadow comparisons as:
+* 1 if ref op texel,
+* 0 otherwise.
+*
+* The hardware does:
+* 0 if texel op ref,
+* 1 otherwise.
+*
+* So, these look a bit strange because there's both a negation
+* and swapping of the arguments involved.
+*/
Thanks for adding this! I've had to do this a few times as well.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
switch (func) {
case GL_NEVER:
return BRW_COMPAREFUNCTION_ALWAYS;
@@ -50,11 +61,11 @@ intel_translate_shadow_compare_func(GLenum func)
case GL_GREATER:
return BRW_COMPAREFUNCTION_GEQUAL;
case GL_GEQUAL:
- return BRW_COMPAREFUNCTION_GREATER;
+ return BRW_COMPAREFUNCTION_GREATER;
Although your patch makes the 6-7 space indent consistent...we really
want to use 2*3=6, not 7. :) If you wouldn't mind switching that before
pushing...
case GL_NOTEQUAL:
- return BRW_COMPAREFUNCTION_EQUAL;
+ return BRW_COMPAREFUNCTION_EQUAL;
case GL_EQUAL:
- return BRW_COMPAREFUNCTION_NOTEQUAL;
+ return BRW_COMPAREFUNCTION_NOTEQUAL;
case GL_ALWAYS:
return BRW_COMPAREFUNCTION_NEVER;
}
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[Mesa-dev] [PATCH 1/2] mesa: Track max enabled tex image unit
This gives us a better bound for some hot loops in the drivers than MAX_COMBINED_TEXTURE_IMAGE_UNITS, which is ridiculously large on modern hardware, and only getting worse as more shader stages are added. Signed-off-by: Chris Forbes chr...@ijw.co.nz --- src/mesa/main/mtypes.h | 3 +++ src/mesa/main/texstate.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index 4d014d1..6694383 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -1402,6 +1402,9 @@ struct gl_texture_attrib /** Bitwise-OR of all Texture.Unit[i]._GenFlags */ GLbitfield _GenFlags; + + /** Upper bound on _ReallyEnabled texunits. */ + GLint _MaxEnabledTexImageUnit; }; diff --git a/src/mesa/main/texstate.c b/src/mesa/main/texstate.c index fcae878..b68920c 100644 --- a/src/mesa/main/texstate.c +++ b/src/mesa/main/texstate.c @@ -550,6 +550,7 @@ update_texture_state( struct gl_context *ctx ) ctx-Texture._GenFlags = 0x0; ctx-Texture._TexMatEnabled = 0x0; ctx-Texture._TexGenEnabled = 0x0; + ctx-Texture._MaxEnabledTexImageUnit = -1; /* * Update texture unit state. @@ -636,6 +637,7 @@ update_texture_state( struct gl_context *ctx ) /* if we get here, we know this texture unit is enabled */ ctx-Texture._EnabledUnits |= (1 unit); + ctx-Texture._MaxEnabledTexImageUnit = unit; if (enabledTargetsByStage[MESA_SHADER_FRAGMENT]) enabledFragUnits |= (1 unit); -- 1.9.2 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] gallium/targets: #include radeon_winsys.h in a couple of more places
A similar fix from somebody else has already been pushed. Marek On Sat, Apr 12, 2014 at 7:39 AM, Michel Dänzer mic...@daenzer.net wrote: On 2014/04/11, at 19:43, Marek Olšák mar...@gmail.com wrote: Thanks. Reviewed-by: Marek Olšák marek.ol...@amd.com Thank you. Can you or someone push this please? I probably won't get to it before Monday. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] i965: Use ctx-Texture._MaxEnabledTexImageUnit for upper bound
Avoid looping over 32/48/96 (!!) tex image units every draw, most of
which we don't care about.
Improves performance on everyone's favorite not-a-benchmark by 2.9% on
Haswell.
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_draw.c | 3 ++-
src/mesa/drivers/dri/i965/brw_tex.c | 3 ++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 583c7d6..34afc26 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -315,7 +315,8 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
intel_renderbuffer_resolve_hiz(brw, depth_irb);
/* Resolve depth buffer and render cache of each enabled texture. */
- for (int i = 0; i ctx-Const.MaxCombinedTextureImageUnits; i++) {
+ int maxEnabledUnit = ctx-Texture._MaxEnabledTexImageUnit;
+ for (int i = 0; i = maxEnabledUnit; i++) {
if (!ctx-Texture.Unit[i]._ReallyEnabled)
continue;
tex_obj = intel_texture_object(ctx-Texture.Unit[i]._Current);
diff --git a/src/mesa/drivers/dri/i965/brw_tex.c
b/src/mesa/drivers/dri/i965/brw_tex.c
index b1f4de0..305d83d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex.c
+++ b/src/mesa/drivers/dri/i965/brw_tex.c
@@ -46,8 +46,9 @@ void brw_validate_textures( struct brw_context *brw )
{
struct gl_context *ctx = brw-ctx;
int i;
+ int maxEnabledUnit = ctx-Texture._MaxEnabledTexImageUnit;
- for (i = 0; i ctx-Const.MaxCombinedTextureImageUnits; i++) {
+ for (i = 0; i = maxEnabledUnit; i++) {
struct gl_texture_unit *texUnit = ctx-Texture.Unit[i];
if (texUnit-_ReallyEnabled) {
--
1.9.2
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[Mesa-dev] [PATCH 2/2] glsl: Fix redeclaration rules for gl_FragDepth too.
Previously we disallowed any redeclarations after any use, and detected
conflicting layout qualifiers based on what we know the default to be.
Use ir_variable::data::how_declared instead to determine whether this
has already been redeclared, and allow identical redeclarations after
use, provided the first redeclaration was before the first use.
(These are the same rules as for gl_FragCoord, since the spec language
is identical.)
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_to_hir.cpp | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index d1eb3e2..535b11b 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2770,14 +2770,15 @@ get_variable_being_redeclared(ir_variable *var, YYLTYPE
loc,
* Within any shader, the first redeclarations of gl_FragDepth
* must appear before any use of gl_FragDepth.
*/
- if (earlier-data.used) {
-_mesa_glsl_error(loc, state,
- the first redeclaration of gl_FragDepth
- must appear before any use of gl_FragDepth);
+ if (earlier-data.used
+ earlier-data.how_declared == ir_var_declared_implicitly) {
+ _mesa_glsl_error(loc, state,
+ the first redeclaration of gl_FragDepth
+ must appear before any use of gl_FragDepth);
}
/* Prevent inconsistent redeclaration of depth layout qualifier. */
- if (earlier-data.depth_layout != ir_depth_layout_none
+ if (earlier-data.how_declared != ir_var_declared_implicitly
earlier-data.depth_layout != var-data.depth_layout) {
_mesa_glsl_error(loc, state,
gl_FragDepth: depth layout is declared here
--
1.9.2
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[Mesa-dev] [PATCH 1/2] glsl: Fix redeclaration rules for gl_FragCoord.
The ARB_fragment_coord_conventions spec, section 4.3.x (Input Layout
Qualifiers) says:
All redeclarations of gl_FragCoord in all fragment shaders in a
single program must have the same set of qualifiers. Within any
shader, the first redeclarations of gl_FragCoord must appear before
any use of gl_FragCoord.
Fixes piglit's tests:
arb_fragment_coord_conventions/compiler/redeclaration-after-use
arb_fragment_coord_conventions/compiler/redeclaration-around-use
glsl-1.50/compiler/fragment_coord_conventions/layout-qualifiers-conflicting-case-1
glsl-1.50/compiler/fragment_coord_conventions/layout-qualifiers-conflicting-case-2
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/glsl/ast_to_hir.cpp | 20
1 file changed, 20 insertions(+)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 9b9d511..d1eb3e2 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -2715,9 +2715,29 @@ get_variable_being_redeclared(ir_variable *var, YYLTYPE
loc,
/* Allow redeclaration of gl_FragCoord for ARB_fcc layout
* qualifiers.
*/
+
+ if (earlier-data.how_declared != ir_var_declared_implicitly
+ (earlier-data.origin_upper_left != var-data.origin_upper_left
+ || earlier-data.pixel_center_integer !=
var-data.pixel_center_integer)) {
+ _mesa_glsl_error(loc, state,
+ Inconsistent redeclarations of gl_FragCoord);
+ }
+
earlier-data.origin_upper_left = var-data.origin_upper_left;
earlier-data.pixel_center_integer = var-data.pixel_center_integer;
+ if (earlier-data.used
+ earlier-data.how_declared == ir_var_declared_implicitly) {
+ /* ARB_fragment_coord_conventions spec Section 4.3.x.1
+ * (Input Layout Qualifier) says:
+ *
+ * Within any shader, the first redeclarations of gl_FragCoord
+ * must appear before any use of gl_FragCoord.
+ */
+ _mesa_glsl_error(loc, state,
+ First redeclaration of gl_FragCoord must appear
before any use);
+ }
+
/* According to section 4.3.7 of the GLSL 1.30 spec,
* the following built-in varaibles can be redeclared with an
* interpolation qualifier:
--
1.9.2
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