Re: [Mesa-dev] [PATCH v6.2] egl: Allow creation of per surface out fence

[Marathe, Yogesh]

Tomasz,

> -Original Message-
> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
> Of Tomasz Figa
> Sent: Friday, September 1, 2017 9:53 AM
> To: Marathe, Yogesh 
> Cc: Gao, Shuo ; Liu, Zhiquan ;
> dani...@collabora.com; nicolai.haeh...@amd.com; Antognolli, Rafael
> ; e...@engestrom.ch; Emil Velikov
> ; Wu, Zhongmin ;
> kenn...@whitecape.org; mesa-dev@lists.freedesktop.org;
> fernetme...@online.de; Kondapally, Kalyan ;
> tarc...@itsqueeze.com; varad.gau...@collabora.com
> Subject: Re: [Mesa-dev] [PATCH v6.2] egl: Allow creation of per surface out
> fence
> 
> On Thu, Aug 31, 2017 at 2:18 AM, Marathe, Yogesh
>  wrote:
> >> -Original Message-
> >> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
> >> Behalf Of Emil Velikov
> >> Sent: Wednesday, August 30, 2017 9:44 PM
> >> To: Marathe, Yogesh 
> >> Cc: Gao, Shuo ; Liu, Zhiquan
> >> ; dani...@collabora.com;
> >> nicolai.haeh...@amd.com; Antognolli, Rafael
> >> ; e...@engestrom.ch; Wu, Zhongmin
> >> ; tf...@chromium.org; kenn...@whitecape.org;
> >> Kondapally, Kalyan ;
> >> fernetme...@online.de; mesa-dev@lists.freedesktop.org;
> >> tarc...@itsqueeze.com; varad.gau...@collabora.com
> >> Subject: Re: [Mesa-dev] [PATCH v6.2] egl: Allow creation of per
> >> surface out fence
> >>
> >> On 30 August 2017 at 15:39, Marathe, Yogesh
> >> 
> >> wrote:
> >>
> >> >
> >> > Thank you, Tomasz and all involved for the help and guidance.
> >> >
> >> Our excitement was short lived - see commit
> >> 8c9df0daf20206fafb7df77b1edcbc41b8e91372.
> >>
> >> Seems the patch was not run through the Intel CI, though I'm should
> >> not have assumed that you're aware of if.
> >> Please get in touch with Mark Janes (Cc'd here, janesma on IRC). He
> >> can set you up and/or run a branch for you.
> >>
> >
> > No problem. I will contact Mark.
> >
> > Primarily looks like platform / kernel version issue.
> > intel_get_boolean() for I915_PARAM_HAS_EXEC_FENCE is false, but I see
> > following in i915_drv.c:915_getparam in kernel, no clue why that would
> > come false in UMD.
> >
> > ...
> > case I915_PARAM_HAS_EXEC_FENCE:
> > /* For the time being all of these are always true;
> >  * if some supported hardware does not have one of these
> >  * features this value needs to be provided from
> >  * INTEL_INFO(), a feature macro, or similar.
> >  */
> > value = 1;
> > break;
> > ...
> 
> Which kernel are you looking at? Remember that not everyone uses current
> upstream master. There is a number of upstream stable releases and
> downstream forks. Grepping for I915_PARAM_HAS_EXEC_FENCE on
> http://elixir.free-electrons.com, shows that it was only added in Linux 4.12.
> 

I'm on 4.9.x but I see my kernel  tree has following patch, so this looks like 
it is
done for android (cherry picked / backport). That’s why it worked for me always!

commit f0683754f03fa308a2657cb1dadbf235c9607188
Author: Chris Wilson 
Date:   Fri Jan 27 09:40:08 2017 +

drm/i915: Support explicit fencing for execbuf

Nonetheless, as you mentioned, I've synced up with Mark and we've created a 
separate branch where CTS / intel mesa CI can run. Let me try to fix this.

Caveat: To have flatland running on android  there was another issue in kernel 
which
needed a fix. Details - https://bugs.freedesktop.org/show_bug.cgi?id=101656

> Best regards,
> Tomasz
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Re: [Mesa-dev] [PATCH v6.2] egl: Allow creation of per surface out fence

[Tomasz Figa]

On Thu, Aug 31, 2017 at 2:18 AM, Marathe, Yogesh
 wrote:
>> -Original Message-
>> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
>> Of Emil Velikov
>> Sent: Wednesday, August 30, 2017 9:44 PM
>> To: Marathe, Yogesh 
>> Cc: Gao, Shuo ; Liu, Zhiquan ;
>> dani...@collabora.com; nicolai.haeh...@amd.com; Antognolli, Rafael
>> ; e...@engestrom.ch; Wu, Zhongmin
>> ; tf...@chromium.org; kenn...@whitecape.org;
>> Kondapally, Kalyan ; fernetme...@online.de;
>> mesa-dev@lists.freedesktop.org; tarc...@itsqueeze.com;
>> varad.gau...@collabora.com
>> Subject: Re: [Mesa-dev] [PATCH v6.2] egl: Allow creation of per surface out
>> fence
>>
>> On 30 August 2017 at 15:39, Marathe, Yogesh 
>> wrote:
>>
>> >
>> > Thank you, Tomasz and all involved for the help and guidance.
>> >
>> Our excitement was short lived - see commit
>> 8c9df0daf20206fafb7df77b1edcbc41b8e91372.
>>
>> Seems the patch was not run through the Intel CI, though I'm should not have
>> assumed that you're aware of if.
>> Please get in touch with Mark Janes (Cc'd here, janesma on IRC). He can set 
>> you
>> up and/or run a branch for you.
>>
>
> No problem. I will contact Mark.
>
> Primarily looks like platform / kernel version issue. intel_get_boolean() for
> I915_PARAM_HAS_EXEC_FENCE is false, but I see following in
> i915_drv.c:915_getparam in kernel, no clue why that would come false
> in UMD.
>
> ...
> case I915_PARAM_HAS_EXEC_FENCE:
> /* For the time being all of these are always true;
>  * if some supported hardware does not have one of these
>  * features this value needs to be provided from
>  * INTEL_INFO(), a feature macro, or similar.
>  */
> value = 1;
> break;
> ...

Which kernel are you looking at? Remember that not everyone uses
current upstream master. There is a number of upstream stable releases
and downstream forks. Grepping for I915_PARAM_HAS_EXEC_FENCE on
http://elixir.free-electrons.com, shows that it was only added in
Linux 4.12.

Best regards,
Tomasz
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[Mesa-dev] [Bug 102125] [softpipe] piglit arb_texture_view-targets regression

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102125

Brian Paul  changed:

   What|Removed |Added

 Resolution|--- |FIXED
 Status|NEW |RESOLVED

--- Comment #1 from Brian Paul  ---
Fixed w/ commit 9eca7e0ddb58808af77c6f251f5d368ea328c894

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Re: [Mesa-dev] [PATCH 2/2] swr: Report format max_samples=1 to maintain support for "fake" msaa.

[Brian Paul]

I'm not familiar with this driver so I'll give this an

Acked-by: Brian Paul 

Roland gave me his R-b for the state tracker patch off-list.

I'll commit that and you can take care of this one.  Feel free to close 
the bug then.


-Brian


On 08/25/2017 01:59 PM, Bruce Cherniak wrote:

Accompanying patch "st/mesa: only try to create 1x msaa surfaces for
'fake' msaa" requires driver to report max_samples=1 to enable "fake"
msaa. Previously, 0 and 1 were treated equivalently in st_init_extensions()
and either could enable "fake" msaa.

This patch raises the swr default msaa_max_count from 0 to 1, so that
swr_is_format_supported will report max_samples=1.

Real msaa can still be enabled by exporting SWR_MSAA_MAX_COUNT with a
pow2 value between 2 and 16.

This patch is necessary to prevent an OpenSWR regression resulting from
the st/mesa patch.

Bugzilla: 
https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.freedesktop.org_show-5Fbug.cgi-3Fid-3D102038=DwIBAg=uilaK90D4TOVoH58JNXRgQ=Ie7_encNUsqxbSRbqbNgofw0ITcfE8JKfaUjIQhncGA=qdD02tm0IRZ3cDM-14sDyg5PjXgN7HpvqxwdIKPKG_0=Lfh53G7s15bwea6KD_n-r5t38aWcMLmz8Dp-k0TfKbA=
---
  src/gallium/drivers/swr/swr_screen.cpp | 22 +++---
  1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_screen.cpp 
b/src/gallium/drivers/swr/swr_screen.cpp
index 3287bc6fee..cc8d9955b8 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -255,13 +255,13 @@ swr_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
return 1;

 /* MSAA support
-* If user has explicitly set max_sample_count = 0 (via SWR_MSAA_MAX_COUNT)
-* then disable all MSAA support and go back to old caps. */
+* If user has explicitly set max_sample_count = 1 (via SWR_MSAA_MAX_COUNT)
+* then disable all MSAA support and go back to old (FAKE_SW_MSAA) caps. */
 case PIPE_CAP_TEXTURE_MULTISAMPLE:
 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
-  return swr_screen(screen)->msaa_max_count ? 1 : 0;
+  return (swr_screen(screen)->msaa_max_count > 1) ? 1 : 0;
 case PIPE_CAP_FAKE_SW_MSAA:
-  return swr_screen(screen)->msaa_max_count ? 0 : 1;
+  return (swr_screen(screen)->msaa_max_count > 1) ? 0 : 1;

/* unsupported features */
 case PIPE_CAP_ANISOTROPIC_FILTER:
@@ -1079,22 +1079,22 @@ swr_validate_env_options(struct swr_screen *screen)
screen->client_copy_limit = client_copy_limit;

 /* XXX msaa under development, disable by default for now */
-   screen->msaa_max_count = 0; /* was SWR_MAX_NUM_MULTISAMPLES; */
+   screen->msaa_max_count = 1; /* was SWR_MAX_NUM_MULTISAMPLES; */

 /* validate env override values, within range and power of 2 */
-   int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 0);
-   if (msaa_max_count) {
-  if ((msaa_max_count < 0) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
+   int msaa_max_count = debug_get_num_option("SWR_MSAA_MAX_COUNT", 1);
+   if (msaa_max_count != 1) {
+  if ((msaa_max_count < 1) || (msaa_max_count > SWR_MAX_NUM_MULTISAMPLES)
  || !util_is_power_of_two(msaa_max_count)) {
   fprintf(stderr, "SWR_MSAA_MAX_COUNT invalid: %d\n", msaa_max_count);
   fprintf(stderr, "must be power of 2 between 1 and %d" \
- " (or 0 to disable msaa)\n",
+ " (or 1 to disable msaa)\n",
 SWR_MAX_NUM_MULTISAMPLES);
- msaa_max_count = 0;
+ msaa_max_count = 1;
}

fprintf(stderr, "SWR_MSAA_MAX_COUNT: %d\n", msaa_max_count);
-  if (!msaa_max_count)
+  if (msaa_max_count == 1)
   fprintf(stderr, "(msaa disabled)\n");

screen->msaa_max_count = msaa_max_count;



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[Mesa-dev] [Bug 100613] Regression in Mesa 17 on s390x (zSystems)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=100613

--- Comment #45 from Roland Scheidegger  ---
(In reply to Ben Crocker from comment #44)
> By the way, draw-vertices-2101010 is failing across all architectures:
> X86 and PPC64LE as well as PPC64/S390x.
Yes, but this isn't related to swizzling (at least on x86, unless ppc64 has
additional errors), but is rather due to GL weirdness with converting signed
numbers. Pre-GL 4.2 there's 2 different formulas depending on if it's used as a
vertex format or a pixel format, and the test expects the result of the formula
used for vertex formats. GL 4.2 and up ditched this formula entirely
(obviously, two formulas don't make all that much sense if pixel and vertex
data is all in the same buffers anyway...), and that's the one we always use,
no matter the GL version.
The difference in the formulas usually isn't all that large, but with just 2
bits the error is huge: the four values you can represent are [-1.0, -0.333,
0.333, 1.0] for the old formula and [-1.0, -1.0, 0.0, 1.0] for the new one,
hence the failure (Expected: ... 0.333000, Observed: ... 0.00).

Note that at least some hw/drivers will ignore these old GL rules too (after
all, GL 4.2 is supposed to be backwards compatible, and clearly with the
different formula gone it can't quite be), therefore we don't consider this a
driver bug, rather a test bug:
https://bugs.freedesktop.org/show_bug.cgi?id=59150

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[Mesa-dev] [Bug 99591] Segmentation fault when running vulkaninfo with RADV Radeon Vulkan driver

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99591

--- Comment #12 from Michel Dänzer  ---
This might be related to building LLVM with -DBUILD_SHARED_LIBS=ON. Does it
also happen when building LLVM with -DLLVM_BUILD_LLVM_DYLIB=ON instead?

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[Mesa-dev] [Bug 99591] Segmentation fault when running vulkaninfo with RADV Radeon Vulkan driver

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=99591

--- Comment #11 from Matias N. Goldberg  ---
There is a similar ticket in
https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/issues/1978

where they suggest export LD_BIND_NOW=1 and that has indeed fixed the issue but
later crashed with:
vulkaninfo:
/home/matias/Projects/Mesa/llvm/llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp:719:
bool (anonymous namespace)::SIPeepholeSDWA::convertToSDWA(llvm::MachineInstr &,
const SDWAOperandsVector &): Assertion `AMDGPU::getNamedOperandIdx(SDWAOpcode,
AMDGPU::OpName::omod) != -1' failed.

I've compiled LLVM on my own (I don't know if LTO is enabled, if there's a
quick way to tell, someone let me know how to check that and I'll paste it
here).
It's also possible that assert may go away if I update LLVM (it's not latest,
it's 5.0.0 unknown svn version from a few months ago).

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Re: [Mesa-dev] [PATCH] m4: Use older autoconf 2.63 compatible ax_check_compile_flag.

[Matt Turner]

Reviewed-by: Matt Turner 

I checked the revision history of this, and it changed between #serial
3 and 4 with a commit message saying it was "Modernizing" it [1]. Not
compelling enough.

[1] 
http://git.savannah.gnu.org/gitweb/?p=autoconf-archive.git;a=commit;h=1a869696e4129279f7b99c3f9052717354b79a86
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Re: [Mesa-dev] [PATCH] intel/eu/validate: Look up types on demand in execution_type()

[Matt Turner]

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH] st/mesa: fix view template initialization in try_pbo_readpixels

[Roland Scheidegger]

Am 01.09.2017 um 02:32 schrieb Brian Paul:
> On 08/31/2017 05:53 PM, srol...@vmware.com wrote:
>> From: Roland Scheidegger 
>>
>> I think this is what the code was meant to do, albeit as far as I can
>> tell
>> the redundant initialization some analyzers complain about should work as
>> well just fine (only the first layer will be used, if the view
>> contains one
>> or more layers doesn't really matter).
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102467
>> ---
>>   src/mesa/state_tracker/st_cb_readpixels.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/state_tracker/st_cb_readpixels.c
>> b/src/mesa/state_tracker/st_cb_readpixels.c
>> index 0bcf2eb..84dd2d5 100644
>> --- a/src/mesa/state_tracker/st_cb_readpixels.c
>> +++ b/src/mesa/state_tracker/st_cb_readpixels.c
>> @@ -175,7 +175,7 @@ try_pbo_readpixels(struct st_context *st, struct
>> st_renderbuffer *strb,
>>
>>     if (view_target != PIPE_TEXTURE_3D) {
>>    templ.u.tex.first_layer = surface->u.tex.first_layer;
>> - templ.u.tex.last_layer = templ.u.tex.last_layer;
>> + templ.u.tex.last_layer = templ.u.tex.first_layer;
>>     } else {
>>    addr.constants.layer_offset = surface->u.tex.first_layer;
>>     }
>>
> 
> Reviewed-by: Brian Paul 
> 
> Add cc for stable branch?
> 

I can do that, though as said while clearly the code was meant to do
something different it looks like it's a cosmetic issue only.

Roland

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[Mesa-dev] [PATCH 3/3] radeonsi/gfx9: implement primitive binning

[Marek Olšák]

From: Marek Olšák 

This increases performance, but it was tuned for Raven, not Vega.
We don't know yet how Vega will perform, hopefully not worse.
---
 src/gallium/drivers/radeon/r600_pipe_common.c   |   2 +
 src/gallium/drivers/radeon/r600_pipe_common.h   |   2 +
 src/gallium/drivers/radeonsi/Makefile.sources   |   1 +
 src/gallium/drivers/radeonsi/si_hw_context.c|   2 +
 src/gallium/drivers/radeonsi/si_pipe.c  |   5 +
 src/gallium/drivers/radeonsi/si_pipe.h  |   2 +
 src/gallium/drivers/radeonsi/si_state.c |  26 +-
 src/gallium/drivers/radeonsi/si_state.h |   6 +-
 src/gallium/drivers/radeonsi/si_state_binning.c | 448 
 src/gallium/drivers/radeonsi/si_state_shaders.c |   2 +
 10 files changed, 489 insertions(+), 7 deletions(-)
 create mode 100644 src/gallium/drivers/radeonsi/si_state_binning.c

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6b61901..1799b69 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -816,20 +816,22 @@ static const struct debug_named_value 
common_debug_options[] = {
{ "precompile", DBG_PRECOMPILE, "Compile one shader variant at shader 
creation." },
{ "nowc", DBG_NO_WC, "Disable GTT write combining" },
{ "check_vm", DBG_CHECK_VM, "Check VM faults and dump debug info." },
{ "nodcc", DBG_NO_DCC, "Disable DCC." },
{ "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
{ "norbplus", DBG_NO_RB_PLUS, "Disable RB+." },
{ "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction 
Scheduler." },
{ "mono", DBG_MONOLITHIC_SHADERS, "Use old-style monolithic shaders 
compiled on demand" },
{ "unsafemath", DBG_UNSAFE_MATH, "Enable unsafe math shader 
optimizations" },
{ "nodccfb", DBG_NO_DCC_FB, "Disable separate DCC on the main 
framebuffer" },
+   { "nodpbb", DBG_NO_DPBB, "Disable DPBB." },
+   { "nodfsm", DBG_NO_DFSM, "Disable DFSM." },
 
DEBUG_NAMED_VALUE_END /* must be last */
 };
 
 static const char* r600_get_vendor(struct pipe_screen* pscreen)
 {
return "X.Org";
 }
 
 static const char* r600_get_device_vendor(struct pipe_screen* pscreen)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 1f3c854..ca921f9 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -108,20 +108,22 @@ struct u_log_context;
 #define DBG_NO_DCC_CLEAR   (1ull << 44)
 #define DBG_NO_RB_PLUS (1ull << 45)
 #define DBG_SI_SCHED   (1ull << 46)
 #define DBG_MONOLITHIC_SHADERS (1ull << 47)
 /* gap */
 #define DBG_UNSAFE_MATH(1ull << 49)
 #define DBG_NO_DCC_FB  (1ull << 50)
 #define DBG_TEST_VMFAULT_CP(1ull << 51)
 #define DBG_TEST_VMFAULT_SDMA  (1ull << 52)
 #define DBG_TEST_VMFAULT_SHADER(1ull << 53)
+#define DBG_NO_DPBB(1ull << 54)
+#define DBG_NO_DFSM(1ull << 55)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 #define R600_MAX_VIEWPORTS16
 
 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
 
 enum r600_coherency {
R600_COHERENCY_NONE, /* no cache flushes needed */
R600_COHERENCY_SHADER,
R600_COHERENCY_CB_META,
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources 
b/src/gallium/drivers/radeonsi/Makefile.sources
index 74df4d7..3795bed 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -20,14 +20,15 @@ C_SOURCES := \
si_perfcounter.c \
si_public.h \
si_shader.c \
si_shader.h \
si_shader_internal.h \
si_shader_nir.c \
si_shader_tgsi_alu.c \
si_shader_tgsi_mem.c \
si_shader_tgsi_setup.c \
si_state.c \
+   si_state_binning.c \
si_state_draw.c \
si_state_shaders.c \
si_state.h \
si_uvd.c
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c 
b/src/gallium/drivers/radeonsi/si_hw_context.c
index f3af8dc..d090eea 100644
--- a/src/gallium/drivers/radeonsi/si_hw_context.c
+++ b/src/gallium/drivers/radeonsi/si_hw_context.c
@@ -232,20 +232,22 @@ void si_begin_new_cs(struct si_context *ctx)
si_mark_atom_dirty(ctx, >msaa_sample_locs.atom);
si_mark_atom_dirty(ctx, >msaa_config);
/* CLEAR_STATE sets 0x. */
if (!has_clear_state || ctx->sample_mask.sample_mask != 0x)
si_mark_atom_dirty(ctx, >sample_mask.atom);
si_mark_atom_dirty(ctx, >cb_render_state);
/* CLEAR_STATE sets zeros. */
if (!has_clear_state || ctx->blend_color.any_nonzeros)
si_mark_atom_dirty(ctx, >blend_color.atom);
si_mark_atom_dirty(ctx, >db_render_state);
+   if (ctx->b.chip_class >= GFX9)
+   si_mark_atom_dirty(ctx, 

[Mesa-dev] [PATCH 2/3] radeonsi: add more state flags into si_state_dsa

[Marek Olšák]

From: Marek Olšák 

3 flags for primitive binning, 2 flags for out-of-order rasterization
(but that will be done some other time)
---
 src/gallium/drivers/radeonsi/si_state.c | 17 +
 src/gallium/drivers/radeonsi/si_state.h |  7 ++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 2edd982..076b583 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1037,20 +1037,28 @@ static uint32_t si_translate_stencil_op(int s_op)
case PIPE_STENCIL_OP_INVERT:
return V_02842C_STENCIL_INVERT;
default:
R600_ERR("Unknown stencil op %d", s_op);
assert(0);
break;
}
return 0;
 }
 
+static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
+{
+   return s->enabled && s->writemask &&
+  (s->fail_op  != PIPE_STENCIL_OP_KEEP ||
+   s->zfail_op != PIPE_STENCIL_OP_KEEP ||
+   s->zpass_op != PIPE_STENCIL_OP_KEEP);
+}
+
 static void *si_create_dsa_state(struct pipe_context *ctx,
 const struct pipe_depth_stencil_alpha_state 
*state)
 {
struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
struct si_pm4_state *pm4 = >pm4;
unsigned db_depth_control;
uint32_t db_stencil_control = 0;
 
if (!dsa) {
return NULL;
@@ -1094,20 +1102,29 @@ static void *si_create_dsa_state(struct pipe_context 
*ctx,
}
 
si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
if (state->stencil[0].enabled)
si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, 
db_stencil_control);
if (state->depth.bounds_test) {
si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 
fui(state->depth.bounds_min));
si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 
fui(state->depth.bounds_max));
}
 
+   dsa->depth_enabled = state->depth.enabled;
+   dsa->depth_write_enabled = state->depth.enabled &&
+  state->depth.writemask;
+   dsa->stencil_enabled = state->stencil[0].enabled;
+   dsa->stencil_write_enabled = state->stencil[0].enabled &&
+(si_dsa_writes_stencil(>stencil[0]) 
||
+ 
si_dsa_writes_stencil(>stencil[1]));
+   dsa->db_can_write = dsa->depth_write_enabled ||
+   dsa->stencil_write_enabled;
return dsa;
 }
 
 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
 {
 struct si_context *sctx = (struct si_context *)ctx;
struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
 struct si_state_dsa *dsa = state;
 
 if (!state)
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index 7b7d96c..9770960 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -84,22 +84,27 @@ struct si_state_rasterizer {
unsignedclip_halfz:1;
 };
 
 struct si_dsa_stencil_ref_part {
uint8_t valuemask[2];
uint8_t writemask[2];
 };
 
 struct si_state_dsa {
struct si_pm4_state pm4;
-   unsignedalpha_func;
struct si_dsa_stencil_ref_part  stencil_ref;
+   ubyte   alpha_func:3;
+   booldepth_enabled:1;
+   booldepth_write_enabled:1;
+   boolstencil_enabled:1;
+   boolstencil_write_enabled:1;
+   booldb_can_write:1;
 };
 
 struct si_stencil_ref {
struct r600_atomatom;
struct pipe_stencil_ref state;
struct si_dsa_stencil_ref_part  dsa_part;
 };
 
 struct si_vertex_elements
 {
-- 
2.7.4

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[Mesa-dev] [PATCH 1/3] radeonsi/gfx9: don't use BREAK_BATCH and FLUSH_DFSM if DFSM is disabled

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_pipe.h  | 1 +
 src/gallium/drivers/radeonsi/si_state.c | 6 +++---
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index 386a6dc..0228b32 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -89,20 +89,21 @@ struct u_suballocator;
 
 struct si_screen {
struct r600_common_screen   b;
unsignedgs_table_depth;
unsignedtess_offchip_block_dw_size;
boolhas_clear_state;
boolhas_distributed_tess;
boolhas_draw_indirect_multi;
boolhas_ds_bpermute;
boolhas_msaa_sample_loc_bug;
+   booldfsm_allowed;
boolllvm_has_working_vgpr_indexing;
 
/* Whether shaders are monolithic (1-part) or separate (3-part). */
booluse_monolithic_shaders;
boolrecord_llvm_ir;
 
mtx_t   shader_parts_mutex;
struct si_shader_part   *vs_prologs;
struct si_shader_part   *tcs_epilogs;
struct si_shader_part   *gs_prologs;
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 5ee8bb9..2edd982 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -108,21 +108,21 @@ static void si_emit_cb_render_state(struct si_context 
*sctx, struct r600_atom *a
if (blend && blend->dual_src_blend &&
sctx->ps_shader.cso &&
(sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
cb_target_mask = 0;
 
radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
 
/* GFX9: Flush DFSM when CB_TARGET_MASK changes.
 * I think we don't have to do anything between IBs.
 */
-   if (sctx->b.chip_class >= GFX9 &&
+   if (sctx->screen->dfsm_allowed &&
sctx->last_cb_target_mask != cb_target_mask) {
sctx->last_cb_target_mask = cb_target_mask;
 
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | 
EVENT_INDEX(0));
}
 
/* RB+ register settings. */
if (sctx->screen->b.rbplus_allowed) {
unsigned spi_shader_col_format =
@@ -2952,21 +2952,21 @@ static void si_emit_framebuffer_state(struct si_context 
*sctx, struct r600_atom
 
radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* 
DB_Z_INFO */
radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* 
DB_STENCIL_INFO */
}
 
/* Framebuffer dimensions. */
 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
   S_028208_BR_X(state->width) | 
S_028208_BR_Y(state->height));
 
-   if (sctx->b.chip_class >= GFX9) {
+   if (sctx->screen->dfsm_allowed) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | 
EVENT_INDEX(0));
}
 
sctx->framebuffer.dirty_cbufs = 0;
sctx->framebuffer.dirty_zsbuf = false;
 }
 
 static void si_emit_msaa_sample_locs(struct si_context *sctx,
 struct r600_atom *atom)
@@ -3030,21 +3030,21 @@ static void si_emit_msaa_config(struct si_context 
*sctx, struct r600_atom *atom)
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
S_028A4C_FORCE_EOV_REZ_ENABLE(1);
 
cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
sctx->ps_iter_samples,
sctx->smoothing_enabled ? 
SI_NUM_SMOOTH_AA_SAMPLES : 0,
sc_mode_cntl_1);
 
/* GFX9: Flush DFSM when the AA mode changes. */
-   if (sctx->b.chip_class >= GFX9) {
+   if (sctx->screen->dfsm_allowed) {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | 
EVENT_INDEX(0));
}
 }
 
 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
 {
struct si_context *sctx = (struct si_context *)ctx;
 
if (sctx->ps_iter_samples == min_samples)
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] st/mesa: fix view template initialization in try_pbo_readpixels

[Brian Paul]

On 08/31/2017 05:53 PM, srol...@vmware.com wrote:

From: Roland Scheidegger 

I think this is what the code was meant to do, albeit as far as I can tell
the redundant initialization some analyzers complain about should work as
well just fine (only the first layer will be used, if the view contains one
or more layers doesn't really matter).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102467
---
  src/mesa/state_tracker/st_cb_readpixels.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_cb_readpixels.c 
b/src/mesa/state_tracker/st_cb_readpixels.c
index 0bcf2eb..84dd2d5 100644
--- a/src/mesa/state_tracker/st_cb_readpixels.c
+++ b/src/mesa/state_tracker/st_cb_readpixels.c
@@ -175,7 +175,7 @@ try_pbo_readpixels(struct st_context *st, struct 
st_renderbuffer *strb,

if (view_target != PIPE_TEXTURE_3D) {
   templ.u.tex.first_layer = surface->u.tex.first_layer;
- templ.u.tex.last_layer = templ.u.tex.last_layer;
+ templ.u.tex.last_layer = templ.u.tex.first_layer;
} else {
   addr.constants.layer_offset = surface->u.tex.first_layer;
}



Reviewed-by: Brian Paul 

Add cc for stable branch?

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[Mesa-dev] [PATCH] st/mesa: fix view template initialization in try_pbo_readpixels

[sroland]

From: Roland Scheidegger 

I think this is what the code was meant to do, albeit as far as I can tell
the redundant initialization some analyzers complain about should work as
well just fine (only the first layer will be used, if the view contains one
or more layers doesn't really matter).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102467
---
 src/mesa/state_tracker/st_cb_readpixels.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_cb_readpixels.c 
b/src/mesa/state_tracker/st_cb_readpixels.c
index 0bcf2eb..84dd2d5 100644
--- a/src/mesa/state_tracker/st_cb_readpixels.c
+++ b/src/mesa/state_tracker/st_cb_readpixels.c
@@ -175,7 +175,7 @@ try_pbo_readpixels(struct st_context *st, struct 
st_renderbuffer *strb,
 
   if (view_target != PIPE_TEXTURE_3D) {
  templ.u.tex.first_layer = surface->u.tex.first_layer;
- templ.u.tex.last_layer = templ.u.tex.last_layer;
+ templ.u.tex.last_layer = templ.u.tex.first_layer;
   } else {
  addr.constants.layer_offset = surface->u.tex.first_layer;
   }
-- 
2.7.4

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[Mesa-dev] [Bug 102502] [bisected] Kodi crashes since commit 707d2e8b - gallium: fold u_trim_pipe_prim call from st/mesa to drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102502

Alexandre Demers  changed:

   What|Removed |Added

 CC||alexandre.f.dem...@gmail.co
   ||m, bri...@vmware.com,
   ||mar...@gmail.com

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[Mesa-dev] [Bug 102502] [bisected] Kodi crashes since commit 707d2e8b - gallium: fold u_trim_pipe_prim call from st/mesa to drivers

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102502

Bug ID: 102502
   Summary: [bisected] Kodi crashes since commit 707d2e8b -
gallium: fold u_trim_pipe_prim call from st/mesa to
drivers
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: alexandre.f.dem...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

I noticed Kodi 17 crashing in the last few weeks. Kodi spits the following
backtrace when segfaulting:

Thread debugging using libthread_db enabled]
Using host libthread_db library "/usr/lib/libthread_db.so.1".
Core was generated by `/usr/lib/kodi/kodi.bin'.
Program terminated with signal SIGSEGV, Segmentation fault.
#0  0x7fe6734f8670 in __memcpy_ssse3 () from /usr/lib/libc.so.6
[Current thread is 1 (Thread 0x7fe67aa4a540 (LWP 7020))]
[...]
Thread 1 (Thread 0x7fe67aa4a540 (LWP 7020)):
#0  0x7fe6734f8670 in __memcpy_ssse3 () from /usr/lib/libc.so.6
#1  0x7fe6374624fd in u_upload_data (upload=0x55d0709e65d0,
min_out_offset=0, size=4294967288, alignment=4, data=0x55d070d61130,
out_offset=0x55d070af4424, outbuf=0x55d070af4428) at
../../../.././src/gallium/auxiliary/util/u_upload_mgr.c:267
#2  0x7fe637465444 in u_vbuf_upload_buffers (mgr=0x55d070af3c10,
start_vertex=0, num_vertices=0, start_instance=0, num_instances=1) at
../../../.././src/gallium/auxiliary/util/u_vbuf.c:990
#3  0x7fe637465fcf in u_vbuf_draw_vbo (mgr=0x55d070af3c10,
info=0x7ffc5a42e7e0) at ../../../.././src/gallium/auxiliary/util/u_vbuf.c:1265
#4  0x7fe6373aa746 in cso_draw_vbo (cso=0x55d070b27e70,
info=0x7ffc5a42e7e0) at
../../../.././src/gallium/auxiliary/cso_cache/cso_context.c:1730
#5  0x7fe63717a503 in st_draw_vbo (ctx=0x55d070ac5d10,
prims=0x7ffc5a42e8c0, nr_prims=1, ib=0x0, index_bounds_valid=1 '\001',
min_index=0, max_index=4294967295, tfb_vertcount=0x0, stream=0, indirect=0x0)
at ../../.././src/mesa/state_tracker/st_draw.c:255
#6  0x7fe63711d71a in vbo_draw_arrays (ctx=0x55d070ac5d10, mode=7, start=0,
count=0, numInstances=1, baseInstance=0, drawID=0) at
../../.././src/mesa/vbo/vbo_exec_array.c:486
#7  0x7fe63711df1e in vbo_exec_DrawArrays (mode=7, start=0, count=0) at
../../.././src/mesa/vbo/vbo_exec_array.c:641
#8  0x55d06dff63d9 in CGUIFontTTFGL::LastEnd() ()
#9  0x55d06dfb6772 in CGUITextLayout::Render(float, float, float, unsigned
int, unsigned int, unsigned int, float, bool) ()
#10 0x55d06df26367 in CGUIControl::DoRender() ()
#11 0x55d06df3c8a0 in CGUIControlGroupList::Render() ()
#12 0x55d06df26367 in CGUIControl::DoRender() ()
#13 0x55d06df3c8a0 in CGUIControlGroupList::Render() ()
#14 0x55d06df26367 in CGUIControl::DoRender() ()
#15 0x55d06df38c2e in CGUIControlGroup::Render() ()
#16 0x55d06df26367 in CGUIControl::DoRender() ()
#17 0x55d06df38c2e in CGUIControlGroup::Render() ()
#18 0x55d06df26367 in CGUIControl::DoRender() ()
#19 0x55d06df38c2e in CGUIControlGroup::Render() ()
#20 0x55d06df26367 in CGUIControl::DoRender() ()
#21 0x55d06df38c2e in CGUIControlGroup::Render() ()
#22 0x55d06df26367 in CGUIControl::DoRender() ()
#23 0x55d06df38c2e in CGUIControlGroup::Render() ()
#24 0x55d06df26367 in CGUIControl::DoRender() ()
#25 0x55d06dfc4ddf in CGUIWindow::DoRender() ()
#26 0x55d06dfce19c in CGUIWindowManager::RenderPass() const ()
#27 0x55d06dfce565 in CGUIWindowManager::Render() ()
#28 0x55d06e1940fe in CApplication::Render() ()
#29 0x55d06e2632ab in CXBApplicationEx::Run(CFileItemList&) ()
#30 0x55d06de9705a in XBMC_Run ()
#31 0x55d06d9143ac in main ()
# END STACK TRACE ###


After investigation and bisection, I ended up with:
707d2e8b3e53c761720adaca7137b242dff344b6 is the first bad commit
commit 707d2e8b3e53c761720adaca7137b242dff344b6
Author: Marek Olšák 
Date:   Sun Apr 9 15:57:45 2017 +0200

gallium: fold u_trim_pipe_prim call from st/mesa to drivers

Most drivers don't need it and shouldn't need it because it can't be used
in some cases (indirect draws, primitive restart, count from streamout).

Reviewed-by: Brian Paul 

:04 04 91dbfe3f2d3d2d6c3a5169dd76d07a7f5812c2f5
c876ef71cf4d79da0e099ad4e695cf529118d498 M  src

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[Mesa-dev] [PATCH] intel/eu/validate: Look up types on demand in execution_type()

[Jason Ekstrand]

We are looking up the execution type prior to checking how many sources
we have.  This leads to looking for a type for src1 on MOV instructions
which is bogus.  On BDW+, the src1 register type overlaps with the
64-bit immediate and causes us problems.
---
 src/intel/compiler/brw_eu_validate.c | 6 ++
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/intel/compiler/brw_eu_validate.c 
b/src/intel/compiler/brw_eu_validate.c
index 249342f..d72c0a0 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -300,15 +300,13 @@ execution_type(const struct gen_device_info *devinfo, 
const brw_inst *inst)
 {
unsigned num_sources = num_sources_from_inst(devinfo, inst);
enum brw_reg_type src0_exec_type, src1_exec_type;
-   enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst);
-   enum brw_reg_type src1_type = brw_inst_src1_type(devinfo, inst);
 
/* Execution data type is independent of destination data type, except in
 * mixed F/HF instructions on CHV and SKL+.
 */
enum brw_reg_type dst_exec_type = brw_inst_dst_type(devinfo, inst);
 
-   src0_exec_type = execution_type_for_type(src0_type);
+   src0_exec_type = execution_type_for_type(brw_inst_src0_type(devinfo, inst));
if (num_sources == 1) {
   if ((devinfo->gen >= 9 || devinfo->is_cherryview) &&
   src0_exec_type == BRW_REGISTER_TYPE_HF) {
@@ -317,7 +315,7 @@ execution_type(const struct gen_device_info *devinfo, const 
brw_inst *inst)
   return src0_exec_type;
}
 
-   src1_exec_type = execution_type_for_type(src1_type);
+   src1_exec_type = execution_type_for_type(brw_inst_src1_type(devinfo, inst));
if (src0_exec_type == src1_exec_type)
   return src0_exec_type;
 
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH] m4: Use older autoconf 2.63 compatible ax_check_compile_flag.

[Vinson Lee]

CentOS 6 and RHEL 6 have autoconf 2.63.

Fixes: e4b2b69e828c ("configure: Add and use AX_CHECK_COMPILE_FLAG")
Signed-off-by: Vinson Lee 
---
 m4/ax_check_compile_flag.m4 |   10 +-
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/m4/ax_check_compile_flag.m4 b/m4/ax_check_compile_flag.m4
index dcabb92..51df0c0 100644
--- a/m4/ax_check_compile_flag.m4
+++ b/m4/ax_check_compile_flag.m4
@@ -1,5 +1,5 @@
 # ===
-#  https://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html
+#   http://www.gnu.org/software/autoconf-archive/ax_check_compile_flag.html
 # ===
 #
 # SYNOPSIS
@@ -40,7 +40,7 @@
 #   Public License for more details.
 #
 #   You should have received a copy of the GNU General Public License along
-#   with this program. If not, see .
+#   with this program. If not, see .
 #
 #   As a special exception, the respective Autoconf Macro's copyright owner
 #   gives unlimited permission to copy, distribute and modify the configure
@@ -55,10 +55,10 @@
 #   modified version of the Autoconf Macro, you may extend this special
 #   exception to the GPL to apply to your modified version as well.
 
-#serial 5
+#serial 3
 
 AC_DEFUN([AX_CHECK_COMPILE_FLAG],
-[AC_PREREQ(2.64)dnl for _AC_LANG_PREFIX and AS_VAR_IF
+[AC_PREREQ(2.59)dnl for _AC_LANG_PREFIX
 AS_VAR_PUSHDEF([CACHEVAR],[ax_cv_check_[]_AC_LANG_ABBREV[]flags_$4_$1])dnl
 AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], CACHEVAR, [
   ax_check_save_flags=$[]_AC_LANG_PREFIX[]FLAGS
@@ -67,7 +67,7 @@ AC_CACHE_CHECK([whether _AC_LANG compiler accepts $1], 
CACHEVAR, [
 [AS_VAR_SET(CACHEVAR,[yes])],
 [AS_VAR_SET(CACHEVAR,[no])])
   _AC_LANG_PREFIX[]FLAGS=$ax_check_save_flags])
-AS_VAR_IF(CACHEVAR,yes,
+AS_IF([test x"AS_VAR_GET(CACHEVAR)" = xyes],
   [m4_default([$2], :)],
   [m4_default([$3], :)])
 AS_VAR_POPDEF([CACHEVAR])dnl
-- 
1.7.1

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Re: [Mesa-dev] [PATCH 1/5] intel/eu: Use EXECUTE_1 for JMPI

[Matt Turner]

On Thu, Aug 31, 2017 at 2:25 PM, Jason Ekstrand  wrote:
> There doesn't seem to be a good reason for using EXECUTE_2 for JMPI and
> brw_fs_generator manually stomps it to 1.  This is a functional change
> because it changes all of the clip and SF programs on gen4-5 to use
> EXECUTE_1 for JMPI.  Piglit says that this is ok.

The PRM says "The execution size must be 1."

> ---
>  src/intel/compiler/brw_eu_emit.c| 2 +-
>  src/intel/compiler/brw_fs_generator.cpp | 1 -
>  2 files changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/src/intel/compiler/brw_eu_emit.c 
> b/src/intel/compiler/brw_eu_emit.c
> index 8c952e7..ada550c 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -1183,7 +1183,7 @@ brw_JMPI(struct brw_codegen *p, struct brw_reg index,
> struct brw_reg ip = brw_ip_reg();
> brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
>
> -   brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_2);
> +   brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_1);

This is fixing a bug added in 2009 in commit
73137997e23ff6c1145d036315d1a9ad96651281

| insn->header.execution_size = 1;

But the execution size encodings are

   BRW_EXECUTE_1  = 0,
   BRW_EXECUTE_2  = 1,
   BRW_EXECUTE_4  = 2,

etc.

With an updated commit message that contains this information:

Reviewed-by: Matt Turner 
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Re: [Mesa-dev] [PATCH] anv/formats: Nicely handle unknown VkFormat enums

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 31/08/17 22:10, Jason Ekstrand wrote:

This fixes some crashes in the dEQP-VK.memory.requirements.core.* tests.
I'm not sure whether or not passing out-of-bound formats into the query
is supposed to be allowed but there's no harm in protecting ourselves
from it.

Bugzilla: https://bugs.freedesktop.org/101956
Cc: mesa-sta...@lists.freedesktop.org
---
  src/intel/vulkan/anv_formats.c | 19 ++-
  1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 6ce609a..c23b143 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -250,6 +250,15 @@ static const struct anv_format anv_formats[] = {
  
  #undef fmt
  
+static bool

+format_supported(VkFormat vk_format)
+{
+   if (vk_format > ARRAY_SIZE(anv_formats))
+  return false;
+
+   return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
+}
+
  /**
   * Exactly one bit must be set in \a aspect.
   */
@@ -257,10 +266,10 @@ struct anv_format
  anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
 VkImageAspectFlags aspect, VkImageTiling tiling)
  {
-   struct anv_format format = anv_formats[vk_format];
+   if (!format_supported(vk_format))
+  return anv_formats[VK_FORMAT_UNDEFINED];
  
-   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)

-  return format;
+   struct anv_format format = anv_formats[vk_format];
  
 if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {

assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
@@ -391,7 +400,7 @@ anv_physical_device_get_format_properties(struct 
anv_physical_device *physical_d
gen += 5;
  
 VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0;

-   if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED) {
+   if (!format_supported(format)) {
/* Nothing to do here */
 } else if (vk_format_is_depth_or_stencil(format)) {
tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
@@ -489,7 +498,7 @@ anv_get_image_format_properties(
 uint32_t maxArraySize;
 VkSampleCountFlags sampleCounts = VK_SAMPLE_COUNT_1_BIT;
  
-   if (anv_formats[info->format].isl_format == ISL_FORMAT_UNSUPPORTED)

+   if (!format_supported(info->format))
goto unsupported;
  
 anv_physical_device_get_format_properties(physical_device, info->format,



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[Mesa-dev] [PATCH 5/5] intel/fs: Don't use automatic exec size inference

[Jason Ekstrand]

The automatic exec size inference can accidentally mess things up if
we're not careful.  For instance, if we have

add(4)g38.2<4>Dg38.1<8,2,4>Dg38.2<8,2,4>D

then the destination register will end up having a width of 2 with a
horizontal stride of 4 and a vertical stride of 8.  The EU emit code
sees the width of 2 and decides that we really wanted an exec size of 2
which doesn't do what we wanted.
---
 src/intel/compiler/brw_fs_generator.cpp | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index ad6b0fc..5d332e9 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -190,6 +190,12 @@ fs_generator::fs_generator(const struct brw_compiler 
*compiler, void *log_data,
 {
p = rzalloc(mem_ctx, struct brw_codegen);
brw_init_codegen(devinfo, p, mem_ctx);
+
+   /* In the FS code generator, we are very careful to ensure that we always
+* set the right execution size so we don't need the EU code to "help" us
+* by trying to infer it.  Sometimes, it infers the wrong thing.
+*/
+   p->automatic_exec_sizes = false;
 }
 
 fs_generator::~fs_generator()
@@ -395,17 +401,17 @@ fs_generator::generate_fb_write(fs_inst *inst, struct 
brw_reg payload)
   struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), 
BRW_REGISTER_TYPE_UD));
 
   /* Check runtime bit to detect if we have to send AA data or not */
-  brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
   brw_push_insn_state(p);
-  brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
+  brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_AND(p,
   v1_null_ud,
   retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
   brw_imm_ud(1<<26));
   brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, 
BRW_CONDITIONAL_NZ);
-  brw_pop_insn_state(p);
 
   int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
+  brw_pop_insn_state(p);
   {
  /* Don't send AA data */
  fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 2/5] intel/eu: Make automatic exec sizes a configurable option

[Jason Ekstrand]

We have had a feature in codegen for some time that tries to
automatically infer the execution size of an instruction from the width
of its destination.  For things such as fixed function GS, clipper, and
SF programs, this is very useful because they tend to have lots of
hand-rolled register setup and trying to specify the exec size all the
time would be prohibitive.  For things that come from a higher-level IR,
however, it's easier to just set the right size all the time and the
automatic exec sizes can, in fact, cause problems.  This commit makes it
optional while enabling it by default.
---
 src/intel/compiler/brw_eu.c  |  1 +
 src/intel/compiler/brw_eu.h  | 10 ++
 src/intel/compiler/brw_eu_emit.c | 32 ++--
 3 files changed, 29 insertions(+), 14 deletions(-)

diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index b0bdc38..bc297a2 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -296,6 +296,7 @@ brw_init_codegen(const struct gen_device_info *devinfo,
memset(p, 0, sizeof(*p));
 
p->devinfo = devinfo;
+   p->automatic_exec_sizes = true;
/*
 * Set the initial instruction store array size to 1024, if found that
 * isn't enough, then it will double the store size at brw_next_insn()
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 8e597b2..8abebeb 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -65,6 +65,16 @@ struct brw_codegen {
bool compressed_stack[BRW_EU_MAX_INSN_STACK];
brw_inst *current;
 
+   /** Whether or not the user wants automatic exec sizes
+*
+* If true, codegen will try to automatically infer the exec size of an
+* instruction from the width of the destination register.  If false, it
+* will take whatever is set by brw_set_default_exec_size verbatim.
+*
+* This is set to true by default in brw_init_codegen.
+*/
+   bool automatic_exec_sizes;
+
bool single_program_flow;
const struct gen_device_info *devinfo;
 
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ada550c..0e36544 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -141,22 +141,26 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, 
struct brw_reg dest)
 
/* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
 * or 16 (SIMD16), as that's normally correct.  However, when dealing with
-* small registers, we automatically reduce it to match the register size.
-*
-* In platforms that support fp64 we can emit instructions with a width of
-* 4 that need two SIMD8 registers and an exec_size of 8 or 16. In these
-* cases we need to make sure that these instructions have their exec sizes
-* set properly when they are emitted and we can't rely on this code to fix
-* it.
+* small registers, it can be useful for us toautomatically reduce it to
+* match the register size.
 */
-   bool fix_exec_size;
-   if (devinfo->gen >= 6)
-  fix_exec_size = dest.width < BRW_EXECUTE_4;
-   else
-  fix_exec_size = dest.width < BRW_EXECUTE_8;
+   if (p->automatic_exec_sizes) {
+  /*
+   * In platforms that support fp64 we can emit instructions with a width
+   * of 4 that need two SIMD8 registers and an exec_size of 8 or 16. In
+   * these cases we need to make sure that these instructions have their
+   * exec sizes set properly when they are emitted and we can't rely on
+   * this code to fix it.
+   */
+  bool fix_exec_size;
+  if (devinfo->gen >= 6)
+ fix_exec_size = dest.width < BRW_EXECUTE_4;
+  else
+ fix_exec_size = dest.width < BRW_EXECUTE_8;
 
-   if (fix_exec_size)
-  brw_inst_set_exec_size(devinfo, inst, dest.width);
+  if (fix_exec_size)
+ brw_inst_set_exec_size(devinfo, inst, dest.width);
+   }
 }
 
 static void
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 1/5] intel/eu: Use EXECUTE_1 for JMPI

[Jason Ekstrand]

There doesn't seem to be a good reason for using EXECUTE_2 for JMPI and
brw_fs_generator manually stomps it to 1.  This is a functional change
because it changes all of the clip and SF programs on gen4-5 to use
EXECUTE_1 for JMPI.  Piglit says that this is ok.
---
 src/intel/compiler/brw_eu_emit.c| 2 +-
 src/intel/compiler/brw_fs_generator.cpp | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 8c952e7..ada550c 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1183,7 +1183,7 @@ brw_JMPI(struct brw_codegen *p, struct brw_reg index,
struct brw_reg ip = brw_ip_reg();
brw_inst *inst = brw_alu2(p, BRW_OPCODE_JMPI, ip, ip, index);
 
-   brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_2);
+   brw_inst_set_exec_size(devinfo, inst, BRW_EXECUTE_1);
brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
brw_inst_set_mask_control(devinfo, inst, BRW_MASK_DISABLE);
brw_inst_set_pred_control(devinfo, inst, predicate_control);
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index afaec5c..3f109f3 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -402,7 +402,6 @@ fs_generator::generate_fb_write(fs_inst *inst, struct 
brw_reg payload)
   brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, 
BRW_CONDITIONAL_NZ);
 
   int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
-  brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
   {
  /* Don't send AA data */
  fire_fb_write(inst, offset(payload, 1), implied_header, inst->mlen-1);
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 4/5] intel/fs: Explicitly set EXECUTE_1 where needed

[Jason Ekstrand]

---
 src/intel/compiler/brw_fs.cpp   | 2 +-
 src/intel/compiler/brw_fs_generator.cpp | 8 
 src/intel/compiler/brw_fs_visitor.cpp   | 7 +++
 3 files changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index eb9b4c3..1c49b5a 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -4269,7 +4269,7 @@ emit_surface_header(const fs_builder , const fs_reg 
_mask)
fs_builder ubld = bld.exec_all().group(8, 0);
const fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_UD);
ubld.MOV(dst, brw_imm_d(0));
-   ubld.MOV(component(dst, 7), sample_mask);
+   ubld.group(1, 0).MOV(component(dst, 7), sample_mask);
return dst;
 }
 
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 3f109f3..ad6b0fc 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -323,6 +323,7 @@ fs_generator::generate_fb_write(fs_inst *inst, struct 
brw_reg payload)
if (inst->header_size != 0) {
   brw_push_insn_state(p);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
   brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
   brw_set_default_flag_reg(p, 0, 0);
@@ -395,11 +396,14 @@ fs_generator::generate_fb_write(fs_inst *inst, struct 
brw_reg payload)
 
   /* Check runtime bit to detect if we have to send AA data or not */
   brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+  brw_push_insn_state(p);
+  brw_inst_set_exec_size(p->devinfo, brw_last_inst, BRW_EXECUTE_1);
   brw_AND(p,
   v1_null_ud,
   retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD),
   brw_imm_ud(1<<26));
   brw_inst_set_cond_modifier(p->devinfo, brw_last_inst, 
BRW_CONDITIONAL_NZ);
+  brw_pop_insn_state(p);
 
   int jmp = brw_JMPI(p, brw_imm_ud(0), BRW_PREDICATE_NORMAL) - p->store;
   {
@@ -941,6 +945,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
  /* Explicitly set up the message header by copying g0 to the MRF. */
  brw_MOV(p, header_reg, brw_vec8_grf(0, 0));
 
+ /* The rest of header setup is one channel at a time. */
+ brw_set_default_exec_size(p, BRW_EXECUTE_1);
  if (inst->offset) {
 /* Set the offset bits in DWord 2. */
 brw_MOV(p, get_element_ud(header_reg, 2),
@@ -994,6 +1000,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
   brw_push_insn_state(p);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
   brw_set_default_access_mode(p, BRW_ALIGN_1);
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
 
   if (brw_regs_equal(_reg, _reg)) {
  brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
@@ -1441,6 +1448,7 @@ fs_generator::generate_mov_dispatch_to_flags(fs_inst 
*inst)
 
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+   brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_MOV(p, flags, dispatch_mask);
brw_pop_insn_state(p);
 }
diff --git a/src/intel/compiler/brw_fs_visitor.cpp 
b/src/intel/compiler/brw_fs_visitor.cpp
index 758c8bf..394d978 100644
--- a/src/intel/compiler/brw_fs_visitor.cpp
+++ b/src/intel/compiler/brw_fs_visitor.cpp
@@ -786,14 +786,13 @@ fs_visitor::emit_barrier()
 
fs_reg payload = fs_reg(VGRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
 
-   const fs_builder pbld = bld.exec_all().group(8, 0);
-
/* Clear the message payload */
-   pbld.MOV(payload, brw_imm_ud(0u));
+   bld.exec_all().group(8, 0).MOV(payload, brw_imm_ud(0u));
 
/* Copy the barrier id from r0.2 to the message payload reg.2 */
fs_reg r0_2 = fs_reg(retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD));
-   pbld.AND(component(payload, 2), r0_2, brw_imm_ud(barrier_id_mask));
+   bld.exec_all().group(1, 0).AND(component(payload, 2), r0_2,
+  brw_imm_ud(barrier_id_mask));
 
/* Emit a gateway "barrier" message using the payload we set up, followed
 * by a wait instruction.
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 3/5] intel/eu: Explicitly set EXECUTE_1 where needed

[Jason Ekstrand]

---
 src/intel/compiler/brw_eu_emit.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 0e36544..7ed4fb8 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -1976,6 +1976,7 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
   brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 
   /* set message header global offset field (reg 0, element 2) */
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_MOV(p,
  retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
  mrf.nr,
@@ -2095,6 +2096,7 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
   brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 
   /* set message header global offset field (reg 0, element 2) */
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_MOV(p, get_element_ud(mrf, 2), brw_imm_ud(offset));
 
   brw_pop_insn_state(p);
@@ -2193,6 +2195,7 @@ void brw_oword_block_read(struct brw_codegen *p,
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
 
/* set message header global offset field (reg 0, element 2) */
+   brw_set_default_exec_size(p, BRW_EXECUTE_1);
brw_MOV(p,
   retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
   mrf.nr,
@@ -2441,6 +2444,7 @@ void brw_urb_WRITE(struct brw_codegen *p,
   brw_push_insn_state(p);
   brw_set_default_access_mode(p, BRW_ALIGN_1);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
   BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
@@ -2500,6 +2504,7 @@ brw_send_indirect_message(struct brw_codegen *p,
   brw_push_insn_state(p);
   brw_set_default_access_mode(p, BRW_ALIGN_1);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
 
   /* Load the indirect descriptor to an address register using OR so the
@@ -2544,6 +2549,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
   brw_push_insn_state(p);
   brw_set_default_access_mode(p, BRW_ALIGN_1);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_exec_size(p, BRW_EXECUTE_1);
   brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
 
   /* Mask out invalid bits from the surface index to avoid hangs e.g. when
@@ -3271,6 +3277,7 @@ brw_find_live_channel(struct brw_codegen *p, struct 
brw_reg dst,
  struct brw_reg exec_mask =
 retype(brw_mask_reg(0), BRW_REGISTER_TYPE_UD);
 
+ brw_set_default_exec_size(p, BRW_EXECUTE_1);
  if (mask.file != BRW_IMMEDIATE_VALUE || mask.ud != 0x) {
 /* Unfortunately, ce0 does not take into account the thread
  * dispatch mask, which may be a problem in cases where it's not
@@ -3292,6 +3299,7 @@ brw_find_live_channel(struct brw_codegen *p, struct 
brw_reg dst,
   } else {
  const struct brw_reg flag = brw_flag_reg(1, 0);
 
+ brw_set_default_exec_size(p, BRW_EXECUTE_1);
  brw_MOV(p, retype(flag, BRW_REGISTER_TYPE_UD), brw_imm_ud(0));
 
  /* Run enough instructions returning zero with execution masking and
@@ -3317,6 +3325,7 @@ brw_find_live_channel(struct brw_codegen *p, struct 
brw_reg dst,
   * instructions.
   */
  const enum brw_reg_type type = brw_int_type(exec_size / 8, false);
+ brw_set_default_exec_size(p, BRW_EXECUTE_1);
  brw_FBL(p, vec1(dst), byte_offset(retype(flag, type), qtr_control));
   }
} else {
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH] radv: silent a compiler warning in radv_emit_framebuffer_state()

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Mon, Aug 28, 2017, at 12:17, Samuel Pitoiset wrote:
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index fcc14dd936..b567bee329 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1240,9 +1240,9 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer
> *cmd_buffer)
>   struct radv_attachment_info *att = 
> >attachments[idx];
>   struct radv_image *image = att->attachment->image;
>   cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, 
> att->attachment->bo, 8);
> -   uint32_t queue_mask = radv_image_queue_family_mask(image,
> - 
> cmd_buffer->queue_family_index,
> - 
> cmd_buffer->queue_family_index);
> +   MAYBE_UNUSED uint32_t queue_mask =
> radv_image_queue_family_mask(image,
> +
>   cmd_buffer->queue_family_index,
> +
>   cmd_buffer->queue_family_index);
>   /* We currently don't support writing decompressed HTILE */
>   assert(radv_layout_has_htile(image, layout, queue_mask) ==
>  radv_layout_is_htile_compressed(image, layout, 
> queue_mask));
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH 3/3] radv: report VM faults if detected

[Bas Nieuwenhuizen]

This series is:

Reviewed-by: Bas Nieuwenhuizen 

Awesome to see this implemented!

On Thu, Aug 31, 2017, at 11:44, Samuel Pitoiset wrote:
> It's fairly simple for now, but this might be quite useful.
> 
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_debug.c   | 13 +
>  src/amd/vulkan/radv_private.h |  3 +++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
> index 4024f75da8..949eeea2f3 100644
> --- a/src/amd/vulkan/radv_debug.c
> +++ b/src/amd/vulkan/radv_debug.c
> @@ -28,6 +28,7 @@
>  #include 
>  #include 
>  
> +#include "ac_debug.h"
>  #include "radv_debug.h"
>  
>  bool
> @@ -44,6 +45,9 @@ radv_init_trace(struct radv_device *device)
>   if (!device->trace_id_ptr)
>   return false;
>  
> +   ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
> +   >dmesg_timestamp, NULL);
> +
>   return true;
>  }
>  
> @@ -80,9 +84,18 @@ radv_gpu_hang_occured(struct radv_queue *queue)
>  void
>  radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs
>  *cs)
>  {
> +   struct radv_device *device = queue->device;
> +   uint64_t addr;
> +
>   if (!radv_gpu_hang_occured(queue))
>   return;
>  
> +   if
> (ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
> +   >dmesg_timestamp, )) {
> +   fprintf(stderr, "VM fault report.\n\n");
> +   fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n",
> addr);
> +   }
> +
>   radv_dump_trace(queue->device, cs);
>   abort();
>  }
> diff --git a/src/amd/vulkan/radv_private.h
> b/src/amd/vulkan/radv_private.h
> index 73f7bdbe8a..28e70e6915 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -555,6 +555,9 @@ struct radv_device {
>   uint32_t fmask_mrt_offset_counter;
>   struct list_head shader_slabs;
>   mtx_t shader_slab_mutex;
> +
> +   /* For detecting VM faults reported by dmesg. */
> +   uint64_t dmesg_timestamp;
>  };
>  
>  struct radv_device_memory {
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH 2/2] radv: disassemble SPIR-V binaries with RADV_DEBUG=spirv

[Bas Nieuwenhuizen]

This series is

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Aug 30, 2017, at 15:12, Samuel Pitoiset wrote:
> This introduces a new separate option because the output can
> be quite verbose. If spirv-dis is not found in the path, this
> debug option is useless.
> 
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_debug.c| 30 ++
>  src/amd/vulkan/radv_debug.h|  3 +++
>  src/amd/vulkan/radv_device.c   |  1 +
>  src/amd/vulkan/radv_pipeline.c |  3 +++
>  4 files changed, 37 insertions(+)
> 
> diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
> index 8105d1f47e..e6bbf21aba 100644
> --- a/src/amd/vulkan/radv_debug.c
> +++ b/src/amd/vulkan/radv_debug.c
> @@ -60,3 +60,33 @@ void radv_dump_trace(struct radv_device *device,
> struct radeon_winsys_cs *cs)
>   device->ws->cs_dump(cs, f, (const int*)device->trace_id_ptr, 2);
>   fclose(f);
>  }
> +
> +void radv_print_spirv(struct radv_shader_module *module, FILE *fp)
> +{
> +   char path[] = "/tmp/fileXX";
> +   char line[2048], command[128];
> +   FILE *p;
> +   int fd;
> +
> +   /* Dump the binary into a temporary file. */
> +   fd = mkstemp(path);
> +   if (fd < 0)
> +   return;
> +
> +   if (write(fd, module->data, module->size) == -1)
> +   goto fail;
> +
> +   sprintf(command, "spirv-dis %s", path);
> +
> +   /* Disassemble using spirv-dis if installed. */
> +   p = popen(command, "r");
> +   if (p) {
> +   while (fgets(line, sizeof(line), p))
> +   fprintf(fp, "%s", line);
> +   pclose(p);
> +   }
> +
> +fail:
> +   close(fd);
> +   unlink(path);
> +}
> diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
> index c9d5fcc73f..d2fbe695fc 100644
> --- a/src/amd/vulkan/radv_debug.h
> +++ b/src/amd/vulkan/radv_debug.h
> @@ -37,6 +37,7 @@ enum {
>   RADV_DEBUG_UNSAFE_MATH   =  0x80,
>   RADV_DEBUG_ALL_BOS   = 0x100,
>   RADV_DEBUG_NO_IBS= 0x200,
> +   RADV_DEBUG_DUMP_SPIRV= 0x400,
>  };
>  
>  enum {
> @@ -48,4 +49,6 @@ bool radv_init_trace(struct radv_device *device);
>  
>  void radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs
>  *cs);
>  
> +void radv_print_spirv(struct radv_shader_module *module, FILE *fp);
> +
>  #endif
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index aae3488318..cbba04a5d6 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -409,6 +409,7 @@ static const struct debug_control
> radv_debug_options[] = {
>   {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
>   {"allbos", RADV_DEBUG_ALL_BOS},
>   {"noibs", RADV_DEBUG_NO_IBS},
> +   {"spirv", RADV_DEBUG_DUMP_SPIRV},
>   {NULL, 0}
>  };
>  
> diff --git a/src/amd/vulkan/radv_pipeline.c
> b/src/amd/vulkan/radv_pipeline.c
> index ef5c646317..f2d1b491b7 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -207,6 +207,9 @@ radv_shader_compile_to_nir(struct radv_device
> *device,
>   uint32_t *spirv = (uint32_t *) module->data;
>   assert(module->size % 4 == 0);
>  
> +   if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
> +   radv_print_spirv(module, stderr);
> +
>   uint32_t num_spec_entries = 0;
>   struct nir_spirv_specialization *spec_entries = NULL;
>   if (spec_info && spec_info->mapEntryCount > 0) {
> -- 
> 2.14.1
> 
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[Mesa-dev] [PATCH] anv/formats: Nicely handle unknown VkFormat enums

[Jason Ekstrand]

This fixes some crashes in the dEQP-VK.memory.requirements.core.* tests.
I'm not sure whether or not passing out-of-bound formats into the query
is supposed to be allowed but there's no harm in protecting ourselves
from it.

Bugzilla: https://bugs.freedesktop.org/101956
Cc: mesa-sta...@lists.freedesktop.org
---
 src/intel/vulkan/anv_formats.c | 19 ++-
 1 file changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 6ce609a..c23b143 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -250,6 +250,15 @@ static const struct anv_format anv_formats[] = {
 
 #undef fmt
 
+static bool
+format_supported(VkFormat vk_format)
+{
+   if (vk_format > ARRAY_SIZE(anv_formats))
+  return false;
+
+   return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
+}
+
 /**
  * Exactly one bit must be set in \a aspect.
  */
@@ -257,10 +266,10 @@ struct anv_format
 anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
VkImageAspectFlags aspect, VkImageTiling tiling)
 {
-   struct anv_format format = anv_formats[vk_format];
+   if (!format_supported(vk_format))
+  return anv_formats[VK_FORMAT_UNDEFINED];
 
-   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
-  return format;
+   struct anv_format format = anv_formats[vk_format];
 
if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
   assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
@@ -391,7 +400,7 @@ anv_physical_device_get_format_properties(struct 
anv_physical_device *physical_d
   gen += 5;
 
VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0;
-   if (anv_formats[format].isl_format == ISL_FORMAT_UNSUPPORTED) {
+   if (!format_supported(format)) {
   /* Nothing to do here */
} else if (vk_format_is_depth_or_stencil(format)) {
   tiled |= VK_FORMAT_FEATURE_DEPTH_STENCIL_ATTACHMENT_BIT;
@@ -489,7 +498,7 @@ anv_get_image_format_properties(
uint32_t maxArraySize;
VkSampleCountFlags sampleCounts = VK_SAMPLE_COUNT_1_BIT;
 
-   if (anv_formats[info->format].isl_format == ISL_FORMAT_UNSUPPORTED)
+   if (!format_supported(info->format))
   goto unsupported;
 
anv_physical_device_get_format_properties(physical_device, info->format,
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 5/5] i965: Move BATCH_SZ define into intel_batchbuffer.c.

[Kenneth Graunke]

It's only used in one file.
---
 src/mesa/drivers/dri/i965/brw_context.h   | 1 -
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 38f9b5fc670..92fc16de136 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -449,7 +449,6 @@ struct intel_batchbuffer {
uint32_t *map_next;
uint32_t *map;
uint32_t *cpu_map;
-#define BATCH_SZ (8192*sizeof(uint32_t))
 
uint32_t state_batch_offset;
enum brw_gpu_ring ring;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 6e67a523ca5..417c0ea949f 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -40,6 +40,8 @@
 
 #define FILE_DEBUG_FLAG DEBUG_BUFMGR
 
+#define BATCH_SZ (8192*sizeof(uint32_t))
+
 static void
 intel_batchbuffer_reset(struct intel_batchbuffer *batch,
 struct brw_bufmgr *bufmgr,
-- 
2.14.1

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[Mesa-dev] [PATCH 4/5] i965: Drop batch_size argument from brw_bufmgr_init().

[Kenneth Graunke]

This is dead code and hasn't been used in a long time.
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c   | 2 +-
 src/mesa/drivers/dri/i965/brw_bufmgr.h   | 3 +--
 src/mesa/drivers/dri/i965/intel_screen.c | 2 +-
 3 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 4fae824d80d..d33754d9497 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -1331,7 +1331,7 @@ gem_param(int fd, int name)
  * \param fd File descriptor of the opened DRM device.
  */
 struct brw_bufmgr *
-brw_bufmgr_init(struct gen_device_info *devinfo, int fd, int batch_size)
+brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
 {
struct brw_bufmgr *bufmgr;
 
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index c88d1ecac6b..20abcd31f3c 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -291,8 +291,7 @@ int brw_bo_busy(struct brw_bo *bo);
 int brw_bo_madvise(struct brw_bo *bo, int madv);
 
 /* drm_bacon_bufmgr_gem.c */
-struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo,
-   int fd, int batch_size);
+struct brw_bufmgr *brw_bufmgr_init(struct gen_device_info *devinfo, int fd);
 struct brw_bo *brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
const char *name,
unsigned int handle);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e0827cab36c..d39509bcb8c 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1613,7 +1613,7 @@ intel_init_bufmgr(struct intel_screen *screen)
if (getenv("INTEL_NO_HW") != NULL)
   screen->no_hw = true;
 
-   screen->bufmgr = brw_bufmgr_init(>devinfo, dri_screen->fd, 
BATCH_SZ);
+   screen->bufmgr = brw_bufmgr_init(>devinfo, dri_screen->fd);
if (screen->bufmgr == NULL) {
   fprintf(stderr, "[%s:%u] Error initializing buffer manager.\n",
  __func__, __LINE__);
-- 
2.14.1

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[Mesa-dev] [PATCH 1/5] i965: Don't double count the batch in aperture_space.

[Kenneth Graunke]

intel_batchbuffer_reset calls add_exec_bo on the batch right away,
which adds in the batch BO size.

Fixes: 29ba502a4e28 ("i965: Use I915_EXEC_BATCH_FIRST when available.")
---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Here are some misc. cleanups I made while working on the batch code.

diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 6a049014952..daed8526eae 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -454,7 +454,7 @@ brw_new_batch(struct brw_context *brw)
}
brw->batch.reloc_count = 0;
brw->batch.exec_count = 0;
-   brw->batch.aperture_space = BATCH_SZ;
+   brw->batch.aperture_space = 0;
 
/* Create a new batchbuffer and reset the associated state: */
intel_batchbuffer_reset_and_clear_render_cache(brw);
-- 
2.14.1

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[Mesa-dev] [PATCH 3/5] i965: Rename brw_bo::offset64 to presumed_offset.

[Kenneth Graunke]

We can drop the meaningless "64" suffix - libdrm_intel originally had
an "offset" field that was an "unsigned long" which was the wrong size,
and we couldn't remove/alter that field without breaking ABI, so we had
to add a uint64_t "offset64" field.

"presumed_offset" is a bit more descriptive than "offset".
---
 src/mesa/drivers/dri/i965/brw_bufmgr.c|  2 +-
 src/mesa/drivers/dri/i965/brw_bufmgr.h|  2 +-
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 13 +++--
 3 files changed, 9 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 5b4e784ae24..4fae824d80d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -517,7 +517,7 @@ brw_bo_gem_create_from_name(struct brw_bufmgr *bufmgr,
p_atomic_set(>refcount, 1);
 
bo->size = open_arg.size;
-   bo->offset64 = 0;
+   bo->presumed_offset = 0;
bo->bufmgr = bufmgr;
bo->gem_handle = open_arg.handle;
bo->name = name;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 7423dde2d36..c88d1ecac6b 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -74,7 +74,7 @@ struct brw_bo {
 * aperture) for the object.  This should be used to fill relocation
 * entries when calling brw_bo_emit_reloc()
 */
-   uint64_t offset64;
+   uint64_t presumed_offset;
 
/**
 * The validation list index for this buffer, or -1 when not in a batch.
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index daed8526eae..6e67a523ca5 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -130,7 +130,7 @@ add_exec_bo(struct intel_batchbuffer *batch, struct brw_bo 
*bo)
   (struct drm_i915_gem_exec_object2) {
  .handle = bo->gem_handle,
  .alignment = bo->align,
- .offset = bo->offset64,
+ .offset = bo->presumed_offset,
  .flags = bo->kflags,
   };
 
@@ -310,7 +310,7 @@ do_batch_dump(struct brw_context *brw)
 
uint32_t *data = map ? map : batch->map;
uint32_t *end = data + USED_BATCH(*batch);
-   uint32_t gtt_offset = map ? batch->bo->offset64 : 0;
+   uint32_t gtt_offset = map ? batch->bo->presumed_offset : 0;
int length;
 
bool color = INTEL_DEBUG & DEBUG_COLOR;
@@ -614,11 +614,12 @@ execbuffer(int fd,
   bo->idle = false;
   bo->index = -1;
 
-  /* Update brw_bo::offset64 */
-  if (batch->validation_list[i].offset != bo->offset64) {
+  /* Update brw_bo::presumed_offset */
+  if (batch->validation_list[i].offset != bo->presumed_offset) {
  DBG("BO %d migrated: 0x%" PRIx64 " -> 0x%llx\n",
- bo->gem_handle, bo->offset64, batch->validation_list[i].offset);
- bo->offset64 = batch->validation_list[i].offset;
+ bo->gem_handle, bo->presumed_offset,
+ batch->validation_list[i].offset);
+ bo->presumed_offset = batch->validation_list[i].offset;
   }
}
 
-- 
2.14.1

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[Mesa-dev] [PATCH 2/5] i965: Drop the BRW_BATCH_STRUCT macro.

[Kenneth Graunke]

It's used in exactly one place these days, and not much simpler than
just calling intel_batchbuffer_data directly.
---
 src/mesa/drivers/dri/i965/brw_state.h | 3 ---
 src/mesa/drivers/dri/i965/brw_urb.c   | 2 +-
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index a07e70341df..1cbddaba786 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -187,9 +187,6 @@ void brw_print_program_cache(struct brw_context *brw);
 /***
  * brw_state_batch.c
  */
-#define BRW_BATCH_STRUCT(brw, s) \
-   intel_batchbuffer_data(brw, (s), sizeof(*(s)), RENDER_RING)
-
 void *brw_state_batch(struct brw_context *brw,
   int size, int alignment, uint32_t *out_offset);
 uint32_t brw_state_batch_size(struct brw_context *brw, uint32_t offset);
diff --git a/src/mesa/drivers/dri/i965/brw_urb.c 
b/src/mesa/drivers/dri/i965/brw_urb.c
index af68b9706b4..a86fa78acaf 100644
--- a/src/mesa/drivers/dri/i965/brw_urb.c
+++ b/src/mesa/drivers/dri/i965/brw_urb.c
@@ -264,5 +264,5 @@ void brw_upload_urb_fence(struct brw_context *brw)
   while (--pad);
}
 
-   BRW_BATCH_STRUCT(brw, );
+   intel_batchbuffer_data(brw, , sizeof(uf), RENDER_RING);
 }
-- 
2.14.1

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[Mesa-dev] [Bug 102496] Frontbuffer rendering corruption on mesa master

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102496

Bruce Cherniak  changed:

   What|Removed |Added

   Keywords||bisected, regression
 CC||bruce.chern...@intel.com,
   ||thellst...@vmware.com

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[Mesa-dev] [Bug 102496] Frontbuffer rendering corruption on mesa master

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102496

Bug ID: 102496
   Summary: Frontbuffer rendering corruption on mesa master
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: bruce.chern...@intel.com
QA Contact: mesa-dev@lists.freedesktop.org

Frontbuffer applications aren't flushing correctly.

GLUT Olympic rings run single buffered (-sb) on llvmpipe, swr, and softpipe
displays corruption.
(https://www.opengl.org/archives/resources/code/samples/glut_examples/examples/olympic.c)

Other frontbuffer applications display similar errors.

Bistected to:
eceb6710024716433069d705fbd873d6d136c2cc is the first bad commit
commit eceb6710024716433069d705fbd873d6d136c2cc

Author: Thomas Hellstrom   2017-06-20 14:12:50
Committer: Thomas Hellstrom   2017-08-02 04:55:35

mesa/st: Reduce the number of frontbuffer flush calls

The mesa state tracker was needlessly flushing the front buffer even if it
hadn't been drawn to since the last flush. This was happening during
glXSwapBuffers if we at some point previously had set that frontbuffer as
a read- or draw renderbuffer, or at glFlush() or glFinish() if we at some
point previously had rendered to the front buffer. Since the frontbuffer
flush typically means a full drawable copy, it's a pretty big waste.

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Re: [Mesa-dev] [PATCH] radv: compute correct maximum wave count per SIMD

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Wed, Aug 30, 2017, at 15:12, Samuel Pitoiset wrote:
> Ported from RadeonSI (original patch by Marek).
> 
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_pipeline.c | 13 -
>  1 file changed, 12 insertions(+), 1 deletion(-)
> 
> diff --git a/src/amd/vulkan/radv_pipeline.c
> b/src/amd/vulkan/radv_pipeline.c
> index 637fed625f..e3a8dff992 100644
> --- a/src/amd/vulkan/radv_pipeline.c
> +++ b/src/amd/vulkan/radv_pipeline.c
> @@ -320,9 +320,20 @@ static void radv_dump_pipeline_stats(struct
> radv_device *device, struct radv_pip
>   struct ac_shader_config *conf;
>   int i;
>   FILE *file = stderr;
> -   unsigned max_simd_waves = 10;
> +   unsigned max_simd_waves;
>   unsigned lds_per_wave = 0;
>  
> +   switch (device->physical_device->rad_info.family) {
> +   /* These always have 8 waves: */
> +   case CHIP_POLARIS10:
> +   case CHIP_POLARIS11:
> +   case CHIP_POLARIS12:
> +   max_simd_waves = 8;
> +   break;
> +   default:
> +   max_simd_waves = 10;
> +   }
> +
>   for (i = 0; i < MESA_SHADER_STAGES; i++) {
>   if (!pipeline->shaders[i])
>   continue;
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH mesa] util: improve compiler guard

[Rob Herring]

On Thu, Aug 31, 2017 at 11:54 AM, Eric Engestrom
 wrote:
> Glibc 2.26 has dropped xlocale.h, but the functions needed (strtod_l()
> and strdof_l()) can be found in stdlib.h.
> Improve the detection method to allow newer builds to still make use of
> the locale-setting.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102454
> Cc: Laurent Carlier 
> Cc: Emil Velikov 
> Cc: Rob Herring 
> Signed-off-by: Eric Engestrom 
> ---
>
> Rob, any idea if android needs locale-setting? Emil suggested it might
> always use "C" anyway.

Looking at bionic, it just throws away the locale parameter. So it
doesn't really matter which code path mesa uses.

Rob
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Re: [Mesa-dev] [PATCH 2/2] i965: Implement ARB_indirect_parameters

[Ilia Mirkin]

On Thu, Aug 31, 2017 at 1:45 PM, Bas Nieuwenhuizen
 wrote:
>
>
> On Wed, Aug 30, 2017, at 14:59, Ilia Mirkin wrote:
>> On Wed, Aug 30, 2017 at 3:17 AM, Bas Nieuwenhuizen
>>  wrote:
>> > So as a random drive-by review, I think the risk in this implementation
>> > is that apps just set maxdrawcount to some high value . If I'm reading
>> > the spec correctly there is no real bound on the value except for the
>> > max-representable value for the integer.  Also AFAIK the AMD and NVidia
>> > implementation don't really get slower if you specify maxdrawcount very
>>
>> Can't speak for AMD, but this is actually extremely similar (in
>> principle) to how this is handled on NVIDIA. It's a little cleaner
>> since there's a nice macro, but since macros can't have a variable
>> number of arguments, you have to feed it maxdrawcount args. Admittedly
>> this is the nouveau impl, but I'm almost certain that the blob does it
>> in a similar way.
>
> I thought, you had a macro that looped, but seems that was a
> misunderstanding on my side.  If nvidia does it that way, then I suppose
> there is little risk of games expecting something more efficient. Never
> mind my comments then.

There indeed is a macro that loops. However that macro takes a number
of parameters determined at the time of cmd stream generation. Also
the indirect draw arguments have to be added into the cmd stream (via
IB references). Here's how nouveau does it:

https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/drivers/nouveau/nvc0/nvc0_vbo.c#n798

I don't remember if I looked precisely at what NVIDIA does, but I
definitely can't think of another way. Even if you use the command
which takes the argument length as a separate word, that won't be
right since it's count * N arguments. macros can't read arbitrary
things either, it has to come out of the cmdstream.

  -ilia
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Re: [Mesa-dev] [PATCH 1/2] glx: add support for GLX_ARB_create_context_no_error

[Adam Jackson]

On Thu, 2017-08-03 at 20:07 +0200, Grigori Goronzy wrote:

> @@ -592,4 +601,45 @@ dri2_convert_glx_attribs(unsigned num_attribs, const 
> uint32_t *attribs,
> return true;
>  }
>  
> +_X_HIDDEN bool
> +dri2_check_no_error(uint32_t flags, struct glx_context *share_context,
> +int major, unsigned *error)
> +{
> +   Bool noError = flags & __DRI_CTX_FLAG_NO_ERROR;


Right here you should have:

   if (!noError)
  return true;

> +
> +   /* The KHR_no_error specs say:
> +*
> +*Requires OpenGL ES 2.0 or OpenGL 2.0.
> +*/
> +   if (major < 2) {
> +  *error = __DRI_CTX_ERROR_UNKNOWN_ATTRIBUTE;
> +  return false;
> +   }

... because if you don't, this will break creating any GL 1.x context,
regardless of whether no_error was requested.

- ajax
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Re: [Mesa-dev] [PATCH] vbo: fix offset in minmax cache key

[Brian Paul]

Reviewed-by: Brian Paul 


On 08/30/2017 11:20 PM, Charmaine Lee wrote:

Instead of saving primitive offset in the minmax cache key,
save the actual buffer offset which is used in the cache lookup.

Fixes rendering artifact seen with GoogleEarth when run with
VMware driver.

v2: Per Brian's comment, initialize offset to avoid compiler warning.

Cc: mesa-sta...@lists.freedesktop.org
---
  src/mesa/vbo/vbo_minmax_index.c | 8 +---
  1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/vbo/vbo_minmax_index.c b/src/mesa/vbo/vbo_minmax_index.c
index 4c17a08..58a2af4 100644
--- a/src/mesa/vbo/vbo_minmax_index.c
+++ b/src/mesa/vbo/vbo_minmax_index.c
@@ -245,6 +245,7 @@ vbo_get_minmax_index(struct gl_context *ctx,
_mesa_primitive_restart_index(ctx, ib->index_size);
 const char *indices;
 GLuint i;
+   GLintptr offset = 0;

 indices = (char *) ib->ptr + prim->start * ib->index_size;
 if (_mesa_is_bufferobj(ib->obj)) {
@@ -254,7 +255,8 @@ vbo_get_minmax_index(struct gl_context *ctx,
  count, min_index, max_index))
   return;

-  indices = ctx->Driver.MapBufferRange(ctx, (GLintptr) indices, size,
+  offset = indices;
+  indices = ctx->Driver.MapBufferRange(ctx, offset, size,
 GL_MAP_READ_BIT, ib->obj,
 MAP_INTERNAL);
 }
@@ -337,8 +339,8 @@ vbo_get_minmax_index(struct gl_context *ctx,
 }

 if (_mesa_is_bufferobj(ib->obj)) {
-  vbo_minmax_cache_store(ctx, ib->obj, ib->index_size, prim->start, count,
- *min_index, *max_index);
+  vbo_minmax_cache_store(ctx, ib->obj, ib->index_size, offset,
+ count, *min_index, *max_index);
ctx->Driver.UnmapBuffer(ctx, ib->obj, MAP_INTERNAL);
 }
  }



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Re: [Mesa-dev] [PATCH 2/2] i965: Implement ARB_indirect_parameters

[Bas Nieuwenhuizen]

On Wed, Aug 30, 2017, at 14:59, Ilia Mirkin wrote:
> On Wed, Aug 30, 2017 at 3:17 AM, Bas Nieuwenhuizen
>  wrote:
> > So as a random drive-by review, I think the risk in this implementation
> > is that apps just set maxdrawcount to some high value . If I'm reading
> > the spec correctly there is no real bound on the value except for the
> > max-representable value for the integer.  Also AFAIK the AMD and NVidia
> > implementation don't really get slower if you specify maxdrawcount very
> 
> Can't speak for AMD, but this is actually extremely similar (in
> principle) to how this is handled on NVIDIA. It's a little cleaner
> since there's a nice macro, but since macros can't have a variable
> number of arguments, you have to feed it maxdrawcount args. Admittedly
> this is the nouveau impl, but I'm almost certain that the blob does it
> in a similar way.

I thought, you had a macro that looped, but seems that was a
misunderstanding on my side.  If nvidia does it that way, then I suppose
there is little risk of games expecting something more efficient. Never
mind my comments then.

> 
> > large, so I wouldn't be surprised if a good number of apps would set the
> > maxdrawcount really high, like MAX_INT or something. I suspect you
> > wouldn't want to emit that .
> 
> Let's hope not!
> 
>   -ilia
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[Mesa-dev] [PATCH mesa] util: improve compiler guard

[Eric Engestrom]

Glibc 2.26 has dropped xlocale.h, but the functions needed (strtod_l()
and strdof_l()) can be found in stdlib.h.
Improve the detection method to allow newer builds to still make use of
the locale-setting.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102454
Cc: Laurent Carlier 
Cc: Emil Velikov 
Cc: Rob Herring 
Signed-off-by: Eric Engestrom 
---

Rob, any idea if android needs locale-setting? Emil suggested it might
always use "C" anyway.

For SCons, I added a trivial "does this function exist" check, but
I don't even know what headers it includes when checking that. There's
a chance this might break the scons build (appveyor is happy though,
fwiw).

If anyone knows how to do the same check in scons that I'm doing in
autoconf, speak up :)

---
 configure.ac  | 21 +
 scons/gallium.py  | 16 
 src/util/strtod.c | 12 ++--
 3 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/configure.ac b/configure.ac
index 53d52f6d52..f4d83e1c10 100644
--- a/configure.ac
+++ b/configure.ac
@@ -826,6 +826,27 @@ AC_CHECK_HEADER([sys/sysctl.h], [DEFINES="$DEFINES 
-DHAVE_SYS_SYSCTL_H"])
 AC_CHECK_FUNC([strtof], [DEFINES="$DEFINES -DHAVE_STRTOF"])
 AC_CHECK_FUNC([mkostemp], [DEFINES="$DEFINES -DHAVE_MKOSTEMP"])
 
+AC_MSG_CHECKING([whether strtod has locale support])
+AC_LINK_IFELSE([AC_LANG_SOURCE([[
+#define _GNU_SOURCE
+#include 
+#include 
+#ifdef HAVE_XLOCALE_H
+#include 
+#endif
+int main() {
+   locale_t loc = newlocale(LC_CTYPE_MASK, "C", NULL);
+   const char *s = "1.0";
+   char *end;
+   double d = strtod_l(s, end, loc);
+   float f = strtof_l(s, end, loc);
+   freelocale(loc);
+   return 0;
+}]])],
+  [DEFINES="$DEFINES -DHAVE_STRTOD_L"];
+   AC_MSG_RESULT([yes]),
+   AC_MSG_RESULT([no]))
+
 dnl Check to see if dlopen is in default libraries (like Solaris, which
 dnl has it in libc), or if libdl is needed to get it.
 AC_CHECK_FUNC([dlopen], [DEFINES="$DEFINES -DHAVE_DLOPEN"],
diff --git a/scons/gallium.py b/scons/gallium.py
index c8e47a39db..1e35ef434a 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -157,6 +157,19 @@ def check_header(env, header):
 env = conf.Finish()
 return have_header
 
+def check_functions(env, functions):
+'''Check if all of the functions exist'''
+
+conf = SCons.Script.Configure(env)
+have_functions = True
+
+for function in functions:
+if not conf.CheckFunc(function):
+have_functions = False
+
+env = conf.Finish()
+return have_functions
+
 def check_prog(env, prog):
 """Check whether this program exists."""
 
@@ -339,6 +352,9 @@ def generate(env):
 if check_header(env, 'xlocale.h'):
 cppdefines += ['HAVE_XLOCALE_H']
 
+if check_functions(env, ['strtod_l', 'strtof_l']):
+cppdefines += ['HAVE_STRTOD_L']
+
 if platform == 'windows':
 cppdefines += [
 'WIN32',
diff --git a/src/util/strtod.c b/src/util/strtod.c
index ea7d395e2d..de695d64b4 100644
--- a/src/util/strtod.c
+++ b/src/util/strtod.c
@@ -26,13 +26,13 @@
 
 #include 
 
-#ifdef _GNU_SOURCE
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
 #include 
 #ifdef HAVE_XLOCALE_H
 #include 
+#endif
 static locale_t loc;
 #endif
-#endif
 
 #include "strtod.h"
 
@@ -40,7 +40,7 @@ static locale_t loc;
 void
 _mesa_locale_init(void)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
loc = newlocale(LC_CTYPE_MASK, "C", NULL);
 #endif
 }
@@ -48,7 +48,7 @@ _mesa_locale_init(void)
 void
 _mesa_locale_fini(void)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
freelocale(loc);
 #endif
 }
@@ -60,7 +60,7 @@ _mesa_locale_fini(void)
 double
 _mesa_strtod(const char *s, char **end)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
return strtod_l(s, end, loc);
 #else
return strtod(s, end);
@@ -75,7 +75,7 @@ _mesa_strtod(const char *s, char **end)
 float
 _mesa_strtof(const char *s, char **end)
 {
-#if defined(_GNU_SOURCE) && defined(HAVE_XLOCALE_H)
+#if defined(_GNU_SOURCE) && defined(HAVE_STRTOD_L)
return strtof_l(s, end, loc);
 #elif defined(HAVE_STRTOF)
return strtof(s, end);
-- 
Cheers,
  Eric

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Re: [Mesa-dev] [PATCH 2/2] st/glx: add support for GLX_ARB_create_context_no_error

[Adam Jackson]

On Thu, 2017-08-31 at 11:41 -0400, Adam Jackson wrote:
> On Thu, 2017-08-03 at 20:07 +0200, Grigori Goronzy wrote:
> > @@ -981,6 +983,8 @@ XMesaContext XMesaCreateContext( XMesaVisual v,
> > XMesaContext share_list,
> >attribs.flags |= ST_CONTEXT_FLAG_DEBUG;
> > if (contextFlags & GLX_CONTEXT_ROBUST_ACCESS_BIT_ARB)
> >attribs.flags |= ST_CONTEXT_FLAG_ROBUST_ACCESS;
> > +   if (noError)
> > +  attribs.flags |= ST_CONTEXT_FLAG_NO_ERROR;
> >  
> > switch (profileMask) {
> > case GLX_CONTEXT_CORE_PROFILE_BIT_ARB:
> 
> This seems weird to me. Why add an argument when there's already a
> flag bit for this?

My mistake. For st it's a flag, for GL it's an attribute.

- ajax
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[Mesa-dev] [Bug 102454] glibc 2.26 doesn't provide anymore xlocale.h

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102454

--- Comment #4 from Eric Engestrom  ---
(In reply to Laurent carlier from comment #2)
> Created attachment 133909 [details] [review]
> WIP patch
> 
> Work in progress patch

Your patch checks for `locale_t`, but I don't think this is the thing that
might be missing; `strtod_l()` is.
I had also started working on this, I just pushed my WIP here:
https://github.com/1ace/mesa  wip/strtod-fix

(quick diff link:)
https://github.com/mesa3d/mesa/compare/master...1ace:wip/strtod-fix

I'm having a couple issues though, I'm on IRC if you want to work together :)

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[Mesa-dev] [Bug 102454] glibc 2.26 doesn't provide anymore xlocale.h

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102454

--- Comment #3 from Emil Velikov  ---
The locale_t check does not seem like a good idea.

The struct is used by {new,free}locale API, which pulls locale.h.
Aka the struct may be available, even when strto{f,d}_l is not.

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Re: [Mesa-dev] [PATCH 2/2] st/glx: add support for GLX_ARB_create_context_no_error

[Adam Jackson]

On Thu, 2017-08-03 at 20:07 +0200, Grigori Goronzy wrote:

> diff --git a/src/gallium/state_trackers/glx/xlib/xm_api.c 
> b/src/gallium/state_trackers/glx/xlib/xm_api.c
> index 828253b..508db5c 100644
> --- a/src/gallium/state_trackers/glx/xlib/xm_api.c
> +++ b/src/gallium/state_trackers/glx/xlib/xm_api.c
> @@ -952,7 +952,8 @@ xmesa_init( Display *display )
>  PUBLIC
>  XMesaContext XMesaCreateContext( XMesaVisual v, XMesaContext share_list,
>   GLuint major, GLuint minor,
> - GLuint profileMask, GLuint contextFlags)
> + GLuint profileMask, GLuint contextFlags,
> + GLboolean noError)
>  {
> XMesaDisplay xmdpy = xmesa_init_display(v->display);
> struct st_context_attribs attribs;
> @@ -970,6 +971,7 @@ XMesaContext XMesaCreateContext( XMesaVisual v, 
> XMesaContext share_list,
> c->xm_visual = v;
> c->xm_buffer = NULL;   /* set later by XMesaMakeCurrent */
> c->xm_read_buffer = NULL;
> +   c->no_error = noError;
>  
> memset(, 0, sizeof(attribs));
> attribs.visual = v->stvis;
> @@ -981,6 +983,8 @@ XMesaContext XMesaCreateContext( XMesaVisual v, 
> XMesaContext share_list,
>attribs.flags |= ST_CONTEXT_FLAG_DEBUG;
> if (contextFlags & GLX_CONTEXT_ROBUST_ACCESS_BIT_ARB)
>attribs.flags |= ST_CONTEXT_FLAG_ROBUST_ACCESS;
> +   if (noError)
> +  attribs.flags |= ST_CONTEXT_FLAG_NO_ERROR;
>  
> switch (profileMask) {
> case GLX_CONTEXT_CORE_PROFILE_BIT_ARB:

This seems weird to me. Why add an argument when there's already a flag
bit for this?

- ajax
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Re: [Mesa-dev] [PATCH v2 1/5] anv: implementation of VK_EXT_debug_report extension

[Tapani Pälli]

On 08/29/2017 08:44 AM, Tapani Pälli wrote:

Patch adds required functionality for extension to manage a list of
application provided callbacks and handle debug reporting from driver
and application side.

v2: remove useless helper anv_debug_report_call
 add locking around callbacks list
 use vk_alloc2, vk_free2 helpers
 refactor CreateDebugReportCallbackEXT
 fix bugs found with crucible testing

Signed-off-by: Tapani Pälli 
---
  src/intel/Makefile.sources  |   1 +
  src/intel/vulkan/anv_debug_report.c | 124 
  src/intel/vulkan/anv_device.c   |  46 +
  src/intel/vulkan/anv_extensions.py  |   1 +
  src/intel/vulkan/anv_private.h  |  24 +++
  5 files changed, 196 insertions(+)
  create mode 100644 src/intel/vulkan/anv_debug_report.c


8<


+void
+anv_debug_report(struct anv_instance *instance,
+ VkDebugReportFlagsEXT flags,
+ VkDebugReportObjectTypeEXT object_type,
+ uint64_t handle,
+ size_t location,
+ int32_t messageCode,
+ const char* pLayerPrefix,
+ const char *pMessage)
+{
+   /* Allow NULL for convinience, return if no callbacks registered. */
+   if (!instance || list_empty(>callbacks))
+  return;
+
+   pthread_mutex_lock(>callbacks_mutex);
+
+   /* Section 33.2 of the Vulkan 1.0.59 spec says:
+*
+*"callback is an externally synchronized object and must not be
+*used on more than one thread at a time. This means that
+*vkDestroyDebugReportCallbackEXT must not be called when a callback
+*is active."
+*/
+   list_for_each_entry_safe(struct anv_debug_callback, cb,


self-review, I forgot to take away '_safe', this is now fixed locally.


+>callbacks, link) {
+  if (cb->flags & flags)
+ cb->callback(flags, object_type, handle, location, messageCode,
+  pLayerPrefix, pMessage, cb->data);
+   }
+
+   pthread_mutex_unlock(>callbacks_mutex);
+}
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 2e0fa19b1a..7e091246a8 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -443,9 +443,28 @@ VkResult anv_CreateInstance(
  VkInstance* pInstance)
  {
 struct anv_instance *instance;
+   VkDebugReportCallbackCreateInfoEXT *ctor_cb = NULL;
  
 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
  
+   /* Check if user passed a debug report callback to be used during

+* Create/Destroy of instance.
+*/
+   vk_foreach_struct(ext, pCreateInfo->pNext) {
+  switch (ext->sType) {
+  case VK_STRUCTURE_TYPE_DEBUG_REPORT_CALLBACK_CREATE_INFO_EXT: {
+ ctor_cb = (VkDebugReportCallbackCreateInfoEXT *) ext;
+ break;
+  }
+  default:
+ /* We ignore any other type by purpose here, we are only
+  * interested if debug report callback was found for instance
+  * ctor/dtor.
+  */
+ break;
+  }
+   };
+
 uint32_t client_version;
 if (pCreateInfo->pApplicationInfo &&
 pCreateInfo->pApplicationInfo->apiVersion != 0) {
@@ -456,6 +475,17 @@ VkResult anv_CreateInstance(
  
 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||

 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
+
+  if (ctor_cb && ctor_cb->flags & VK_DEBUG_REPORT_ERROR_BIT_EXT)
+ ctor_cb->pfnCallback(VK_DEBUG_REPORT_ERROR_BIT_EXT,
+  VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT,
+  0, /* No handle available yet. */
+  __LINE__,
+  0,
+  "anv",
+  "incompatible driver version",
+  ctor_cb->pUserData);
+
return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
 "Client requested version %d.%d.%d",
 VK_VERSION_MAJOR(client_version),
@@ -484,6 +514,20 @@ VkResult anv_CreateInstance(
 instance->apiVersion = client_version;
 instance->physicalDeviceCount = -1;
  
+   if (pthread_mutex_init(>callbacks_mutex, NULL) != 0) {

+  vk_free2(_alloc, pAllocator, instance);
+  return vk_error(VK_ERROR_INITIALIZATION_FAILED);
+   }
+
+   list_inithead(>callbacks);
+
+   /* Store report debug callback to be used during DestroyInstance. */
+   if (ctor_cb) {
+  instance->dtor_cb.flags = ctor_cb->flags;
+  instance->dtor_cb.callback = ctor_cb->pfnCallback;
+  instance->dtor_cb.data = ctor_cb->pUserData;
+   }
+
 _mesa_locale_init();
  
 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));

@@ -510,6 +554,8 @@ void anv_DestroyInstance(
  
 VG(VALGRIND_DESTROY_MEMPOOL(instance));
  
+   pthread_mutex_destroy(>callbacks_mutex);

+
 _mesa_locale_fini();
  
 

[Mesa-dev] [Bug 102454] glibc 2.26 doesn't provide anymore xlocale.h

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102454

--- Comment #2 from Laurent carlier  ---
Created attachment 133909
  --> https://bugs.freedesktop.org/attachment.cgi?id=133909=edit
WIP patch

Work in progress patch

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Re: [Mesa-dev] [PATCH] anv: fix build errors on android

[Jason Ekstrand]

Sure


On August 31, 2017 00:10:49 Tapani Pälli  wrote:




On 08/31/2017 10:08 AM, Jason Ekstrand wrote:

VK_NULL_HANDLE?


Sure, r-b with that?



On August 30, 2017 22:52:32 Tapani Pälli  wrote:


error: incompatible pointer to integer conversion initializing 'VkFence'
   (aka 'unsigned long long') with an expression of type 'void *'
[-Werror,-Wint-conversion]

Signed-off-by: Tapani Pälli 
---
 src/intel/vulkan/anv_queue.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 429bac9739..d675e8667e 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -169,7 +169,7 @@ VkResult anv_QueueSubmit(

for (uint32_t i = 0; i < submitCount; i++) {
   /* Fence for this submit.  NULL for all but the last one */
-  VkFence submit_fence = (i == submitCount - 1) ? fence : NULL;
+  VkFence submit_fence = (i == submitCount - 1) ? fence : 0;

   if (pSubmits[i].commandBufferCount == 0) {
  /* If we don't have any command buffers, we need to submit a
dummy
@@ -197,7 +197,7 @@ VkResult anv_QueueSubmit(

  /* Fence for this execbuf.  NULL for all but the last one */
  VkFence execbuf_fence =
-(j == pSubmits[i].commandBufferCount - 1) ? submit_fence
: NULL;
+(j == pSubmits[i].commandBufferCount - 1) ? submit_fence
: 0;

  const VkSemaphore *in_semaphores = NULL, *out_semaphores =
NULL;
  uint32_t num_in_semaphores = 0, num_out_semaphores = 0;
--
2.13.5







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Re: [Mesa-dev] [RFC v2 06/23] anv: Add func anv_get_raw_format()

[Eric Engestrom]

On Thursday, 2017-08-31 00:24:04 -0400, Louis-Francis Ratté-Boulianne wrote:
> From: Chad Versace 
> 
> Like anv_get_format(), but the returned format is not adjusted, not even
> for the aspect.
> 
> Add anv_get_raw_isl_format() too, to match anv_get_isl_format().
> ---
>  src/intel/vulkan/anv_formats.c | 7 +++
>  src/intel/vulkan/anv_private.h | 8 
>  2 files changed, 15 insertions(+)
> 
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
> index 9808508523..57202f4aca 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -250,6 +250,13 @@ static const struct anv_format anv_formats[] = {
>  
>  #undef fmt
>  
> +/** Like anv_get_format(), except the returned format is not adjusted. */
> +struct anv_format
> +anv_get_raw_format(const struct gen_device_info *devinfo, VkFormat vk_format)
> +{
> +   return anv_formats[vk_format];
> +}

Why the gen_device_info struct? Are you anticipating a use for it later?
Otherwise, I'd suggest removing it (and in the wrapper below).
(Note: choose_isl_format() in patch 17 will need updating as well)

> +
>  /**
>   * Exactly one bit must be set in \a aspect.
>   */
> diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
> index b30b71f336..7b4e9dfbe0 100644
> --- a/src/intel/vulkan/anv_private.h
> +++ b/src/intel/vulkan/anv_private.h
> @@ -2030,10 +2030,18 @@ struct anv_format {
> struct isl_swizzle swizzle;
>  };
>  
> +struct anv_format ATTRIBUTE_PURE
> +anv_get_raw_format(const struct gen_device_info *devinfo, VkFormat 
> vk_format);
> +
>  struct anv_format
>  anv_get_format(const struct gen_device_info *devinfo, VkFormat format,
> VkImageAspectFlags aspect, VkImageTiling tiling);
>  
> +static inline enum isl_format ATTRIBUTE_PURE
> +anv_get_raw_isl_format(const struct gen_device_info *devinfo, VkFormat 
> vk_format) {
> +   return anv_get_raw_format(devinfo, vk_format).isl_format;
> +}
> +
>  static inline enum isl_format
>  anv_get_isl_format(const struct gen_device_info *devinfo, VkFormat vk_format,
> VkImageAspectFlags aspect, VkImageTiling tiling)
> -- 
> 2.13.0
> 
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Re: [Mesa-dev] [PATCH 2/3] radeonsi: move si_vm_fault_occured() to AMD common code

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Aug 31, 2017 at 11:43 AM, Samuel Pitoiset
 wrote:
> For radv, in order to report VM faults when detected.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/common/ac_debug.c   | 109 
> 
>  src/amd/common/ac_debug.h   |   4 ++
>  src/gallium/drivers/radeonsi/si_debug.c | 106 ++-
>  3 files changed, 117 insertions(+), 102 deletions(-)
>
> diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
> index d46fc27a9e..0de00e27e7 100644
> --- a/src/amd/common/ac_debug.c
> +++ b/src/amd/common/ac_debug.c
> @@ -34,6 +34,8 @@
>  #define VG(x)
>  #endif
>
> +#include 
> +
>  #include "sid.h"
>  #include "gfx9d.h"
>  #include "sid_tables.h"
> @@ -597,3 +599,110 @@ void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, 
> const int *trace_ids,
>
> fprintf(f, "--- %s end ---\n\n", 
> name);
>  }
> +
> +/**
> + * Parse dmesg and return TRUE if a VM fault has been detected.
> + *
> + * \param chip_class   chip class
> + * \param old_dmesg_timestamp  previous dmesg timestamp parsed at init time
> + * \param out_addr detected VM fault addr
> + */
> +bool ac_vm_fault_occured(enum chip_class chip_class,
> +uint64_t *old_dmesg_timestamp, uint64_t *out_addr)
> +{
> +   char line[2000];
> +   unsigned sec, usec;
> +   int progress = 0;
> +   uint64_t dmesg_timestamp = 0;
> +   bool fault = false;
> +
> +   FILE *p = popen("dmesg", "r");
> +   if (!p)
> +   return false;
> +
> +   while (fgets(line, sizeof(line), p)) {
> +   char *msg, len;
> +
> +   if (!line[0] || line[0] == '\n')
> +   continue;
> +
> +   /* Get the timestamp. */
> +   if (sscanf(line, "[%u.%u]", , ) != 2) {
> +   static bool hit = false;
> +   if (!hit) {
> +   fprintf(stderr, "%s: failed to parse line 
> '%s'\n",
> +   __func__, line);
> +   hit = true;
> +   }
> +   continue;
> +   }
> +   dmesg_timestamp = sec * 100ull + usec;
> +
> +   /* If just updating the timestamp. */
> +   if (!out_addr)
> +   continue;
> +
> +   /* Process messages only if the timestamp is newer. */
> +   if (dmesg_timestamp <= *old_dmesg_timestamp)
> +   continue;
> +
> +   /* Only process the first VM fault. */
> +   if (fault)
> +   continue;
> +
> +   /* Remove trailing \n */
> +   len = strlen(line);
> +   if (len && line[len-1] == '\n')
> +   line[len-1] = 0;
> +
> +   /* Get the message part. */
> +   msg = strchr(line, ']');
> +   if (!msg)
> +   continue;
> +   msg++;
> +
> +   const char *header_line, *addr_line_prefix, *addr_line_format;
> +
> +   if (chip_class >= GFX9) {
> +   /* Match this:
> +* ..: [gfxhub] VMC page fault (src_id:0 ring:158 
> vm_id:2 pas_id:0)
> +* ..:   at page 0x000219f8f000 from 27
> +* ..: VM_L2_PROTECTION_FAULT_STATUS:0x0020113C
> +*/
> +   header_line = "VMC page fault";
> +   addr_line_prefix = "   at page";
> +   addr_line_format = "%"PRIx64;
> +   } else {
> +   header_line = "GPU fault detected:";
> +   addr_line_prefix = 
> "VM_CONTEXT1_PROTECTION_FAULT_ADDR";
> +   addr_line_format = "%"PRIX64;
> +   }
> +
> +   switch (progress) {
> +   case 0:
> +   if (strstr(msg, header_line))
> +   progress = 1;
> +   break;
> +   case 1:
> +   msg = strstr(msg, addr_line_prefix);
> +   if (msg) {
> +   msg = strstr(msg, "0x");
> +   if (msg) {
> +   msg += 2;
> +   if (sscanf(msg, addr_line_format, 
> out_addr) == 1)
> +   fault = true;
> +   }
> +   }
> +   progress = 0;
> +   break;
> +   default:
> +   progress = 0;
> +   }
> +   }
> +   pclose(p);
> +
> +   if 

[Mesa-dev] [PATCH v3 5/7] i965: perf: add support for userspace configurations

[Lionel Landwerlin]

This allows us to deploy new configurations without touching the
kernel.

v2: Detect loadable configs without creating one (Chris)

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 98 ++-
 1 file changed, 95 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 4b585c95b7d..6ec6b417e52 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1717,11 +1717,11 @@ read_file_uint64(const char *file, uint64_t *val)
 
 fd = open(file, 0);
 if (fd < 0)
-   return false;
+return false;
 n = read(fd, buf, sizeof (buf) - 1);
 close(fd);
 if (n < 0)
-   return false;
+return false;
 
 buf[n] = '\0';
 *val = strtoull(buf, NULL, 0);
@@ -1807,6 +1807,95 @@ read_sysfs_drm_device_file_uint64(struct brw_context 
*brw,
return read_file_uint64(buf, value);
 }
 
+static bool
+kernel_has_dynamic_config_support(struct brw_context *brw,
+  const char *sysfs_dev_dir)
+{
+   __DRIscreen *screen = brw->screen->driScrnPriv;
+   struct hash_entry *entry;
+
+   hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
+  struct brw_perf_query_info *query = entry->data;
+  char config_path[256];
+  uint64_t config_id;
+
+  snprintf(config_path, sizeof(config_path),
+   "%s/metrics/%s/id", sysfs_dev_dir, query->guid);
+
+  /* Look for the test config, which we know we can't replace. */
+  if (read_file_uint64(config_path, _id) && config_id == 1) {
+ uint32_t mux_regs[] = { 0x9888 /* NOA_WRITE */, 0x0 };
+ struct drm_i915_perf_oa_config config;
+
+ memset(, 0, sizeof(config));
+
+ memcpy(config.uuid, query->guid, sizeof(config.uuid));
+
+ config.n_mux_regs = 1;
+ config.mux_regs_ptr = (uintptr_t) mux_regs;
+
+ if (ioctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id) 
< 0 &&
+ errno == ENOENT)
+return true;
+
+ break;
+  }
+   }
+
+   return false;
+}
+
+static void
+init_oa_configs(struct brw_context *brw, const char *sysfs_dev_dir)
+{
+   __DRIscreen *screen = brw->screen->driScrnPriv;
+   struct hash_entry *entry;
+
+   hash_table_foreach(brw->perfquery.oa_metrics_table, entry) {
+  struct brw_perf_query_info *query = entry->data;
+  struct drm_i915_perf_oa_config config;
+  char config_path[256];
+  uint64_t config_id;
+  int ret;
+
+  snprintf(config_path, sizeof(config_path),
+   "%s/metrics/%s/id", sysfs_dev_dir, query->guid);
+
+  if (read_file_uint64(config_path, _id)) {
+ if (config_id <= 1)
+continue;
+
+ ioctl(screen->fd, DRM_IOCTL_I915_PERF_REMOVE_CONFIG, _id);
+  }
+
+  memset(, 0, sizeof(config));
+
+  memcpy(config.uuid, query->guid, sizeof(config.uuid));
+
+  config.n_mux_regs = query->n_mux_regs;
+  config.mux_regs_ptr = (uintptr_t) query->mux_regs;
+
+  config.n_boolean_regs = query->n_b_counter_regs;
+  config.boolean_regs_ptr = (uintptr_t) query->b_counter_regs;
+
+  config.n_flex_regs = query->n_flex_regs;
+  config.flex_regs_ptr = (uintptr_t) query->flex_regs;
+
+  ret = ioctl(screen->fd, DRM_IOCTL_I915_PERF_ADD_CONFIG, );
+  if (ret < 0) {
+ DBG("Failed to load \"%s\" (%s) metrics set in kernel: %s\n",
+ query->name, query->guid, strerror(errno));
+  } else {
+ struct brw_perf_query_info *registred_query =
+append_query_info(brw);
+ *registred_query = *query;
+ registred_query->oa_metrics_set_id = ret;
+ DBG("metric set registred: id = %" PRIu64", guid = %s\n",
+ registred_query->oa_metrics_set_id, query->guid);
+  }
+   }
+}
+
 static bool
 init_oa_sys_vars(struct brw_context *brw, const char *sysfs_dev_dir)
 {
@@ -2054,7 +2143,10 @@ brw_init_perf_query_info(struct gl_context *ctx)
*/
   oa_register(brw);
 
-  enumerate_sysfs_metrics(brw, sysfs_dev_dir);
+  if (kernel_has_dynamic_config_support(brw, sysfs_dev_dir))
+ init_oa_configs(brw, sysfs_dev_dir);
+  else
+ enumerate_sysfs_metrics(brw, sysfs_dev_dir);
}
 
brw->perfquery.unaccumulated =
-- 
2.14.1

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[Mesa-dev] [PATCH v3 6/7] i965: add a debug option to disable oa config loading

[Lionel Landwerlin]

This provides a good way to verify we haven't broken using the perf
driver on older kernels (which don't have the oa config loading
mechanism).

Signed-off-by: Lionel Landwerlin 
---
 src/intel/common/gen_debug.c  | 1 +
 src/intel/common/gen_debug.h  | 2 +-
 src/mesa/drivers/dri/i965/brw_performance_query.c | 3 ++-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c
index b604d56ef86..a17d628f577 100644
--- a/src/intel/common/gen_debug.c
+++ b/src/intel/common/gen_debug.c
@@ -57,6 +57,7 @@ static const struct debug_control debug_control[] = {
{ "vert",DEBUG_VERTS },
{ "dri", DEBUG_DRI },
{ "sf",  DEBUG_SF },
+   { "no-oaconfig", DEBUG_NO_OACONFIG },
{ "wm",  DEBUG_WM },
{ "urb", DEBUG_URB },
{ "vs",  DEBUG_VS },
diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h
index d290303682e..8c8cce4f846 100644
--- a/src/intel/common/gen_debug.h
+++ b/src/intel/common/gen_debug.h
@@ -57,7 +57,7 @@ extern uint64_t INTEL_DEBUG;
 #define DEBUG_VERTS   (1ull << 13)
 #define DEBUG_DRI (1ull << 14)
 #define DEBUG_SF  (1ull << 15)
-/* Hole - feel free to reuse  (1ull << 16) */
+#define DEBUG_NO_OACONFIG (1ull << 16)
 #define DEBUG_WM  (1ull << 17)
 #define DEBUG_URB (1ull << 18)
 #define DEBUG_VS  (1ull << 19)
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 6ec6b417e52..34e79f398ab 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -2143,7 +2143,8 @@ brw_init_perf_query_info(struct gl_context *ctx)
*/
   oa_register(brw);
 
-  if (kernel_has_dynamic_config_support(brw, sysfs_dev_dir))
+  if (likely((INTEL_DEBUG & DEBUG_NO_OACONFIG) == 0) &&
+  kernel_has_dynamic_config_support(brw, sysfs_dev_dir))
  init_oa_configs(brw, sysfs_dev_dir);
   else
  enumerate_sysfs_metrics(brw, sysfs_dev_dir);
-- 
2.14.1

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[Mesa-dev] [PATCH v3 2/7] i965: perf: factorize code for availability

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_oa.py | 28 
 1 file changed, 16 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_oa.py 
b/src/mesa/drivers/dri/i965/brw_oa.py
index 91f7ecb5731..8c35923462f 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -325,6 +325,21 @@ semantic_type_map = {
 "ratio": "event"
 }
 
+def output_availability(set, availability, counter_name):
+expression = splice_rpn_expression(set, counter_name, availability)
+lines = expression.split(' && ')
+n_lines = len(lines)
+if n_lines == 1:
+c("if (" + lines[0] + ") {")
+else:
+c("if (" + lines[0] + " &&")
+c_indent(4)
+for i in range(1, (n_lines - 1)):
+c(lines[i] + " &&")
+c(lines[(n_lines - 1)] + ") {")
+c_outdent(4)
+
+
 def output_counter_report(set, counter, current_offset):
 data_type = counter.get('data_type')
 data_type_uc = data_type.upper()
@@ -343,18 +358,7 @@ def output_counter_report(set, counter, current_offset):
 
 availability = counter.get('availability')
 if availability:
-expression = splice_rpn_expression(set, counter, availability)
-lines = expression.split(' && ')
-n_lines = len(lines)
-if n_lines == 1:
-c("if (" + lines[0] + ") {")
-else:
-c("if (" + lines[0] + " &&")
-c_indent(4)
-for i in range(1, (n_lines - 1)):
-c(lines[i] + " &&")
-c(lines[(n_lines - 1)] + ") {")
-c_outdent(4)
+output_availability(set, availability, counter.get('name'))
 c_indent(3)
 
 c("counter = >counters[query->n_counters++];\n")
-- 
2.14.1

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[Mesa-dev] [PATCH v3 0/7] i965: add support for loadable OA configs

[Lionel Landwerlin]

Just a quick update with 2 changes :

 - I forgot to update the configs to register listing (some
   registers are left to be programmed by the configs, not the
   kernel anymore) in patch 3
 - adding Coffeelake support (patch 7)

Cheers,

Lionel Landwerlin (7):
  i965: perf: make revision variable available
  i965: perf: factorize code for availability
  i965: perf: update configs for loading from userspace
  i965: perf: list registers to program for queries
  i965: perf: add support for userspace configurations
  i965: add a debug option to disable oa config loading
  i965: perf: add support for CoffeeLake GT2

 src/intel/common/gen_debug.c  | 1 +
 src/intel/common/gen_debug.h  | 2 +-
 src/mesa/drivers/dri/i965/Makefile.am | 1 +
 src/mesa/drivers/dri/i965/Makefile.sources| 4 +-
 src/mesa/drivers/dri/i965/brw_context.h   |16 +
 src/mesa/drivers/dri/i965/brw_oa.py   |80 +-
 src/mesa/drivers/dri/i965/brw_oa_bdw.xml  |58 +
 src/mesa/drivers/dri/i965/brw_oa_bxt.xml  |16 +
 src/mesa/drivers/dri/i965/brw_oa_cflgt2.xml   | 10473 
 src/mesa/drivers/dri/i965/brw_oa_chv.xml  |28 +
 src/mesa/drivers/dri/i965/brw_oa_glk.xml  |15 +
 src/mesa/drivers/dri/i965/brw_oa_hsw.xml  | 6 +
 src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml   |18 +
 src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml   |18 +
 src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml   |48 +
 src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml   |18 +
 src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml   |18 +
 src/mesa/drivers/dri/i965/brw_performance_query.c |   109 +-
 src/mesa/drivers/dri/i965/intel_screen.c  | 9 +-
 src/mesa/drivers/dri/i965/intel_screen.h  | 3 +
 20 files changed, 10916 insertions(+), 25 deletions(-)
 create mode 100644 src/mesa/drivers/dri/i965/brw_oa_cflgt2.xml

--
2.14.1
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[Mesa-dev] [PATCH v3 3/7] i965: perf: update configs for loading from userspace

[Lionel Landwerlin]

When making configs loadable from userspace in the kernel, we left to
userspace more responsability around programming some registers. In
particular one register we use to set directly in the driver has now
been moved into the configs.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_oa_bdw.xml| 58 +
 src/mesa/drivers/dri/i965/brw_oa_bxt.xml| 16 
 src/mesa/drivers/dri/i965/brw_oa_chv.xml| 28 ++
 src/mesa/drivers/dri/i965/brw_oa_glk.xml| 15 
 src/mesa/drivers/dri/i965/brw_oa_hsw.xml|  6 +++
 src/mesa/drivers/dri/i965/brw_oa_kblgt2.xml | 18 +
 src/mesa/drivers/dri/i965/brw_oa_kblgt3.xml | 18 +
 src/mesa/drivers/dri/i965/brw_oa_sklgt2.xml | 48 
 src/mesa/drivers/dri/i965/brw_oa_sklgt3.xml | 18 +
 src/mesa/drivers/dri/i965/brw_oa_sklgt4.xml | 18 +
 10 files changed, 243 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_oa_bdw.xml 
b/src/mesa/drivers/dri/i965/brw_oa_bdw.xml
index ee3c359e1ba..7b5ecabe861 100644
--- a/src/mesa/drivers/dri/i965/brw_oa_bdw.xml
+++ b/src/mesa/drivers/dri/i965/brw_oa_bdw.xml
@@ -726,6 +726,7 @@
  availability="$SliceMask 0x01 AND"
  priority="0"
  >
+
 
 
 
@@ -831,11 +832,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -946,6 +949,7 @@
 
 
 
+
 
 
 
@@ -1502,6 +1506,7 @@
  availability="$SliceMask 0x01 AND"
  priority="0"
  >
+
 
 
 
@@ -1585,11 +1590,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -1685,6 +1692,7 @@
 
 
 
+
 
 
 
@@ -2313,6 +2321,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -2422,6 +2431,7 @@
 
 
 
+
 
 
 
@@ -3018,6 +3028,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -3066,6 +3077,7 @@
 
 
 
+
 
 
 
@@ -3656,6 +3668,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -3703,6 +3716,7 @@
 
 
 
+
 
 
 
@@ -4262,6 +4276,7 @@
  availability="$SubsliceMask 0x01 AND"
  priority="0"
  >
+
 
 
 
@@ -4374,11 +4389,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -4474,11 +4491,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -4566,11 +4585,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -4699,11 +4720,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -4815,11 +4838,13 @@
 
 
 
+
 
 
+
 
 
 
@@ -4923,6 +4948,7 @@
 
 
 
+
 
 
 
@@ -5756,6 +5782,7 @@
  mdapi_hw_unit_type="gpu"
  />
 
+
 
 
 
@@ -5861,6 +5888,7 @@
 
 
 
+
 
 
 
@@ -6366,6 +6394,7 @@
  availability="$SubsliceMask 0x01 AND"
  priority="0"
  >
+
 
 
 
@@ -6478,6 +6507,7 @@
 
 
 
+
 
 
 
@@ -7033,6 +7063,7 @@
  availability="$SubsliceMask 0x01 AND"
  priority="0"
  >
+
 
 
 
@@ -7141,6 +7172,7 @@
 
 
 
+
 
 
 
@@ -7761,6 +7793,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -7857,6 +7890,7 @@
 
 
 
+
 
 
 
@@ -8417,6 +8451,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -8506,6 +8541,7 @@
 
 
 
+
 
 
 
@@ -9080,6 +9116,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -9156,6 +9193,7 @@
 
 
 
+
 
 
 
@@ -9730,6 +9768,7 @@
  mdapi_group="L3/Data Port/Atomics"
  />
 
+
 
 
 
@@ -9822,6 

[Mesa-dev] [PATCH v3 1/7] i965: perf: make revision variable available

[Lionel Landwerlin]

This will be used in the next commit to build up register programming.

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_context.h   | 1 +
 src/mesa/drivers/dri/i965/brw_oa.py   | 1 +
 src/mesa/drivers/dri/i965/brw_performance_query.c | 4 +++-
 src/mesa/drivers/dri/i965/intel_screen.c  | 9 ++---
 src/mesa/drivers/dri/i965/intel_screen.h  | 3 +++
 5 files changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 38f9b5fc670..3d3de1b7b83 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1079,6 +1079,7 @@ struct brw_context
  uint64_t subslice_mask;   /** $SubsliceMask */
  uint64_t gt_min_freq; /** $GpuMinFrequency */
  uint64_t gt_max_freq; /** $GpuMaxFrequency */
+ uint64_t revision;/** $SkuRevisionId */
   } sys_vars;
 
   /* OA metric sets, indexed by GUID, as know by Mesa at build time,
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py 
b/src/mesa/drivers/dri/i965/brw_oa.py
index 254c512a7da..91f7ecb5731 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -175,6 +175,7 @@ hw_vars["$SubsliceMask"] = 
"brw->perfquery.sys_vars.subslice_mask"
 hw_vars["$GpuTimestampFrequency"] = 
"brw->perfquery.sys_vars.timestamp_frequency"
 hw_vars["$GpuMinFrequency"] = "brw->perfquery.sys_vars.gt_min_freq"
 hw_vars["$GpuMaxFrequency"] = "brw->perfquery.sys_vars.gt_max_freq"
+hw_vars["$SkuRevisionId"] = "brw->perfquery.sys_vars.revision"
 
 def output_rpn_equation_code(set, counter, equation, counter_vars):
 c("/* RPN equation: " + equation + " */")
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index d8680b48793..4b585c95b7d 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1812,6 +1812,7 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
 {
const struct gen_device_info *devinfo = >screen->devinfo;
uint64_t min_freq_mhz = 0, max_freq_mhz = 0;
+   __DRIscreen *screen = brw->screen->driScrnPriv;
 
if (!read_sysfs_drm_device_file_uint64(brw, sysfs_dev_dir,
   "gt_min_freq_mhz",
@@ -1826,6 +1827,8 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
brw->perfquery.sys_vars.gt_min_freq = min_freq_mhz * 100;
brw->perfquery.sys_vars.gt_max_freq = max_freq_mhz * 100;
brw->perfquery.sys_vars.timestamp_frequency = devinfo->timestamp_frequency;
+
+   brw->perfquery.sys_vars.revision = intel_device_get_revision(screen->fd);
brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices;
/* Assuming uniform distribution of subslices per slices. */
brw->perfquery.sys_vars.n_eu_sub_slices = devinfo->num_subslices[0];
@@ -1848,7 +1851,6 @@ init_oa_sys_vars(struct brw_context *brw, const char 
*sysfs_dev_dir)
   } else
  unreachable("not reached");
} else {
-  __DRIscreen *screen = brw->screen->driScrnPriv;
   drm_i915_getparam_t gp;
   int ret;
   int slice_mask = 0;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index e0827cab36c..54e6dc33bb4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2065,14 +2065,9 @@ set_max_gl_versions(struct intel_screen *screen)
 /**
  * Return the revision (generally the revid field of the PCI header) of the
  * graphics device.
- *
- * XXX: This function is useful to keep around even if it is not currently in
- * use. It is necessary for new platforms and revision specific workarounds or
- * features. Please don't remove it so that we know it at least continues to
- * build.
  */
-static __attribute__((__unused__)) int
-brw_get_revision(int fd)
+int
+intel_device_get_revision(int fd)
 {
struct drm_i915_getparam gp;
int revision;
diff --git a/src/mesa/drivers/dri/i965/intel_screen.h 
b/src/mesa/drivers/dri/i965/intel_screen.h
index 41e1dbdd4e9..7948617b7f0 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.h
+++ b/src/mesa/drivers/dri/i965/intel_screen.h
@@ -136,6 +136,9 @@ double get_time(void);
 const int*
 intel_supported_msaa_modes(const struct intel_screen  *screen);
 
+int
+intel_device_get_revision(int fd);
+
 static inline bool
 can_do_pipelined_register_writes(const struct intel_screen *screen)
 {
-- 
2.14.1

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[Mesa-dev] [PATCH v3 4/7] i965: perf: list registers to program for queries

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/mesa/drivers/dri/i965/brw_context.h | 15 ++
 src/mesa/drivers/dri/i965/brw_oa.py | 51 +
 2 files changed, 66 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 3d3de1b7b83..7f3f394d00d 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -603,6 +603,11 @@ enum brw_query_kind {
PIPELINE_STATS
 };
 
+struct brw_perf_query_register_prog {
+   uint32_t reg;
+   uint32_t val;
+};
+
 struct brw_perf_query_info
 {
enum brw_query_kind kind;
@@ -622,6 +627,16 @@ struct brw_perf_query_info
int a_offset;
int b_offset;
int c_offset;
+
+   /* Register programming for a given query */
+   struct brw_perf_query_register_prog *flex_regs;
+   uint32_t n_flex_regs;
+
+   struct brw_perf_query_register_prog *mux_regs;
+   uint32_t n_mux_regs;
+
+   struct brw_perf_query_register_prog *b_counter_regs;
+   uint32_t n_b_counter_regs;
 };
 
 /**
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py 
b/src/mesa/drivers/dri/i965/brw_oa.py
index 8c35923462f..576ea6687fc 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -380,6 +380,45 @@ def output_counter_report(set, counter, current_offset):
 return current_offset + sizeof(c_type)
 
 
+register_types = {
+'FLEX': 'flex_regs',
+'NOA': 'mux_regs',
+'OA': 'b_counter_regs',
+}
+
+def compute_register_lengths(set):
+register_lengths = {}
+register_configs = set.findall('register_config')
+for register_config in register_configs:
+t = register_types[register_config.get('type')]
+if t not in register_lengths:
+register_lengths[t] = len(register_config.findall('register'))
+else:
+register_lengths[t] += len(register_config.findall('register'))
+
+return register_lengths
+
+
+def generate_register_configs(set):
+register_configs = set.findall('register_config')
+for register_config in register_configs:
+t = register_types[register_config.get('type')]
+
+availability = register_config.get('availability')
+if availability:
+output_availability(set, availability, register_config.get('type') 
+ ' register config')
+c_indent(3)
+
+for register in register_config.findall('register'):
+c("query->%s[query->n_%s++] = (struct 
brw_perf_query_register_prog) { .reg = %s, .val = %s };" %
+  (t, t, register.get('address'), register.get('value')))
+
+if availability:
+c_outdent(3)
+c("}")
+c("\n")
+
+
 def main():
 global c_file
 global header_file
@@ -475,6 +514,12 @@ def main():
 max_values[counter.get('symbol_name')] = output_counter_max(set, 
counter, empty_vars)
 counter_vars["$" + counter.get('symbol_name')] = counter
 
+c("\n")
+register_lengths = compute_register_lengths(set);
+for reg_type, reg_length in register_lengths.iteritems():
+c("static struct brw_perf_query_register_prog 
{0}_{1}_{2}[{3}];".format(chipset,
+   
 set.get('underscore_name'),
+   
 reg_type, reg_length))
 
 c("\nstatic struct brw_perf_query_counter 
{0}_{1}_query_counters[{2}];\n".format(chipset, set.get('underscore_name'), 
len(counters)))
 c("static struct brw_perf_query_info " + chipset + "_" + 
set.get('underscore_name') + "_query = {\n")
@@ -510,6 +555,10 @@ def main():
 .c_offset = 46,
 """))
 
+for reg_type, reg_length in register_lengths.iteritems():
+c(".{0} = {1}_{2}_{3},".format(reg_type, chipset, 
set.get('underscore_name'), reg_type))
+c(".n_{0} = 0, /* Determined at runtime */".format(reg_type))
+
 c_outdent(3)
 c("};\n")
 
@@ -528,6 +577,8 @@ def main():
 c("\nif (!query->data_size) {")
 c_indent(3)
 
+generate_register_configs(set)
+
 offset = 0
 for counter in counters:
 offset = output_counter_report(set, counter, offset)
-- 
2.14.1

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[Mesa-dev] [PATCH 1/1] android: VK_ANDROID_native_buffer implementation WIP

[Tapani Pälli]

Signed-off-by: Tapani Pälli 
---
 Android.common.mk   |  3 ++
 include/vulkan/vulkan_intel.h   | 12 +
 src/intel/Android.vulkan.mk |  4 +-
 src/intel/Makefile.sources  |  3 ++
 src/intel/vulkan/anv_entrypoints_gen.py | 24 ++
 src/intel/vulkan/anv_extensions.py  |  1 +
 src/intel/vulkan/anv_image.c| 69 +++
 src/intel/vulkan/anv_wsi_android.c  | 82 +
 src/vulkan/registry/vk.xml  |  2 +-
 9 files changed, 198 insertions(+), 2 deletions(-)
 create mode 100644 src/intel/vulkan/anv_wsi_android.c

diff --git a/Android.common.mk b/Android.common.mk
index ecbbd87165..66f9ccdeec 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -103,6 +103,9 @@ endif
 LOCAL_CFLAGS_32 += 
-DDEFAULT_DRIVER_DIR=\"/system/lib/$(MESA_DRI_MODULE_REL_PATH)\"
 LOCAL_CFLAGS_64 += 
-DDEFAULT_DRIVER_DIR=\"/system/lib64/$(MESA_DRI_MODULE_REL_PATH)\"
 
+# Enable VK_ANDROID_native_buffer
+LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR
+
 # uncomment to keep the debug symbols
 #LOCAL_STRIP_MODULE := false
 
diff --git a/include/vulkan/vulkan_intel.h b/include/vulkan/vulkan_intel.h
index 8ede61b53d..23078fcc34 100644
--- a/include/vulkan/vulkan_intel.h
+++ b/include/vulkan/vulkan_intel.h
@@ -55,6 +55,18 @@ VKAPI_ATTR VkResult VKAPI_CALL vkCreateDmaBufImageINTEL(
 
 #endif
 
+#ifdef VK_USE_PLATFORM_ANDROID_KHR
+#ifndef PFN_vkGetSwapchainGrallocUsageANDROID
+typedef VkResult (VKAPI_PTR *PFN_vkGetSwapchainGrallocUsageANDROID)(VkDevice 
device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage);
+#endif
+#ifndef PFN_vkAcquireImageANDROID
+typedef VkResult (VKAPI_PTR *PFN_vkAcquireImageANDROID)(VkDevice device, 
VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence);
+#endif
+#ifndef PFN_vkQueueSignalReleaseImageANDROID
+typedef VkResult (VKAPI_PTR *PFN_vkQueueSignalReleaseImageANDROID)(VkQueue 
queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage 
image, int* pNativeFenceFd);
+#endif
+#endif
+
 #ifdef __cplusplus
 } // extern "C"
 #endif // __cplusplus
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 44edafd24f..bd5ec01468 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -194,12 +194,14 @@ LOCAL_MODULE_CLASS := STATIC_LIBRARIES
 
 intermediates := $(call local-generated-sources-dir)
 
-LOCAL_SRC_FILES := $(VULKAN_FILES)
+LOCAL_SRC_FILES := $(VULKAN_FILES) $(VULKAN_WSI_ANDROID_FILES)
 
 LOCAL_C_INCLUDES := \
$(ANV_INCLUDES) \
$(MESA_TOP)/src/compiler
 
+LOCAL_CFLAGS += -isystem frameworks/native/vulkan/include
+
 LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_anv_entrypoints \
libmesa_genxml \
diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index 4074ba9ee5..752e137b6b 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -232,6 +232,9 @@ VULKAN_WSI_WAYLAND_FILES := \
 VULKAN_WSI_X11_FILES := \
vulkan/anv_wsi_x11.c
 
+VULKAN_WSI_ANDROID_FILES := \
+   vulkan/anv_wsi_android.c
+
 VULKAN_GEM_FILES := \
vulkan/anv_gem.c
 
diff --git a/src/intel/vulkan/anv_entrypoints_gen.py 
b/src/intel/vulkan/anv_entrypoints_gen.py
index f5c527ed92..7ddfcad839 100644
--- a/src/intel/vulkan/anv_entrypoints_gen.py
+++ b/src/intel/vulkan/anv_entrypoints_gen.py
@@ -360,6 +360,30 @@ def main():
 'VkImage* pImage', len(entrypoints),
 cal_hash('vkCreateDmaBufImageINTEL'), None))
 
+# Insert Android specific entrypoints
+entrypoints.append(('VkResult', 'GetSwapchainGrallocUsageANDROID',
+'VkDevice device, ' +
+'VkFormat fmt, ' +
+'VkImageUsageFlags usage, ' +
+'int *grallocUsage', len(entrypoints),
+cal_hash('vkGetSwapchainGrallocUsageANDROID'), None))
+
+entrypoints.append(('VkResult', 'AcquireImageANDROID',
+'VkDevice device, ' +
+'VkImage image, ' +
+'int nativeFenceFd, ' +
+'VkSemaphore semaphore, ' +
+'VkFence fence', len(entrypoints),
+cal_hash('vkAcquireImageANDROID'), None))
+
+entrypoints.append(('VkResult', 'QueueSignalReleaseImageANDROID',
+'VkQueue queue, ' +
+'uint32_t waitSemaphoreCount, ' +
+'const VkSemaphore* pWaitSemaphores, ' +
+'VkImage image, ' +
+'int *pNativeFenceFd', len(entrypoints),
+cal_hash('vkQueueSignalReleaseImageANDROID'), None))
+
 # For outputting entrypoints.h we generate a anv_EntryPoint() prototype
 # per entry point.
 with open(os.path.join(args.outdir, 'anv_entrypoints.h'), 'wb') as 

[Mesa-dev] [PATCH 0/1] VK_ANDROID_native_buffer RFC

[Tapani Pälli]

Hi;

Here's a rebased and fixed version of VK_ANDROID_native_buffer
extension implementation. I did a initial implementation of this
around 7 months ago here:

   https://github.com/tpalli/external-mesa/tree/vulkan

For a number of reasons we decided for that code to live in our
Vulkan HAL implementation instead (which is used currently):

   https://github.com/intel/external-vulkan_hal

Now as I noticed familiar patches from Louis-Francis removing the
precious vkCreateDmaBufImageINTEL() function, I've decided to send
this for comments or just generic mockery. The CreateImage part
could be changed to use VK_KHX_external_memory_fd, like I've done
here for HAL:

https://github.com/tpalli/external-vulkan_hal/tree/new-image-import

but I've been blocked waiting for VK_MESAX_external_memory_dma_buf
to materialize, could use 'get_tiling ioctl' though.

Any comments appreciated;


Tapani Pälli (1):
  android: VK_ANDROID_native_buffer implementation WIP

 Android.common.mk   |  3 ++
 include/vulkan/vulkan_intel.h   | 12 +
 src/intel/Android.vulkan.mk |  4 +-
 src/intel/Makefile.sources  |  3 ++
 src/intel/vulkan/anv_entrypoints_gen.py | 24 ++
 src/intel/vulkan/anv_extensions.py  |  1 +
 src/intel/vulkan/anv_image.c| 69 +++
 src/intel/vulkan/anv_wsi_android.c  | 82 +
 src/vulkan/registry/vk.xml  |  2 +-
 9 files changed, 198 insertions(+), 2 deletions(-)
 create mode 100644 src/intel/vulkan/anv_wsi_android.c

-- 
2.13.5

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[Mesa-dev] [PATCH 1/3] radv: add radv_check_gpu_hangs() helper function

[Samuel Pitoiset]

That way, most of the debug code will be at the same place.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_debug.c  | 26 +-
 src/amd/vulkan/radv_debug.h  |  3 ++-
 src/amd/vulkan/radv_device.c | 11 +--
 3 files changed, 28 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 9913c06ec2..4024f75da8 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -47,7 +47,7 @@ radv_init_trace(struct radv_device *device)
return true;
 }
 
-void
+static void
 radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs)
 {
const char *filename = getenv("RADV_TRACE_FILE");
@@ -63,6 +63,30 @@ radv_dump_trace(struct radv_device *device, struct 
radeon_winsys_cs *cs)
fclose(f);
 }
 
+static bool
+radv_gpu_hang_occured(struct radv_queue *queue)
+{
+   struct radeon_winsys *ws = queue->device->ws;
+   enum ring_type ring;
+
+   ring = radv_queue_family_to_ring(queue->queue_family_index);
+
+   if (!ws->ctx_wait_idle(queue->hw_ctx, ring, queue->queue_idx))
+   return true;
+
+   return false;
+}
+
+void
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
+{
+   if (!radv_gpu_hang_occured(queue))
+   return;
+
+   radv_dump_trace(queue->device, cs);
+   abort();
+}
+
 void
 radv_print_spirv(struct radv_shader_module *module, FILE *fp)
 {
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index d2fbe695fc..cafb0ee20f 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -47,7 +47,8 @@ enum {
 
 bool radv_init_trace(struct radv_device *device);
 
-void radv_dump_trace(struct radv_device *device, struct radeon_winsys_cs *cs);
+void
+radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs);
 
 void radv_print_spirv(struct radv_shader_module *module, FILE *fp);
 
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index cbba04a5d6..a5898691df 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2129,16 +2129,7 @@ VkResult radv_QueueSubmit(
}
fence_emitted = true;
if (queue->device->trace_bo) {
-   bool success = queue->device->ws->ctx_wait_idle(
-   queue->hw_ctx,
-   
radv_queue_family_to_ring(
-   
queue->queue_family_index),
-   queue->queue_idx);
-
-   if (!success) { /* Hang */
-   radv_dump_trace(queue->device, 
cs_array[j]);
-   abort();
-   }
+   radv_check_gpu_hangs(queue, cs_array[j]);
}
}
 
-- 
2.14.1

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[Mesa-dev] [PATCH 2/3] radeonsi: move si_vm_fault_occured() to AMD common code

[Samuel Pitoiset]

For radv, in order to report VM faults when detected.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/common/ac_debug.c   | 109 
 src/amd/common/ac_debug.h   |   4 ++
 src/gallium/drivers/radeonsi/si_debug.c | 106 ++-
 3 files changed, 117 insertions(+), 102 deletions(-)

diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index d46fc27a9e..0de00e27e7 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -34,6 +34,8 @@
 #define VG(x)
 #endif
 
+#include 
+
 #include "sid.h"
 #include "gfx9d.h"
 #include "sid_tables.h"
@@ -597,3 +599,110 @@ void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw, const 
int *trace_ids,
 
fprintf(f, "--- %s end ---\n\n", name);
 }
+
+/**
+ * Parse dmesg and return TRUE if a VM fault has been detected.
+ *
+ * \param chip_class   chip class
+ * \param old_dmesg_timestamp  previous dmesg timestamp parsed at init time
+ * \param out_addr detected VM fault addr
+ */
+bool ac_vm_fault_occured(enum chip_class chip_class,
+uint64_t *old_dmesg_timestamp, uint64_t *out_addr)
+{
+   char line[2000];
+   unsigned sec, usec;
+   int progress = 0;
+   uint64_t dmesg_timestamp = 0;
+   bool fault = false;
+
+   FILE *p = popen("dmesg", "r");
+   if (!p)
+   return false;
+
+   while (fgets(line, sizeof(line), p)) {
+   char *msg, len;
+
+   if (!line[0] || line[0] == '\n')
+   continue;
+
+   /* Get the timestamp. */
+   if (sscanf(line, "[%u.%u]", , ) != 2) {
+   static bool hit = false;
+   if (!hit) {
+   fprintf(stderr, "%s: failed to parse line 
'%s'\n",
+   __func__, line);
+   hit = true;
+   }
+   continue;
+   }
+   dmesg_timestamp = sec * 100ull + usec;
+
+   /* If just updating the timestamp. */
+   if (!out_addr)
+   continue;
+
+   /* Process messages only if the timestamp is newer. */
+   if (dmesg_timestamp <= *old_dmesg_timestamp)
+   continue;
+
+   /* Only process the first VM fault. */
+   if (fault)
+   continue;
+
+   /* Remove trailing \n */
+   len = strlen(line);
+   if (len && line[len-1] == '\n')
+   line[len-1] = 0;
+
+   /* Get the message part. */
+   msg = strchr(line, ']');
+   if (!msg)
+   continue;
+   msg++;
+
+   const char *header_line, *addr_line_prefix, *addr_line_format;
+
+   if (chip_class >= GFX9) {
+   /* Match this:
+* ..: [gfxhub] VMC page fault (src_id:0 ring:158 
vm_id:2 pas_id:0)
+* ..:   at page 0x000219f8f000 from 27
+* ..: VM_L2_PROTECTION_FAULT_STATUS:0x0020113C
+*/
+   header_line = "VMC page fault";
+   addr_line_prefix = "   at page";
+   addr_line_format = "%"PRIx64;
+   } else {
+   header_line = "GPU fault detected:";
+   addr_line_prefix = "VM_CONTEXT1_PROTECTION_FAULT_ADDR";
+   addr_line_format = "%"PRIX64;
+   }
+
+   switch (progress) {
+   case 0:
+   if (strstr(msg, header_line))
+   progress = 1;
+   break;
+   case 1:
+   msg = strstr(msg, addr_line_prefix);
+   if (msg) {
+   msg = strstr(msg, "0x");
+   if (msg) {
+   msg += 2;
+   if (sscanf(msg, addr_line_format, 
out_addr) == 1)
+   fault = true;
+   }
+   }
+   progress = 0;
+   break;
+   default:
+   progress = 0;
+   }
+   }
+   pclose(p);
+
+   if (dmesg_timestamp > *old_dmesg_timestamp)
+   *old_dmesg_timestamp = dmesg_timestamp;
+
+   return fault;
+}
diff --git a/src/amd/common/ac_debug.h b/src/amd/common/ac_debug.h
index a37acd2029..277025d8b6 100644
--- a/src/amd/common/ac_debug.h
+++ b/src/amd/common/ac_debug.h
@@ -28,6 +28,7 @@
 
 #include 
 #include 
+#include 
 
 #include "amd_family.h"
 
@@ -46,4 +47,7 @@ void ac_parse_ib(FILE 

[Mesa-dev] [PATCH 3/3] radv: report VM faults if detected

[Samuel Pitoiset]

It's fairly simple for now, but this might be quite useful.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_debug.c   | 13 +
 src/amd/vulkan/radv_private.h |  3 +++
 2 files changed, 16 insertions(+)

diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index 4024f75da8..949eeea2f3 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 
+#include "ac_debug.h"
 #include "radv_debug.h"
 
 bool
@@ -44,6 +45,9 @@ radv_init_trace(struct radv_device *device)
if (!device->trace_id_ptr)
return false;
 
+   ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
+   >dmesg_timestamp, NULL);
+
return true;
 }
 
@@ -80,9 +84,18 @@ radv_gpu_hang_occured(struct radv_queue *queue)
 void
 radv_check_gpu_hangs(struct radv_queue *queue, struct radeon_winsys_cs *cs)
 {
+   struct radv_device *device = queue->device;
+   uint64_t addr;
+
if (!radv_gpu_hang_occured(queue))
return;
 
+   if (ac_vm_fault_occured(device->physical_device->rad_info.chip_class,
+   >dmesg_timestamp, )) {
+   fprintf(stderr, "VM fault report.\n\n");
+   fprintf(stderr, "Failing VM page: 0x%08"PRIx64"\n\n", addr);
+   }
+
radv_dump_trace(queue->device, cs);
abort();
 }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 73f7bdbe8a..28e70e6915 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -555,6 +555,9 @@ struct radv_device {
uint32_t fmask_mrt_offset_counter;
struct list_head shader_slabs;
mtx_t shader_slab_mutex;
+
+   /* For detecting VM faults reported by dmesg. */
+   uint64_t dmesg_timestamp;
 };
 
 struct radv_device_memory {
-- 
2.14.1

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[Mesa-dev] [ANNOUNCE] mesa 17.2.0-rc6

[Emil Velikov]

The sixth release candidate for Mesa 17.2.0 is now available.

Promotion to Mesa 17.2.0 (final) will happen in approximately 48 hours and
only crucial fixes will be accepted at this point.

Further fixes will have to wait for the 17.2.1 release.

Bas Nieuwenhuizen (5):
  ac/nir: Cast sources of integer ops to int.
  radv: Remove some intel comments from the resolve code.
  radv: Don't set a new subpass on compute resolve.
  radv: Fix off by one in MAX_VBS assert.
  radv: Fix sparse BO mapping merging.

Christian Gmeiner (1):
  etnaviv: use correct param for etna_compatible_rs_format(..)

Christoph Haag (1):
  mesa: only copy requested compressed teximage cubemap faces

Daniel Stone (2):
  egl: Update headers from Khronos
  egl: Add dma_buf_import_modifiers for glvnd

Dave Airlie (16):
  radv: disable texture gather workaround on gfx9.
  ac/nir: fixup layer/viewport export for GFX9.
  radv/gfx9: use total levels in texture descriptor
  radv/gfx9: fix level count in color register setup.
  radv/gfx9: fixup db/stencil disable.
  radv: bump space check for indexed draw.
  radv/gfx9: emit sx_mrt_blend registers
  radv: cleanup some image view descriptor setup.
  radv/image: don't rescale width/height if the format isn't changing
  radv/gfx9: only minify image view width/height/depth before gfx9.
  radv: don't degrade tiling mode for small compressed or depth texture.
  radv/gfx9: don't expose linear depth on vega.
  radv/gfx9: gfx9 has buffer sizing rules like pre-VI.
  radv: fix predication on gfx9
  radv: don't crash if we have no framebuffer
  radv/wsi: Compute correct row_pitch for GFX9.

Emil Velikov (7):
  util: move string_to_uint_map to glsl
  egl: don't NULL deref the .get_capabilities function pointer
  egl/wayland: plug leaks in dri2_wl_create_window_surface() error path
  egl/wayland: polish object teardown in dri2_wl_destroy_surface
  egl/wayland: set correct format with wl_dmabuf as wl_drm is missing
  egl/wayland: make sure HAS_$FORMAT is set for wl_dmabuf
  Update version to 17.2.0-rc6

Grazvydas Ignotas (1):
  radv: clear dynamic_shader_stages on create

Ilia Mirkin (3):
  nv50/ir: properly set sType for TXF ops to U32
  glsl: fix counting of vertex shader output slots used by explicit vars
  st/mesa: fix handling of vertex array double inputs

Jason Ekstrand (10):
  i965/miptree Remove layout_flags parameter form is_mcs_supported
  i965/miptree: Delete some unused layout flags
  i965/miptree: Delete MIPTREE_LAYOUT_FOR_SCANOUT
  i965/miptree: Delete MIPTREE_LAYOUT_TILING_(Y|ANY)
  i965/miptree: Rework create flags
  i965: Stop looking at NewDriverState when emitting 3DSTATE_URB
  i965/miptree: Return NONE from texture_aux_usage when fully resolved
  i965/tex: Don't pass samples to miptree_create_for_teximage
  i965/clear: Quantize the depth clear value based on the format
  nir: Fix system_value_from_intrinsic for subgroups

Kai Chen (1):
  egl/wayland: Use roundtrips when awaiting buffer release

Kenneth Graunke (2):
  i965: Mark all EGLimages as non-coherent.
  i965: Make a BRW_NEW_FAST_CLEAR_COLOR dirty bit.

Marek Olšák (3):
  radeonsi/gfx9: add a temporary workaround for a tessellation driver bug
  radeonsi/gfx9: properly handle imported textures with unexpected
swizzle mode
  radeonsi: emit VGT_REUSE_OFF in the right place

Rob Herring (1):
  Android: Fix LLVM duplicated symbols linking for N and M

Samuel Pitoiset (1):
  radeonsi: update non-resident bindless descriptors if needed

Timothy Arceri (1):
  mesa: fix ES only draw if we have vertex positions

Topi Pohjolainen (1):
  intel/blorp: Adjust intra-tile x when faking rgb with red-only

git tag: mesa-17.2.0-rc6

https://mesa.freedesktop.org/archive/mesa-17.2.0-rc6.tar.gz
MD5:  742645a95da0bb5a11e1966212467420  mesa-17.2.0-rc6.tar.gz
SHA1: d8bba8b66c613225f6c6f8bc04344c0c9404d026  mesa-17.2.0-rc6.tar.gz
SHA256: ce25345b7da886cdc730299065e2f27ac285eddc75c89595be16cb8ec8497fcc
 mesa-17.2.0-rc6.tar.gz
SHA512: 
5e079aa6e6f1b20c5072071f1ae628d24ece53d8712f159e7a9ee4abff97448854a0e61ad5e83e100245178ce24d45f0d614c8ea74f2056a4d7e536d9a580bcc
 mesa-17.2.0-rc6.tar.gz
PGP:  https://mesa.freedesktop.org/archive/mesa-17.2.0-rc6.tar.gz.sig

https://mesa.freedesktop.org/archive/mesa-17.2.0-rc6.tar.xz
MD5:  714fd2b76cb7d5c3177ab74a4f1f3e81  mesa-17.2.0-rc6.tar.xz
SHA1: 6fcee1ac3a1ae67846f2501340396e7410441236  mesa-17.2.0-rc6.tar.xz
SHA256: 579d928682675b69b433521e4c44a21bd65c2ad021f43e9d4b98dd93002da5b1
 mesa-17.2.0-rc6.tar.xz
SHA512: 
5a7c0d987f13d6213b427af8a1da6da1c7a27388c24d7b764815faa4f11607d85e5bf9247180ccb22db835923e77e38a7446041564ac921f9223b4aefdb65697
 mesa-17.2.0-rc6.tar.xz
PGP:  https://mesa.freedesktop.org/archive/mesa-17.2.0-rc6.tar.xz.sig
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[Mesa-dev] [PATCH v2] radv/meta: missing initialisations in create_pass().

[Xavier Bouchoux]

Otherwise radv_cmd_state_setup_attachments() will complain it has no 
clearvalues,
when called via radv_process_depth_image_inplace().

v2: use LOAD/STORE instead of DONT_CARE, to preserve stencil values.

Signed-off-by: Xavier Bouchoux 
---
 src/amd/vulkan/radv_meta_decompress.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_decompress.c 
b/src/amd/vulkan/radv_meta_decompress.c
index f68ce8d2b0..1395207b83 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -38,10 +38,13 @@ create_pass(struct radv_device *device,
const VkAllocationCallbacks *alloc = >meta_state.alloc;
VkAttachmentDescription attachment;
 
+   attachment.flags = 0;
attachment.format = VK_FORMAT_D32_SFLOAT_S8_UINT;
attachment.samples = samples;
attachment.loadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
attachment.storeOp = VK_ATTACHMENT_STORE_OP_STORE;
+   attachment.stencilLoadOp = VK_ATTACHMENT_LOAD_OP_LOAD;
+   attachment.stencilStoreOp = VK_ATTACHMENT_STORE_OP_STORE;
attachment.initialLayout = 
VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
attachment.finalLayout = 
VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL;
 
-- 
2.14.1

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[Mesa-dev] [Bug 102488] radv_handle_depth_image_transition() wrongly clearing depth data when transitioning to htile.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=102488

Bug ID: 102488
   Summary: radv_handle_depth_image_transition() wrongly clearing
depth data when transitioning to htile.
   Product: Mesa
   Version: git
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: xavi...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 133895
  --> https://bugs.freedesktop.org/attachment.cgi?id=133895=edit
proposed fix

Hello,

I had a problem with a program doing manipulation of the depth buffer 
(to do downscaled rendering of part of the scene), and attached patch fixes it. 

However, I really have no idea of what the flush flags should be
(as they are different in radv_initialize_htile()), nor if it's the correct way 
nor if it should only apply in some cases...

I also tested that "Mad Max" still works.

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Re: [Mesa-dev] [PATCH] anv: fix build errors on android

[Tapani Pälli]

On 08/31/2017 10:08 AM, Jason Ekstrand wrote:

VK_NULL_HANDLE?


Sure, r-b with that?



On August 30, 2017 22:52:32 Tapani Pälli  wrote:


error: incompatible pointer to integer conversion initializing 'VkFence'
   (aka 'unsigned long long') with an expression of type 'void *'
[-Werror,-Wint-conversion]


Signed-off-by: Tapani Pälli 
---
 src/intel/vulkan/anv_queue.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 429bac9739..d675e8667e 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -169,7 +169,7 @@ VkResult anv_QueueSubmit(

for (uint32_t i = 0; i < submitCount; i++) {
   /* Fence for this submit.  NULL for all but the last one */
-  VkFence submit_fence = (i == submitCount - 1) ? fence : NULL;
+  VkFence submit_fence = (i == submitCount - 1) ? fence : 0;

   if (pSubmits[i].commandBufferCount == 0) {
  /* If we don't have any command buffers, we need to submit a 
dummy

@@ -197,7 +197,7 @@ VkResult anv_QueueSubmit(

  /* Fence for this execbuf.  NULL for all but the last one */
  VkFence execbuf_fence =
-(j == pSubmits[i].commandBufferCount - 1) ? submit_fence 
: NULL;
+(j == pSubmits[i].commandBufferCount - 1) ? submit_fence 
: 0;


  const VkSemaphore *in_semaphores = NULL, *out_semaphores = 
NULL;

  uint32_t num_in_semaphores = 0, num_out_semaphores = 0;
--
2.13.5





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Re: [Mesa-dev] [PATCH] anv: fix build errors on android

[Jason Ekstrand]

VK_NULL_HANDLE?


On August 30, 2017 22:52:32 Tapani Pälli  wrote:


error: incompatible pointer to integer conversion initializing 'VkFence'
   (aka 'unsigned long long') with an expression of type 'void *' 
   [-Werror,-Wint-conversion]


Signed-off-by: Tapani Pälli 
---
 src/intel/vulkan/anv_queue.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_queue.c b/src/intel/vulkan/anv_queue.c
index 429bac9739..d675e8667e 100644
--- a/src/intel/vulkan/anv_queue.c
+++ b/src/intel/vulkan/anv_queue.c
@@ -169,7 +169,7 @@ VkResult anv_QueueSubmit(

for (uint32_t i = 0; i < submitCount; i++) {
   /* Fence for this submit.  NULL for all but the last one */
-  VkFence submit_fence = (i == submitCount - 1) ? fence : NULL;
+  VkFence submit_fence = (i == submitCount - 1) ? fence : 0;

   if (pSubmits[i].commandBufferCount == 0) {
  /* If we don't have any command buffers, we need to submit a dummy
@@ -197,7 +197,7 @@ VkResult anv_QueueSubmit(

  /* Fence for this execbuf.  NULL for all but the last one */
  VkFence execbuf_fence =
-(j == pSubmits[i].commandBufferCount - 1) ? submit_fence : NULL;
+(j == pSubmits[i].commandBufferCount - 1) ? submit_fence : 0;

  const VkSemaphore *in_semaphores = NULL, *out_semaphores = NULL;
  uint32_t num_in_semaphores = 0, num_out_semaphores = 0;
--
2.13.5




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Re: [Mesa-dev] [PATCH] anv: fix build errors on android

[Samuel Iglesias Gonsálvez]

Reviewed-by: Samuel Iglesias Gonsálvez 

On Thu, 2017-08-31 at 08:52 +0300, Tapani Pälli wrote:
> error: incompatible pointer to integer conversion initializing
> 'VkFence'
>    (aka 'unsigned long long') with an expression of type 'void *' [-
> Werror,-Wint-conversion]
> 
> Signed-off-by: Tapani Pälli 
> ---
>  src/intel/vulkan/anv_queue.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_queue.c
> b/src/intel/vulkan/anv_queue.c
> index 429bac9739..d675e8667e 100644
> --- a/src/intel/vulkan/anv_queue.c
> +++ b/src/intel/vulkan/anv_queue.c
> @@ -169,7 +169,7 @@ VkResult anv_QueueSubmit(
>  
> for (uint32_t i = 0; i < submitCount; i++) {
>    /* Fence for this submit.  NULL for all but the last one */
> -  VkFence submit_fence = (i == submitCount - 1) ? fence : NULL;
> +  VkFence submit_fence = (i == submitCount - 1) ? fence : 0;
>  
>    if (pSubmits[i].commandBufferCount == 0) {
>   /* If we don't have any command buffers, we need to submit
> a dummy
> @@ -197,7 +197,7 @@ VkResult anv_QueueSubmit(
>  
>   /* Fence for this execbuf.  NULL for all but the last one
> */
>   VkFence execbuf_fence =
> -(j == pSubmits[i].commandBufferCount - 1) ? submit_fence
> : NULL;
> +(j == pSubmits[i].commandBufferCount - 1) ? submit_fence
> : 0;
>  
>   const VkSemaphore *in_semaphores = NULL, *out_semaphores =
> NULL;
>   uint32_t num_in_semaphores = 0, num_out_semaphores = 0;

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