[Mesa-dev] [PATCH 11/11] spirv: Rework asserts in var_decoration_cb

2017-12-16 Thread Jason Ekstrand 
Now that higher levels are enforcing decoration sanity, we don't need
the vtn_asserts here.  This function *should* be safe but we still want
a few well-placed regular asserts in case something goes awry.
---
 src/compiler/spirv/vtn_variables.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 2a413a4..d69b056 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -1465,11 +1465,11 @@ var_decoration_cb(struct vtn_builder *b, struct 
vtn_value *val, int member,
}
 
if (val->value_type == vtn_value_type_pointer) {
-  vtn_assert(val->pointer->var == void_var);
-  vtn_assert(val->pointer->chain == NULL);
-  vtn_assert(member == -1);
+  assert(val->pointer->var == void_var);
+  assert(val->pointer->chain == NULL);
+  assert(member == -1);
} else {
-  vtn_assert(val->value_type == vtn_value_type_type);
+  assert(val->value_type == vtn_value_type_type);
}
 
/* Location is odd.  If applied to a split structure, we have to walk the
@@ -1501,7 +1501,7 @@ var_decoration_cb(struct vtn_builder *b, struct vtn_value 
*val, int member,
  vtn_var->var->data.location = location;
   } else {
  /* This handles the structure member case */
- vtn_assert(vtn_var->members);
+ assert(vtn_var->members);
  unsigned length =
 glsl_get_length(glsl_without_array(vtn_var->type->type));
  for (unsigned i = 0; i < length; i++) {
@@ -1514,11 +1514,12 @@ var_decoration_cb(struct vtn_builder *b, struct 
vtn_value *val, int member,
   return;
} else {
   if (vtn_var->var) {
- vtn_assert(member <= 0);
+ assert(member == -1);
  apply_var_decoration(b, vtn_var->var, dec);
   } else if (vtn_var->members) {
  if (member >= 0) {
-vtn_assert(vtn_var->members);
+/* Member decorations must come from a type */
+assert(val->value_type == vtn_value_type_type);
 apply_var_decoration(b, vtn_var->members[member], dec);
  } else {
 unsigned length =
-- 
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[Mesa-dev] [PATCH 10/11] spirv: Rework error checking for decorations

2017-12-16 Thread Jason Ekstrand 
This reworks the error checking on our generic handling of decorations.
The objective is to validate all of the SPIR-V assumptions we make
up-front and convert redundant checks to compiled-out asserts.  The most
important part of this is to ensure that member decorations only occur
on OpTypeStruct and that the member is never out-of-bounds.  This way
later code can assume that the member is sane and not have to worry
about OOB array access due to a misplaced OpMemberDecorate.
---
 src/compiler/spirv/spirv_to_nir.c | 41 ++-
 1 file changed, 32 insertions(+), 9 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index ffea442..dcff56f 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -376,15 +376,27 @@ _foreach_decoration_helper(struct vtn_builder *b,
   if (dec->scope == VTN_DEC_DECORATION) {
  member = parent_member;
   } else if (dec->scope >= VTN_DEC_STRUCT_MEMBER0) {
- vtn_assert(parent_member == -1);
+ vtn_fail_if(value->value_type != vtn_value_type_type ||
+ value->type->base_type != vtn_base_type_struct,
+ "OpMemberDecorate and OpGroupMemberDecorate are only "
+ "allowed on OpTypeStruct");
+ /* This means we haven't recursed yet */
+ assert(value == base_value);
+
  member = dec->scope - VTN_DEC_STRUCT_MEMBER0;
+
+ vtn_fail_if(member >= base_value->type->length,
+ "OpMemberDecorate specifies member %d but the "
+ "OpTypeStruct has only %u members",
+ member, base_value->type->length);
   } else {
  /* Not a decoration */
+ assert(dec->scope == VTN_DEC_EXECUTION_MODE);
  continue;
   }
 
   if (dec->group) {
- vtn_assert(dec->group->value_type == vtn_value_type_decoration_group);
+ assert(dec->group->value_type == vtn_value_type_decoration_group);
  _foreach_decoration_helper(b, base_value, member, dec->group,
 cb, data);
   } else {
@@ -414,7 +426,7 @@ vtn_foreach_execution_mode(struct vtn_builder *b, struct 
vtn_value *value,
   if (dec->scope != VTN_DEC_EXECUTION_MODE)
  continue;
 
-  vtn_assert(dec->group == NULL);
+  assert(dec->group == NULL);
   cb(b, value, dec, data);
}
 }
@@ -435,7 +447,7 @@ vtn_handle_decoration(struct vtn_builder *b, SpvOp opcode,
case SpvOpDecorate:
case SpvOpMemberDecorate:
case SpvOpExecutionMode: {
-  struct vtn_value *val = >values[target];
+  struct vtn_value *val = vtn_untyped_value(b, target);
 
   struct vtn_decoration *dec = rzalloc(b, struct vtn_decoration);
   switch (opcode) {
@@ -444,12 +456,14 @@ vtn_handle_decoration(struct vtn_builder *b, SpvOp opcode,
  break;
   case SpvOpMemberDecorate:
  dec->scope = VTN_DEC_STRUCT_MEMBER0 + *(w++);
+ vtn_fail_if(dec->scope < VTN_DEC_STRUCT_MEMBER0, /* overflow */
+ "Member argument of OpMemberDecorate too large");
  break;
   case SpvOpExecutionMode:
  dec->scope = VTN_DEC_EXECUTION_MODE;
  break;
   default:
- vtn_fail("Invalid decoration opcode");
+ unreachable("Invalid decoration opcode");
   }
   dec->decoration = *(w++);
   dec->literals = w;
@@ -474,6 +488,8 @@ vtn_handle_decoration(struct vtn_builder *b, SpvOp opcode,
 dec->scope = VTN_DEC_DECORATION;
  } else {
 dec->scope = VTN_DEC_STRUCT_MEMBER0 + *(++w);
+vtn_fail_if(dec->scope < 0, /* Check for overflow */
+"Member argument of OpGroupMemberDecorate too large");
  }
 
  /* Link into the list */
@@ -484,7 +500,7 @@ vtn_handle_decoration(struct vtn_builder *b, SpvOp opcode,
}
 
default:
-  vtn_fail("Unhandled opcode");
+  unreachable("Unhandled opcode");
}
 }
 
@@ -561,7 +577,7 @@ struct_member_decoration_cb(struct vtn_builder *b,
if (member < 0)
   return;
 
-   vtn_assert(member < ctx->num_fields);
+   assert(member < ctx->num_fields);
 
switch (dec->decoration) {
case SpvDecorationNonWritable:
@@ -664,7 +680,10 @@ struct_member_matrix_stride_cb(struct vtn_builder *b,
 {
if (dec->decoration != SpvDecorationMatrixStride)
   return;
-   vtn_assert(member >= 0);
+
+   vtn_fail_if(member < 0,
+   "The MatrixStride decoration is only allowed on members "
+   "of OpTypeStruct");
 
struct member_decoration_ctx *ctx = void_ctx;
 
@@ -686,8 +705,12 @@ type_decoration_cb(struct vtn_builder *b,
 {
struct vtn_type *type = val->type;
 
-   if (member != -1)
+   if (member != -1) {
+  /* This should have been handled by OpTypeStruct */
+  assert(val->type->base_type == vtn_base_type_struct);
+  assert(member >= 0 && member <

[Mesa-dev] [PATCH 08/11] spirv: Switch on vtn_base_type in OpComposite(Extract|Insert)

2017-12-16 Thread Jason Ekstrand 
This is a bit simpler since we have fewer enum values in the case.  It's
also a bit more efficient because we're making fewer glsl_get_* calls.
While we're at it, add better type validation.
---
 src/compiler/spirv/spirv_to_nir.c | 69 ++-
 1 file changed, 32 insertions(+), 37 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 4a30a23..83c75c7 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1486,44 +1486,39 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
 
  int elem = -1;
  int col = 0;
- const struct glsl_type *type = comp->type->type;
+ const struct vtn_type *type = comp->type;
  for (unsigned i = deref_start; i < count; i++) {
-switch (glsl_get_base_type(type)) {
-case GLSL_TYPE_UINT:
-case GLSL_TYPE_INT:
-case GLSL_TYPE_UINT16:
-case GLSL_TYPE_INT16:
-case GLSL_TYPE_UINT64:
-case GLSL_TYPE_INT64:
-case GLSL_TYPE_FLOAT:
-case GLSL_TYPE_FLOAT16:
-case GLSL_TYPE_DOUBLE:
-case GLSL_TYPE_BOOL:
-   /* If we hit this granularity, we're picking off an element */
-   if (glsl_type_is_matrix(type)) {
-  vtn_assert(col == 0 && elem == -1);
-  col = w[i];
-  elem = 0;
-  type = glsl_get_column_type(type);
-   } else {
-  vtn_assert(elem <= 0 && glsl_type_is_vector(type));
-  elem = w[i];
-  type = glsl_scalar_type(glsl_get_base_type(type));
-   }
-   continue;
-
-case GLSL_TYPE_ARRAY:
+vtn_fail_if(w[i] > type->length,
+"%uth index of %s is %u but the type has only "
+"%u elements", i - deref_start,
+spirv_op_to_string(opcode), w[i], type->length);
+
+switch (type->base_type) {
+case vtn_base_type_vector:
+   elem = w[i];
+   type = type->array_element;
+   break;
+
+case vtn_base_type_matrix:
+   assert(col == 0 && elem == -1);
+   col = w[i];
+   elem = 0;
+   type = type->array_element;
+   break;
+
+case vtn_base_type_array:
c = &(*c)->elements[w[i]];
-   type = glsl_get_array_element(type);
-   continue;
+   type = type->array_element;
+   break;
 
-case GLSL_TYPE_STRUCT:
+case vtn_base_type_struct:
c = &(*c)->elements[w[i]];
-   type = glsl_get_struct_field(type, w[i]);
-   continue;
+   type = type->members[w[i]];
+   break;
 
 default:
-   vtn_fail("Invalid constant type");
+   vtn_fail("%s must only index into composite types",
+spirv_op_to_string(opcode));
 }
  }
 
@@ -1531,8 +1526,8 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
 if (elem == -1) {
val->constant = *c;
 } else {
-   unsigned num_components = glsl_get_vector_elements(type);
-   unsigned bit_size = glsl_get_bit_size(type);
+   unsigned num_components = type->length;
+   unsigned bit_size = glsl_get_bit_size(type->type);
for (unsigned i = 0; i < num_components; i++)
   switch(bit_size) {
   case 64:
@@ -1551,12 +1546,12 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
  } else {
 struct vtn_value *insert =
vtn_value(b, w[4], vtn_value_type_constant);
-vtn_assert(insert->type->type == type);
+vtn_assert(insert->type == type);
 if (elem == -1) {
*c = insert->constant;
 } else {
-   unsigned num_components = glsl_get_vector_elements(type);
-   unsigned bit_size = glsl_get_bit_size(type);
+   unsigned num_components = type->length;
+   unsigned bit_size = glsl_get_bit_size(type->type);
for (unsigned i = 0; i < num_components; i++)
   switch (bit_size) {
   case 64:
-- 
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[Mesa-dev] [PATCH 07/11] spirv: Refactor Op[Spec]ConstantComposite and add better validation

2017-12-16 Thread Jason Ekstrand 
Now that vtn_base_type is a real and full base type, we can switch on
that instead of the GLSL base type which is a lot fewer cases in our
switch.
---
 src/compiler/spirv/spirv_to_nir.c | 68 ++-
 1 file changed, 32 insertions(+), 36 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index d65c0d0..4a30a23 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1342,60 +1342,56 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
   }
   break;
}
+
case SpvOpSpecConstantComposite:
case SpvOpConstantComposite: {
   unsigned elem_count = count - 3;
+  vtn_fail_if(elem_count != val->type->length,
+  "%s has %u constituents, expected %u",
+  spirv_op_to_string(opcode), elem_count, val->type->length);
+
   nir_constant **elems = ralloc_array(b, nir_constant *, elem_count);
   for (unsigned i = 0; i < elem_count; i++)
  elems[i] = vtn_value(b, w[i + 3], vtn_value_type_constant)->constant;
 
-  switch (glsl_get_base_type(val->type->type)) {
-  case GLSL_TYPE_UINT:
-  case GLSL_TYPE_INT:
-  case GLSL_TYPE_UINT16:
-  case GLSL_TYPE_INT16:
-  case GLSL_TYPE_UINT64:
-  case GLSL_TYPE_INT64:
-  case GLSL_TYPE_FLOAT:
-  case GLSL_TYPE_FLOAT16:
-  case GLSL_TYPE_BOOL:
-  case GLSL_TYPE_DOUBLE: {
+  switch (val->type->base_type) {
+  case vtn_base_type_vector: {
+ assert(glsl_type_is_vector(val->type->type));
  int bit_size = glsl_get_bit_size(val->type->type);
- if (glsl_type_is_matrix(val->type->type)) {
-vtn_assert(glsl_get_matrix_columns(val->type->type) == elem_count);
-for (unsigned i = 0; i < elem_count; i++)
-   val->constant->values[i] = elems[i]->values[0];
- } else {
-vtn_assert(glsl_type_is_vector(val->type->type));
-vtn_assert(glsl_get_vector_elements(val->type->type) == 
elem_count);
-for (unsigned i = 0; i < elem_count; i++) {
-   switch (bit_size) {
-   case 64:
-  val->constant->values[0].u64[i] = elems[i]->values[0].u64[0];
-  break;
-   case 32:
-  val->constant->values[0].u32[i] = elems[i]->values[0].u32[0];
-  break;
-   case 16:
-  val->constant->values[0].u16[i] = elems[i]->values[0].u16[0];
-  break;
-   default:
-  vtn_fail("Invalid SpvOpConstantComposite bit size");
-   }
+ for (unsigned i = 0; i < elem_count; i++) {
+switch (bit_size) {
+case 64:
+   val->constant->values[0].u64[i] = elems[i]->values[0].u64[0];
+   break;
+case 32:
+   val->constant->values[0].u32[i] = elems[i]->values[0].u32[0];
+   break;
+case 16:
+   val->constant->values[0].u16[i] = elems[i]->values[0].u16[0];
+   break;
+default:
+   vtn_fail("Invalid SpvOpConstantComposite bit size");
 }
  }
- ralloc_free(elems);
  break;
   }
-  case GLSL_TYPE_STRUCT:
-  case GLSL_TYPE_ARRAY:
+
+  case vtn_base_type_matrix:
+ assert(glsl_type_is_matrix(val->type->type));
+ for (unsigned i = 0; i < elem_count; i++)
+val->constant->values[i] = elems[i]->values[0];
+ break;
+
+  case vtn_base_type_struct:
+  case vtn_base_type_array:
  ralloc_steal(val->constant, elems);
  val->constant->num_elements = elem_count;
  val->constant->elements = elems;
  break;
 
   default:
- vtn_fail("Unsupported type for constants");
+ vtn_fail("Result type of %s must be a composite type",
+  spirv_op_to_string(opcode));
   }
   break;
}
-- 
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[Mesa-dev] [PATCH 09/11] spirv: Add better type validation to OpTypeImage

2017-12-16 Thread Jason Ekstrand 
---
 src/compiler/spirv/spirv_to_nir.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 83c75c7..ffea442 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1075,10 +1075,12 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
case SpvOpTypeImage: {
   val->type->base_type = vtn_base_type_image;
 
-  const struct glsl_type *sampled_type =
- vtn_value(b, w[2], vtn_value_type_type)->type->type;
+  const struct vtn_type *sampled_type =
+ vtn_value(b, w[2], vtn_value_type_type)->type;
 
-  vtn_assert(glsl_type_is_vector_or_scalar(sampled_type));
+  vtn_fail_if(sampled_type->base_type != vtn_base_type_scalar ||
+  glsl_get_bit_size(sampled_type->type) != 32,
+  "Sampled type of OpTypeImage must be a 32-bit scalar");
 
   enum glsl_sampler_dim dim;
   switch ((SpvDim)w[3]) {
@@ -1090,7 +1092,7 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
   case SpvDimBuffer:   dim = GLSL_SAMPLER_DIM_BUF;   break;
   case SpvDimSubpassData: dim = GLSL_SAMPLER_DIM_SUBPASS; break;
   default:
- vtn_fail("Invalid SPIR-V Sampler dimension");
+ vtn_fail("Invalid SPIR-V image dimensionality");
   }
 
   bool is_shadow = w[4];
@@ -1115,15 +1117,16 @@ vtn_handle_type(struct vtn_builder *b, SpvOp opcode,
 
   val->type->image_format = translate_image_format(b, format);
 
+  enum glsl_base_type sampled_base_type =
+ glsl_get_base_type(sampled_type->type);
   if (sampled == 1) {
  val->type->sampled = true;
  val->type->type = glsl_sampler_type(dim, is_shadow, is_array,
- glsl_get_base_type(sampled_type));
+ sampled_base_type);
   } else if (sampled == 2) {
  vtn_assert(!is_shadow);
  val->type->sampled = false;
- val->type->type = glsl_image_type(dim, is_array,
-   glsl_get_base_type(sampled_type));
+ val->type->type = glsl_image_type(dim, is_array, sampled_base_type);
   } else {
  vtn_fail("We need to know if the image will be sampled");
   }
-- 
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[Mesa-dev] [PATCH 01/11] spirv: Add better error messages in vtn_value helpers

2017-12-16 Thread Jason Ekstrand 
---
 src/compiler/spirv/vtn_private.h | 26 +++---
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/src/compiler/spirv/vtn_private.h b/src/compiler/spirv/vtn_private.h
index 7cb69d7..f7d8f49 100644
--- a/src/compiler/spirv/vtn_private.h
+++ b/src/compiler/spirv/vtn_private.h
@@ -585,14 +585,24 @@ vtn_pointer_from_ssa(struct vtn_builder *b, nir_ssa_def 
*ssa,
  struct vtn_type *ptr_type);
 
 static inline struct vtn_value *
+vtn_untyped_value(struct vtn_builder *b, uint32_t value_id)
+{
+   vtn_fail_if(value_id >= b->value_id_bound,
+   "SPIR-V id %u is out-of-bounds", value_id);
+   return >values[value_id];
+}
+
+static inline struct vtn_value *
 vtn_push_value(struct vtn_builder *b, uint32_t value_id,
enum vtn_value_type value_type)
 {
-   assert(value_id < b->value_id_bound);
-   assert(b->values[value_id].value_type == vtn_value_type_invalid);
+   struct vtn_value *val = vtn_untyped_value(b, value_id);
 
-   b->values[value_id].value_type = value_type;
+   vtn_fail_if(val->value_type != vtn_value_type_invalid,
+   "SPIR-V id %u has already been written by another instruction",
+   value_id);
 
+   val->value_type = value_type;
return >values[value_id];
 }
 
@@ -612,18 +622,12 @@ vtn_push_ssa(struct vtn_builder *b, uint32_t value_id,
 }
 
 static inline struct vtn_value *
-vtn_untyped_value(struct vtn_builder *b, uint32_t value_id)
-{
-   assert(value_id < b->value_id_bound);
-   return >values[value_id];
-}
-
-static inline struct vtn_value *
 vtn_value(struct vtn_builder *b, uint32_t value_id,
   enum vtn_value_type value_type)
 {
struct vtn_value *val = vtn_untyped_value(b, value_id);
-   assert(val->value_type == value_type);
+   vtn_fail_if(val->value_type != value_type,
+   "SPIR-V id %u is the wrong kind of value", value_id);
return val;
 }
 
-- 
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[Mesa-dev] [PATCH 04/11] spirv: Unify boolean constants and add better validation

2017-12-16 Thread Jason Ekstrand 
---
 src/compiler/spirv/spirv_to_nir.c | 21 +++--
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 0493dd3..9a67690 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1281,19 +1281,20 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
val->constant = rzalloc(b, nir_constant);
switch (opcode) {
case SpvOpConstantTrue:
-  vtn_assert(val->type->type == glsl_bool_type());
-  val->constant->values[0].u32[0] = NIR_TRUE;
-  break;
case SpvOpConstantFalse:
-  vtn_assert(val->type->type == glsl_bool_type());
-  val->constant->values[0].u32[0] = NIR_FALSE;
-  break;
-
case SpvOpSpecConstantTrue:
case SpvOpSpecConstantFalse: {
-  vtn_assert(val->type->type == glsl_bool_type());
-  uint32_t int_val =
- get_specialization(b, val, (opcode == SpvOpSpecConstantTrue));
+  vtn_fail_if(val->type->type != glsl_bool_type(),
+  "Result type of %s must be OpTypeBool",
+  spirv_op_to_string(opcode));
+
+  uint32_t int_val = (opcode == SpvOpConstantTrue ||
+  opcode == SpvOpSpecConstantTrue);
+
+  if (opcode == SpvOpSpecConstantTrue ||
+  opcode == SpvOpSpecConstantFalse)
+ int_val = get_specialization(b, val, int_val);
+
   val->constant->values[0].u32[0] = int_val ? NIR_TRUE : NIR_FALSE;
   break;
}
-- 
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[Mesa-dev] [PATCH 06/11] spirv: Add better validation to Op[Spec]Constant

2017-12-16 Thread Jason Ekstrand 
---
 src/compiler/spirv/spirv_to_nir.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 208ec95..d65c0d0 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1300,6 +1300,9 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
}
 
case SpvOpConstant: {
+  vtn_fail_if(val->type->base_type != vtn_base_type_scalar,
+  "Result type of %s must be a scalar",
+  spirv_op_to_string(opcode));
   vtn_assert(glsl_type_is_scalar(val->type->type));
   int bit_size = glsl_get_bit_size(val->type->type);
   switch (bit_size) {
@@ -1317,8 +1320,11 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
   }
   break;
}
+
case SpvOpSpecConstant: {
-  vtn_assert(glsl_type_is_scalar(val->type->type));
+  vtn_fail_if(val->type->base_type != vtn_base_type_scalar,
+  "Result type of %s must be a scalar",
+  spirv_op_to_string(opcode));
   int bit_size = glsl_get_bit_size(val->type->type);
   switch (bit_size) {
   case 64:
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 05/11] spirv: Remove a pointless assignment in SpvOpSpecConstant

2017-12-16 Thread Jason Ekstrand 
We re-assign later inside the bit_size switch
---
 src/compiler/spirv/spirv_to_nir.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 9a67690..208ec95 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -1319,7 +1319,6 @@ vtn_handle_constant(struct vtn_builder *b, SpvOp opcode,
}
case SpvOpSpecConstant: {
   vtn_assert(glsl_type_is_scalar(val->type->type));
-  val->constant->values[0].u32[0] = get_specialization(b, val, w[3]);
   int bit_size = glsl_get_bit_size(val->type->type);
   switch (bit_size) {
   case 64:
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 02/11] spirv: Make 'info' a local array spirv_info_c.py

2017-12-16 Thread Jason Ekstrand 
---
 src/compiler/spirv/spirv_info_c.py | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/compiler/spirv/spirv_info_c.py 
b/src/compiler/spirv/spirv_info_c.py
index d898bf0..4a6a815 100644
--- a/src/compiler/spirv/spirv_info_c.py
+++ b/src/compiler/spirv/spirv_info_c.py
@@ -78,8 +78,10 @@ if __name__ == "__main__":
 
 spirv_info = json.JSONDecoder().decode(open(pargs.json, "r").read())
 
-capabilities = collect_data(spirv_info, "Capability")
-decorations = collect_data(spirv_info, "Decoration")
+info = [
+collect_data(spirv_info, "Capability"),
+collect_data(spirv_info, "Decoration"),
+]
 
 with open(pargs.out, 'w') as f:
-f.write(TEMPLATE.render(info=[capabilities, decorations]))
+f.write(TEMPLATE.render(info=info))
-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 00/11] SPIR-V More error checking/validation improvements

2017-12-16 Thread Jason Ekstrand 
This series is another 11 patches in the direction of improving SPIR-V
error messages and validation.  The purpose here isn't really to validate
the SPIR-V (I'm sure there will be many things we won't error on) but to
make it such that the assumptions we do make about the incoming SPIR-V and
require for correctness are well-documented and based on actual SPIR-V
constructs instead of obscure asserts deep inside spirv_to_nir.

A good example of this is the penultimate patch of this series which
reworks our error checking for decorations.  The biggest potential failure
point for decorations is struct member decorations which are either not on
an OpTypeStruct or have a member literal that is out-of-bounds.  By
carefully checking for all this up-front, we can allow later code to just
assume everything is sane.  It's also theoretically possible to construct
(invalid) SPIR-V which has nested member decorations.  This isn't allowed
by the spec but it's nicer to throw an error than to just get confused or,
even worse, crash.  The final patch in the series follows this up by
replacing a bunch of vtn_asserts in various bits of decoration handling
code with regular debug-only asserts that should now be guaranteed to never
trigger.

Jason Ekstrand (11):
  spirv: Add better error messages in vtn_value helpers
  spirv: Make 'info' a local array spirv_info_c.py
  spirv/info: Add spirv_op_to_string
  spirv: Unify boolean constants and add better validation
  spirv: Remove a pointless assignment in SpvOpSpecConstant
  spirv: Add better validation to Op[Spec]Constant
  spirv: Refactor Op[Spec]ConstantComposite and add better validation
  spirv: Switch on vtn_base_type in OpComposite(Extract|Insert)
  spirv: Add better type validation to OpTypeImage
  spirv: Rework error checking for decorations
  spirv: Rework asserts in var_decoration_cb

 src/compiler/spirv/spirv_info.h|   1 +
 src/compiler/spirv/spirv_info_c.py |  18 ++-
 src/compiler/spirv/spirv_to_nir.c  | 225 -
 src/compiler/spirv/vtn_private.h   |  26 +++--
 src/compiler/spirv/vtn_variables.c |  15 +--
 5 files changed, 163 insertions(+), 122 deletions(-)

-- 
2.5.0.400.gff86faf

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[Mesa-dev] [PATCH 03/11] spirv/info: Add spirv_op_to_string

2017-12-16 Thread Jason Ekstrand 
---
 src/compiler/spirv/spirv_info.h|  1 +
 src/compiler/spirv/spirv_info_c.py | 10 ++
 2 files changed, 11 insertions(+)

diff --git a/src/compiler/spirv/spirv_info.h b/src/compiler/spirv/spirv_info.h
index 81d43ec..121ffd2 100644
--- a/src/compiler/spirv/spirv_info.h
+++ b/src/compiler/spirv/spirv_info.h
@@ -28,5 +28,6 @@
 
 const char *spirv_capability_to_string(SpvCapability cap);
 const char *spirv_decoration_to_string(SpvDecoration dec);
+const char *spirv_op_to_string(SpvOp op);
 
 #endif /* SPIRV_INFO_H */
diff --git a/src/compiler/spirv/spirv_info_c.py 
b/src/compiler/spirv/spirv_info_c.py
index 4a6a815..ff7942b 100644
--- a/src/compiler/spirv/spirv_info_c.py
+++ b/src/compiler/spirv/spirv_info_c.py
@@ -45,6 +45,15 @@ def collect_data(spirv, kind):
 
 return (kind, values)
 
+def collect_opcodes(spirv):
+values = []
+for x in spirv["instructions"]:
+name = x["opname"]
+assert name.startswith("Op")
+values.append(name[2:])
+
+return ("Op", values)
+
 def parse_args():
 p = argparse.ArgumentParser()
 p.add_argument("json")
@@ -81,6 +90,7 @@ if __name__ == "__main__":
 info = [
 collect_data(spirv_info, "Capability"),
 collect_data(spirv_info, "Decoration"),
+collect_opcodes(spirv_info),
 ]
 
 with open(pargs.out, 'w') as f:
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH] st/st_glsl_to_nir: call nir_lower_64bit_pack

2017-12-16 Thread Timothy Arceri 

On 17/12/17 09:07, Erik Faye-Lund wrote:

On Thu, Dec 14, 2017 at 6:02 AM, Timothy Arceri  wrote:

Fixes 56 crashes in radeonsi.


56 crashes with what? Piglit?



Yes fixes 56 piglit crashes
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[Mesa-dev] [PATCH 6/6] radv: Add external fence support.

2017-12-16 Thread Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c  | 20 
 src/amd/vulkan/radv_extensions.py |  2 ++
 2 files changed, 22 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 94562fda875..a4ec912ff2c 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3793,3 +3793,23 @@ VkResult radv_GetFenceFdKHR(VkDevice _device,
return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
return VK_SUCCESS;
 }
+
+void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
+   VkPhysicalDevicephysicalDevice,
+   const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
+   VkExternalFencePropertiesKHR*   pExternalFenceProperties)
+{
+   RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
+
+   if (pdevice->rad_info.has_syncobj_wait &&
+   pExternalFenceInfo->handleType == 
VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
+   pExternalFenceProperties->exportFromImportedHandleTypes = 
VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
+   pExternalFenceProperties->compatibleHandleTypes = 
VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
+   pExternalFenceProperties->externalFenceFeatures = 
VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
+   VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
+   } else {
+   pExternalFenceProperties->exportFromImportedHandleTypes = 0;
+   pExternalFenceProperties->compatibleHandleTypes = 0;
+   pExternalFenceProperties->externalFenceFeatures = 0;
+   }
+}
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 3188735ea78..9af941fab35 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -53,6 +53,8 @@ EXTENSIONS = [
 Extension('VK_KHR_bind_memory2',  1, True),
 Extension('VK_KHR_dedicated_allocation',  1, True),
 Extension('VK_KHR_descriptor_update_template',1, True),
+Extension('VK_KHR_external_fence',1, 
'device->rad_info.has_syncobj_wait'),
+Extension('VK_KHR_external_fence_capabilities',   1, True),
 Extension('VK_KHR_external_fence_fd', 1, 
'device->rad_info.has_syncobj_wait'),
 Extension('VK_KHR_external_memory',   1, True),
 Extension('VK_KHR_external_memory_capabilities',  1, True),
-- 
2.15.1

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[Mesa-dev] [PATCH 1/6] configure/meson: Bump libdrm_amdgpu version requirement.

2017-12-16 Thread Bas Nieuwenhuizen 
For the radv dependencies on syncobj signal/reset.
---
 configure.ac | 2 +-
 meson.build  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/configure.ac b/configure.ac
index a4564d23f4c..138459c6f79 100644
--- a/configure.ac
+++ b/configure.ac
@@ -74,7 +74,7 @@ AC_SUBST([OPENCL_VERSION])
 # in the first entry.
 LIBDRM_REQUIRED=2.4.75
 LIBDRM_RADEON_REQUIRED=2.4.71
-LIBDRM_AMDGPU_REQUIRED=2.4.88
+LIBDRM_AMDGPU_REQUIRED=2.4.89
 LIBDRM_INTEL_REQUIRED=2.4.75
 LIBDRM_NVVIEUX_REQUIRED=2.4.66
 LIBDRM_NOUVEAU_REQUIRED=2.4.66
diff --git a/meson.build b/meson.build
index 6e5ae4d24e9..6ce6d55e17d 100644
--- a/meson.build
+++ b/meson.build
@@ -947,7 +947,7 @@ dep_libdrm_nouveau = []
 dep_libdrm_etnaviv = []
 dep_libdrm_freedreno = []
 if with_amd_vk or with_gallium_radeonsi
-  dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.88')
+  dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.89')
 endif
 if (with_gallium_radeonsi or with_dri_r100 or with_dri_r200 or
 with_gallium_r300 or with_gallium_r600)
-- 
2.15.1

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[Mesa-dev] [PATCH 4/6] radv: Implement fences based on syncobjs.

2017-12-16 Thread Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c  | 113 --
 src/amd/vulkan/radv_private.h |   6 ++-
 src/amd/vulkan/radv_wsi.c |   5 ++
 3 files changed, 109 insertions(+), 15 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 7c0971d190d..fc9fb59f991 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1850,12 +1850,14 @@ fail:
 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
  int num_sems,
  const VkSemaphore *sems,
+ VkFence _fence,
  bool reset_temp)
 {
int syncobj_idx = 0, sem_idx = 0;
 
-   if (num_sems == 0)
+   if (num_sems == 0 && _fence == VK_NULL_HANDLE)
return VK_SUCCESS;
+
for (uint32_t i = 0; i < num_sems; i++) {
RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
 
@@ -1865,6 +1867,12 @@ static VkResult radv_alloc_sem_counts(struct 
radv_winsys_sem_counts *counts,
counts->sem_count++;
}
 
+   if (_fence != VK_NULL_HANDLE) {
+   RADV_FROM_HANDLE(radv_fence, fence, _fence);
+   if (fence->temp_syncobj || fence->syncobj)
+   counts->syncobj_count++;
+   }
+
if (counts->syncobj_count) {
counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * 
counts->syncobj_count);
if (!counts->syncobj)
@@ -1893,6 +1901,14 @@ static VkResult radv_alloc_sem_counts(struct 
radv_winsys_sem_counts *counts,
}
}
 
+   if (_fence != VK_NULL_HANDLE) {
+   RADV_FROM_HANDLE(radv_fence, fence, _fence);
+   if (fence->temp_syncobj)
+   counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
+   else if (fence->syncobj)
+   counts->syncobj[syncobj_idx++] = fence->syncobj;
+   }
+
return VK_SUCCESS;
 }
 
@@ -1923,15 +1939,16 @@ VkResult radv_alloc_sem_info(struct 
radv_winsys_sem_info *sem_info,
 int num_wait_sems,
 const VkSemaphore *wait_sems,
 int num_signal_sems,
-const VkSemaphore *signal_sems)
+const VkSemaphore *signal_sems,
+VkFence fence)
 {
VkResult ret;
memset(sem_info, 0, sizeof(*sem_info));
 
-   ret = radv_alloc_sem_counts(_info->wait, num_wait_sems, wait_sems, 
true);
+   ret = radv_alloc_sem_counts(_info->wait, num_wait_sems, wait_sems, 
VK_NULL_HANDLE, true);
if (ret)
return ret;
-   ret = radv_alloc_sem_counts(_info->signal, num_signal_sems, 
signal_sems, false);
+   ret = radv_alloc_sem_counts(_info->signal, num_signal_sems, 
signal_sems, fence, false);
if (ret)
radv_free_sem_info(sem_info);
 
@@ -1997,7 +2014,8 @@ VkResult radv_QueueSubmit(
 pSubmits[i].waitSemaphoreCount,
 pSubmits[i].pWaitSemaphores,
 pSubmits[i].signalSemaphoreCount,
-pSubmits[i].pSignalSemaphores);
+pSubmits[i].pSignalSemaphores,
+_fence);
if (result != VK_SUCCESS)
return result;
 
@@ -2068,11 +2086,18 @@ VkResult radv_QueueSubmit(
 
if (fence) {
if (!fence_emitted) {
-   struct radv_winsys_sem_info sem_info = {0};
+   struct radv_winsys_sem_info sem_info;
+
+   result = radv_alloc_sem_info(_info, 0, NULL, 0, 
NULL,
+_fence);
+   if (result != VK_SUCCESS)
+   return result;
+
ret = queue->device->ws->cs_submit(ctx, 
queue->queue_idx,
   
>device->empty_cs[queue->queue_family_index],
   1, NULL, NULL, 
_info,
   false, base_fence);
+   radv_free_sem_info(_info);
}
fence->submitted = true;
}
@@ -2573,7 +2598,8 @@ radv_sparse_image_opaque_bind_memory(struct radv_device 
*device,
 pBindInfo[i].waitSemaphoreCount,
 pBindInfo[i].pWaitSemaphores,
 pBindInfo[i].signalSemaphoreCount,
-pBindInfo[i].pSignalSemaphores);
+

[Mesa-dev] [PATCH 2/6] radv: Add syncobj signal/reset/wait to winsys.

2017-12-16 Thread Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_radeon_winsys.h   |  4 +++
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 40 +++
 2 files changed, 44 insertions(+)

diff --git a/src/amd/vulkan/radv_radeon_winsys.h 
b/src/amd/vulkan/radv_radeon_winsys.h
index 2b815d9c5a9..e851c3edf86 100644
--- a/src/amd/vulkan/radv_radeon_winsys.h
+++ b/src/amd/vulkan/radv_radeon_winsys.h
@@ -274,6 +274,10 @@ struct radeon_winsys {
int (*create_syncobj)(struct radeon_winsys *ws, uint32_t *handle);
void (*destroy_syncobj)(struct radeon_winsys *ws, uint32_t handle);
 
+   void (*reset_syncobj)(struct radeon_winsys *ws, uint32_t handle);
+   void (*signal_syncobj)(struct radeon_winsys *ws, uint32_t handle);
+   bool (*wait_syncobj)(struct radeon_winsys *ws, uint32_t handle, 
uint64_t timeout);
+
int (*export_syncobj)(struct radeon_winsys *ws, uint32_t syncobj, int 
*fd);
int (*import_syncobj)(struct radeon_winsys *ws, int fd, uint32_t 
*syncobj);
 
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index e5ea312aeeb..e4d444b8524 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -1281,6 +1281,43 @@ static void radv_amdgpu_destroy_syncobj(struct 
radeon_winsys *_ws,
amdgpu_cs_destroy_syncobj(ws->dev, handle);
 }
 
+static void radv_amdgpu_reset_syncobj(struct radeon_winsys *_ws,
+   uint32_t handle)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+   amdgpu_cs_syncobj_reset(ws->dev, , 1);
+}
+
+static void radv_amdgpu_signal_syncobj(struct radeon_winsys *_ws,
+   uint32_t handle)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+   amdgpu_cs_syncobj_signal(ws->dev, , 1);
+}
+
+static bool radv_amdgpu_wait_syncobj(struct radeon_winsys *_ws,
+   uint32_t handle, uint64_t timeout)
+{
+   struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
+   uint32_t tmp;
+
+   /* The timeouts are signed, while vulkan timeouts are unsigned. */
+   timeout = MIN2(timeout, INT64_MAX);
+
+   int ret = amdgpu_cs_syncobj_wait(ws->dev, , 1, timeout,
+DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT 
|
+DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL,
+);
+   if (ret == 0) {
+   return true;
+   } else if (ret == -1 && errno == ETIME) {
+   return false;
+   } else {
+   fprintf(stderr, "amdgpu: radv_amdgpu_wait_syncobj 
failed!\nerrno: %d\n", errno);
+   return false;
+   }
+}
+
 static int radv_amdgpu_export_syncobj(struct radeon_winsys *_ws,
  uint32_t syncobj,
  int *fd)
@@ -1319,6 +1356,9 @@ void radv_amdgpu_cs_init_functions(struct 
radv_amdgpu_winsys *ws)
ws->base.destroy_sem = radv_amdgpu_destroy_sem;
ws->base.create_syncobj = radv_amdgpu_create_syncobj;
ws->base.destroy_syncobj = radv_amdgpu_destroy_syncobj;
+   ws->base.reset_syncobj = radv_amdgpu_reset_syncobj;
+   ws->base.signal_syncobj = radv_amdgpu_signal_syncobj;
+   ws->base.wait_syncobj = radv_amdgpu_wait_syncobj;
ws->base.export_syncobj = radv_amdgpu_export_syncobj;
ws->base.import_syncobj = radv_amdgpu_import_syncobj;
ws->base.fence_wait = radv_amdgpu_fence_wait;
-- 
2.15.1

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[Mesa-dev] [PATCH 5/6] radv: Implement VK_KHR_external_fence_fd.

2017-12-16 Thread Bas Nieuwenhuizen 
---
 src/amd/vulkan/radv_device.c  | 47 +++
 src/amd/vulkan/radv_extensions.py |  1 +
 2 files changed, 48 insertions(+)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index fc9fb59f991..94562fda875 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3746,3 +3746,50 @@ void 
radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
}
 }
+
+VkResult radv_ImportFenceFdKHR(VkDevice _device,
+  const VkImportFenceFdInfoKHR 
*pImportFenceFdInfo)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
+   uint32_t syncobj_handle = 0;
+   uint32_t *syncobj_dst = NULL;
+   assert(pImportFenceFdInfo->handleType == 
VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
+
+   int ret = device->ws->import_syncobj(device->ws, 
pImportFenceFdInfo->fd, _handle);
+   if (ret != 0)
+   return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
+
+   if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
+   syncobj_dst = >temp_syncobj;
+   } else {
+   syncobj_dst = >syncobj;
+   }
+
+   if (*syncobj_dst)
+   device->ws->destroy_syncobj(device->ws, *syncobj_dst);
+
+   *syncobj_dst = syncobj_handle;
+   close(pImportFenceFdInfo->fd);
+   return VK_SUCCESS;
+}
+
+VkResult radv_GetFenceFdKHR(VkDevice _device,
+   const VkFenceGetFdInfoKHR *pGetFdInfo,
+   int *pFd)
+{
+   RADV_FROM_HANDLE(radv_device, device, _device);
+   RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
+   int ret;
+   uint32_t syncobj_handle;
+
+   assert(pGetFdInfo->handleType == 
VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
+   if (fence->temp_syncobj)
+   syncobj_handle = fence->temp_syncobj;
+   else
+   syncobj_handle = fence->syncobj;
+   ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
+   if (ret)
+   return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
+   return VK_SUCCESS;
+}
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index 2c1c71ecdc7..3188735ea78 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -53,6 +53,7 @@ EXTENSIONS = [
 Extension('VK_KHR_bind_memory2',  1, True),
 Extension('VK_KHR_dedicated_allocation',  1, True),
 Extension('VK_KHR_descriptor_update_template',1, True),
+Extension('VK_KHR_external_fence_fd', 1, 
'device->rad_info.has_syncobj_wait'),
 Extension('VK_KHR_external_memory',   1, True),
 Extension('VK_KHR_external_memory_capabilities',  1, True),
 Extension('VK_KHR_external_memory_fd',1, True),
-- 
2.15.1

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Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Disable regular fast-clears (CCS_D) on gen9+"

2017-12-16 Thread Jason Ekstrand 

On December 16, 2017 14:35:29 Nanley Chery  wrote:


On Wed, Dec 13, 2017 at 05:52:03PM -0800, Jason Ekstrand wrote:

This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68.

Cc: "17.3" 
---
 src/mesa/drivers/dri/i965/brw_meta_util.c | 10 -
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 57 ---
 2 files changed, 25 insertions(+), 42 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
b/src/mesa/drivers/dri/i965/brw_meta_util.c

index 54dc6a5..b311815 100644
--- a/src/mesa/drivers/dri/i965/brw_meta_util.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
@@ -293,17 +293,7 @@ brw_is_color_fast_clear_compatible(struct brw_context 
*brw,

brw->mesa_to_isl_render_format[mt->format])
   return false;

-   /* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
-* GL_FRAMEBUFFER_SRGB is enabled any color renderbuffers will be
-* resolved in intel_update_state. In that case it's pointless to do a
-* fast clear because it's very likely to be immediately resolved.
-*/
const bool srgb_rb = _mesa_get_srgb_format_linear(mt->format) != mt->format;
-   if (devinfo->gen >= 9 &&
-   mt->surf.samples == 1 &&
-   ctx->Color.sRGBEnabled && srgb_rb)
-  return false;
-
   /* Gen10 doesn't automatically decode the clear color of sRGB buffers. Since
* we currently don't perform this decode in software, avoid a fast-clear
* altogether. TODO: Do this in software.
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

index c1a4ce1..b87d356 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -207,13 +207,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
if (!brw->mesa_format_supports_render[mt->format])
   return false;

-   if (devinfo->gen >= 9) {
-  mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
-  const enum isl_format isl_format =
- brw_isl_format_for_mesa_format(linear_format);
-  return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
-   } else
-  return true;
+   return true;
 }

 static bool
@@ -256,7 +250,7 @@ intel_miptree_supports_hiz(const struct brw_context *brw,
  * our HW tends to support more linear formats than sRGB ones, we use this
  * format variant for check for CCS_E compatibility.
  */
-MAYBE_UNUSED static bool
+static bool
 format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
  const struct intel_mipmap_tree *mt,
  enum isl_format access_format)
@@ -290,12 +284,13 @@ intel_miptree_supports_ccs_e(struct brw_context *brw,
if (!intel_miptree_supports_ccs(brw, mt))
   return false;

-   /* Fast clear can be also used to clear srgb surfaces by using equivalent
-* linear format. This trick, however, can't be extended to be used with
-* lossless compression and therefore a check is needed to see if the 
format

-* really is linear.
+   /* Many window system buffers are sRGB even if they are never rendered as
+* sRGB.  For those, we want CCS_E for when sRGBEncode is false.  When the
+* surface is used as sRGB, we fall back to CCS_D.
 */
-   return _mesa_get_srgb_format_linear(mt->format) == mt->format;
+   mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+   enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
+   return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
 }

 /**
@@ -2686,29 +2681,27 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
   return ISL_AUX_USAGE_MCS;

case ISL_AUX_USAGE_CCS_D:
-  /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
-   * the single-sampled color renderbuffers because the CCS buffer isn't
-   * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
-   * enabled because otherwise the surface state will be programmed with
-   * the linear equivalent format anyway.
-   */
-  if (isl_format_is_srgb(render_format) &&
-  _mesa_get_srgb_format_linear(mt->format) != mt->format) {
- return ISL_AUX_USAGE_NONE;
-  } else if (!mt->mcs_buf) {
- return ISL_AUX_USAGE_NONE;
-  } else {
- return ISL_AUX_USAGE_CCS_D;
-  }
+  return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;

case ISL_AUX_USAGE_CCS_E: {
-  /* Lossless compression is not supported for SRGB formats, it
-   * should be impossible to get here with such surfaces.
+  /* If the format supports CCS_E and is compatible with the miptree,
+   * then we can use it.
*/
-  assert(!isl_format_is_srgb(render_format) ||
- _mesa_get_srgb_format_linear(mt->format) == mt->format);
+  if

Re: [Mesa-dev] [PATCH 3/3] Revert "i965: Disable regular fast-clears (CCS_D) on gen9+"

2017-12-16 Thread Nanley Chery 
On Wed, Dec 13, 2017 at 05:52:03PM -0800, Jason Ekstrand wrote:
> This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68.
> 
> Cc: "17.3" 
> ---
>  src/mesa/drivers/dri/i965/brw_meta_util.c | 10 -
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 57 
> ---
>  2 files changed, 25 insertions(+), 42 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_meta_util.c 
> b/src/mesa/drivers/dri/i965/brw_meta_util.c
> index 54dc6a5..b311815 100644
> --- a/src/mesa/drivers/dri/i965/brw_meta_util.c
> +++ b/src/mesa/drivers/dri/i965/brw_meta_util.c
> @@ -293,17 +293,7 @@ brw_is_color_fast_clear_compatible(struct brw_context 
> *brw,
> brw->mesa_to_isl_render_format[mt->format])
>return false;
>  
> -   /* Gen9 doesn't support fast clear on single-sampled SRGB buffers. When
> -* GL_FRAMEBUFFER_SRGB is enabled any color renderbuffers will be
> -* resolved in intel_update_state. In that case it's pointless to do a
> -* fast clear because it's very likely to be immediately resolved.
> -*/
> const bool srgb_rb = _mesa_get_srgb_format_linear(mt->format) != 
> mt->format;
> -   if (devinfo->gen >= 9 &&
> -   mt->surf.samples == 1 &&
> -   ctx->Color.sRGBEnabled && srgb_rb)
> -  return false;
> -
>/* Gen10 doesn't automatically decode the clear color of sRGB buffers. 
> Since
> * we currently don't perform this decode in software, avoid a fast-clear
> * altogether. TODO: Do this in software.
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index c1a4ce1..b87d356 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -207,13 +207,7 @@ intel_miptree_supports_ccs(struct brw_context *brw,
> if (!brw->mesa_format_supports_render[mt->format])
>return false;
>  
> -   if (devinfo->gen >= 9) {
> -  mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
> -  const enum isl_format isl_format =
> - brw_isl_format_for_mesa_format(linear_format);
> -  return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
> -   } else
> -  return true;
> +   return true;
>  }
>  
>  static bool
> @@ -256,7 +250,7 @@ intel_miptree_supports_hiz(const struct brw_context *brw,
>   * our HW tends to support more linear formats than sRGB ones, we use this
>   * format variant for check for CCS_E compatibility.
>   */
> -MAYBE_UNUSED static bool
> +static bool
>  format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
>   const struct intel_mipmap_tree *mt,
>   enum isl_format access_format)
> @@ -290,12 +284,13 @@ intel_miptree_supports_ccs_e(struct brw_context *brw,
> if (!intel_miptree_supports_ccs(brw, mt))
>return false;
>  
> -   /* Fast clear can be also used to clear srgb surfaces by using equivalent
> -* linear format. This trick, however, can't be extended to be used with
> -* lossless compression and therefore a check is needed to see if the 
> format
> -* really is linear.
> +   /* Many window system buffers are sRGB even if they are never rendered as
> +* sRGB.  For those, we want CCS_E for when sRGBEncode is false.  When the
> +* surface is used as sRGB, we fall back to CCS_D.
>  */
> -   return _mesa_get_srgb_format_linear(mt->format) == mt->format;
> +   mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
> +   enum isl_format isl_format = 
> brw_isl_format_for_mesa_format(linear_format);
> +   return isl_format_supports_ccs_e(>screen->devinfo, isl_format);
>  }
>  
>  /**
> @@ -2686,29 +2681,27 @@ intel_miptree_render_aux_usage(struct brw_context 
> *brw,
>return ISL_AUX_USAGE_MCS;
>  
> case ISL_AUX_USAGE_CCS_D:
> -  /* If FRAMEBUFFER_SRGB is used on Gen9+ then we need to resolve any of
> -   * the single-sampled color renderbuffers because the CCS buffer isn't
> -   * supported for SRGB formats. This only matters if FRAMEBUFFER_SRGB is
> -   * enabled because otherwise the surface state will be programmed with
> -   * the linear equivalent format anyway.
> -   */
> -  if (isl_format_is_srgb(render_format) &&
> -  _mesa_get_srgb_format_linear(mt->format) != mt->format) {
> - return ISL_AUX_USAGE_NONE;
> -  } else if (!mt->mcs_buf) {
> - return ISL_AUX_USAGE_NONE;
> -  } else {
> - return ISL_AUX_USAGE_CCS_D;
> -  }
> +  return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
>  
> case ISL_AUX_USAGE_CCS_E: {
> -  /* Lossless compression is not supported for SRGB formats, it
> -   * should be impossible to get here with such surfaces.
> +  /* If the format supports CCS_E and is compatible with the miptree,
> +   * then we can use it.
> */
> -

Re: [Mesa-dev] [PATCH] st/st_glsl_to_nir: call nir_lower_64bit_pack

2017-12-16 Thread Erik Faye-Lund 
On Thu, Dec 14, 2017 at 6:02 AM, Timothy Arceri  wrote:
> Fixes 56 crashes in radeonsi.

56 crashes with what? Piglit?
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Re: [Mesa-dev] [PATCH] anv: Remove unused variable.

2017-12-16 Thread Jason Ekstrand 

Rb


On December 16, 2017 13:03:41 Bas Nieuwenhuizen  
wrote:



---
 src/intel/vulkan/anv_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 59767c2..4638f311dd1 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -741,8 +741,6 @@ void anv_GetPhysicalDeviceFeatures2KHR(
   }

   case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES_KHR: {
- ANV_FROM_HANDLE(anv_physical_device, pdevice, physicalDevice);
-
  VkPhysicalDevice16BitStorageFeaturesKHR *features =
 (VkPhysicalDevice16BitStorageFeaturesKHR *)ext;

--
2.15.1

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[Mesa-dev] [PATCH] anv: Remove unused variable.

2017-12-16 Thread Bas Nieuwenhuizen 
---
 src/intel/vulkan/anv_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 59767c2..4638f311dd1 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -741,8 +741,6 @@ void anv_GetPhysicalDeviceFeatures2KHR(
   }
 
   case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES_KHR: {
- ANV_FROM_HANDLE(anv_physical_device, pdevice, physicalDevice);
-
  VkPhysicalDevice16BitStorageFeaturesKHR *features =
 (VkPhysicalDevice16BitStorageFeaturesKHR *)ext;
 
-- 
2.15.1

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[Mesa-dev] [Bug 104290] Multisampling gives corrupt rendering

2017-12-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=104290

--- Comment #1 from mais...@archlinux.us ---
./samples/rotating_texture/rotating_texture is basically the exact same thing,
but does not have this issue.

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[Mesa-dev] [Bug 104290] Multisampling gives corrupt rendering

2017-12-16 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=104290

Bug ID: 104290
   Summary: Multisampling gives corrupt rendering
   Product: Mesa
   Version: 17.3
  Hardware: Other
OS: All
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: mais...@archlinux.us
QA Contact: mesa-dev@lists.freedesktop.org

Created attachment 136218
  --> https://bugs.freedesktop.org/attachment.cgi?id=136218=edit
Noisy output

Repro:
https://github.com/ARM-software/vulkan-sdk/tree/master/samples/multisampling

Checkout, build (cmake -DPLATFORM=wayland/xcb) and run
./samples/multisampling/multisampling

There is some weird noise in the output when rendering with multisampling shown
in screenshot at certain angles.

GPU: RX470.
I'm not sure which versions are affected, but it affects at least:
Name: vulkan-radeon
Version : 17.3.0-2
Description : Radeon's Vulkan mesa driver

as packaged in Arch.

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[Mesa-dev] [PATCH v2 1/3] nv50: Fix unused var warning in release build

2017-12-16 Thread Rhys Kidd 
Signed-off-by: Rhys Kidd 
---
 src/gallium/drivers/nouveau/nv50/nv98_video.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv98_video.c 
b/src/gallium/drivers/nouveau/nv50/nv98_video.c
index 92526d9f64..da0267e646 100644
--- a/src/gallium/drivers/nouveau/nv50/nv98_video.c
+++ b/src/gallium/drivers/nouveau/nv50/nv98_video.c
@@ -40,7 +40,8 @@ nv98_decoder_decode_bitstream(struct pipe_video_codec 
*decoder,
uint32_t comm_seq = ++dec->fence_seq;
union pipe_desc desc;
 
-   unsigned vp_caps, is_ref, ret;
+   unsigned vp_caps, is_ref;
+   MAYBE_UNUSED unsigned ret; /* used in debug checks */
struct nouveau_vp3_video_buffer *refs[16] = {};
 
desc.base = picture;
-- 
2.14.1

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[Mesa-dev] [PATCH v2 0/3] nouveau compiler warning cleanups

2017-12-16 Thread Rhys Kidd 
Couple of little compiler warning cleanups so that nouveau builds without any
warnings for meson's debug and release builds with gcc 7.2.0

v2: Add preventative comment (Ilia Mirkin)

Rhys Kidd (3):
  nv50: Fix unused var warning in release build
  nvc0: Fix unused var warnings in release build
  nv50/ir: Fix unused var warnings in release build

 src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 2 +-
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp  | 4 +++-
 src/gallium/drivers/nouveau/nv50/nv98_video.c | 3 ++-
 src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 7 ---
 4 files changed, 10 insertions(+), 6 deletions(-)

-- 
2.14.1

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[Mesa-dev] [PATCH v2 2/3] nvc0: Fix unused var warnings in release build

2017-12-16 Thread Rhys Kidd 
Signed-off-by: Rhys Kidd 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_video.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c
index b5e7bba5f9..5c1cf899ca 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_video.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_video.c
@@ -32,7 +32,7 @@ nvc0_decoder_begin_frame(struct pipe_video_codec *decoder,
 {
struct nouveau_vp3_decoder *dec = (struct nouveau_vp3_decoder *)decoder;
uint32_t comm_seq = ++dec->fence_seq;
-   unsigned ret = 0;
+   MAYBE_UNUSED unsigned ret = 0; /* used in debug checks */
 
assert(dec);
assert(target);
@@ -53,7 +53,7 @@ nvc0_decoder_decode_bitstream(struct pipe_video_codec 
*decoder,
 {
struct nouveau_vp3_decoder *dec = (struct nouveau_vp3_decoder *)decoder;
uint32_t comm_seq = dec->fence_seq;
-   unsigned ret = 0;
+   MAYBE_UNUSED unsigned ret = 0; /* used in debug checks */
 
assert(decoder);
 
@@ -72,7 +72,8 @@ nvc0_decoder_end_frame(struct pipe_video_codec *decoder,
uint32_t comm_seq = dec->fence_seq;
union pipe_desc desc;
 
-   unsigned vp_caps, is_ref, ret;
+   unsigned vp_caps, is_ref;
+   MAYBE_UNUSED unsigned ret; /* used in debug checks */
struct nouveau_vp3_video_buffer *refs[16] = {};
 
desc.base = picture;
-- 
2.14.1

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[Mesa-dev] [PATCH v2 3/3] nv50/ir: Fix unused var warnings in release build

2017-12-16 Thread Rhys Kidd 
v2: Add preventative comment (Ilia Mirkin)

Reviewed-by: Eric Engestrom 
Signed-off-by: Rhys Kidd 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 2 +-
 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp  | 4 +++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
index cc2a88eb40..139ff4a31d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
@@ -621,7 +621,7 @@ void
 CodeEmitterNV50::emitLOAD(const Instruction *i)
 {
DataFile sf = i->src(0).getFile();
-   int32_t offset = i->getSrc(0)->reg.data.offset;
+   MAYBE_UNUSED int32_t offset = i->getSrc(0)->reg.data.offset;
 
switch (sf) {
case FILE_SHADER_INPUT:
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 61d4e6a2d0..0bbf21312f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3308,7 +3308,9 @@ PostRaLoadPropagation::handleMADforNV50(Instruction *i)
  i->setSrc(1, def->getSrc(0));
   } else {
  ImmediateValue val;
- bool ret = def->src(0).getImmediate(val);
+ // getImmediate() has side-effects on the argument so this *shouldn't*
+ // be folded into the assert()
+ MAYBE_UNUSED bool ret = def->src(0).getImmediate(val);
  assert(ret);
  if (i->getSrc(1)->reg.data.id & 1)
 val.reg.data.u32 >>= 16;
-- 
2.14.1

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