Re: [Mesa-dev] [PATCH 3/8] spirv: Add basic type validation for OpLoad, OpStore, and OpCopyMemory

2017-12-30 Thread Jason Ekstrand 
On Sat, Dec 30, 2017 at 3:57 PM, Grazvydas Ignotas 
wrote:

> Hi,
>
> I don't know if it's the game's fault, but it appears this change broke
> DOOM.
> here is the offending spirv binary:
> https://people.freedesktop.org/~notaz/doom_compute_spirv
>

Have you filed a bug?  Please do and assign it to me.  I'll take a look at
it in a week or so.

--Jason



> Gražvydas
>
>
> On Thu, Dec 7, 2017 at 6:12 PM, Jason Ekstrand 
> wrote:
> > ---
> >  src/compiler/spirv/vtn_variables.c | 18 ++
> >  1 file changed, 14 insertions(+), 4 deletions(-)
> >
> > diff --git a/src/compiler/spirv/vtn_variables.c
> b/src/compiler/spirv/vtn_variables.c
> > index cf44ed3..8ce19ff 100644
> > --- a/src/compiler/spirv/vtn_variables.c
> > +++ b/src/compiler/spirv/vtn_variables.c
> > @@ -1969,6 +1969,9 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp
> opcode,
> >struct vtn_value *dest = vtn_value(b, w[1],
> vtn_value_type_pointer);
> >struct vtn_value *src = vtn_value(b, w[2],
> vtn_value_type_pointer);
> >
> > +  vtn_fail_if(dest->type->deref != src->type->deref,
> > +  "Result and pointer types of OpLoad do not match");
> > +
> >vtn_variable_copy(b, dest->pointer, src->pointer);
> >break;
> > }
> > @@ -1976,8 +1979,11 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp
> opcode,
> > case SpvOpLoad: {
> >struct vtn_type *res_type =
> >   vtn_value(b, w[1], vtn_value_type_type)->type;
> > -  struct vtn_pointer *src =
> > - vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
> > +  struct vtn_value *src_val = vtn_value(b, w[3],
> vtn_value_type_pointer);
> > +  struct vtn_pointer *src = src_val->pointer;
> > +
> > +  vtn_fail_if(res_type != src_val->type->deref,
> > +  "Result and pointer types of OpLoad do not match");
> >
> >if (src->mode == vtn_variable_mode_image ||
> >src->mode == vtn_variable_mode_sampler) {
> > @@ -1990,8 +1996,12 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp
> opcode,
> > }
> >
> > case SpvOpStore: {
> > -  struct vtn_pointer *dest =
> > - vtn_value(b, w[1], vtn_value_type_pointer)->pointer;
> > +  struct vtn_value *dest_val = vtn_value(b, w[1],
> vtn_value_type_pointer);
> > +  struct vtn_pointer *dest = dest_val->pointer;
> > +  struct vtn_value *src_val = vtn_untyped_value(b, w[2]);
> > +
> > +  vtn_fail_if(dest_val->type->deref != src_val->type,
> > +  "Value and pointer types of OpStore do not match");
> >
> >if (glsl_type_is_sampler(dest->type->type)) {
> >   vtn_warn("OpStore of a sampler detected.  Doing on-the-fly
> copy "
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH 3/8] spirv: Add basic type validation for OpLoad, OpStore, and OpCopyMemory

2017-12-30 Thread Grazvydas Ignotas 
Hi,

I don't know if it's the game's fault, but it appears this change broke DOOM.
here is the offending spirv binary:
https://people.freedesktop.org/~notaz/doom_compute_spirv

Gražvydas


On Thu, Dec 7, 2017 at 6:12 PM, Jason Ekstrand  wrote:
> ---
>  src/compiler/spirv/vtn_variables.c | 18 ++
>  1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/src/compiler/spirv/vtn_variables.c 
> b/src/compiler/spirv/vtn_variables.c
> index cf44ed3..8ce19ff 100644
> --- a/src/compiler/spirv/vtn_variables.c
> +++ b/src/compiler/spirv/vtn_variables.c
> @@ -1969,6 +1969,9 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp 
> opcode,
>struct vtn_value *dest = vtn_value(b, w[1], vtn_value_type_pointer);
>struct vtn_value *src = vtn_value(b, w[2], vtn_value_type_pointer);
>
> +  vtn_fail_if(dest->type->deref != src->type->deref,
> +  "Result and pointer types of OpLoad do not match");
> +
>vtn_variable_copy(b, dest->pointer, src->pointer);
>break;
> }
> @@ -1976,8 +1979,11 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp 
> opcode,
> case SpvOpLoad: {
>struct vtn_type *res_type =
>   vtn_value(b, w[1], vtn_value_type_type)->type;
> -  struct vtn_pointer *src =
> - vtn_value(b, w[3], vtn_value_type_pointer)->pointer;
> +  struct vtn_value *src_val = vtn_value(b, w[3], vtn_value_type_pointer);
> +  struct vtn_pointer *src = src_val->pointer;
> +
> +  vtn_fail_if(res_type != src_val->type->deref,
> +  "Result and pointer types of OpLoad do not match");
>
>if (src->mode == vtn_variable_mode_image ||
>src->mode == vtn_variable_mode_sampler) {
> @@ -1990,8 +1996,12 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp 
> opcode,
> }
>
> case SpvOpStore: {
> -  struct vtn_pointer *dest =
> - vtn_value(b, w[1], vtn_value_type_pointer)->pointer;
> +  struct vtn_value *dest_val = vtn_value(b, w[1], 
> vtn_value_type_pointer);
> +  struct vtn_pointer *dest = dest_val->pointer;
> +  struct vtn_value *src_val = vtn_untyped_value(b, w[2]);
> +
> +  vtn_fail_if(dest_val->type->deref != src_val->type,
> +  "Value and pointer types of OpStore do not match");
>
>if (glsl_type_is_sampler(dest->type->type)) {
>   vtn_warn("OpStore of a sampler detected.  Doing on-the-fly copy "
> --
> 2.5.0.400.gff86faf
>
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[Mesa-dev] [PATCH] radv: Use the alternative workaround for GFX9 scissor issues.

2017-12-30 Thread Bas Nieuwenhuizen 
I don't like having to fush, so this introduces the other workaround.
Since my experience is that context register writes are pretty cheap,
this should not have too much overhead.

I haven't seen any significant perf changes in benchmarks or games
though.
---
 src/amd/vulkan/radv_cmd_buffer.c | 22 --
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c735d201802..0ca33cc67bc 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1102,10 +1102,6 @@ radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)
 {
uint32_t count = cmd_buffer->state.dynamic.scissor.count;
 
-   if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
-   cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
-   si_emit_cache_flush(cmd_buffer);
-   }
si_write_scissors(cmd_buffer->cs, 0, count,
  cmd_buffer->state.dynamic.scissor.scissors,
  cmd_buffer->state.dynamic.viewport.viewports,
@@ -1866,7 +1862,8 @@ radv_upload_graphics_shader_descriptors(struct 
radv_cmd_buffer *cmd_buffer, bool
 static void
 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, bool indexed_draw,
 bool instanced_draw, bool indirect_draw,
-uint32_t draw_vertex_count)
+uint32_t draw_vertex_count,
+bool *gfx9_context_roll)
 {
struct radeon_info *info = 
_buffer->device->physical_device->rad_info;
struct radv_cmd_state *state = _buffer->state;
@@ -1921,6 +1918,7 @@ radv_emit_draw_registers(struct radv_cmd_buffer 
*cmd_buffer, bool indexed_draw,
   
R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
   primitive_reset_index);
state->last_primitive_reset_index = 
primitive_reset_index;
+   *gfx9_context_roll = true;
}
}
 }
@@ -3279,6 +3277,9 @@ static void
 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer,
  const struct radv_draw_info *info)
 {
+   bool context_roll = cmd_buffer->state.dirty & 
~RADV_CMD_DIRTY_INDEX_BUFFER;
+   bool scissor_emitted = cmd_buffer->state.dirty & 
(RADV_CMD_DIRTY_DYNAMIC_SCISSOR | RADV_CMD_DIRTY_DYNAMIC_VIEWPORT);
+
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
radv_emit_graphics_pipeline(cmd_buffer);
 
@@ -3303,7 +3304,16 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer 
*cmd_buffer,
 
radv_emit_draw_registers(cmd_buffer, info->indexed,
 info->instance_count > 1, info->indirect,
-info->indirect ? 0 : info->count);
+info->indirect ? 0 : info->count,
+_roll);
+
+   /* VEGA10 and RAVEN need a workaround for scissor registers. Either we 
need to
+* do a PS_APRTIAL_FLUSH before writing them, or we need to always 
write it if
+* a context roll happens. This does the lattter. */
+   if (context_roll && !scissor_emitted &&
+   (cmd_buffer->device->physical_device->rad_info.family == 
CHIP_VEGA10 ||
+cmd_buffer->device->physical_device->rad_info.family == 
CHIP_RAVEN))
+   radv_emit_scissor(cmd_buffer);
 }
 
 static void
-- 
2.15.1

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[Mesa-dev] [PATCH 2/2] radv: Implement binning on GFX9.

2017-12-30 Thread Bas Nieuwenhuizen 
Overall it does not really help or hurt. The deferred demo gets 1%
improvement and some games a 3% decrease, so I don't think this
should be enabled by default.

But with the code upstream it is easier to experiment with it.
---
 src/amd/vulkan/radv_cmd_buffer.c |  16 ++
 src/amd/vulkan/radv_pipeline.c   | 325 +++
 src/amd/vulkan/radv_private.h|   7 +
 3 files changed, 348 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index c735d201802..261344e939b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1042,6 +1042,21 @@ radv_emit_vgt_vertex_reuse(struct radv_cmd_buffer 
*cmd_buffer,
   pipeline->graphics.vtx_reuse_depth);
 }
 
+static void
+radv_emit_binning_state(struct radv_cmd_buffer *cmd_buffer,
+  struct radv_pipeline *pipeline)
+{
+   struct radeon_winsys_cs *cs = cmd_buffer->cs;
+
+   if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)
+   return;
+
+   radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0,
+  pipeline->graphics.bin.pa_sc_binner_cntl_0);
+   radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL,
+  pipeline->graphics.bin.db_dfsm_control);
+}
+
 static void
 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
 {
@@ -1059,6 +1074,7 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer 
*cmd_buffer)
radv_emit_geometry_shader(cmd_buffer, pipeline);
radv_emit_fragment_shader(cmd_buffer, pipeline);
radv_emit_vgt_vertex_reuse(cmd_buffer, pipeline);
+   radv_emit_binning_state(cmd_buffer, pipeline);
 
cmd_buffer->scratch_size_needed =
  MAX2(cmd_buffer->scratch_size_needed,
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 14ada20d525..1654b0f0186 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2002,6 +2002,329 @@ radv_pipeline_stage_to_user_data_0(struct radv_pipeline 
*pipeline,
}
 }
 
+struct radv_bin_size_entry {
+   unsigned bpp;
+   VkExtent2D extent;
+};
+
+static VkExtent2D
+radv_compute_bin_size(struct radv_pipeline *pipeline, const 
VkGraphicsPipelineCreateInfo *pCreateInfo)
+{
+   static const struct radv_bin_size_entry color_size_table[][3][9] = {
+   {
+   /* One RB / SE */
+   {
+   /* One shader engine */
+   {0, {128,  128}},
+   {1, { 64,  128}},
+   {2, { 32,  128}},
+   {3, { 16,  128}},
+   {   17, {  0,0}},
+   { UINT_MAX, {  0,0}},
+   },
+   {
+   /* Two shader engines */
+   {0, {128,  128}},
+   {2, { 64,  128}},
+   {3, { 32,  128}},
+   {5, { 16,  128}},
+   {   17, {  0,0}},
+   { UINT_MAX, {  0,0}},
+   },
+   {
+   /* Four shader engines */
+   {0, {128,  128}},
+   {3, { 64,  128}},
+   {5, { 16,  128}},
+   {   17, {  0,0}},
+   { UINT_MAX, {  0,0}},
+   },
+   },
+   {
+   /* Two RB / SE */
+   {
+   /* One shader engine */
+   {0, {128,  128}},
+   {2, { 64,  128}},
+   {3, { 32,  128}},
+   {5, { 16,  128}},
+   {   33, {  0,0}},
+   { UINT_MAX, {  0,0}},
+   },
+   {
+   /* Two shader engines */
+   {0, {128,  128}},
+   {3, { 64,  128}},
+   {5, { 32,  128}},
+   {9, { 16,  128}},
+   {   33, {  0,0}},
+   { UINT_MAX, {  0,0}},
+   },
+   {
+   /* Four shader engines */
+   {0, {256,  256}},
+

[Mesa-dev] [PATCH 1/2] radv: Add flag for enabling binning.

2017-12-30 Thread Bas Nieuwenhuizen 
Letting it be disabled by default.
---
 src/amd/vulkan/radv_debug.h  | 1 +
 src/amd/vulkan/radv_device.c | 8 
 2 files changed, 9 insertions(+)

diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index af07564833e..5b37bfe0847 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -48,6 +48,7 @@ enum {
RADV_PERFTEST_NO_BATCHCHAIN  =   0x1,
RADV_PERFTEST_SISCHED=   0x2,
RADV_PERFTEST_LOCAL_BOS  =   0x4,
+   RADV_PERFTEST_BINNING =   0x8,
 };
 
 bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 130b4222bcd..ed46692cefb 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -344,6 +344,7 @@ static const struct debug_control radv_perftest_options[] = 
{
{"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
{"sisched", RADV_PERFTEST_SISCHED},
{"localbos", RADV_PERFTEST_LOCAL_BOS},
+   {"binning", RADV_PERFTEST_BINNING},
{NULL, 0}
 };
 
@@ -1080,6 +1081,13 @@ VkResult radv_CreateDevice(
}
}
 
+   device->pbb_allowed = device->physical_device->rad_info.chip_class >= 
GFX9 &&
+ (device->instance->perftest_flags & 
RADV_PERFTEST_BINNING);
+
+   /* Disabled and not implemented for now. */
+   device->dfsm_allowed = device->pbb_allowed && false;
+
+
 #if HAVE_LLVM < 0x0400
device->llvm_supports_spill = false;
 #else
-- 
2.15.1

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Re: [Mesa-dev] [PATCH] i965: Combine {VS, FS}_OPCODE_GET_BUFFER_SIZE opcodes.

2017-12-30 Thread Jason Ekstrand 

Rb


On December 29, 2017 23:39:21 Kenneth Graunke  wrote:


These are the same, we don't need a separate opcode enum per backend.
---
 src/intel/compiler/brw_eu_defines.h   | 5 ++---
 src/intel/compiler/brw_fs.cpp | 2 +-
 src/intel/compiler/brw_fs_generator.cpp   | 2 +-
 src/intel/compiler/brw_fs_nir.cpp | 2 +-
 src/intel/compiler/brw_shader.cpp | 9 +++--
 src/intel/compiler/brw_vec4.cpp   | 2 +-
 src/intel/compiler/brw_vec4_generator.cpp | 9 -
 src/intel/compiler/brw_vec4_nir.cpp   | 2 +-
 8 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h

index 8ed97912b4d..30e2e8f0708 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -451,6 +451,8 @@ enum opcode {
 */
SHADER_OPCODE_BROADCAST,

+   SHADER_OPCODE_GET_BUFFER_SIZE,
+
VEC4_OPCODE_MOV_BYTES,
VEC4_OPCODE_PACK_BYTES,
VEC4_OPCODE_UNPACK_UNIFORM,
@@ -479,7 +481,6 @@ enum opcode {
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
-   FS_OPCODE_GET_BUFFER_SIZE,
FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
FS_OPCODE_DISCARD_JUMP,
FS_OPCODE_SET_SAMPLE_ID,
@@ -496,8 +497,6 @@ enum opcode {
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,

-   VS_OPCODE_GET_BUFFER_SIZE,
-
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,

/**
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6d9f0eccb29..9d0546e5797 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5007,7 +5007,7 @@ get_lowered_simd_width(const struct gen_device_info 
*devinfo,

   return MIN2(8, inst->exec_size);

case FS_OPCODE_LINTERP:
-   case FS_OPCODE_GET_BUFFER_SIZE:
+   case SHADER_OPCODE_GET_BUFFER_SIZE:
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDX_FINE:
case FS_OPCODE_DDY_COARSE:
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp

index 6a3b2dcf8a3..37b8f07769e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1964,7 +1964,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)

  src[0].subnr = 4 * type_sz(src[0].type);
  brw_MOV(p, dst, stride(src[0], 8, 4, 1));
  break;
-  case FS_OPCODE_GET_BUFFER_SIZE:
+  case SHADER_OPCODE_GET_BUFFER_SIZE:
  generate_get_buffer_size(inst, dst, src[0], src[1]);
  break;
   case SHADER_OPCODE_TEX:
diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp

index 01651dda444..ab132f700a3 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4290,7 +4290,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr

   ubld.MOV(src_payload, brw_imm_d(0));

   const unsigned index = prog_data->binding_table.ssbo_start + ssbo_index;
-  fs_inst *inst = ubld.emit(FS_OPCODE_GET_BUFFER_SIZE, ret_payload,
+  fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload,
 src_payload, brw_imm_ud(index));
   inst->header_size = 0;
   inst->mlen = 1;
diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp

index 74b52976d74..1df4f35cd8e 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -331,6 +331,9 @@ brw_instruction_name(const struct gen_device_info 
*devinfo, enum opcode op)

case SHADER_OPCODE_BROADCAST:
   return "broadcast";

+   case SHADER_OPCODE_GET_BUFFER_SIZE:
+  return "get_buffer_size";
+
case VEC4_OPCODE_MOV_BYTES:
   return "mov_bytes";
case VEC4_OPCODE_PACK_BYTES:
@@ -373,9 +376,6 @@ brw_instruction_name(const struct gen_device_info 
*devinfo, enum opcode op)

case FS_OPCODE_PIXEL_Y:
   return "pixel_y";

-   case FS_OPCODE_GET_BUFFER_SIZE:
-  return "fs_get_buffer_size";
-
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
   return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
@@ -422,9 +422,6 @@ brw_instruction_name(const struct gen_device_info 
*devinfo, enum opcode op)

case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
   return "set_simd4x2_header_gen9";

-   case VS_OPCODE_GET_BUFFER_SIZE:
-  return "vs_get_buffer_size";
-
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
   return "unpack_flags_simd4x2";

diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 73c40ad6009..3ddbe6c57fc 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -361,7 +361,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
-   case VS_OPCODE_GET_BUFFER_SIZE:

Re: [Mesa-dev] [PATCH] i965: Combine {VS, FS}_OPCODE_GET_BUFFER_SIZE opcodes.

2017-12-30 Thread Jason Ekstrand 

Rb


On December 29, 2017 23:39:21 Kenneth Graunke  wrote:


These are the same, we don't need a separate opcode enum per backend.
---
 src/intel/compiler/brw_eu_defines.h   | 5 ++---
 src/intel/compiler/brw_fs.cpp | 2 +-
 src/intel/compiler/brw_fs_generator.cpp   | 2 +-
 src/intel/compiler/brw_fs_nir.cpp | 2 +-
 src/intel/compiler/brw_shader.cpp | 9 +++--
 src/intel/compiler/brw_vec4.cpp   | 2 +-
 src/intel/compiler/brw_vec4_generator.cpp | 9 -
 src/intel/compiler/brw_vec4_nir.cpp   | 2 +-
 8 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h

index 8ed97912b4d..30e2e8f0708 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -451,6 +451,8 @@ enum opcode {
 */
SHADER_OPCODE_BROADCAST,

+   SHADER_OPCODE_GET_BUFFER_SIZE,
+
VEC4_OPCODE_MOV_BYTES,
VEC4_OPCODE_PACK_BYTES,
VEC4_OPCODE_UNPACK_UNIFORM,
@@ -479,7 +481,6 @@ enum opcode {
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN4,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL,
-   FS_OPCODE_GET_BUFFER_SIZE,
FS_OPCODE_MOV_DISPATCH_TO_FLAGS,
FS_OPCODE_DISCARD_JUMP,
FS_OPCODE_SET_SAMPLE_ID,
@@ -496,8 +497,6 @@ enum opcode {
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_SET_SIMD4X2_HEADER_GEN9,

-   VS_OPCODE_GET_BUFFER_SIZE,
-
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,

/**
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 6d9f0eccb29..9d0546e5797 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -5007,7 +5007,7 @@ get_lowered_simd_width(const struct gen_device_info 
*devinfo,

   return MIN2(8, inst->exec_size);

case FS_OPCODE_LINTERP:
-   case FS_OPCODE_GET_BUFFER_SIZE:
+   case SHADER_OPCODE_GET_BUFFER_SIZE:
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDX_FINE:
case FS_OPCODE_DDY_COARSE:
diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp

index 6a3b2dcf8a3..37b8f07769e 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1964,7 +1964,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)

  src[0].subnr = 4 * type_sz(src[0].type);
  brw_MOV(p, dst, stride(src[0], 8, 4, 1));
  break;
-  case FS_OPCODE_GET_BUFFER_SIZE:
+  case SHADER_OPCODE_GET_BUFFER_SIZE:
  generate_get_buffer_size(inst, dst, src[0], src[1]);
  break;
   case SHADER_OPCODE_TEX:
diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp

index 01651dda444..ab132f700a3 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4290,7 +4290,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr

   ubld.MOV(src_payload, brw_imm_d(0));

   const unsigned index = prog_data->binding_table.ssbo_start + ssbo_index;
-  fs_inst *inst = ubld.emit(FS_OPCODE_GET_BUFFER_SIZE, ret_payload,
+  fs_inst *inst = ubld.emit(SHADER_OPCODE_GET_BUFFER_SIZE, ret_payload,
 src_payload, brw_imm_ud(index));
   inst->header_size = 0;
   inst->mlen = 1;
diff --git a/src/intel/compiler/brw_shader.cpp 
b/src/intel/compiler/brw_shader.cpp

index 74b52976d74..1df4f35cd8e 100644
--- a/src/intel/compiler/brw_shader.cpp
+++ b/src/intel/compiler/brw_shader.cpp
@@ -331,6 +331,9 @@ brw_instruction_name(const struct gen_device_info 
*devinfo, enum opcode op)

case SHADER_OPCODE_BROADCAST:
   return "broadcast";

+   case SHADER_OPCODE_GET_BUFFER_SIZE:
+  return "get_buffer_size";
+
case VEC4_OPCODE_MOV_BYTES:
   return "mov_bytes";
case VEC4_OPCODE_PACK_BYTES:
@@ -373,9 +376,6 @@ brw_instruction_name(const struct gen_device_info 
*devinfo, enum opcode op)

case FS_OPCODE_PIXEL_Y:
   return "pixel_y";

-   case FS_OPCODE_GET_BUFFER_SIZE:
-  return "fs_get_buffer_size";
-
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
   return "uniform_pull_const";
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7:
@@ -422,9 +422,6 @@ brw_instruction_name(const struct gen_device_info 
*devinfo, enum opcode op)

case VS_OPCODE_SET_SIMD4X2_HEADER_GEN9:
   return "set_simd4x2_header_gen9";

-   case VS_OPCODE_GET_BUFFER_SIZE:
-  return "vs_get_buffer_size";
-
case VS_OPCODE_UNPACK_FLAGS_SIMD4X2:
   return "unpack_flags_simd4x2";

diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp
index 73c40ad6009..3ddbe6c57fc 100644
--- a/src/intel/compiler/brw_vec4.cpp
+++ b/src/intel/compiler/brw_vec4.cpp
@@ -361,7 +361,7 @@ vec4_visitor::implied_mrf_writes(vec4_instruction *inst)
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
-   case VS_OPCODE_GET_BUFFER_SIZE: