date:20180303

Re: [Mesa-dev] [PATCH 08/29] nir/format_convert: Add linear <-> sRGB helpers

2018-03-03 Thread Pohjolainen, Topi

On Fri, Jan 26, 2018 at 05:59:37PM -0800, Jason Ekstrand wrote:
> ---
>  src/compiler/nir/nir_format_convert.h | 26 ++
>  1 file changed, 26 insertions(+)

I don't what is the official reference for the formulas and I just took what
google gave me first. There was discussion about the cutoff point between
linear and curved. I got the impression that what you chose below
(open-ended: 0 <= linear < 0.0031308f and 0 <= linear < 0.04045f instead of
close-ended) was more "correct". Just thought I check that anyway (that you
chose that on purpose).

Reviewed-by: Topi Pohjolainen 

> 
> diff --git a/src/compiler/nir/nir_format_convert.h 
> b/src/compiler/nir/nir_format_convert.h
> index e09c955..07618dc 100644
> --- a/src/compiler/nir/nir_format_convert.h
> +++ b/src/compiler/nir/nir_format_convert.h
> @@ -104,3 +104,29 @@ nir_format_pack_uint(nir_builder *b, nir_ssa_def *color,
> return nir_format_pack_uint_unmasked(b, nir_iand(b, color, mask_imm),
>  bits, num_components);
>  }
> +
> +static inline nir_ssa_def *
> +nir_format_linear_to_srgb(nir_builder *b, nir_ssa_def *c)
> +{
> +   nir_ssa_def *linear = nir_fmul(b, c, nir_imm_float(b, 12.92f));
> +   nir_ssa_def *curved =
> +  nir_fsub(b, nir_fmul(b, nir_imm_float(b, 1.055f),
> +  nir_fpow(b, c, nir_imm_float(b, 1.0 / 2.4))),
> +  nir_imm_float(b, 0.055f));
> +
> +   return nir_fsat(b, nir_bcsel(b, nir_flt(b, c, nir_imm_float(b, 
> 0.0031308f)),
> +   linear, curved));
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_srgb_to_linear(nir_builder *b, nir_ssa_def *c)
> +{
> +   nir_ssa_def *linear = nir_fdiv(b, c, nir_imm_float(b, 12.92f));
> +   nir_ssa_def *curved =
> +  nir_fpow(b, nir_fdiv(b, nir_fadd(b, c, nir_imm_float(b, 0.055f)),
> +  nir_imm_float(b, 1.055f)),
> +  nir_imm_float(b, 2.4f));
> +
> +   return nir_fsat(b, nir_bcsel(b, nir_flt(b, c, nir_imm_float(b, 0.04045f)),
> +   linear, curved));
> +}
> -- 
> 2.5.0.400.gff86faf
> 
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Re: [Mesa-dev] [PATCH 07/29] nir: Add the start of a format conversion helper header

2018-03-03 Thread Pohjolainen, Topi

On Fri, Jan 26, 2018 at 05:59:36PM -0800, Jason Ekstrand wrote:
> ---
>  src/compiler/Makefile.sources |   1 +
>  src/compiler/nir/meson.build  |   1 +
>  src/compiler/nir/nir_format_convert.h | 106 
> ++
>  3 files changed, 108 insertions(+)
>  create mode 100644 src/compiler/nir/nir_format_convert.h

Reviewed-by: Topi Pohjolainen 

> 
> diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
> index d3f746f..0b7fe7a 100644
> --- a/src/compiler/Makefile.sources
> +++ b/src/compiler/Makefile.sources
> @@ -196,6 +196,7 @@ NIR_FILES = \
>   nir/nir_control_flow.h \
>   nir/nir_control_flow_private.h \
>   nir/nir_dominance.c \
> + nir/nir_format_convert.h \
>   nir/nir_from_ssa.c \
>   nir/nir_gather_info.c \
>   nir/nir_gs_count_vertices.c \
> diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
> index b5f27ad..ed38c4c 100644
> --- a/src/compiler/nir/meson.build
> +++ b/src/compiler/nir/meson.build
> @@ -90,6 +90,7 @@ files_libnir = files(
>'nir_control_flow.h',
>'nir_control_flow_private.h',
>'nir_dominance.c',
> +  'nir_format_convert.h',
>'nir_from_ssa.c',
>'nir_gather_info.c',
>'nir_gs_count_vertices.c',
> diff --git a/src/compiler/nir/nir_format_convert.h 
> b/src/compiler/nir/nir_format_convert.h
> new file mode 100644
> index 000..e09c955
> --- /dev/null
> +++ b/src/compiler/nir/nir_format_convert.h
> @@ -0,0 +1,106 @@
> +/*
> + * Copyright © 2017 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 
> DEALINGS
> + * IN THE SOFTWARE.
> + */
> +
> +#include "nir_builder.h"
> +
> +static inline nir_ssa_def *
> +nir_shift(nir_builder *b, nir_ssa_def *value, int left_shift)
> +{
> +   if (left_shift > 0)
> +  return nir_ishl(b, value, nir_imm_int(b, left_shift));
> +   else if (left_shift < 0)
> +  return nir_ushr(b, value, nir_imm_int(b, -left_shift));
> +   else
> +  return value;
> +}
> +
> +static inline nir_ssa_def *
> +nir_mask_shift(struct nir_builder *b, nir_ssa_def *src,
> +   uint32_t mask, int left_shift)
> +{
> +   return nir_shift(b, nir_iand(b, src, nir_imm_int(b, mask)), left_shift);
> +}
> +
> +static inline nir_ssa_def *
> +nir_mask_shift_or(struct nir_builder *b, nir_ssa_def *dst, nir_ssa_def *src,
> +  uint32_t src_mask, int src_left_shift)
> +{
> +   return nir_ior(b, nir_mask_shift(b, src, src_mask, src_left_shift), dst);
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_unpack_uint(nir_builder *b, nir_ssa_def *packed,
> +   const unsigned *bits, unsigned num_components)
> +{
> +   assert(num_components >= 1 && num_components <= 4);
> +   nir_ssa_def *comps[4];
> +
> +   if (bits[0] >= packed->bit_size) {
> +  assert(bits[0] == packed->bit_size);
> +  assert(num_components == 1);
> +  return packed;
> +   }
> +
> +   unsigned offset = 0;
> +   for (unsigned i = 0; i < num_components; i++) {
> +  assert(bits[i] < 32);
> +  nir_ssa_def *mask = nir_imm_int(b, (1u << bits[i]) - 1);
> +  comps[i] = nir_iand(b, nir_shift(b, packed, -offset), mask);
> +  offset += bits[i];
> +   }
> +   assert(offset <= packed->bit_size);
> +
> +   return nir_vec(b, comps, num_components);
> +}
> +
> +static inline nir_ssa_def *
> +nir_format_pack_uint_unmasked(nir_builder *b, nir_ssa_def *color,
> +  const unsigned *bits, unsigned num_components)
> +{
> +   assert(num_components >= 1 && num_components <= 4);
> +   nir_ssa_def *packed = nir_imm_int(b, 0);
> +   unsigned offset = 0;
> +   for (unsigned i = 0; i < num_components; i++) {
> +  packed = nir_ior(b, packed, nir_shift(b, nir_channel(b, color, i),
> +   offset));
> +  offset += bits[i];
> +   }
> +   assert(offset <=

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

2018-03-03 Thread Mike Lothian

Hi

Sorry to be a pain again

I've just tested this with clang and the 32bit build still fails without
-latomic

libtool: link: /bin/true glsl/.libs/libstandalone.a
libtool: link: rm -fr glsl/.libs/libstandalone.lax
glsl/.libs/libstandalone.lax
libtool: link: ( cd "glsl/.libs" && rm -f "libstandalone.la" && ln -s "../
libstandalone.la" "libstandalone.la" )
/bin/sh ../../libtool  --tag=CXX   --mode=link clang++ -m32
-fvisibility=hidden -Werror=pointer-arith -Werror=vla -O3 -march=native
-pipe -flto=thin -Wall -fno-math-errno -fno-trapping-math
-Qunused-arguments   -O3 -march=native -pipe -flto=thin -o glsl_
compiler glsl/main.o glsl/libstandalone.la
libtool: link: clang++ -m32 -fvisibility=hidden -Werror=pointer-arith
-Werror=vla -O3 -march=native -pipe -flto=thin -Wall -fno-math-errno
-fno-trapping-math -Qunused-arguments -O3 -march=native -pipe -flto=thin -o
glsl_compiler glsl/main.o  glsl/.libs/l
ibstandalone.a -lz -lpthread -pthread
/var/tmp/portage/media-libs/mesa-/temp/lto-llvm-4efaa5.o:disk_cache.c:function
disk_cache_remove: error: undefined reference to '__atomic_fetch_add_8'
clang-7.0: error: linker command failed with exit code 1 (use -v to see
invocation)
make[4]: *** [Makefile:2364: glsl_compiler] Error 1
make[4]: Leaving directory
'/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src/compiler'

make[3]: *** [Makefile:1793: all] Error 2
make[3]: Leaving directory
'/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src/compiler'

make[2]: *** [Makefile:875: all-recursive] Error 1
make[2]: Leaving directory
'/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src'
make[1]: *** [Makefile:660: all] Error 2
make[1]: Leaving directory
'/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86/src'
make: *** [Makefile:668: all-recursive] Error 1
* ERROR: media-libs/mesa-::gentoo failed (compile phase):
*   emake failed
*
* If you need support, post the output of `emerge --info
'=media-libs/mesa-::gentoo'`,
* the complete build log and the output of `emerge -pqv
'=media-libs/mesa-::gentoo'`.
* The complete build log is located at
'/var/tmp/portage/media-libs/mesa-/temp/build.log'.
* The ebuild environment file is located at
'/var/tmp/portage/media-libs/mesa-/temp/environment'.
* Working directory:
'/var/tmp/portage/media-libs/mesa-/work/mesa--abi_x86_32.x86'
* S: '/var/tmp/portage/media-libs/mesa-/work/mesa-'

If I pass -latomic in with the LDFLAGS it builds fine

On Tue, 27 Feb 2018 at 20:22 Matt Turner  wrote:

> On Tue, Feb 27, 2018 at 2:26 AM, Thierry Reding
>  wrote:
> > On Mon, Feb 26, 2018 at 11:14:05AM -0800, Matt Turner wrote:
> >> On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding
> >>  wrote:
> >> > From: Thierry Reding 
> >> >
> >> > The disk cache implementation uses 64-bit atomic operations. For some
> >> > architectures, such as 32-bit ARM, GCC will not be able to translate
> >> > these operations into lock-free instructions and will instead rely on
> >>
> >> Here, and in the comment in meson.build, I think you mean "atomic"
> >> rather than "lock-free" instructions? It's at least confusing, since
> >> on x86 atomic instructions have a "lock" prefix.
> >
> > This uses the terminology used by the GCC documentation, see:
> >
> > https://gcc.gnu.org/wiki/Atomic/GCCMM
> >
> > I think the GCC terms merely mean that you don't need any explicit
> > locking for these operations to be atomic.
> >
> > How about this instead:
> >
> > "... operations into atomic, lock-free instructions..."
> >
> > ?
>
> Ah, I see. Thanks, that works for me.
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[Mesa-dev] [PATCH RFC] radeonsi: Disable IEEE_MODE.

2018-03-03 Thread Jan Vesely

Neither GL nor CL nor SPIRV needs the IEEE handling of sNaNs.

Signed-off-by: Jan Vesely 
---
This is the 3rd way to handle broken fmin/fmax in clover CL.
It can be worked around in libclc (to not use
llvm.fminnum/llvm.fmaxnum)[0]
LLVM can be patched to not use IEEE_MODE[1]
Or it can be fixed in the config reg in mesa.

The third option is arguably the worst (changes semantics of compiled
code), but since the first two efforts have been stalled for months.
Here's the third one.

Jan

[0] http://lists.llvm.org/pipermail/libclc-dev/2017-November/thread.html#2692
[1] https://reviews.llvm.org/D40514


 src/gallium/drivers/radeonsi/si_compute.c | 8 
 src/gallium/drivers/radeonsi/si_shader.c  | 6 +-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index 41927988cf..d0fcba485b 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -70,6 +70,10 @@ static void code_object_to_config(const amd_kernel_code_t 
*code_object,
  struct si_shader_config *out_config) {
 
uint32_t rsrc1 = code_object->compute_pgm_resource_registers;
+   /* Disable IEEE mode. IEEE_MODE determines sNaN handling by fmin/fmax
+* instructions. Nothing wants the IEEE rules here.
+* Ideally LLVM would not emit this configuration. */
+   rsrc1 &= C_00B848_IEEE_MODE;
uint32_t rsrc2 = code_object->compute_pgm_resource_registers >> 32;
out_config->num_sgprs = code_object->wavefront_sgpr_count;
out_config->num_vgprs = code_object->workitem_vgpr_count;
@@ -137,6 +141,10 @@ static void si_create_compute_state_async(void *job, int 
thread_index)
S_00B848_SGPRS((shader->config.num_sgprs - 1) / 8) |
S_00B848_DX10_CLAMP(1) |
S_00B848_FLOAT_MODE(shader->config.float_mode);
+   /* Disable IEEE mode. IEEE_MODE determines sNaN handling by
+* fmin/fmax instructions. Nothing wants the IEEE rules.
+* Ideally LLVM would not emit this configuration. */
+   shader->config.rsrc1 &= C_00B848_IEEE_MODE;
 
shader->config.rsrc2 =
S_00B84C_USER_SGPR(user_sgprs) |
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 2a50b266f6..01bad71a4e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5178,7 +5178,11 @@ void si_shader_binary_read_config(struct 
ac_shader_binary *binary,
conf->num_sgprs = MAX2(conf->num_sgprs, 
(G_00B028_SGPRS(value) + 1) * 8);
conf->num_vgprs = MAX2(conf->num_vgprs, 
(G_00B028_VGPRS(value) + 1) * 4);
conf->float_mode =  G_00B028_FLOAT_MODE(value);
-   conf->rsrc1 = value;
+   /* Disable IEEE mode. IEEE_MODE determines sNaN
+* handling by fmin/fmax instructions.
+* Nothing wants the IEEE rules here.
+* Ideally LLVM would not emit this configuration. */
+   conf->rsrc1 = value & C_00B848_IEEE_MODE;
break;
case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
conf->lds_size = MAX2(conf->lds_size, 
G_00B02C_EXTRA_LDS_SIZE(value));
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 05/29] intel/isl: Add a helper for inverting swizzles

2018-03-03 Thread Pohjolainen, Topi

On Thu, Mar 01, 2018 at 03:04:14PM -0800, Jason Ekstrand wrote:
> On Thu, Mar 1, 2018 at 6:49 AM, Pohjolainen, Topi <
> topi.pohjolai...@gmail.com> wrote:
> 
> > On Mon, Feb 26, 2018 at 08:42:42AM -0800, Jason Ekstrand wrote:
> > > On Mon, Feb 26, 2018 at 6:19 AM, Pohjolainen, Topi <
> > > topi.pohjolai...@gmail.com> wrote:
> > >
> > > > On Fri, Jan 26, 2018 at 05:59:34PM -0800, Jason Ekstrand wrote:
> > > > > ---
> > > > >  src/intel/isl/isl.c | 30 ++
> > > > >  src/intel/isl/isl.h |  2 ++
> > > > >  2 files changed, 32 insertions(+)
> > > > >
> > > > > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> > > > > index a2d3ae6..420d387 100644
> > > > > --- a/src/intel/isl/isl.c
> > > > > +++ b/src/intel/isl/isl.c
> > > > > @@ -2379,3 +2379,33 @@ isl_swizzle_compose(struct isl_swizzle first,
> > > > struct isl_swizzle second)
> > > > >.a = swizzle_select(first.a, second),
> > > > > };
> > > > >  }
> > > > > +
> > > > > +/**
> > > > > + * Returns a swizzle that is the pseudo-inverse of this swizzle.
> > > > > + */
> > > > > +struct isl_swizzle
> > > > > +isl_swizzle_invert(struct isl_swizzle swizzle)
> > > > > +{
> > > > > +   /* Default to zero for channels which do not show up in the
> > swizzle
> > > > */
> > > > > +   enum isl_channel_select chans[4] = {
> > > > > +  ISL_CHANNEL_SELECT_ZERO,
> > > > > +  ISL_CHANNEL_SELECT_ZERO,
> > > > > +  ISL_CHANNEL_SELECT_ZERO,
> > > > > +  ISL_CHANNEL_SELECT_ZERO,
> > > > > +   };
> > > > > +
> > > > > +   /* We go in ABGR order so that, if there are any duplicates, the
> > > > first one
> > > > > +* is taken if you look at it in RGBA order.  This is what
> > Haswell
> > > > hardware
> > > > > +* does for render target swizzles.
> > > > > +*/
> > > > > +   if ((unsigned)(swizzle.a - ISL_CHANNEL_SELECT_RED) < 4)
> > > > > +  chans[swizzle.a - ISL_CHANNEL_SELECT_RED] =
> > > > ISL_CHANNEL_SELECT_ALPHA;
> > > > > +   if ((unsigned)(swizzle.b - ISL_CHANNEL_SELECT_RED) < 4)
> > > > > +  chans[swizzle.b - ISL_CHANNEL_SELECT_RED] =
> > > > ISL_CHANNEL_SELECT_BLUE;
> > > > > +   if ((unsigned)(swizzle.g - ISL_CHANNEL_SELECT_RED) < 4)
> > > > > +  chans[swizzle.g - ISL_CHANNEL_SELECT_RED] =
> > > > ISL_CHANNEL_SELECT_GREEN;
> > > > > +   if ((unsigned)(swizzle.r - ISL_CHANNEL_SELECT_RED) < 4)
> > > > > +  chans[swizzle.r - ISL_CHANNEL_SELECT_RED] =
> > > > ISL_CHANNEL_SELECT_RED;
> > > > > +
> > > > > +   return (struct isl_swizzle) { chans[0], chans[1], chans[2],
> > chans[3]
> > > > };
> > > >
> > > > If given
> > > >
> > > > swizzle == { ISL_CHANNEL_SELECT_RED,
> > > >  ISL_CHANNEL_SELECT_GREEN,
> > > >  ISL_CHANNEL_SELECT_BLUE,
> > > >  ISL_CHANNEL_SELECT_ALPHA },
> > > >
> > > > then
> > > > chans[ISL_CHANNEL_SELECT_ALPHA - ISL_CHANNEL_SELECT_RED] ==
> > chans[3] ==
> > > > ISL_CHANNEL_SELECT_ALPHA
> > > >
> > > > and so on, and the function returns the same swizzle as given?
> > >
> > >
> > > Yes, that is how the subtraction works.
> >
> > I was expecting it to "invert" that, i.e., to return ABGR. But okay, if
> > given
> > identity swizzle it returns identity.
> >
> > In order to understand how it works I thought I read further the series to
> > find an example - there seems to be one in patch 12 and another in patch
> > 16.
> > In case of 16 and destination format B4G4R4A4 the swizzle looks to be BGRA
> > (looking at anv_formats.c::main_formats).
> >
> > In that case we get:
> >
> >chans[ALPHA - RED] = chans[3] = ALPHA
> >chans[RED   - RED] = chans[0] = BLUE
> >chans[GREEN - RED] = chans[1] = GREEN
> >chans[BLUE  - RED] = chans[2] = RED
> >
> > and as a swizzle BLUE, GREEN, RED, ALPHA. This is again the same as given.
> > What am I not understanding?
> >
> 
> I think the confusion is what "invert" means.  It doesn't mean we reverse
> the channels or anything like that.  It's an inverse in the sense that when
> you compose a swizzle with it's inverse, you get the identity back out.
> The inverse of BGRA is BGRA because if you apply the BGRA swizzle twice,
> you get RGBA again.  If you start with ARGB, you get
> 
> chans[BLUE - RED] = chans[2] = ALPHA
> chans[GREEN - RED] = chans[1] = BLUE
> chans[RED - RED] = chans[0] = GREEN
> chans[ALPHA - RED] = chans[3] = RED
> 
> This gives an inverse swizzle of GBAR which is certainly a weird swizzle.
> However, if you apply ARGB and then GBAR, you get back to identity since
> one is a left rotate and one is a right rotate.  Does that make a bit more
> sense?

Thanks again for taking the time to explain. That does makes sense per se.
But I'm still failing to understand its use in patch 16 - I guess that is
partly why I had trouble here. I tried to understand the meaning of "inverse"
via its use.
Looking patches 6 and 16, I'm seeing anvil giving blorp destination format
as ISL_FORMAT_A4B4G4R4_UNORM and swizzle as BGRA. In blorp blit I'm thinking
that blorp considers

Re: [Mesa-dev] [Mesa-stable] [PATCH] [RFC] gallivm: Use new LLVM fast-math-flags API

2018-03-03 Thread Marek Olšák

On Fri, Mar 2, 2018 at 1:38 PM, Emil Velikov  wrote:
> Hi Alex,
>
> On 28 February 2018 at 15:25, Alex Smith  wrote:
>> Hi,
>>
>> Could this (commit 5d61fa4e68b7eb6d481a37efdbb35fdce675a6ad on master) be
>> backported to the 17.3 branch to allow it to build with LLVM 6?
>>
> Normally we don't aim to support LLVM versions released after the .0
> Mesa release is out.
> Not that we don't want to - there is simply not enough testing happening.
>
> Sometimes picking the odd build fix is enough, but not always.
>
> As a matter of fact, the only feedback for the AMD drivers status
> (brokenness) is the LunarG testing rig.
>
> Michel, usually you are usually more realistic/conservative on with
> this kind of changes.

Are you saying that I'm less realistic? :)

Marek
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Re: [Mesa-dev] [PATCH kmscube v2] Detect gst_bo_map/_unmap and use it (or avoid it)

2018-03-03 Thread Rob Clark

On Fri, Mar 2, 2018 at 7:55 PM, Daniel Díaz Rodríguez
 wrote:
> Hello, Rob!
>
>
> On 14 July 2017 at 10:29, Daniel Díaz  wrote:
>> Those functions are not available on libMali, thus breaking
>> builds and creating havoc.
>>
>> Removing the specific parts of the code that deal with
>> gbm_bo_map() and gbm_bo_unmap() renders the kmscube utility
>> a little less useful, but still valuable.
>
> Last time we talked about this patch you mentioned you were hesitant
> and deciding whether to do this using this approach or at run time.
> Have you, by any chance, had any thoughts on this recently?

Hmm, would it work instead for kmscube to provide __weak versions of
those fxns that just return NULL?  (or exit(-1) or whatever?)

That way it is at least a runtime thing instead of a compile-time thing..

BR,
-R

> Greetings! See you soon.
>
> Daniel Díaz
> daniel.d...@linaro.org
>
>
>
>> Signed-off-by: Daniel Díaz 
>> Cc: Rob Clark 
>> Reviewed-by: Eric Engestrom 
>>
>> ---
>> v2: Formatting, add informational message.
>>
>>  Makefile.am   | 5 -
>>  configure.ac  | 3 +++
>>  gst-decoder.c | 7 ++-
>>  kmscube.c | 4 
>>  4 files changed, 17 insertions(+), 2 deletions(-)
>>
>> diff --git a/Makefile.am b/Makefile.am
>> index a36087d..ab4adbf 100644
>> --- a/Makefile.am
>> +++ b/Makefile.am
>> @@ -43,7 +43,6 @@ kmscube_SOURCES = \
>> common.c \
>> common.h \
>> cube-smooth.c \
>> -   cube-tex.c \
>> drm-atomic.c \
>> drm-common.c \
>> drm-common.h \
>> @@ -59,3 +58,7 @@ kmscube_LDADD += $(GST_LIBS)
>>  kmscube_CFLAGS += $(GST_CFLAGS)
>>  kmscube_SOURCES += cube-video.c gst-decoder.c
>>  endif
>> +
>> +if ENABLE_GBM_MAP
>> +kmscube_SOURCES += cube-tex.c
>> +endif
>> diff --git a/configure.ac b/configure.ac
>> index 8397f7b..c7f1f4d 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -65,5 +65,8 @@ if test "x$enable_gbm_modifiers" = xyes; then
>> AC_DEFINE(HAVE_GBM_MODIFIERS, 1, [Define if you can use GBM 
>> properties.])
>>  fi
>>
>> +AC_CHECK_LIB([gbm], [gbm_bo_map], [HAVE_GBM_BO_MAP=yes], [])
>> +AM_CONDITIONAL(ENABLE_GBM_MAP, [test "x$HAVE_GBM_BO_MAP" = "xyes"])
>> +
>>  AC_CONFIG_FILES([Makefile])
>>  AC_OUTPUT
>> diff --git a/gst-decoder.c b/gst-decoder.c
>> index 2d6d581..b84980e 100644
>> --- a/gst-decoder.c
>> +++ b/gst-decoder.c
>> @@ -332,6 +332,7 @@ set_last_frame(struct decoder *dec, EGLImage frame, 
>> GstSample *samp)
>> dec->last_samp = samp;
>>  }
>>
>> +#if HAVE_GBM_BO_MAP
>>  // TODO this could probably be a helper re-used by cube-tex:
>>  static int
>>  buf_to_fd(const struct gbm *gbm, int size, void *ptr)
>> @@ -357,6 +358,7 @@ buf_to_fd(const struct gbm *gbm, int size, void *ptr)
>>
>> return fd;
>>  }
>> +#endif
>>
>>  static EGLImage
>>  buffer_to_image(struct decoder *dec, GstBuffer *buf)
>> @@ -410,12 +412,15 @@ buffer_to_image(struct decoder *dec, GstBuffer *buf)
>>
>> if (is_dmabuf_mem) {
>> dmabuf_fd = dup(gst_dmabuf_memory_get_fd(mem));
>> -   } else {
>> +   }
>> +#if HAVE_GBM_BO_MAP
>> +   else {
>> GstMapInfo map_info;
>> gst_buffer_map(buf, _info, GST_MAP_READ);
>> dmabuf_fd = buf_to_fd(dec->gbm, map_info.size, 
>> map_info.data);
>> gst_buffer_unmap(buf, _info);
>> }
>> +#endif
>>
>> if (dmabuf_fd < 0) {
>> GST_ERROR("could not obtain DMABUF FD");
>> diff --git a/kmscube.c b/kmscube.c
>> index 3a2c4dd..276dc55 100644
>> --- a/kmscube.c
>> +++ b/kmscube.c
>> @@ -142,7 +142,11 @@ int main(int argc, char *argv[])
>> else if (mode == VIDEO)
>> egl = init_cube_video(gbm, video);
>> else
>> +#if HAVE_GBM_BO_MAP
>> egl = init_cube_tex(gbm, mode);
>> +#else
>> +   printf("gbm_bo_map() support missing\n");
>> +#endif
>>
>> if (!egl) {
>> printf("failed to initialize EGL\n");
>> --
>> 2.7.4
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[Mesa-dev] [PATCH] r600/egd_tables.py: make the script python 2+3 compatible

2018-03-03 Thread Stefan Dirsch

Patch by "Tomas Chvatal"  with modifications
by "Michal Srb"  to not break python 2.

https://bugzilla.suse.com/show_bug.cgi?id=1082303

v2:
- no longer try to encode a unicode
- make use of 'from __future__ import print_function', so semantics
  of print statements in python2 are closer to print functions in python3

https://lists.freedesktop.org/archives/mesa-dev/2018-February/187056.html

v3:
- convert bytes object to unicode in order to fix output with python3

https://lists.freedesktop.org/archives/mesa-dev/2018-March/187492.html

Signed-off-by: Stefan Dirsch 
Reviewed-by: Tomas Chvatal 
Reviewed-by: Dylan Baker 
Reviewed-by: Eric Engestrom 
---
 src/gallium/drivers/r600/egd_tables.py | 53 +-
 1 file changed, 27 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/r600/egd_tables.py 
b/src/gallium/drivers/r600/egd_tables.py
index d7b78c7fb1..2d37a5bcc9 100644
--- a/src/gallium/drivers/r600/egd_tables.py
+++ b/src/gallium/drivers/r600/egd_tables.py
@@ -1,3 +1,4 @@
+from __future__ import print_function
 
 CopyRight = '''
 /*
@@ -60,7 +61,7 @@ class StringTable:
 """
 fragments = [
 '"%s\\0" /* %s */' % (
-te[0].encode('string_escape'),
+te[0].encode('unicode_escape').decode('utf-8'),
 ', '.join(str(idx) for idx in te[2])
 )
 for te in self.table
@@ -217,10 +218,10 @@ def write_tables(regs, packets):
 strings = StringTable()
 strings_offsets = IntTable("int")
 
-print '/* This file is autogenerated by egd_tables.py from evergreend.h. 
Do not edit directly. */'
-print
-print CopyRight.strip()
-print '''
+print('/* This file is autogenerated by egd_tables.py from evergreend.h. 
Do not edit directly. */')
+print('')
+print(CopyRight.strip())
+print('''
 #ifndef EG_TABLES_H
 #define EG_TABLES_H
 
@@ -242,20 +243,20 @@ struct eg_packet3 {
 unsigned name_offset;
 unsigned op;
 };
-'''
+''')
 
-print 'static const struct eg_packet3 packet3_table[] = {'
+print('static const struct eg_packet3 packet3_table[] = {')
 for pkt in packets:
-print '\t{%s, %s},' % (strings.add(pkt[5:]), pkt)
-print '};'
-print
+print('\t{%s, %s},' % (strings.add(pkt[5:]), pkt))
+print('};')
+print('')
 
-print 'static const struct eg_field egd_fields_table[] = {'
+print('static const struct eg_field egd_fields_table[] = {')
 
 fields_idx = 0
 for reg in regs:
 if len(reg.fields) and reg.own_fields:
-print '\t/* %s */' % (fields_idx)
+print('\t/* %s */' % (fields_idx))
 
 reg.fields_idx = fields_idx
 
@@ -266,34 +267,34 @@ struct eg_packet3 {
 while value[1] >= len(values_offsets):
 values_offsets.append(-1)
 values_offsets[value[1]] = 
strings.add(strip_prefix(value[0]))
-print '\t{%s, %s(~0u), %s, %s},' % (
+print('\t{%s, %s(~0u), %s, %s},' % (
 strings.add(field.name), field.s_name,
-len(values_offsets), 
strings_offsets.add(values_offsets))
+len(values_offsets), 
strings_offsets.add(values_offsets)))
 else:
-print '\t{%s, %s(~0u)},' % (strings.add(field.name), 
field.s_name)
+print('\t{%s, %s(~0u)},' % (strings.add(field.name), 
field.s_name))
 fields_idx += 1
 
-print '};'
-print
+print('};')
+print('')
 
-print 'static const struct eg_reg egd_reg_table[] = {'
+print('static const struct eg_reg egd_reg_table[] = {')
 for reg in regs:
 if len(reg.fields):
-print '\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
-len(reg.fields), reg.fields_idx if reg.own_fields else 
reg.fields_owner.fields_idx)
+print('\t{%s, %s, %s, %s},' % (strings.add(reg.name), reg.r_name,
+len(reg.fields), reg.fields_idx if reg.own_fields else 
reg.fields_owner.fields_idx))
 else:
-print '\t{%s, %s},' % (strings.add(reg.name), reg.r_name)
-print '};'
-print
+print('\t{%s, %s},' % (strings.add(reg.name), reg.r_name))
+print('};')
+print('')
 
 strings.emit(sys.stdout, "egd_strings")
 
-print
+print('')
 
 strings_offsets.emit(sys.stdout, "egd_strings_offsets")
 
-print
-print '#endif'
+print('')
+print('#endif')
 
 
 def main():
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 08/29] nir/format_convert: Add linear <-> sRGB helpers

Re: [Mesa-dev] [PATCH 07/29] nir: Add the start of a format conversion helper header

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

[Mesa-dev] [PATCH RFC] radeonsi: Disable IEEE_MODE.

Re: [Mesa-dev] [PATCH 05/29] intel/isl: Add a helper for inverting swizzles

Re: [Mesa-dev] [Mesa-stable] [PATCH] [RFC] gallivm: Use new LLVM fast-math-flags API

Re: [Mesa-dev] [PATCH kmscube v2] Detect gst_bo_map/_unmap and use it (or avoid it)

[Mesa-dev] [PATCH] r600/egd_tables.py: make the script python 2+3 compatible

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