Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

[Pohjolainen, Topi]

On Thu, Apr 05, 2018 at 04:11:33PM -0700, Nanley Chery wrote:
> On Wed, Apr 04, 2018 at 07:40:43AM +0300, Pohjolainen, Topi wrote:
> > On Tue, Apr 03, 2018 at 09:38:52PM -0700, Jason Ekstrand wrote:
> > > On Tue, Apr 3, 2018 at 8:23 PM, Pohjolainen, Topi <
> > > topi.pohjolai...@gmail.com> wrote:
> > > 
> > > > On Tue, Apr 03, 2018 at 02:55:31PM -0700, Jason Ekstrand wrote:
> > > > > On Tue, Apr 3, 2018 at 8:05 AM, Pohjolainen, Topi <
> > > > > topi.pohjolai...@gmail.com> wrote:
> > > > >
> > > > > > On Thu, Mar 29, 2018 at 10:58:40AM -0700, Rafael Antognolli wrote:
> > > > > > > gen10 can emit the clear color by setting it on a buffer 
> > > > > > > somewhere,
> > > > and
> > > > > > > then adding only the address to the surface state.
> > > > > > >
> > > > > > > This commit add support for that on isl_surf_fill_state, and if 
> > > > > > > that
> > > > is
> > > > > > > requested, skip setting the clear value itself.
> > > > > > >
> > > > > > > v2: Add assert to make sure we are at least on gen10.
> > > > > > >
> > > > > > > Signed-off-by: Rafael Antognolli 
> > > > > > > Reviewed-by: Jordan Justen 
> > > > > > > ---
> > > > > > >  src/intel/isl/isl.h   |  9 +
> > > > > > >  src/intel/isl/isl_surface_state.c | 18 ++
> > > > > > >  2 files changed, 23 insertions(+), 4 deletions(-)
> > > > > > >
> > > > > > > diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> > > > > > > index 2edf0522e32..c50b78d4701 100644
> > > > > > > --- a/src/intel/isl/isl.h
> > > > > > > +++ b/src/intel/isl/isl.h
> > > > > > > @@ -1307,6 +1307,15 @@ struct isl_surf_fill_state_info {
> > > > > > >  */
> > > > > > > union isl_color_value clear_color;
> > > > > > >
> > > > > > > +   /**
> > > > > > > +* Send only the clear value address
> > > > > > > +*
> > > > > > > +* If set, we only pass the clear address to the GPU and it 
> > > > > > > will
> > > > > > fetch it
> > > > > > > +* from wherever it is.
> > > > > > > +*/
> > > > > > > +   bool use_clear_address;
> > > > > > > +   uint64_t clear_address;
> > > > > > > +
> > > > > > > /**
> > > > > > >  * Surface write disables for gen4-5
> > > > > > >  */
> > > > > > > diff --git a/src/intel/isl/isl_surface_state.c
> > > > > > b/src/intel/isl/isl_surface_state.c
> > > > > > > index 32a5429f2bf..bff9693f02d 100644
> > > > > > > --- a/src/intel/isl/isl_surface_state.c
> > > > > > > +++ b/src/intel/isl/isl_surface_state.c
> > > > > > > @@ -637,11 +637,21 @@ isl_genX(surf_fill_state_s)(const struct
> > > > > > isl_device *dev, void *state,
> > > > > > >  #endif
> > > > > > >
> > > > > > > if (info->aux_usage != ISL_AUX_USAGE_NONE) {
> > > > > > > +  if (info->use_clear_address) {
> > > > > > > +#if GEN_GEN >= 10
> > > > > > > + s.ClearValueAddressEnable = true;
> > > > > >
> > > > > > This will set it for multisampled also and upset piglit tests. We 
> > > > > > need
> > > > > > something of this sort:
> > > > > >
> > > > > > s.ClearValueAddressEnable = info->aux_usage !=
> > > > > > ISL_AUX_USAGE_MCS;
> > > > > >
> > > > >
> > > > > Can we assert instead?  If the caller asks for a clear address to be 
> > > > > set
> > > > > they should get it and not have it magically disabled when they ask 
> > > > > for
> > > > MCS.
> > > >
> > > > Right, here an assert would be just fine. I should have made the comment
> > > > in patch in 19 where it belongs. There we start setting the flag
> > > > unconditionally for "info->aux_usage != ISL_AUX_USAGE_NONE". If we 
> > > > don't,
> > > > then on ICL we start failing multisampling tests.
> > > >
> > > 
> > > Is this a known hardware restriction or is there just something weird 
> > > going
> > > on with MCS?
> > 
> > Bspec says the clear address is only for CCS_D and CCS_E. And setting it for
> > MCS seems to upset both the simulator and hardware. At least with
> > 
> > ext_framebuffer_multisample-accuracy 2 color
> > 
> 
> Could you help me find the Bspec restriction?
> 
> The Bspec says that the clear address exists for
> 
> [Auxiliary Surface Mode] == 'AUX_CCS_D' OR
> [Auxiliary Surface Mode] == 'AUX_CCS_E'
> 
> In the definition of Auxiliary Surface Mode, it states that AUX_CCS_* is
> equal to MCS if the sample count > 1.

Right you are, I keep forgetting that CCS_D/CCS_E stands for MCS when
sample count > 1. So it should work for multisampled surfaces as well. Looks
like there is more debugging for me to do to understand why the tests start
failing on ICL if clear color address is enabled for MCS surface. Thanks for
reading it more carefully than I did!

> 
> -Nanley
> 
> > > 
> > > 
> > > > >
> > > > >
> > > > > > > + s.ClearValueAddress = info->clear_address;
> > > > > > > +#else
> > > > > > > + unreachable("Gen9 and earlier do not support indirect 
> > > > > > > clear
> > > > > > colors");
> > > > > > > +#endif
> > > > > > > +  }
> > > > > > >  #if GEN_GEN >= 9
> 

[Mesa-dev] [Bug 105918] Mesa 18.0.0-2 video color issues and distorted video with system hang on restart (Apple Mac Pro 6, 1 with AMD D300 GPUs)

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105918

Bug ID: 105918
   Summary: Mesa 18.0.0-2 video color issues and distorted video
with system hang on restart (Apple Mac Pro 6,1 with
AMD D300 GPUs)
   Product: Mesa
   Version: unspecified
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Mesa core
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: c...@fuckyouprius.com
QA Contact: mesa-dev@lists.freedesktop.org

Apple Mac Pro 6,1 (black trash can) with dual AMD D300 GPUs has improper video
color (e.g., all terminals whether vte based or not [tested termite and
alacritty which uses the GPU], black background is instead blue, window title
bar text is very difficult to read, almost white on white using Adwaita theme
under i3wm) or will distort video with distorted rectangles upon reboot attempt
(cannot use MagicSysKey and REISUB as it appears hard locked).

This happened originally with amdgpu, kernel 4.15.15, Arch Linux after a full
(not partial) system update when Mesa 18.0.0-2 hit the main repos.

Tried switching to kernel 4.14.x, no change. Tried vanilla and zen kernels, no
change.

Tried changing from amdgpu to radeon along with various kernels, no change.

Went back to amdgpu, downgraded the following (all at once since they were in
the batch of updates that caused the issue) to 17.3.7-1 and normal video has
been restored: mesa, mesa-vdpau, libva-mesa-driver, lib32-libva-mesa-driver,
lib32-mesa, lib32-mesa-vdpau, lib32-vulkan-radeon, opencl-mesa and
vulkan-radeon.

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Re: [Mesa-dev] [PATCH] anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS

[Nanley Chery]

On Thu, Apr 05, 2018 at 10:51:21AM -0700, Jason Ekstrand wrote:
> ping?
> 

I haven't yet gotten around to seeing how the users of the modifier API
would use the newly-exposed CCS surface, but all the changes within anv
look good to me. 

This patch is
Acked-by: Nanley Chery 



> On Wed, Feb 21, 2018 at 11:17 AM, Jason Ekstrand 
> wrote:
> 
> > v2 (Jason Ekstrand):
> >  - Return the correct enum values from anv_layout_to_fast_clear_type
> >
> > v3 (Jason Ekstrand):
> >  - Always return ANV_FAST_CLEAR_NONE and leave doing the right thing for
> >the patch which adds a modifier which supports fast-clears.
> > ---
> >  src/intel/vulkan/anv_formats.c |  9 
> >  src/intel/vulkan/anv_image.c   | 50 ++
> > 
> >  2 files changed, 40 insertions(+), 19 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> > formats.c
> > index 9c52ad5..3c17366 100644
> > --- a/src/intel/vulkan/anv_formats.c
> > +++ b/src/intel/vulkan/anv_formats.c
> > @@ -671,9 +671,18 @@ get_wsi_format_modifier_properties_list(const struct
> > anv_physical_device *physic
> >DRM_FORMAT_MOD_LINEAR,
> >I915_FORMAT_MOD_X_TILED,
> >I915_FORMAT_MOD_Y_TILED,
> > +  I915_FORMAT_MOD_Y_TILED_CCS,
> > };
> >
> > for (uint32_t i = 0; i < ARRAY_SIZE(modifiers); i++) {
> > +  const struct isl_drm_modifier_info *mod_info =
> > + isl_drm_modifier_get_info(modifiers[i]);
> > +
> > +  if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E &&
> > +  !isl_format_supports_ccs_e(_device->info,
> > + anv_format->planes[0].isl_format))
> > + continue;
> > +
> >vk_outarray_append(, mod_props) {
> >   mod_props->modifier = modifiers[i];
> >   if (isl_drm_modifier_has_aux(modifiers[i]))
> > diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> > index a2bae7b..9897e58 100644
> > --- a/src/intel/vulkan/anv_image.c
> > +++ b/src/intel/vulkan/anv_image.c
> > @@ -515,6 +515,7 @@ score_drm_format_mod(uint64_t modifier)
> > case DRM_FORMAT_MOD_LINEAR: return 1;
> > case I915_FORMAT_MOD_X_TILED: return 2;
> > case I915_FORMAT_MOD_Y_TILED: return 3;
> > +   case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
> > default: unreachable("bad DRM format modifier");
> > }
> >  }
> > @@ -746,8 +747,14 @@ void anv_GetImageSubresourceLayout(
> >  VkSubresourceLayout*layout)
> >  {
> > ANV_FROM_HANDLE(anv_image, image, _image);
> > -   const struct anv_surface *surface =
> > -  get_surface(image, subresource->aspectMask);
> > +
> > +   const struct anv_surface *surface;
> > +   if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT_KHR &&
> > +   image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
> > +   isl_drm_modifier_has_aux(image->drm_format_mod))
> > +  surface = >planes[0].aux_surface;
> > +   else
> > +  surface = get_surface(image, subresource->aspectMask);
> >
> > assert(__builtin_popcount(subresource->aspectMask) == 1);
> >
> > @@ -862,25 +869,20 @@ anv_layout_to_aux_usage(const struct gen_device_info
> > * const devinfo,
> >}
> >
> >
> > -   case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
> > +   case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
> >assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> >
> > -  /* On SKL+, the render buffer can be decompressed by the
> > presentation
> > -   * engine. Support for this feature has not yet landed in the wider
> > -   * ecosystem. TODO: Update this code when support lands.
> > -   *
> > -   * From the BDW PRM, Vol 7, Render Target Resolve:
> > -   *
> > -   *If the MCS is enabled on a non-multisampled render target, the
> > -   *render target must be resolved before being used for other
> > -   *purposes (display, texture, CPU lock) The clear value from
> > -   *SURFACE_STATE is written into pixels in the render target
> > -   *indicated as clear in the MCS.
> > -   *
> > -   * Pre-SKL, the render buffer must be resolved before being used for
> > -   * presentation. We can infer that the auxiliary buffer is not used.
> > +  /* When handing the image off to the presentation engine, we need to
> > +   * ensure that things are properly resolved.  For images with no
> > +   * modifier, we assume that they follow the old rules and always
> > need
> > +   * a full resolve because the PE doesn't understand any form of
> > +   * compression.  For images with modifiers, we use the aux usage
> > from
> > +   * the modifier.
> > */
> > -  return ISL_AUX_USAGE_NONE;
> > +  const struct isl_drm_modifier_info *mod_info =
> > + isl_drm_modifier_get_info(image->drm_format_mod);
> > +  return mod_info ? mod_info->aux_usage : ISL_AUX_USAGE_NONE;
> > +   }
> >
> >
> > /* Rendering 

[Mesa-dev] [Bug 105904] Needed to delete mesa shader cache after driver upgrade for 32 bit wine vulkan programs to work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105904

Timothy Arceri  changed:

   What|Removed |Added

 Status|NEW |NEEDINFO

--- Comment #1 from Timothy Arceri  ---
(In reply to Snubb from comment #0)
> After driver update to 18.1~git1804050730.8cd58d~oibaf~b from oibafs ubuntu
> repo my 32 bit game that i run with dxvk stopped working.
> I tried 64 bit cube.exe from LunarG VulkanSDK which worked, 32 bit cube.exe
> from the same SDK didn't work.
> 
> Manually deleting shader cache made 32 bit cube.exe and game running with
> dxvk work.

Can you be more specific about what stopped working means? Did the game have
corruptions? Was is crashing on start-up?

And just to be clear you deleted ~/.cache/mesa_shader_cache/ ?

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Re: [Mesa-dev] [PATCH v5 06/19] intel/isl: Add support to emit clear value address.

[Nanley Chery]

On Wed, Apr 04, 2018 at 07:40:43AM +0300, Pohjolainen, Topi wrote:
> On Tue, Apr 03, 2018 at 09:38:52PM -0700, Jason Ekstrand wrote:
> > On Tue, Apr 3, 2018 at 8:23 PM, Pohjolainen, Topi <
> > topi.pohjolai...@gmail.com> wrote:
> > 
> > > On Tue, Apr 03, 2018 at 02:55:31PM -0700, Jason Ekstrand wrote:
> > > > On Tue, Apr 3, 2018 at 8:05 AM, Pohjolainen, Topi <
> > > > topi.pohjolai...@gmail.com> wrote:
> > > >
> > > > > On Thu, Mar 29, 2018 at 10:58:40AM -0700, Rafael Antognolli wrote:
> > > > > > gen10 can emit the clear color by setting it on a buffer somewhere,
> > > and
> > > > > > then adding only the address to the surface state.
> > > > > >
> > > > > > This commit add support for that on isl_surf_fill_state, and if that
> > > is
> > > > > > requested, skip setting the clear value itself.
> > > > > >
> > > > > > v2: Add assert to make sure we are at least on gen10.
> > > > > >
> > > > > > Signed-off-by: Rafael Antognolli 
> > > > > > Reviewed-by: Jordan Justen 
> > > > > > ---
> > > > > >  src/intel/isl/isl.h   |  9 +
> > > > > >  src/intel/isl/isl_surface_state.c | 18 ++
> > > > > >  2 files changed, 23 insertions(+), 4 deletions(-)
> > > > > >
> > > > > > diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
> > > > > > index 2edf0522e32..c50b78d4701 100644
> > > > > > --- a/src/intel/isl/isl.h
> > > > > > +++ b/src/intel/isl/isl.h
> > > > > > @@ -1307,6 +1307,15 @@ struct isl_surf_fill_state_info {
> > > > > >  */
> > > > > > union isl_color_value clear_color;
> > > > > >
> > > > > > +   /**
> > > > > > +* Send only the clear value address
> > > > > > +*
> > > > > > +* If set, we only pass the clear address to the GPU and it will
> > > > > fetch it
> > > > > > +* from wherever it is.
> > > > > > +*/
> > > > > > +   bool use_clear_address;
> > > > > > +   uint64_t clear_address;
> > > > > > +
> > > > > > /**
> > > > > >  * Surface write disables for gen4-5
> > > > > >  */
> > > > > > diff --git a/src/intel/isl/isl_surface_state.c
> > > > > b/src/intel/isl/isl_surface_state.c
> > > > > > index 32a5429f2bf..bff9693f02d 100644
> > > > > > --- a/src/intel/isl/isl_surface_state.c
> > > > > > +++ b/src/intel/isl/isl_surface_state.c
> > > > > > @@ -637,11 +637,21 @@ isl_genX(surf_fill_state_s)(const struct
> > > > > isl_device *dev, void *state,
> > > > > >  #endif
> > > > > >
> > > > > > if (info->aux_usage != ISL_AUX_USAGE_NONE) {
> > > > > > +  if (info->use_clear_address) {
> > > > > > +#if GEN_GEN >= 10
> > > > > > + s.ClearValueAddressEnable = true;
> > > > >
> > > > > This will set it for multisampled also and upset piglit tests. We need
> > > > > something of this sort:
> > > > >
> > > > > s.ClearValueAddressEnable = info->aux_usage !=
> > > > > ISL_AUX_USAGE_MCS;
> > > > >
> > > >
> > > > Can we assert instead?  If the caller asks for a clear address to be set
> > > > they should get it and not have it magically disabled when they ask for
> > > MCS.
> > >
> > > Right, here an assert would be just fine. I should have made the comment
> > > in patch in 19 where it belongs. There we start setting the flag
> > > unconditionally for "info->aux_usage != ISL_AUX_USAGE_NONE". If we don't,
> > > then on ICL we start failing multisampling tests.
> > >
> > 
> > Is this a known hardware restriction or is there just something weird going
> > on with MCS?
> 
> Bspec says the clear address is only for CCS_D and CCS_E. And setting it for
> MCS seems to upset both the simulator and hardware. At least with
> 
> ext_framebuffer_multisample-accuracy 2 color
> 

Could you help me find the Bspec restriction?

The Bspec says that the clear address exists for

[Auxiliary Surface Mode] == 'AUX_CCS_D' OR
[Auxiliary Surface Mode] == 'AUX_CCS_E'

In the definition of Auxiliary Surface Mode, it states that AUX_CCS_* is
equal to MCS if the sample count > 1.

-Nanley

> > 
> > 
> > > >
> > > >
> > > > > > + s.ClearValueAddress = info->clear_address;
> > > > > > +#else
> > > > > > + unreachable("Gen9 and earlier do not support indirect 
> > > > > > clear
> > > > > colors");
> > > > > > +#endif
> > > > > > +  }
> > > > > >  #if GEN_GEN >= 9
> > > > > > -  s.RedClearColor = info->clear_color.u32[0];
> > > > > > -  s.GreenClearColor = info->clear_color.u32[1];
> > > > > > -  s.BlueClearColor = info->clear_color.u32[2];
> > > > > > -  s.AlphaClearColor = info->clear_color.u32[3];
> > > > > > +  if (!info->use_clear_address) {
> > > > > > + s.RedClearColor = info->clear_color.u32[0];
> > > > > > + s.GreenClearColor = info->clear_color.u32[1];
> > > > > > + s.BlueClearColor = info->clear_color.u32[2];
> > > > > > + s.AlphaClearColor = info->clear_color.u32[3];
> > > > > > +  }
> > > > > >  #elif GEN_GEN >= 7
> > > > > >/* Prior to Sky Lake, we only have one bit for the clear 
> > > > > > 

Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

[Laura Ekstrand]

So I spoke with Daniel Stone today about the infrastructure.  He estimates
it will be ready to deploy the website in 2-3 weeks, at the most.  So I'd
say the infrastructure will be there when we are ready.

In the new system, our website will be running in its own container managed
by freedesktop's new Gitlab server. So what we need to do for the deploy is:

1.  Fork mesa into a repo on Gitlab.com (https://gitlab.freedesktop.org).
2.  Create a .gitlab-ci.yml file which compiles the website from the files.
(https://docs.gitlab.com/ee/ci/yaml/).

In order to get the files ready, we need to make sure that they are rebased
on top of Mesa master and reviewed.  I started rebasing here:
https://cgit.freedesktop.org/~ldeks/mesa?h=website2.  That preserves the
git history well, but if it's not a big deal to everyone else, we could
just rebase Jean's branch.  I don't think much has changed.

Thanks.

Laura

On Thu, Apr 5, 2018 at 11:18 AM, Emil Velikov 
wrote:

> On 5 April 2018 at 19:10, Laura Ekstrand  wrote:
> > Emil,
> >
> > Specifically, what infrastructure do you need?  Gallium is already
> carrying
> > Sphinx around as a dependency.
> >
> The gallium docs are hosted on readthedocs.org. And I doubt we want to
> move the main mesa3d.org website there ;-)
> Currently mesa3d.org, most graphics stuff and others are on
> freedesktop.org infrastructure.
>
> HTH
> Emil
> P.S. Can I buy you to use interleaved posting/plain text email, please?
>
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Re: [Mesa-dev] [PATCH 17/17] winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE

[Dieter Nützel]

I've run v2 series yesterday, before the 'Mega cleanup' landed through

glmark2, UH, UV, Blender, FreeCAD, Krita 4.0.0 under KDE Plasma5

on my Polaris 20 / RX580.

With UH and UV I've saw little corruption (flickering) of the 'fps 
counter' in the upper right corner and during 'Benchmark' the 
'Benchmark...' string was somewhat corrupted, too. The right side of 
this text string was flickering. Like there is a big wrongly overlayed 
triangle.


Other than that, series is

Tested-by: Dieter Nützel 

Dieter

Am 04.04.2018 03:59, schrieb Marek Olšák:

From: Marek Olšák 

There is a kernel patch that adds the new flag.
---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 36 
++-

 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a3feeb93026..eb050b8fdb2 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -26,20 +26,24 @@
  * of the Software.
  */

 #include "amdgpu_cs.h"
 #include "util/os_time.h"
 #include 
 #include 

 #include "amd/common/sid.h"

+#ifndef AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE
+#define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
+#endif
+
 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", false)

 /* FENCES */

 static struct pipe_fence_handle *
 amdgpu_fence_create(struct amdgpu_ctx *ctx, unsigned ip_type,
 unsigned ip_instance, unsigned ring)
 {
struct amdgpu_fence *fence = CALLOC_STRUCT(amdgpu_fence);

@@ -801,56 +805,68 @@ static void amdgpu_set_ib_size(struct amdgpu_ib 
*ib)

 }

 static void amdgpu_ib_finalize(struct amdgpu_winsys *ws, struct 
amdgpu_ib *ib)

 {
amdgpu_set_ib_size(ib);
ib->used_ib_space += ib->base.current.cdw * 4;
ib->used_ib_space = align(ib->used_ib_space, 
ws->info.ib_start_alignment);

ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw +
ib->base.current.cdw);
 }

-static bool amdgpu_init_cs_context(struct amdgpu_cs_context *cs,
+static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
+   struct amdgpu_cs_context *cs,
enum ring_type ring_type)
 {
switch (ring_type) {
case RING_DMA:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_DMA;
   break;

case RING_UVD:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
   break;

case RING_UVD_ENC:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
   break;

case RING_VCE:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
   break;

-   case RING_COMPUTE:
-  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_COMPUTE;
-  break;
-
case RING_VCN_DEC:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_DEC;
   break;

-  case RING_VCN_ENC:
+   case RING_VCN_ENC:
   cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
   break;

-   default:
+   case RING_COMPUTE:
case RING_GFX:
-  cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_GFX;
+  cs->ib[IB_MAIN].ip_type = ring_type == RING_GFX ? 
AMDGPU_HW_IP_GFX :
+
AMDGPU_HW_IP_COMPUTE;

+
+  /* The kernel shouldn't invalidate L2 and vL1. The proper place 
for cache
+   * invalidation is the beginning of IBs (the previous commit 
does that),

+   * because completion of an IB doesn't care about the state of
GPU caches,
+   * but the beginning of an IB does. Draw calls from multiple IBs 
can be

+   * executed in parallel, so draw calls from the current IB can
finish after
+   * the next IB starts drawing, and so the cache flush at the end 
of IB

+   * is always late.
+   */
+  if (ws->info.drm_minor >= 26)
+ cs->ib[IB_MAIN].flags = AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE;
   break;
+
+   default:
+  assert(0);
}

memset(cs->buffer_indices_hashlist, -1,
sizeof(cs->buffer_indices_hashlist));
cs->last_added_bo = NULL;
return true;
 }

 static void amdgpu_cs_context_cleanup(struct amdgpu_cs_context *cs)
 {
unsigned i;
@@ -918,26 +934,26 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
cs->flush_data = flush_ctx;
cs->ring_type = ring_type;

struct amdgpu_cs_fence_info fence_info;
fence_info.handle = cs->ctx->user_fence_bo;
fence_info.offset = cs->ring_type;
amdgpu_cs_chunk_fence_info_to_data(_info, 
(void*)>fence_chunk);


cs->main.ib_type = IB_MAIN;

-   if (!amdgpu_init_cs_context(>csc1, ring_type)) {
+   if (!amdgpu_init_cs_context(ctx->ws, >csc1, ring_type)) {
   FREE(cs);
   return NULL;
}

-   if (!amdgpu_init_cs_context(>csc2, ring_type)) {
+   if (!amdgpu_init_cs_context(ctx->ws, >csc2, ring_type)) {
   amdgpu_destroy_cs_context(>csc1);
   FREE(cs);
   return NULL;
}

/* Set the first submission context as current. */
cs->csc = >csc1;
cs->cst = >csc2;

if (!amdgpu_get_new_ib(>ws->base, cs, IB_MAIN)) 

[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105567

--- Comment #9 from Dylan Baker  ---
Your command looks fine, I was just wondering if you had set dri-drivers-path
to an absolute or relative path, in the default case it will be relative, which
may explain why it's failing.

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[Mesa-dev] [PATCH v2 12/12] meson: build graw tests

[Dylan Baker]

This only enables the null and xlib target, so no windows support yet.

Signed-off-by: Dylan Baker 
---
 src/gallium/meson.build   |  4 +++-
 src/gallium/targets/graw-null/meson.build | 34 +++-
 src/gallium/targets/graw-xlib/meson.build | 33 ++-
 src/gallium/tests/graw/meson.build| 36 -
 src/gallium/tests/meson.build |  1 +-
 5 files changed, 108 insertions(+)
 create mode 100644 src/gallium/targets/graw-null/meson.build
 create mode 100644 src/gallium/targets/graw-xlib/meson.build
 create mode 100644 src/gallium/tests/graw/meson.build

diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index 828f6ab..6ac37a2 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -197,5 +197,9 @@ if with_gallium_st_nine
   subdir('targets/d3dadapter9')
 endif
 if with_tests
+  subdir('targets/graw-null')
+  if with_glx == 'gallium-xlib'
+subdir('targets/graw-xlib')
+  endif
   subdir('tests')
 endif
diff --git a/src/gallium/targets/graw-null/meson.build 
b/src/gallium/targets/graw-null/meson.build
new file mode 100644
index 000..8a294f4
--- /dev/null
+++ b/src/gallium/targets/graw-null/meson.build
@@ -0,0 +1,34 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+libgraw_util = static_library(
+  'graw_util',
+  ['graw_util.c'],
+  include_directories : inc_common,
+)
+
+libgraw_null = shared_library(
+  'graw_null',
+  ['graw_null.c'],
+  include_directories : inc_common,
+  link_with : [libmesa_util, libgallium],
+)
+
+libgraw = libgraw_null
diff --git a/src/gallium/targets/graw-xlib/meson.build 
b/src/gallium/targets/graw-xlib/meson.build
new file mode 100644
index 000..4716c54
--- /dev/null
+++ b/src/gallium/targets/graw-xlib/meson.build
@@ -0,0 +1,33 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+libgraw_xlib = shared_library(
+  'graw_xlib',
+  ['graw_xlib.c'],
+  c_args : ['-DGALLIUM_TRACE', '-DGALLIUM_RBUG'],
+  include_directories : [inc_common, inc_gallium_drivers, inc_gallium_winsys],
+  link_with : [
+libgraw_util, libtrace, librbug, libmesa_util, libgallium, libws_xlib
+  ],
+  dependencies : [dep_thread, driver_swrast],
+  version : '1.0',
+)
+
+libgraw = libgraw_xlib
diff --git a/src/gallium/tests/graw/meson.build 
b/src/gallium/tests/graw/meson.build
new file mode 100644
index 000..fd416c1
--- /dev/null
+++ b/src/gallium/tests/graw/meson.build
@@ -0,0 +1,36 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to 

[Mesa-dev] [PATCH v2 11/12] meson: build tests for gallium mesa state tracker

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/mesa/state_tracker/tests/meson.build | 40 +-
 src/meson.build  |  3 ++-
 2 files changed, 43 insertions(+)
 create mode 100644 src/mesa/state_tracker/tests/meson.build

diff --git a/src/mesa/state_tracker/tests/meson.build 
b/src/mesa/state_tracker/tests/meson.build
new file mode 100644
index 000..f62039e
--- /dev/null
+++ b/src/mesa/state_tracker/tests/meson.build
@@ -0,0 +1,40 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+libmesa_st_test_common = static_library(
+  'mesa_st_test_common',
+  ['st_tests_common.cpp', ir_expression_operation_h],
+  include_directories : inc_common,
+  dependencies : dep_thread,
+)
+
+test(
+  'st_renumerate_test',
+  executable(
+'st_renumerate_test',
+['test_glsl_to_tgsi_lifetime.cpp', ir_expression_operation_h],
+include_directories : inc_common,
+link_with : [
+  libmesa_st_test_common, libmesa_gallium, libglapi, libgallium,
+  libmesa_util,
+],
+dependencies : [idep_gtest, dep_thread, dep_llvm]
+  )
+)
diff --git a/src/meson.build b/src/meson.build
index 1900527..03b0656 100644
--- a/src/meson.build
+++ b/src/meson.build
@@ -80,6 +80,9 @@ if with_egl
 endif
 if with_gallium
   subdir('gallium')
+  # This has to be here since it requires libgallium, and subdir cannot
+  # contains ..
+  subdir('mesa/state_tracker/tests')
 endif
 
 # This must be after at least mesa, glx, and gallium, since libgl will be
-- 
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[Mesa-dev] [PATCH v2 04/12] meson: enable optimization-test

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/tests/meson.build | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/compiler/glsl/tests/meson.build 
b/src/compiler/glsl/tests/meson.build
index 040b257..fc7b863 100644
--- a/src/compiler/glsl/tests/meson.build
+++ b/src/compiler/glsl/tests/meson.build
@@ -92,3 +92,8 @@ test(
 ),
   ],
 )
+test(
+  'glsl optimization',
+  find_program('optimization_test.py'),
+  args : ['--test-runner', glsl_test],
+)
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[Mesa-dev] [PATCH v2 07/12] meson: enable glcpp test

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/glcpp/meson.build | 18 +-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/glcpp/meson.build 
b/src/compiler/glsl/glcpp/meson.build
index 03b43b9..e6a3dc8 100644
--- a/src/compiler/glsl/glcpp/meson.build
+++ b/src/compiler/glsl/glcpp/meson.build
@@ -55,4 +55,20 @@ glcpp = executable(
   build_by_default : false,
 )
 
-# TODO: figure out how to make all of these tests work.
+if with_tests
+  modes = ['unix', 'windows', 'oldmac', 'bizarro']
+  if dep_valgrind != [] and dep_valgrind.found()
+modes += ['valgrind']
+  endif
+
+  foreach m : modes
+test(
+  'glcpp test (@0@)'.format(m),
+  find_program('tests/glcpp_test.py'),
+  args : [
+glcpp, join_paths(meson.current_source_dir(), 'tests'),
+'--@0@'.format(m),
+  ],
+)
+  endforeach
+endif
-- 
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[Mesa-dev] [PATCH v2 09/12] meson: Build gallium trivial tests

[Dylan Baker]

Signed-off-by: Dylan Baker 
Reviewed-by: Eric Anholt 
---
 meson.build   |  2 +--
 src/gallium/meson.build   |  6 --
 src/gallium/tests/meson.build | 21 -
 src/gallium/tests/trivial/meson.build | 29 -
 4 files changed, 54 insertions(+), 4 deletions(-)
 create mode 100644 src/gallium/tests/meson.build
 create mode 100644 src/gallium/tests/trivial/meson.build

diff --git a/meson.build b/meson.build
index ee2b415..c98c4ae 100644
--- a/meson.build
+++ b/meson.build
@@ -1302,8 +1302,6 @@ else
   dep_lmsensors = []
 endif
 
-# TODO: gallium tests
-
 # TODO: various libdirs
 
 # TODO: gallium driver dirs
diff --git a/src/gallium/meson.build b/src/gallium/meson.build
index c9bfc0b..828f6ab 100644
--- a/src/gallium/meson.build
+++ b/src/gallium/meson.build
@@ -1,5 +1,5 @@
 # Copyright © 2017 Dylan Baker
-# Copyright © 2017 Intel Corporation
+# Copyright © 2017-2018 Intel Corporation
 
 # Permission is hereby granted, free of charge, to any person obtaining a copy
 # of this software and associated documentation files (the "Software"), to deal
@@ -196,4 +196,6 @@ if with_gallium_st_nine
   subdir('state_trackers/nine')
   subdir('targets/d3dadapter9')
 endif
-# TODO: tests
+if with_tests
+  subdir('tests')
+endif
diff --git a/src/gallium/tests/meson.build b/src/gallium/tests/meson.build
new file mode 100644
index 000..1779874
--- /dev/null
+++ b/src/gallium/tests/meson.build
@@ -0,0 +1,21 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+subdir('trivial')
diff --git a/src/gallium/tests/trivial/meson.build 
b/src/gallium/tests/trivial/meson.build
new file mode 100644
index 000..bbb2551
--- /dev/null
+++ b/src/gallium/tests/trivial/meson.build
@@ -0,0 +1,29 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+foreach t : ['compute', 'tri', 'quad-tex']
+  executable(
+t,
+'@0@.c'.format(t),
+include_directories : inc_common,
+link_with : [libmesa_util, libgallium, libpipe_loader_dynamic],
+install : false,
+  )
+endforeach
-- 
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[Mesa-dev] [PATCH v2 10/12] meson: build gallium unit tests

[Dylan Baker]

v2: - gate unit tests on swrast being enabled (Eric A)

Signed-off-by: Dylan Baker 
Reviewed-by: Eric Anholt 
---
 src/gallium/tests/meson.build  |  3 +++-
 src/gallium/tests/unit/meson.build | 31 +++-
 2 files changed, 34 insertions(+)
 create mode 100644 src/gallium/tests/unit/meson.build

diff --git a/src/gallium/tests/meson.build b/src/gallium/tests/meson.build
index 1779874..57e248d 100644
--- a/src/gallium/tests/meson.build
+++ b/src/gallium/tests/meson.build
@@ -19,3 +19,6 @@
 # SOFTWARE.
 
 subdir('trivial')
+if with_gallium_softpipe
+  subdir('unit')
+endif
diff --git a/src/gallium/tests/unit/meson.build 
b/src/gallium/tests/unit/meson.build
new file mode 100644
index 000..f320c56
--- /dev/null
+++ b/src/gallium/tests/unit/meson.build
@@ -0,0 +1,31 @@
+# Copyright © 2018 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+foreach t : ['pipe_barrier_test', 'u_cache_test', 'u_half_test',
+ 'u_format_test', 'u_format_compatible_test', 'translate_test']
+  executable(
+t,
+'@0@.c'.format(t),
+include_directories : [inc_common, inc_gallium_drivers, 
inc_gallium_winsys],
+link_with : [libgallium, libmesa_util, libtrace, libws_null],
+dependencies : [driver_swrast, dep_thread],
+install : false,
+  )
+endforeach
-- 
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[Mesa-dev] [PATCH v2 08/12] meson: Remove TODO about mesa/main tests

[Dylan Baker]

They're already done.

Signed-off-by: Dylan Baker 
---
 src/mesa/meson.build | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/mesa/meson.build b/src/mesa/meson.build
index d2d058b..8e1a49e 100644
--- a/src/mesa/meson.build
+++ b/src/mesa/meson.build
@@ -18,8 +18,6 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-# TODO: main/tests
-
 subdir('program')
 subdir('main')
 
-- 
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[Mesa-dev] [PATCH v2 01/12] glsl/tests: reimplement warnings-test in python

[Dylan Baker]

This reimplements the test in python with a shell script wrapper that
allows autotools to continue to run the test without realizing that
anything has changed.

Using python has two advantages, first it's portable so this test can be
run on windows as well as Linux since it just requires python, no more
diff, pwd or sh. It's also no longer tied to autotools implementation
details, like the environment variables $srcdir and $abs_builddir,
though the autotools shell wrapper still uses those, which makes it
possible to run the test in meson.

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/tests/warnings-test.sh | 57 +---
 src/compiler/glsl/tests/warnings_test.py | 74 +-
 2 files changed, 75 insertions(+), 56 deletions(-)
 create mode 100755 src/compiler/glsl/tests/warnings_test.py

diff --git a/src/compiler/glsl/tests/warnings-test.sh 
b/src/compiler/glsl/tests/warnings-test.sh
index d5dc3b5..debd6fd 100755
--- a/src/compiler/glsl/tests/warnings-test.sh
+++ b/src/compiler/glsl/tests/warnings-test.sh
@@ -1,58 +1,3 @@
 #!/bin/sh
 
-if [ -z "$srcdir" -o -z "$abs_builddir" ]; then
-echo ""
-echo "Warning: you're invoking the script manually and things may fail."
-echo "Attempting to determine/set srcdir and abs_builddir variables."
-echo ""
-
-# Variable should point to the Makefile.glsl.am
-srcdir=./../../
-cd `dirname "$0"`
-# Variable should point to glsl_compiler
-abs_builddir=`pwd`/../../
-fi
-
-# Execute several shaders, and check that the InfoLog outcome is the expected.
-
-compiler=$abs_builddir/glsl_compiler
-total=0
-pass=0
-
-if [ ! -x "$compiler" ]; then
-echo "Could not find glsl_compiler. Ensure that it is build via make check"
-exit 1
-fi
-
-tests_relative_dir="glsl/tests/warnings"
-
-echo "== Testing compilation output =="
-for test in $srcdir/$tests_relative_dir/*.vert; do
-test_output="$abs_builddir/$tests_relative_dir/`basename $test`"
-mkdir -p $abs_builddir/$tests_relative_dir/
-echo -n "Testing `basename $test`..."
-$compiler --just-log --version 150 "$test" > "$test_output.out" 2>&1
-total=$((total+1))
-if diff "$test.expected" "$test_output.out" >/dev/null 2>&1; then
-echo "PASS"
-pass=$((pass+1))
-else
-echo "FAIL"
-diff "$test.expected" "$test_output.out"
-fi
-done
-
-if [ $total -eq 0 ]; then
-echo "Could not find any tests."
-exit 1
-fi
-
-echo ""
-echo "$pass/$total tests returned correct results"
-echo ""
-
-if [ $pass = $total ]; then
-exit 0
-else
-exit 1
-fi
+$srcdir/glsl/tests/warnings_test.py --glsl-compiler 
$abs_builddir/glsl_compiler --test-directory $srcdir/glsl/tests/warnings/
diff --git a/src/compiler/glsl/tests/warnings_test.py 
b/src/compiler/glsl/tests/warnings_test.py
new file mode 100755
index 000..2e0f231
--- /dev/null
+++ b/src/compiler/glsl/tests/warnings_test.py
@@ -0,0 +1,74 @@
+#!/usr/bin/env python
+# encoding=utf-8
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+from __future__ import print_function
+import argparse
+import os
+import subprocess
+
+
+def arg_parser():
+parser = argparse.ArgumentParser()
+parser.add_argument(
+'--glsl-compiler',
+required=True,
+help='Path to the standalone glsl compiler')
+parser.add_argument(
+'--test-directory',
+required=True,
+help='Directory containing tests to run.')
+return parser.parse_args()
+
+
+def main():
+args = arg_parser()
+files = [f for f in os.listdir(args.test_directory) if f.endswith('.vert')]
+passed = 0
+
+if not files:
+print('Could not find any tests')
+exit(1)
+
+print('== Testing compilation output ==')
+for file in files:
+print('Testing {} ...'.format(file), end='')
+file = os.path.join(args.test_directory, file)
+
+

[Mesa-dev] [PATCH v2 03/12] glsl/tests: Convert optimization-test.sh to pure python

[Dylan Baker]

This patch converts optimization-test.sh to python, in this process it
removes external shell dependencies including diff. It replaces the
python script that generates shell scripts with a python library that
generates test cases and runs them using subprocess.

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/tests/lower_jump_cases.py  | 643 -
 src/compiler/glsl/tests/lower_jumps/.gitignore   |   3 +-
 src/compiler/glsl/tests/lower_jumps/create_test_cases.py | 673 +
 src/compiler/glsl/tests/optimization-test.sh |  87 +-
 src/compiler/glsl/tests/optimization_test.py |  95 +-
 5 files changed, 739 insertions(+), 762 deletions(-)
 create mode 100644 src/compiler/glsl/tests/lower_jump_cases.py
 delete mode 100644 src/compiler/glsl/tests/lower_jumps/.gitignore
 delete mode 100644 src/compiler/glsl/tests/lower_jumps/create_test_cases.py
 create mode 100755 src/compiler/glsl/tests/optimization_test.py

diff --git a/src/compiler/glsl/tests/lower_jump_cases.py 
b/src/compiler/glsl/tests/lower_jump_cases.py
new file mode 100644
index 000..b50ab73
--- /dev/null
+++ b/src/compiler/glsl/tests/lower_jump_cases.py
@@ -0,0 +1,643 @@
+# coding=utf-8
+#
+# Copyright © 2011, 2018 Intel Corporation
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+# DEALINGS IN THE SOFTWARE.
+
+from sexps import *
+
+def make_test_case(f_name, ret_type, body):
+"""Create a simple optimization test case consisting of a single
+function with the given name, return type, and body.
+
+Global declarations are automatically created for any undeclared
+variables that are referenced by the function.  All undeclared
+variables are assumed to be floats.
+"""
+check_sexp(body)
+declarations = {}
+def make_declarations(sexp, already_declared = ()):
+if isinstance(sexp, list):
+if len(sexp) == 2 and sexp[0] == 'var_ref':
+if sexp[1] not in already_declared:
+declarations[sexp[1]] = [
+'declare', ['in'], 'float', sexp[1]]
+elif len(sexp) == 4 and sexp[0] == 'assign':
+assert sexp[2][0] == 'var_ref'
+if sexp[2][1] not in already_declared:
+declarations[sexp[2][1]] = [
+'declare', ['out'], 'float', sexp[2][1]]
+make_declarations(sexp[3], already_declared)
+else:
+already_declared = set(already_declared)
+for s in sexp:
+if isinstance(s, list) and len(s) >= 4 and \
+s[0] == 'declare':
+already_declared.add(s[3])
+else:
+make_declarations(s, already_declared)
+make_declarations(body)
+return declarations.values() + \
+[['function', f_name, ['signature', ret_type, ['parameters'], body]]]
+
+
+# The following functions can be used to build expressions.
+
+def const_float(value):
+"""Create an expression representing the given floating point value."""
+return ['constant', 'float', ['{0:.6f}'.format(value)]]
+
+def const_bool(value):
+"""Create an expression representing the given boolean value.
+
+If value is not a boolean, it is converted to a boolean.  So, for
+instance, const_bool(1) is equivalent to const_bool(True).
+"""
+return ['constant', 'bool', ['{0}'.format(1 if value else 0)]]
+
+def gt_zero(var_name):
+"""Create Construct the expression var_name > 0"""
+return ['expression', 'bool', '<', const_float(0), ['var_ref', var_name]]
+
+
+# The following functions can be used to build complex control flow
+# statements.  All of these functions return statement lists (even
+# those which only create a single statement), so that statements can
+# be sequenced together using the '+' operator.
+
+def return_(value = None):
+

[Mesa-dev] [PATCH v2 06/12] glcpp/tests: Convert shell scripts to a python script

[Dylan Baker]

This ports glcpp-test.sh and glcpp-test-cr-lf.sh to a python script that
accepts arguments for each line ending type. This should allow for
better reporting to users.

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/glcpp/tests/glcpp-test-cr-lf.sh | 148 +--
 src/compiler/glsl/glcpp/tests/glcpp-test.sh   | 121 +
 src/compiler/glsl/glcpp/tests/glcpp_test.py   | 221 +++-
 3 files changed, 223 insertions(+), 267 deletions(-)
 create mode 100755 src/compiler/glsl/glcpp/tests/glcpp_test.py

diff --git a/src/compiler/glsl/glcpp/tests/glcpp-test-cr-lf.sh 
b/src/compiler/glsl/glcpp/tests/glcpp-test-cr-lf.sh
index c1e3929..5b5335f 100755
--- a/src/compiler/glsl/glcpp/tests/glcpp-test-cr-lf.sh
+++ b/src/compiler/glsl/glcpp/tests/glcpp-test-cr-lf.sh
@@ -1,149 +1,3 @@
 #!/bin/sh
 
-if [ -z "$srcdir" -o -z "$abs_builddir" ]; then
-echo ""
-echo "Warning: you're invoking the script manually and things may fail."
-echo "Attempting to determine/set srcdir and abs_builddir variables."
-echo ""
-
-# Should point to `dirname Makefile.glsl.am`
-srcdir=./../../../
-cd `dirname "$0"`
-# Should point to `dirname Makefile` equivalent to the above.
-abs_builddir=`pwd`/../../../
-fi
-
-testdir="$srcdir/glsl/glcpp/tests"
-glcpp_test="$srcdir/glsl/glcpp/tests/glcpp-test.sh"
-
-total=0
-pass=0
-
-# This supports a pipe that doesn't destroy the exit status of first command
-#
-# 
http://unix.stackexchange.com/questions/14270/get-exit-status-of-process-thats-piped-to-another
-stdintoexitstatus() {
-read exitstatus
-return $exitstatus
-}
-
-run_test ()
-{
-cmd="$1"
-
-total=$((total+1))
-
-if [ "$VERBOSE" = "yes" ]; then
-   if $cmd; then
-   echo "PASS"
-   pass=$((pass+1))
-   else
-   echo "FAIL"
-   fi
-else
-   # This is "$cmd | tail -2" but with the exit status of "$cmd" not "tail 
-2"
-   if $cmd; echo $? >&3) | tail -2 | head -1 >&4) 3>&1) | 
stdintoexitstatus) 4>&1; then
-   echo "PASS"
-   pass=$((pass+1))
-   else
-   echo "FAIL"
-   fi
-fi
-}
-
-usage ()
-{
-   cat <&2
-   echo >&2
-   usage
-   exit 1
-   ;;
-   esac
-done
-
-# All tests depend on the .out files being present. So first do a
-# normal run of the test suite, (silently) just to create the .out
-# files as a side effect.
-rm -rf ./subtest-lf
-mkdir subtest-lf
-for file in "$testdir"/*.c; do
-base=$(basename "$file")
-cp "$file" subtest-lf
-done
-
-${glcpp_test} --testdir=subtest-lf >/dev/null 2>&1
-
-echo "= Testing with r line terminators (old Mac format) ="
-
-# Prepare test files with '\r' instead of '\n'
-rm -rf ./subtest-cr
-mkdir subtest-cr
-for file in "$testdir"/*.c; do
-base=$(basename "$file")
-tr "\n" "\r" < "$file" > subtest-cr/"$base"
-cp $abs_builddir/glsl/glcpp/tests/subtest-lf/"$base".out 
subtest-cr/"$base".expected
-done
-
-run_test "${glcpp_test} --testdir=subtest-cr"
-
-echo "= Testing with rn line terminators (DOS format) ="
-
-# Prepare test files with '\r\n' instead of '\n'
-rm -rf ./subtest-cr-lf
-mkdir subtest-cr-lf
-for file in "$testdir"/*.c; do
-base=$(basename "$file")
-sed -e 's/$/
/' < "$file" > subtest-cr-lf/"$base"
-cp $abs_builddir/glsl/glcpp/tests/subtest-lf/"$base".out 
subtest-cr-lf/"$base".expected
-done
-
-run_test "${glcpp_test} --testdir=subtest-cr-lf"
-
-echo "= Testing with nr (bizarre, but allowed by GLSL spec.) ="
-
-# Prepare test files with '\n\r' instead of '\n'
-rm -rf ./subtest-lf-cr
-mkdir subtest-lf-cr
-for file in "$testdir"/*.c; do
-base=$(basename "$file")
-sed -e 's/$/
/' < "$file" | tr "\n\r" "\r\n" > subtest-lf-cr/"$base"
-cp $abs_builddir/glsl/glcpp/tests/subtest-lf/"$base".out 
subtest-lf-cr/"$base".expected
-done
-
-run_test "${glcpp_test} --testdir=subtest-lf-cr"
-
-if [ $total -eq 0 ]; then
-echo "Could not find any tests."
-exit 1
-fi
-
-echo ""
-echo "$pass/$total tests returned correct results"
-echo ""
-
-if [ "$pass" = "$total" ]; then
-exit 0
-else
-exit 1
-fi
+$srcdir/glsl/glcpp/tests/glcpp_test.py $abs_builddir/glsl/glcpp/glcpp 
$srcdir/glsl/glcpp/tests --windows --oldmac --bizarro
diff --git a/src/compiler/glsl/glcpp/tests/glcpp-test.sh 
b/src/compiler/glsl/glcpp/tests/glcpp-test.sh
index 44c9451..d16e2cd 100755
--- a/src/compiler/glsl/glcpp/tests/glcpp-test.sh
+++ b/src/compiler/glsl/glcpp/tests/glcpp-test.sh
@@ -1,122 +1,3 @@
 #!/bin/sh
 
-if [ -z "$srcdir" -o -z "$abs_builddir" ]; then
-echo ""
-echo "Warning: you're invoking the script manually and things may fail."
-echo "Attempting to determine/set srcdir and abs_builddir variables."
-echo ""
-
-# Should point to `dirname Makefile.glsl.am`
-srcdir=./../../../
-cd `dirname "$0"`
-# Should point to `dirname Makefile` equivalent to the above.
-

[Mesa-dev] [PATCH v2 05/12] glsl/tests: Remove unused compare_ir.py script

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/tests/compare_ir.py | 58 +
 1 file changed, 58 deletions(-)
 delete mode 100644 src/compiler/glsl/tests/compare_ir.py

diff --git a/src/compiler/glsl/tests/compare_ir.py 
b/src/compiler/glsl/tests/compare_ir.py
deleted file mode 100644
index ed99339..000
--- a/src/compiler/glsl/tests/compare_ir.py
+++ /dev/null
@@ -1,58 +0,0 @@
-# coding=utf-8
-#
-# Copyright © 2011 Intel Corporation
-#
-# Permission is hereby granted, free of charge, to any person obtaining a
-# copy of this software and associated documentation files (the "Software"),
-# to deal in the Software without restriction, including without limitation
-# the rights to use, copy, modify, merge, publish, distribute, sublicense,
-# and/or sell copies of the Software, and to permit persons to whom the
-# Software is furnished to do so, subject to the following conditions:
-#
-# The above copyright notice and this permission notice (including the next
-# paragraph) shall be included in all copies or substantial portions of the
-# Software.
-#
-# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
-# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
-# DEALINGS IN THE SOFTWARE.
-
-# Compare two files containing IR code.  Ignore formatting differences
-# and declaration order.
-
-import os
-import os.path
-import subprocess
-import sys
-import tempfile
-
-from sexps import *
-
-if len(sys.argv) != 3:
-print 'Usage: python2 ./compare_ir.py  '
-exit(1)
-
-with open(sys.argv[1]) as f:
-ir1 = sort_decls(parse_sexp(f.read()))
-with open(sys.argv[2]) as f:
-ir2 = sort_decls(parse_sexp(f.read()))
-
-if ir1 == ir2:
-exit(0)
-else:
-file1, path1 = tempfile.mkstemp(os.path.basename(sys.argv[1]))
-file2, path2 = tempfile.mkstemp(os.path.basename(sys.argv[2]))
-try:
-os.write(file1, '{0}\n'.format(sexp_to_string(ir1)))
-os.close(file1)
-os.write(file2, '{0}\n'.format(sexp_to_string(ir2)))
-os.close(file2)
-subprocess.call(['diff', '-u', path1, path2])
-finally:
-os.remove(path1)
-os.remove(path2)
-exit(1)
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v2 02/12] meson: run glsl compiler warnings test

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 src/compiler/glsl/tests/meson.build | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/compiler/glsl/tests/meson.build 
b/src/compiler/glsl/tests/meson.build
index 146647a..040b257 100644
--- a/src/compiler/glsl/tests/meson.build
+++ b/src/compiler/glsl/tests/meson.build
@@ -83,4 +83,12 @@ test(
   )
 )
 
-# TODO: figure out how to get the shell based tests to work?
+test(
+  'glsl compiler warnings', find_program('warnings_test.py'),
+  args : [
+'--glsl-compiler', glsl_compiler,
+'--test-directory', join_paths(
+  meson.source_root(), 'src', 'compiler', 'glsl', 'tests', 'warnings'
+),
+  ],
+)
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH v2 00/12] Finish unit tests for meson build

[Dylan Baker]

This series adds the rest of the unit tests in the mesa tree, including
the gallium test binaries. The relevant tests are wired into the `ninja
test` command, and all tests pass.

A big part of this series is converting tests from shell based to a pure
python base. These are mostly straight forward conversions, with one big
exception that the lower_jump_tests is converted from a tool that
generates shell scripts to run, to a single python binary that generates
tests in memory as run, and runs them. The shell scripts have been kept
to allow passing arguments to the python scripts, they are not meant to
be run directly, just to wrap the python scripts for autotools.

v2: - Gate tests that require softpipe on softpipe
- add mesa gallium state tracker tests
- Add graw tests (Thanks to Brian and Jose for explaining these)

Dylan Baker (12):
  glsl/tests: reimplement warnings-test in python
  meson: run glsl compiler warnings test
  glsl/tests: Convert optimization-test.sh to pure python
  meson: enable optimization-test
  glsl/tests: Remove unused compare_ir.py script
  glcpp/tests: Convert shell scripts to a python script
  meson: enable glcpp test
  meson: Remove TODO about mesa/main tests
  meson: Build gallium trivial tests
  meson: build gallium unit tests
  meson: build tests for gallium mesa state tracker
  meson: build graw tests

 meson.build  |   2 +-
 src/compiler/glsl/glcpp/meson.build  |  18 +-
 src/compiler/glsl/glcpp/tests/glcpp-test-cr-lf.sh| 148 +--
 src/compiler/glsl/glcpp/tests/glcpp-test.sh  | 121 +-
 src/compiler/glsl/glcpp/tests/glcpp_test.py  | 221 +++-
 src/compiler/glsl/tests/compare_ir.py|  58 +-
 src/compiler/glsl/tests/lower_jump_cases.py  | 643 -
 src/compiler/glsl/tests/lower_jumps/.gitignore   |   3 +-
 src/compiler/glsl/tests/lower_jumps/create_test_cases.py | 673 +
 src/compiler/glsl/tests/meson.build  |  15 +-
 src/compiler/glsl/tests/optimization-test.sh |  87 +-
 src/compiler/glsl/tests/optimization_test.py |  95 +-
 src/compiler/glsl/tests/warnings-test.sh |  57 +-
 src/compiler/glsl/tests/warnings_test.py |  74 +-
 src/gallium/meson.build  |  10 +-
 src/gallium/targets/graw-null/meson.build|  34 +-
 src/gallium/targets/graw-xlib/meson.build|  33 +-
 src/gallium/tests/graw/meson.build   |  36 +-
 src/gallium/tests/meson.build|  25 +-
 src/gallium/tests/trivial/meson.build|  29 +-
 src/gallium/tests/unit/meson.build   |  31 +-
 src/mesa/meson.build |   2 +-
 src/mesa/state_tracker/tests/meson.build |  40 +-
 src/meson.build  |   3 +-
 24 files changed, 1307 insertions(+), 1151 deletions(-)
 create mode 100755 src/compiler/glsl/glcpp/tests/glcpp_test.py
 delete mode 100644 src/compiler/glsl/tests/compare_ir.py
 create mode 100644 src/compiler/glsl/tests/lower_jump_cases.py
 delete mode 100644 src/compiler/glsl/tests/lower_jumps/.gitignore
 delete mode 100644 src/compiler/glsl/tests/lower_jumps/create_test_cases.py
 create mode 100755 src/compiler/glsl/tests/optimization_test.py
 create mode 100755 src/compiler/glsl/tests/warnings_test.py
 create mode 100644 src/gallium/targets/graw-null/meson.build
 create mode 100644 src/gallium/targets/graw-xlib/meson.build
 create mode 100644 src/gallium/tests/graw/meson.build
 create mode 100644 src/gallium/tests/meson.build
 create mode 100644 src/gallium/tests/trivial/meson.build
 create mode 100644 src/gallium/tests/unit/meson.build
 create mode 100644 src/mesa/state_tracker/tests/meson.build

base-commit: 6ac87c17695ebf300a81ecc61e5703c6492b6e5c
-- 
git-series 0.9.1
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[Mesa-dev] [PATCH] nvc0: finish implementation of PIPE_QUERY_SO_OVERFLOW_PREDICATE

[Rhys Perry]

This also removes some useless code leftover from old changes.

Signed-off-by: Rhys Perry 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_query.c|  3 +-
 src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 42 +++-
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   |  2 +-
 3 files changed, 30 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
index d0a9e0c2c0..1a3e4e794c 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query.c
@@ -113,8 +113,9 @@ nvc0_render_condition(struct pipe_context *pipe,
   /* NOTE: comparison of 2 queries only works if both have completed */
   switch (q->type) {
   case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+  case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
  cond = condition ? NVC0_3D_COND_MODE_EQUAL :
-  NVC0_3D_COND_MODE_NOT_EQUAL;
+NVC0_3D_COND_MODE_NOT_EQUAL;
  wait = true;
  break;
   case PIPE_QUERY_OCCLUSION_COUNTER:
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
index 83a57fa011..e0a874ad1b 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
@@ -181,6 +181,10 @@ nvc0_hw_begin_query(struct nvc0_context *nvc0, struct 
nvc0_query *q)
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
   nvc0_hw_query_get(push, q, 0x10, 0x03005002 | (q->index << 5));
   break;
+   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
+  /* XXX: This get actually writes the number of overflowed streams */
+  nvc0_hw_query_get(push, q, 0x10, 0x0f005002);
+  break;
case PIPE_QUERY_TIME_ELAPSED:
   nvc0_hw_query_get(push, q, 0x10, 0x5002);
   break;
@@ -243,10 +247,11 @@ nvc0_hw_end_query(struct nvc0_context *nvc0, struct 
nvc0_query *q)
   nvc0_hw_query_get(push, q, 0x10, 0x06805002 | (q->index << 5));
   break;
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
-  /* TODO: How do we sum over all streams for render condition ? */
-  /* PRIMS_DROPPED doesn't write sequence, use a ZERO query to sync on */
   nvc0_hw_query_get(push, q, 0x00, 0x03005002 | (q->index << 5));
-  nvc0_hw_query_get(push, q, 0x20, 0x5002);
+  break;
+   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
+  /* XXX: This get actually writes the number of overflowed streams */
+  nvc0_hw_query_get(push, q, 0x00, 0x0f005002);
   break;
case PIPE_QUERY_TIMESTAMP:
case PIPE_QUERY_TIME_ELAPSED:
@@ -334,6 +339,7 @@ nvc0_hw_get_query_result(struct nvc0_context *nvc0, struct 
nvc0_query *q,
   res64[1] = data64[2] - data64[6];
   break;
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
   res8[0] = data64[0] != data64[2];
   break;
case PIPE_QUERY_TIMESTAMP:
@@ -417,15 +423,22 @@ nvc0_hw_get_query_result_resource(struct nvc0_context 
*nvc0,
PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
BEGIN_1IC0(push, NVC0_3D(MACRO_QUERY_BUFFER_WRITE), 9);
-   if (q->type == PIPE_QUERY_OCCLUSION_PREDICATE ||
-   q->type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) /* XXX what if 
64-bit? */
+   switch (q->type) {
+   case PIPE_QUERY_OCCLUSION_PREDICATE:
+   case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: /* XXX what if 64-bit? */
+   case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
   PUSH_DATA(push, 0x0001);
-   else if (result_type == PIPE_QUERY_TYPE_I32)
-  PUSH_DATA(push, 0x7fff);
-   else if (result_type == PIPE_QUERY_TYPE_U32)
-  PUSH_DATA(push, 0x);
-   else
-  PUSH_DATA(push, 0x);
+  break;
+   default:
+  if (result_type == PIPE_QUERY_TYPE_I32)
+ PUSH_DATA(push, 0x7fff);
+  else if (result_type == PIPE_QUERY_TYPE_U32)
+ PUSH_DATA(push, 0x);
+  else
+ PUSH_DATA(push, 0x);
+  break;
+   }
 
switch (q->type) {
case PIPE_QUERY_SO_STATISTICS:
@@ -519,6 +532,7 @@ nvc0_hw_create_query(struct nvc0_context *nvc0, unsigned 
type, unsigned index)
q = >base;
q->funcs = _query_funcs;
q->type = type;
+   q->index = index;
 
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
@@ -532,14 +546,14 @@ nvc0_hw_create_query(struct nvc0_context *nvc0, unsigned 
type, unsigned index)
   space = 512;
   break;
case PIPE_QUERY_SO_STATISTICS:
-   case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
   hq->is64bit = true;
   space = 64;
   break;
+   case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+   case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_PRIMITIVES_EMITTED:
   hq->is64bit = true;
-  q->index = index;
   space = 32;
 

Re: [Mesa-dev] [PATCH] Add more Coffee Lake brand strings

[Matt Turner]

On Thu, Apr 5, 2018 at 2:24 PM, Anuj Phogat  wrote:
> Signed-off-by: Anuj Phogat 
> ---
>  include/pci_ids/i965_pci_ids.h | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
> index 8716d758f0..c740a50bca 100644
> --- a/include/pci_ids/i965_pci_ids.h
> +++ b/include/pci_ids/i965_pci_ids.h
> @@ -165,8 +165,8 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
> (Kaby Lake GT3e)")
>  CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
>  CHIPSET(0x3184, glk, "Intel(R) UHD Graphics 605 (Geminilake)")
>  CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
> -CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> -CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
> +CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
>  CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
>  CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
>  CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")

Reviewed-by: Matt Turner 
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[Mesa-dev] [PATCH 1/2] nvc0: ensure the query's fence has been emitted in nvco_hw_query_fifo_wait

[Rhys Perry]

If the fence has not been emitted, hq->fence->sequence would be zero. This
would result in the semaphore never being triggered, blocking all later
commands in the pushbuf.

Signed-off-by: Rhys Perry 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
index 83a57fa011..75a2d7f172 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
@@ -611,6 +611,10 @@ nvc0_hw_query_fifo_wait(struct nvc0_context *nvc0, struct 
nvc0_query *q)
struct nvc0_hw_query *hq = nvc0_hw_query(q);
unsigned offset = hq->offset;
 
+   /* ensure the query's fence has been emitted */
+   if (hq->is64bit && hq->fence->statetype == PIPE_QUERY_SO_OVERFLOW_PREDICATE) offset += 0x20;
 
PUSH_SPACE(push, 5);
-- 
2.14.3

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[Mesa-dev] [PATCH 2/2] nvc0: change ACQUIRE_EQUAL to ACQUIRE_GEQUAL in nvc0_hw_query_fifo_wait

[Rhys Perry]

If a fence is created in between nvc0_hw_end_query and
nvc0_hw_query_fifo_wait, the sequence number in nvc0->screen->fence.bo can
be larger than hq->fence->sequence before the semaphore is created,
resulting in the semaphore never being triggered.

Signed-off-by: Rhys Perry 
---
 src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
index 75a2d7f172..dd7dbd7420 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c
@@ -630,5 +630,5 @@ nvc0_hw_query_fifo_wait(struct nvc0_context *nvc0, struct 
nvc0_query *q)
   PUSH_DATA (push, hq->sequence);
}
PUSH_DATA (push, (1 << 12) |
-  NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
+  NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
 }
-- 
2.14.3

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[Mesa-dev] [PATCH 0/2] nvc0: Fix a couple of bugs in nvc0_hw_query_fifo_wait

[Rhys Perry]

This series fixes a couple of bugs in nvc0_hw_query_fifo_wait().
The first one is that a query's fence is not guaranteedto be emitted.
The second one is that nvc0_hw_query_fifo_wait() works incorrectly
when a fence has been emitted in between nvc0_hw_end_query() and
nvc0_hw_query_fifo_wait().

Rhys Perry (2):
  nvc0: ensure the query's fence has been emitted in
nvco_hw_query_fifo_wait
  nvc0: change ACQUIRE_EQUAL to ACQUIRE_GEQUAL in
nvc0_hw_query_fifo_wait

 src/gallium/drivers/nouveau/nvc0/nvc0_query_hw.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

-- 
2.14.3

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[Mesa-dev] [PATCH] Add more Coffee Lake brand strings

[Anuj Phogat]

Signed-off-by: Anuj Phogat 
---
 include/pci_ids/i965_pci_ids.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 8716d758f0..c740a50bca 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -165,8 +165,8 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus Graphics 650 
(Kaby Lake GT3e)")
 CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake GT4")
 CHIPSET(0x3184, glk, "Intel(R) UHD Graphics 605 (Geminilake)")
 CHIPSET(0x3185, glk_2x6, "Intel(R) UHD Graphics 600 (Geminilake 2x6)")
-CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E90, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
+CHIPSET(0x3E93, cfl_gt1, "Intel(R) UHD Graphics 610 (Coffeelake 2x6 GT1)")
 CHIPSET(0x3E99, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3EA1, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
 CHIPSET(0x3EA4, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
-- 
2.13.6

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Re: [Mesa-dev] [PATCH 1/1] radeonsi: Reorder checks in si_check_render_feedback

[Jan Vesely]

On Thu, 2018-04-05 at 16:56 -0400, Marek Olšák wrote:
> Even though I've already fixed the crash in master, I'd like to have this
> patch in master too.

I think that's a different crash.
I can still reproduce on c7dd59b06d93e6820189e2d1e087c0811707ee07:
Thread 1 "test-short" received signal SIGSEGV, Segmentation fault.
0x7fffe4910350 in si_get_total_colormask (sctx=0x119ddb0) at si_pipe.h:1236
1236if (sctx->queued.named.rasterizer->rasterizer_discard)
(gdb) p sctx->queued.named.rasterizer
$1 = (struct si_state_rasterizer *) 0x0

> 
> Reviewed-by: Marek Olšák 

thanks, pushed,
Jan

> 
> Marek
> 
> On Thu, Apr 5, 2018 at 4:49 PM, Jan Vesely  wrote:
> 
> > si_get_total_colormask accesses NULL pointer on compute shaders
> > Fixes crashes on clover
> > Fixes: 0669dca9c00261849cee14d69fdea0a5e323c7f7 ("radeonsi: skip DCC
> > render feedback checking if color writes are disabled")
> > CC: Marek Olšák 
> > Signed-off-by: Jan Vesely 
> > ---
> >  src/gallium/drivers/radeonsi/si_blit.c | 6 +++---
> >  1 file changed, 3 insertions(+), 3 deletions(-)
> > 
> > diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/
> > radeonsi/si_blit.c
> > index 40f512a682..35506dd74b 100644
> > --- a/src/gallium/drivers/radeonsi/si_blit.c
> > +++ b/src/gallium/drivers/radeonsi/si_blit.c
> > @@ -710,15 +710,15 @@ static void 
> > si_check_render_feedback_resident_images(struct
> > si_context *sctx)
> > 
> >  static void si_check_render_feedback(struct si_context *sctx)
> >  {
> > +   if (!sctx->need_check_render_feedback)
> > +   return;
> > +
> > /* There is no render feedback if color writes are disabled.
> >  * (e.g. a pixel shader with image stores)
> >  */
> > if (!si_get_total_colormask(sctx))
> > return;
> > 
> > -   if (!sctx->need_check_render_feedback)
> > -   return;
> > -
> > for (int i = 0; i < SI_NUM_SHADERS; ++i) {
> > si_check_render_feedback_images(sctx, >images[i]);
> > si_check_render_feedback_textures(sctx,
> > >samplers[i]);
> > --
> > 2.14.3
> > 
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 


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Re: [Mesa-dev] [PATCH v3 020/104] nir: Support deref instructions in split_var_copies

[Jason Ekstrand]

On Thu, Apr 5, 2018 at 1:31 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> > @@ -268,8 +288,30 @@ split_var_copies_impl(nir_function_impl *impl)
> > state.dead_ctx = ralloc_context(NULL);
> > state.progress = false;
> >
> > +   nir_builder b;
> > +   nir_builder_init(, impl);
> > +
> > nir_foreach_block(block, impl) {
> >split_var_copies_block(block, );
> > +
> > +  nir_foreach_instr_safe(instr, block) {
> > + if (instr->type != nir_instr_type_intrinsic)
> > +continue;
> > +
> > + nir_intrinsic_instr *copy = nir_instr_as_intrinsic(instr);
> > + if (copy->intrinsic != nir_intrinsic_copy_deref)
> > +continue;
>
> Could you 'continue' here if glsl_type_is_vector_or_scalar() returns
> true for one of the srcs? If I understood correctly, it would avoid
> cluttering the 'progress'.
>

Yes, we could.  That sounds like a good follow-on.  I'd like to keep this
patch as close in behavior to the original as possible.
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Re: [Mesa-dev] [PATCH 02/17] ac/surface: don't set the display flag for obviously unsupported cases

[Marek Olšák]

On Thu, Apr 5, 2018 at 4:47 PM, Marek Olšák  wrote:

> On Thu, Apr 5, 2018 at 3:09 AM, Michel Dänzer  wrote:
>
>> On 2018-04-04 07:35 PM, Marek Olšák wrote:
>> > On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer 
>> wrote:
>> >> On 2018-04-04 02:57 PM, Marek Olšák wrote:
>> >>> On Wed, Apr 4, 2018, 6:18 AM Michel Dänzer > >>> > wrote:
>> >>>
>> >>> On 2018-04-04 03:59 AM, Marek Olšák wrote:
>> >>> > From: Marek Olšák  marek.ol...@amd.com
>> 
>> >>> >
>> >>> > This enables the tile swizzle for some cases of the displayable
>> >>> micro mode,
>> >>> > and it also fixes an addrlib assertion failure on Vega.
>> >>> > ---
>> >>> >  src/amd/common/ac_surface.c | 18 ++
>> >>> >  1 file changed, 14 insertions(+), 4 deletions(-)
>> >>> >
>> >>> > diff --git a/src/amd/common/ac_surface.c
>> >> b/src/amd/common/ac_surface.c
>> >>> > index b294cd85259..2b20a553d51 100644
>> >>> > --- a/src/amd/common/ac_surface.c
>> >>> > +++ b/src/amd/common/ac_surface.c
>> >>> > @@ -408,20 +408,29 @@ static unsigned
>> >>> cik_get_macro_tile_index(struct radeon_surf *surf)
>> >>> >   tileb = 8 * 8 * surf->bpe;
>> >>> >   tileb = MIN2(surf->u.legacy.tile_split, tileb);
>> >>> >
>> >>> >   for (index = 0; tileb > 64; index++)
>> >>> >   tileb >>= 1;
>> >>> >
>> >>> >   assert(index < 16);
>> >>> >   return index;
>> >>> >  }
>> >>> >
>> >>> > +static bool get_display_flag(const struct ac_surf_config
>> *config,
>> >>> > +  const struct radeon_surf *surf)
>> >>> > +{
>> >>> > + return surf->flags & RADEON_SURF_SCANOUT &&
>> >>> > +!(surf->flags & RADEON_SURF_FMASK) &&
>> >>> > +config->info.samples <= 1 &&
>> >>> > +surf->bpe >= 4 && surf->bpe <= 8;
>> >>>
>> >>> surf->bpe is the number of bytes used to store each pixel, right?
>> If
>> >> so,
>> >>> this cannot exclude surf->bpe < 4, since 16 bpp and 8 bpp formats
>> >> can be
>> >>> displayed.
>> >>>
>> >>>
>> >>> Sure, but what are the chances they will be displayed with the current
>> >>> stack? GLX doesn't have 16bpp visuals for on-screen rendering.
>> >>
>> >> Maybe not when the X server runs at depth 24, but it can also run at
>> >> depths 8, 15 & 16, in which case displayable surfaces with bpe == 1 or
>> 2
>> >> are needed even before GLX even comes into the picture.
>> >>
>> >
>> > OK. Let me ask differently. Do we wanna support displayable 8, 15, and
>> 16
>> > bpp?
>>
>> We do support it, it's not really a question of whether we want to
>> anymore. :)
>>
>> > Can we just say that we don't support those?
>>
>> I'm afraid we can't.
>>
>>
>> Which kind of surfaces are you trying to exclude like this? Maybe they
>> can be excluded in a different way.
>>
>
> Can we drop support for those formats? i.e. if somebody uses them, the
> person will get garbage.
>
> How likely is it that somebody will use bpp <= 16 for display nowadays?
>

Or put differently: How likely is it that somebody will notice it on
supported distros and supported window managers?

Marek
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[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105567

--- Comment #8 from charlie  ---
1) "build.environment" (file)
export LIBDIRSUFFIX='64'
export XBUILD="/usr"
EOF
-Ddri-drivers-path=${XBUILD}/lib${LIBDIRSUFFIX}/xorg/modules/dri

2) I don't believe there is a typo in my "mesa.cfg2.me" (file).

-Dgallium-drivers=radeonsi,svga,swrast

Perhaps I am building wrong:

"if [[ -e build.ninja ]];then ninja -j$threads 2> build_error.log ||
exitOnError"

The above is executed in a "build" directory after meson generates the
build.ninja file.

I thought that when "build.ninja" exists then ninja can be executed.

I will try replacing "ninja" with "meson".

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Re: [Mesa-dev] [PATCH 1/1] radeonsi: Reorder checks in si_check_render_feedback

[Marek Olšák]

Even though I've already fixed the crash in master, I'd like to have this
patch in master too.

Reviewed-by: Marek Olšák 

Marek

On Thu, Apr 5, 2018 at 4:49 PM, Jan Vesely  wrote:

> si_get_total_colormask accesses NULL pointer on compute shaders
> Fixes crashes on clover
> Fixes: 0669dca9c00261849cee14d69fdea0a5e323c7f7 ("radeonsi: skip DCC
> render feedback checking if color writes are disabled")
> CC: Marek Olšák 
> Signed-off-by: Jan Vesely 
> ---
>  src/gallium/drivers/radeonsi/si_blit.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/
> radeonsi/si_blit.c
> index 40f512a682..35506dd74b 100644
> --- a/src/gallium/drivers/radeonsi/si_blit.c
> +++ b/src/gallium/drivers/radeonsi/si_blit.c
> @@ -710,15 +710,15 @@ static void 
> si_check_render_feedback_resident_images(struct
> si_context *sctx)
>
>  static void si_check_render_feedback(struct si_context *sctx)
>  {
> +   if (!sctx->need_check_render_feedback)
> +   return;
> +
> /* There is no render feedback if color writes are disabled.
>  * (e.g. a pixel shader with image stores)
>  */
> if (!si_get_total_colormask(sctx))
> return;
>
> -   if (!sctx->need_check_render_feedback)
> -   return;
> -
> for (int i = 0; i < SI_NUM_SHADERS; ++i) {
> si_check_render_feedback_images(sctx, >images[i]);
> si_check_render_feedback_textures(sctx,
> >samplers[i]);
> --
> 2.14.3
>
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Re: [Mesa-dev] [PATCH 17/17] winsys/amdgpu: always set AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE

[Marek Olšák]

On Thu, Apr 5, 2018 at 4:22 AM, Samuel Pitoiset 
wrote:

> Patches 16-17 are:
>
> Reviewed-by: Samuel Pitoiset 
>
> Those two are quite interesting. I will probably update my kernel and
> experiment something.


Patch 16 breaks things and needs more changes.

Marek
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Re: [Mesa-dev] [PATCH v3 019/104] nir: Support deref instructions in lower_var_copies

[Jason Ekstrand]

On Thu, Apr 5, 2018 at 12:55 PM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> Hello,
>
> > +static nir_deref_instr *
> > +build_deref_to_next_wildcard(nir_builder *b,
> > + nir_deref_instr *parent,
> > + nir_deref_instr ***deref_arr)
> > +{
> > +   for (; **deref_arr; (*deref_arr)++) {
> > +  if ((**deref_arr)->deref_type == nir_deref_type_array_wildcard)
> > + return parent;
> > +
> > +  parent = nir_build_deref_follower(b, parent, **deref_arr);
> > +   }
> > +
> > +   assert(**deref_arr == NULL);
> > +   *deref_arr = NULL;
> > +   return parent;
> > +}
>
> Question: in a scenario where there are no wildcards in the chain,
> could we just return the original deref (i.e. the last element in
> deref_arr)?
>

Yes, and nir_build_deref_follower magically does that. :-)  It's admittedly
a bit sketchy because we don't know if the if the follower actually
dominates the current builder cursor but all of the callers in this series
do have that guarantee.
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[Mesa-dev] [PATCH 1/1] radeonsi: Reorder checks in si_check_render_feedback

[Jan Vesely]

si_get_total_colormask accesses NULL pointer on compute shaders
Fixes crashes on clover
Fixes: 0669dca9c00261849cee14d69fdea0a5e323c7f7 ("radeonsi: skip DCC render 
feedback checking if color writes are disabled")
CC: Marek Olšák 
Signed-off-by: Jan Vesely 
---
 src/gallium/drivers/radeonsi/si_blit.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 40f512a682..35506dd74b 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -710,15 +710,15 @@ static void 
si_check_render_feedback_resident_images(struct si_context *sctx)
 
 static void si_check_render_feedback(struct si_context *sctx)
 {
+   if (!sctx->need_check_render_feedback)
+   return;
+
/* There is no render feedback if color writes are disabled.
 * (e.g. a pixel shader with image stores)
 */
if (!si_get_total_colormask(sctx))
return;
 
-   if (!sctx->need_check_render_feedback)
-   return;
-
for (int i = 0; i < SI_NUM_SHADERS; ++i) {
si_check_render_feedback_images(sctx, >images[i]);
si_check_render_feedback_textures(sctx, >samplers[i]);
-- 
2.14.3

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Re: [Mesa-dev] [PATCH 02/17] ac/surface: don't set the display flag for obviously unsupported cases

[Marek Olšák]

On Thu, Apr 5, 2018 at 3:09 AM, Michel Dänzer  wrote:

> On 2018-04-04 07:35 PM, Marek Olšák wrote:
> > On Wed, Apr 4, 2018 at 9:01 AM, Michel Dänzer 
> wrote:
> >> On 2018-04-04 02:57 PM, Marek Olšák wrote:
> >>> On Wed, Apr 4, 2018, 6:18 AM Michel Dänzer  >>> > wrote:
> >>>
> >>> On 2018-04-04 03:59 AM, Marek Olšák wrote:
> >>> > From: Marek Olšák  
> >>> >
> >>> > This enables the tile swizzle for some cases of the displayable
> >>> micro mode,
> >>> > and it also fixes an addrlib assertion failure on Vega.
> >>> > ---
> >>> >  src/amd/common/ac_surface.c | 18 ++
> >>> >  1 file changed, 14 insertions(+), 4 deletions(-)
> >>> >
> >>> > diff --git a/src/amd/common/ac_surface.c
> >> b/src/amd/common/ac_surface.c
> >>> > index b294cd85259..2b20a553d51 100644
> >>> > --- a/src/amd/common/ac_surface.c
> >>> > +++ b/src/amd/common/ac_surface.c
> >>> > @@ -408,20 +408,29 @@ static unsigned
> >>> cik_get_macro_tile_index(struct radeon_surf *surf)
> >>> >   tileb = 8 * 8 * surf->bpe;
> >>> >   tileb = MIN2(surf->u.legacy.tile_split, tileb);
> >>> >
> >>> >   for (index = 0; tileb > 64; index++)
> >>> >   tileb >>= 1;
> >>> >
> >>> >   assert(index < 16);
> >>> >   return index;
> >>> >  }
> >>> >
> >>> > +static bool get_display_flag(const struct ac_surf_config
> *config,
> >>> > +  const struct radeon_surf *surf)
> >>> > +{
> >>> > + return surf->flags & RADEON_SURF_SCANOUT &&
> >>> > +!(surf->flags & RADEON_SURF_FMASK) &&
> >>> > +config->info.samples <= 1 &&
> >>> > +surf->bpe >= 4 && surf->bpe <= 8;
> >>>
> >>> surf->bpe is the number of bytes used to store each pixel, right?
> If
> >> so,
> >>> this cannot exclude surf->bpe < 4, since 16 bpp and 8 bpp formats
> >> can be
> >>> displayed.
> >>>
> >>>
> >>> Sure, but what are the chances they will be displayed with the current
> >>> stack? GLX doesn't have 16bpp visuals for on-screen rendering.
> >>
> >> Maybe not when the X server runs at depth 24, but it can also run at
> >> depths 8, 15 & 16, in which case displayable surfaces with bpe == 1 or 2
> >> are needed even before GLX even comes into the picture.
> >>
> >
> > OK. Let me ask differently. Do we wanna support displayable 8, 15, and 16
> > bpp?
>
> We do support it, it's not really a question of whether we want to
> anymore. :)
>
> > Can we just say that we don't support those?
>
> I'm afraid we can't.
>
>
> Which kind of surfaces are you trying to exclude like this? Maybe they
> can be excluded in a different way.
>

Can we drop support for those formats? i.e. if somebody uses them, the
person will get garbage.

How likely is it that somebody will use bpp <= 16 for display nowadays?

Marek
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Re: [Mesa-dev] [PATCH v3 020/104] nir: Support deref instructions in split_var_copies

[Caio Marcelo de Oliveira Filho]

> @@ -268,8 +288,30 @@ split_var_copies_impl(nir_function_impl *impl)
> state.dead_ctx = ralloc_context(NULL);
> state.progress = false;
>  
> +   nir_builder b;
> +   nir_builder_init(, impl);
> +
> nir_foreach_block(block, impl) {
>split_var_copies_block(block, );
> +
> +  nir_foreach_instr_safe(instr, block) {
> + if (instr->type != nir_instr_type_intrinsic)
> +continue;
> +
> + nir_intrinsic_instr *copy = nir_instr_as_intrinsic(instr);
> + if (copy->intrinsic != nir_intrinsic_copy_deref)
> +continue;

Could you 'continue' here if glsl_type_is_vector_or_scalar() returns
true for one of the srcs? If I understood correctly, it would avoid
cluttering the 'progress'.


Thanks,
Caio
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Re: [Mesa-dev] [PATCH v3] intel/tools: new intel_sanitize_gpu tool

[Dylan Baker]

Quoting Scott D Phillips (2018-02-08 17:11:25)
> diff --git a/src/intel/tools/intel_sanitize_gpu.in 
> b/src/intel/tools/intel_sanitize_gpu.in
> new file mode 100755
> index 000..3dac954c408
> --- /dev/null
> +++ b/src/intel/tools/intel_sanitize_gpu.in
> @@ -0,0 +1,4 @@
> +#!/bin/bash
> +# -*- mode: sh -*-
> +
> +LD_PRELOAD="@install_libexecdir@/libintel_sanitize_gpu.so${LD_PRELOAD:+:$LD_PRELOAD}"
>  exec "$@"
> diff --git a/src/intel/tools/meson.build b/src/intel/tools/meson.build
> index 82413041b13..752d826bcb9 100644
> --- a/src/intel/tools/meson.build
> +++ b/src/intel/tools/meson.build
> @@ -41,3 +41,28 @@ aubinator_error_decode = executable(
>build_by_default : with_tools.contains('intel'),
>install : with_tools.contains('intel'),
>  )
> +
> +if with_tools.contains('intel')

Most of the other tools are build_by_default, but I don't see a good way to use
configure_file with install in that way. So I guess this is fine.

> +  sanitize_data = configuration_data()
> +  sanitize_data.set(
> +'install_libexecdir',
> +join_paths(get_option('prefix'), get_option('libexecdir'))
> +  )
> +  configure_file(
> +input: 'intel_sanitize_gpu.in',
> +output: 'intel_sanitize_gpu',

You can use '@BASENAME@' here I think.

> +install_dir: get_option('bindir'),
> +configuration: sanitize_data,
> +  )
> +
> +  libintel_sanitize_gpu = shared_module(
> +'intel_sanitize_gpu',
> +files('intel_sanitize_gpu.c'),
> +dependencies : [dep_dl, cc.find_library('pthread')],

[dep_dl, dep_thread], right?

> +include_directories : [inc_common, inc_intel, inc_drm_uapi],
> +link_with : [libintel_common, libmesa_util],
> +c_args : [c_vis_args, no_override_init_args],
> +install_dir: get_option('libexecdir'),
> +install: true,
> +  )
> +endif
> -- 
> 2.14.3


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Re: [Mesa-dev] [PATCH v2 5/5] i965/miptree: Don't gtt map from map_depthstencil

[Chris Wilson]

Quoting Scott D Phillips (2018-04-03 21:05:45)
> Instead of gtt mapping, call out to other map functions (map_map
> or map_tiled_memcpy) for the depth surface. Removes a place where
> gtt mapping is used.
> 
> v2: add level, slice to debug print (Nanley)
> ---
> @@ -3549,16 +3555,21 @@ intel_miptree_unmap_depthstencil(struct brw_context 
> *brw,
> bool map_z32f_x24s8 = mt->format == MESA_FORMAT_Z_FLOAT32;
>  
> if (map->mode & GL_MAP_WRITE_BIT) {
> +  struct intel_miptree_map z_mt_map = {
> + .mode = map->mode | GL_MAP_INVALIDATE_RANGE_BIT, .x = map->x,
> + .y = map->y, .w = map->w, .h = map->h,
> +  };
> +  if (z_mt->surf.tiling == ISL_TILING_LINEAR)
> + intel_miptree_map_map(brw, z_mt, _mt_map, level, slice);

No easy way to use movntqda to avoid WC reads?

It feels like duplicating the decision tree from intel_miptree_map,
which presumably should be already able to choose the preferred access
for the internal planes. Or does that logic need to be refactored for
reuse here?
-Chris
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Re: [Mesa-dev] [PATCH 4/5] i965/miptree: Map with movntdqa for linear buffers only

[Chris Wilson]

Quoting Scott D Phillips (2018-04-03 21:05:44)
> Removes a place where gtt mapping is used.
> 
> Reviewed-by: Nanley Chery 
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 58ffe868d0d..d8a6fc692ab 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -3735,7 +3735,8 @@ intel_miptree_map(struct brw_context *brw,
>  #if defined(USE_SSE41)
> } else if (!(mode & GL_MAP_WRITE_BIT) &&
>!mt->compressed && cpu_has_sse4_1 &&
> -  (mt->surf.row_pitch % 16 == 0)) {
> +  (mt->surf.row_pitch % 16 == 0) &&
> +  (mt->surf.tiling == ISL_TILING_LINEAR)) {
>intel_miptree_map_movntdqa(brw, mt, map, level, slice);
>  #endif
> } else if (mt->surf.tiling != ISL_TILING_LINEAR &&
> @@ -3781,6 +3782,7 @@ intel_miptree_unmap(struct brw_context *brw,
> } else if (!(map->mode & GL_MAP_WRITE_BIT) &&
>!mt->compressed && cpu_has_sse4_1 &&
>(mt->surf.row_pitch % 16 == 0) &&
> +  (mt->surf.tiling == ISL_TILING_LINEAR) &&
>map->buffer) {
>intel_miptree_unmap_movntdqa(brw, mt, map, level, slice);

And the rules in brw_bo_map() do mean that it will try to use WB/WC
mmaps. And the new map from patch 3 provides the tiled accesss WC.

We could fix up the alignment requirement here to avoid falling through
to map_map.

Reviewed-by: Chris Wilson 
-Chris
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Re: [Mesa-dev] [PATCH v4 3/5] i965/miptree: Use cpu tiling/detiling when mapping

[Chris Wilson]

Quoting Scott D Phillips (2018-04-03 21:05:43)
> Rename the (un)map_gtt functions to (un)map_map (map by
> returning a map) and add new functions (un)map_tiled_memcpy that
> return a shadow buffer populated with the intel_tiled_memcpy
> functions.
> 
> Tiling/detiling with the cpu will be the only way to handle Yf/Ys
> tiling, when support is added for those formats.
> 
> v2: Compute extents properly in the x|y-rounded-down case (Chris Wilson)
> 
> v3: Add units to parameter names of tile_extents (Nanley Chery)
> Use _mesa_align_malloc for the shadow copy (Nanley)
> Continue using gtt maps on gen4 (Nanley)
> 
> v4: Use streaming_load_memcpy when detiling
> ---
>  src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 108 
> --
>  1 file changed, 100 insertions(+), 8 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index 23cb40f3226..58ffe868d0d 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -31,6 +31,7 @@
>  #include "intel_image.h"
>  #include "intel_mipmap_tree.h"
>  #include "intel_tex.h"
> +#include "intel_tiled_memcpy.h"
>  #include "intel_blit.h"
>  #include "intel_fbo.h"
>  
> @@ -3046,10 +3047,10 @@ intel_miptree_unmap_raw(struct intel_mipmap_tree *mt)
>  }
>  
>  static void
> -intel_miptree_map_gtt(struct brw_context *brw,
> - struct intel_mipmap_tree *mt,
> - struct intel_miptree_map *map,
> - unsigned int level, unsigned int slice)
> +intel_miptree_map_map(struct brw_context *brw,
> +  struct intel_mipmap_tree *mt,
> +  struct intel_miptree_map *map,
> +  unsigned int level, unsigned int slice)
>  {
> unsigned int bw, bh;
> void *base;
> @@ -3093,11 +3094,93 @@ intel_miptree_map_gtt(struct brw_context *brw,
>  }
>  
>  static void
> -intel_miptree_unmap_gtt(struct intel_mipmap_tree *mt)
> +intel_miptree_unmap_map(struct intel_mipmap_tree *mt)
>  {
> intel_miptree_unmap_raw(mt);
>  }
>  
> +/* Compute extent parameters for use with tiled_memcpy functions.
> + * xs are in units of bytes and ys are in units of strides. */
> +static inline void
> +tile_extents(struct intel_mipmap_tree *mt, struct intel_miptree_map *map,
> + unsigned int level, unsigned int slice, unsigned int *x1_B,
> + unsigned int *x2_B, unsigned int *y1_el, unsigned int *y2_el)
> +{
> +   unsigned int block_width, block_height;
> +   unsigned int x0_el, y0_el;
> +
> +   _mesa_get_format_block_size(mt->format, _width, _height);
> +
> +   assert(map->x % block_width == 0);
> +   assert(map->y % block_height == 0);
> +
> +   intel_miptree_get_image_offset(mt, level, slice, _el, _el);
> +   *x1_B = (map->x / block_width + x0_el) * mt->cpp;
> +   *y1_el = map->y / block_height + y0_el;
> +   *x2_B = (DIV_ROUND_UP(map->x + map->w, block_width) + x0_el) * mt->cpp;
> +   *y2_el = DIV_ROUND_UP(map->y + map->h, block_height) + y0_el;
> +}
> +
> +static void
> +intel_miptree_map_tiled_memcpy(struct brw_context *brw,
> +   struct intel_mipmap_tree *mt,
> +   struct intel_miptree_map *map,
> +   unsigned int level, unsigned int slice)
> +{
> +   unsigned int x1, x2, y1, y2;
> +   tile_extents(mt, map, level, slice, , , , );
> +   map->stride = ALIGN(_mesa_format_row_stride(mt->format, map->w), 16);
> +
> +   /* The tiling and detiling functions require that the linear buffer
> +* has proper 16-byte alignment (that is, `x0` is 16-byte aligned).

Throw in an its here, i.e.  (that is, its `x0`...) Just spent a few
moments going what x0 before remembering it's the internal x0 of
tiled_to_linear().

We really want to move that knowledge back to intel_tiled_memcpy.c. A
single user isn't enough to justify a lot of effort though (or be sure
you get the interface right).

> +* Here we over-allocate the linear buffer by enough bytes to get
> +* the proper alignment.
> +*/
> +   map->buffer = _mesa_align_malloc(map->stride * (y2 - y1) + (x1 & 0xf), 
> 16);
> +   map->ptr = (char *)map->buffer + (x1 & 0xf);
> +   assert(map->buffer);
> +
> +   if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
> +  char *src = intel_miptree_map_raw(brw, mt, map->mode | MAP_RAW);
> +  src += mt->offset;
> +
> +  const mem_copy_fn fn =
> +#if defined(USE_SSE41)
> + cpu_has_sse4_1 ? (mem_copy_fn)_mesa_streaming_load_memcpy :
> +#endif
> + memcpy;

So always use a streaming load and bypass cache, even coming from WB.
Justifiable I believe, since there is no reason to keep it in cache as
the modification is on map->buffer not the tiled bo.

But do we want to use this path if !USE_SSE41 and WC? Let's see if
that's excluded.

>  static void
>  intel_miptree_map_blit(struct brw_context *brw,
>struct 

[Mesa-dev] [AppVeyor] mesa master #7384 completed

[AppVeyor]

Build mesa 7384 completed



Commit c7dd59b06d by Marek Olšák on 4/5/2018 7:53 PM:

radeonsi: fix a crash if ps_shader.cso is NULL in si_get_total_colormask


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Re: [Mesa-dev] [PATCH 2/5] i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

[Chris Wilson]

Quoting Chris Wilson (2018-04-05 20:54:54)
> Quoting Scott D Phillips (2018-04-03 21:05:42)
> > The reference for MOVNTDQA says:
> > 
> > For WC memory type, the nontemporal hint may be implemented by
> > loading a temporary internal buffer with the equivalent of an
> > aligned cache line without filling this data to the cache.
> > [...] Subsequent MOVNTDQA reads to unread portions of the WC
> > cache line will receive data from the temporary internal
> > buffer if data is available.
> > 
> > This hidden cache line sized temporary buffer can improve the
> > read performance from wc maps.
> > ---
> >  src/mesa/drivers/dri/i965/Makefile.am  |  7 
> >  src/mesa/drivers/dri/i965/Makefile.sources |  6 ++-
> >  src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 52 
> > ++
> >  src/mesa/drivers/dri/i965/meson.build  | 18 +++--
> >  4 files changed, 78 insertions(+), 5 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
> > b/src/mesa/drivers/dri/i965/Makefile.am
> > index 889d4c68a2b..ff47add93f4 100644
> > --- a/src/mesa/drivers/dri/i965/Makefile.am
> > +++ b/src/mesa/drivers/dri/i965/Makefile.am
> > @@ -92,8 +92,14 @@ libi965_gen11_la_CFLAGS = $(AM_CFLAGS) 
> > -DGEN_VERSIONx10=110
> >  
> >  noinst_LTLIBRARIES = \
> > libi965_dri.la \
> > +   libintel_tiled_memcpy.la \
> > $(I965_PERGEN_LIBS)
> >  
> > +libintel_tiled_memcpy_la_SOURCES = \
> > +   $(intel_tiled_memcpy_FILES)
> > +libintel_tiled_memcpy_la_CFLAGS = \
> > +   $(AM_CFLAGS) $(SSE41_CFLAGS)
> > +
> >  libi965_dri_la_SOURCES = \
> > $(i965_FILES) \
> > $(i965_oa_GENERATED_FILES)
> > @@ -104,6 +110,7 @@ libi965_dri_la_LIBADD = \
> > $(top_builddir)/src/intel/compiler/libintel_compiler.la \
> > $(top_builddir)/src/intel/blorp/libblorp.la \
> > $(I965_PERGEN_LIBS) \
> > +   libintel_tiled_memcpy.la
> > $(LIBDRM_LIBS)
> 
> Makes sense.
> 
> > diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c 
> > b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
> > index 7c6bde990d6..d076351b322 100644
> > --- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
> > +++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
> > @@ -36,6 +36,10 @@
> >  #include "brw_context.h"
> >  #include "intel_tiled_memcpy.h"
> >  
> > +#if defined(USE_SSE41)
> > +#include "main/streaming-load-memcpy.h"
> > +#include 
> > +#endif
> >  #if defined(__SSSE3__)
> >  #include 
> >  #elif defined(__SSE2__)
> > @@ -213,6 +217,30 @@ rgba8_copy_aligned_src(void *dst, const void *src, 
> > size_t bytes)
> > return dst;
> >  }
> >  
> > +#if defined(USE_SSE41)
> > +static ALWAYS_INLINE void*
> 
> Space in that void*? (but don't quote me on mesa/i965 preferred style!)
> 
> > +_memcpy_streaming_load(void *dest, const void *src, size_t count)
> > +{
> > +   if (count == 16) {
> > +  __m128i val = _mm_stream_load_si128((__m128i *)src);
> > +  _mm_store_si128((__m128i *)dest, val);
> > +  return dest;
> > +   } else if (count == 64) {
> > +  __m128i val0 = _mm_stream_load_si128(((__m128i *)src) + 0);
> > +  __m128i val1 = _mm_stream_load_si128(((__m128i *)src) + 1);
> > +  __m128i val2 = _mm_stream_load_si128(((__m128i *)src) + 2);
> > +  __m128i val3 = _mm_stream_load_si128(((__m128i *)src) + 3);
> > +  _mm_store_si128(((__m128i *)dest) + 0, val0);
> > +  _mm_store_si128(((__m128i *)dest) + 1, val1);
> > +  _mm_store_si128(((__m128i *)dest) + 2, val2);
> > +  _mm_store_si128(((__m128i *)dest) + 3, val3);
> > +  return dest;
> > +   } else {
> 
> assert(count < 16); or assert(count < 64) ?
> 
> Might as well remind the reader (and caller?!) that this is only for
> copying the residuals.
> 
> > +  return memcpy(dest, src, count);
> > +   }
> > +}
> > +#endif
> > +
> >  /**
> >   * Each row from y0 to y1 is copied in three parts: [x0,x1), [x1,x2), 
> > [x2,x3).
> >   * These ranges are in bytes, i.e. pixels * bytes-per-pixel.
> > @@ -677,6 +705,12 @@ xtiled_to_linear_faster(uint32_t x0, uint32_t x1, 
> > uint32_t x2, uint32_t x3,
> >   return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, 
> > xtile_height,
> >   dst, src, dst_pitch, swizzle_bit,
> >   rgba8_copy, rgba8_copy_aligned_src);
> > +#if defined(USE_SSE41)
> > +  else if (mem_copy == (mem_copy_fn)_mesa_streaming_load_memcpy)
> > + return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, 
> > xtile_height,
> > + dst, src, dst_pitch, swizzle_bit, memcpy,
> > + _memcpy_streaming_load);
> 
> Please group memcpy and _memcpy_streaming_load (put the line brea before
> to keep them on the same line).
> 
> > +#endif
> >else
> >   unreachable("not reached");
> > } else {
> > @@ -687,6 +721,12 @@ xtiled_to_linear_faster(uint32_t x0, uint32_t x1, 
> > 

Re: [Mesa-dev] [PATCH v3 019/104] nir: Support deref instructions in lower_var_copies

[Caio Marcelo de Oliveira Filho]

Hello,

> +static nir_deref_instr *
> +build_deref_to_next_wildcard(nir_builder *b,
> + nir_deref_instr *parent,
> + nir_deref_instr ***deref_arr)
> +{
> +   for (; **deref_arr; (*deref_arr)++) {
> +  if ((**deref_arr)->deref_type == nir_deref_type_array_wildcard)
> + return parent;
> +
> +  parent = nir_build_deref_follower(b, parent, **deref_arr);
> +   }
> +
> +   assert(**deref_arr == NULL);
> +   *deref_arr = NULL;
> +   return parent;
> +}

Question: in a scenario where there are no wildcards in the chain,
could we just return the original deref (i.e. the last element in
deref_arr)?


Thanks,
Caio
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Re: [Mesa-dev] [PATCH 2/5] i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear

[Chris Wilson]

Quoting Scott D Phillips (2018-04-03 21:05:42)
> The reference for MOVNTDQA says:
> 
> For WC memory type, the nontemporal hint may be implemented by
> loading a temporary internal buffer with the equivalent of an
> aligned cache line without filling this data to the cache.
> [...] Subsequent MOVNTDQA reads to unread portions of the WC
> cache line will receive data from the temporary internal
> buffer if data is available.
> 
> This hidden cache line sized temporary buffer can improve the
> read performance from wc maps.
> ---
>  src/mesa/drivers/dri/i965/Makefile.am  |  7 
>  src/mesa/drivers/dri/i965/Makefile.sources |  6 ++-
>  src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 52 
> ++
>  src/mesa/drivers/dri/i965/meson.build  | 18 +++--
>  4 files changed, 78 insertions(+), 5 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/Makefile.am 
> b/src/mesa/drivers/dri/i965/Makefile.am
> index 889d4c68a2b..ff47add93f4 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.am
> +++ b/src/mesa/drivers/dri/i965/Makefile.am
> @@ -92,8 +92,14 @@ libi965_gen11_la_CFLAGS = $(AM_CFLAGS) -DGEN_VERSIONx10=110
>  
>  noinst_LTLIBRARIES = \
> libi965_dri.la \
> +   libintel_tiled_memcpy.la \
> $(I965_PERGEN_LIBS)
>  
> +libintel_tiled_memcpy_la_SOURCES = \
> +   $(intel_tiled_memcpy_FILES)
> +libintel_tiled_memcpy_la_CFLAGS = \
> +   $(AM_CFLAGS) $(SSE41_CFLAGS)
> +
>  libi965_dri_la_SOURCES = \
> $(i965_FILES) \
> $(i965_oa_GENERATED_FILES)
> @@ -104,6 +110,7 @@ libi965_dri_la_LIBADD = \
> $(top_builddir)/src/intel/compiler/libintel_compiler.la \
> $(top_builddir)/src/intel/blorp/libblorp.la \
> $(I965_PERGEN_LIBS) \
> +   libintel_tiled_memcpy.la
> $(LIBDRM_LIBS)

Makes sense.

> diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c 
> b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
> index 7c6bde990d6..d076351b322 100644
> --- a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
> +++ b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c
> @@ -36,6 +36,10 @@
>  #include "brw_context.h"
>  #include "intel_tiled_memcpy.h"
>  
> +#if defined(USE_SSE41)
> +#include "main/streaming-load-memcpy.h"
> +#include 
> +#endif
>  #if defined(__SSSE3__)
>  #include 
>  #elif defined(__SSE2__)
> @@ -213,6 +217,30 @@ rgba8_copy_aligned_src(void *dst, const void *src, 
> size_t bytes)
> return dst;
>  }
>  
> +#if defined(USE_SSE41)
> +static ALWAYS_INLINE void*

Space in that void*? (but don't quote me on mesa/i965 preferred style!)

> +_memcpy_streaming_load(void *dest, const void *src, size_t count)
> +{
> +   if (count == 16) {
> +  __m128i val = _mm_stream_load_si128((__m128i *)src);
> +  _mm_store_si128((__m128i *)dest, val);
> +  return dest;
> +   } else if (count == 64) {
> +  __m128i val0 = _mm_stream_load_si128(((__m128i *)src) + 0);
> +  __m128i val1 = _mm_stream_load_si128(((__m128i *)src) + 1);
> +  __m128i val2 = _mm_stream_load_si128(((__m128i *)src) + 2);
> +  __m128i val3 = _mm_stream_load_si128(((__m128i *)src) + 3);
> +  _mm_store_si128(((__m128i *)dest) + 0, val0);
> +  _mm_store_si128(((__m128i *)dest) + 1, val1);
> +  _mm_store_si128(((__m128i *)dest) + 2, val2);
> +  _mm_store_si128(((__m128i *)dest) + 3, val3);
> +  return dest;
> +   } else {

assert(count < 16); or assert(count < 64) ?

Might as well remind the reader (and caller?!) that this is only for
copying the residuals.

> +  return memcpy(dest, src, count);
> +   }
> +}
> +#endif
> +
>  /**
>   * Each row from y0 to y1 is copied in three parts: [x0,x1), [x1,x2), 
> [x2,x3).
>   * These ranges are in bytes, i.e. pixels * bytes-per-pixel.
> @@ -677,6 +705,12 @@ xtiled_to_linear_faster(uint32_t x0, uint32_t x1, 
> uint32_t x2, uint32_t x3,
>   return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, 
> xtile_height,
>   dst, src, dst_pitch, swizzle_bit,
>   rgba8_copy, rgba8_copy_aligned_src);
> +#if defined(USE_SSE41)
> +  else if (mem_copy == (mem_copy_fn)_mesa_streaming_load_memcpy)
> + return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, 
> xtile_height,
> + dst, src, dst_pitch, swizzle_bit, memcpy,
> + _memcpy_streaming_load);

Please group memcpy and _memcpy_streaming_load (put the line brea before
to keep them on the same line).

> +#endif
>else
>   unreachable("not reached");
> } else {
> @@ -687,6 +721,12 @@ xtiled_to_linear_faster(uint32_t x0, uint32_t x1, 
> uint32_t x2, uint32_t x3,
>   return xtiled_to_linear(x0, x1, x2, x3, y0, y1,
>   dst, src, dst_pitch, swizzle_bit,
>   rgba8_copy, rgba8_copy_aligned_src);
> +#if defined(USE_SSE41)
> +  else if (mem_copy == 

[Mesa-dev] [AppVeyor] mesa master #7383 failed

[AppVeyor]

Build mesa 7383 failed


Commit be4250aa88 by Marek Olšák on 4/2/2018 2:49 AM:

radeonsi: remove more R600 references\n\nAcked-by: Timothy Arceri 


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Re: [Mesa-dev] [PATCH] anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS

[Daniel Stone]

On 21 February 2018 at 19:17, Jason Ekstrand  wrote:
> v2 (Jason Ekstrand):
>  - Return the correct enum values from anv_layout_to_fast_clear_type
>
> v3 (Jason Ekstrand):
>  - Always return ANV_FAST_CLEAR_NONE and leave doing the right thing for
>the patch which adds a modifier which supports fast-clears.

I've been running this for a while and haven't seen any issues with it
so far, so:
Reviewed-by: Daniel Stone 
Tested-by: Daniel Stone 
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Re: [Mesa-dev] [PATCH 3/4] radv: rename radv_cmd_buffer_update_vertex_descriptors()

[Samuel Pitoiset]

On 04/05/2018 05:42 PM, Bas Nieuwenhuizen wrote:

On Thu, Apr 5, 2018 at 11:42 AM, Samuel Pitoiset
 wrote:

... to radv_flush_vertex_buffers().

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_cmd_buffer.c | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3ae3e33c3b..05610adee8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1476,7 +1476,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
  }

  static void
-radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, 
bool pipeline_is_dirty)
+radv_flush_vertex_buffers(struct radv_cmd_buffer *cmd_buffer,


Can we keep descriptors in there instead of buffers? To keep it clear
it does nothing with the data?


Yeah, sounds good to me.




+ bool pipeline_is_dirty)
  {
 if ((pipeline_is_dirty ||
 (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
@@ -1530,7 +1531,7 @@ radv_cmd_buffer_update_vertex_descriptors(struct 
radv_cmd_buffer *cmd_buffer, bo
  static void
  radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, 
bool pipeline_is_dirty)
  {
-   radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, 
pipeline_is_dirty);
+   radv_flush_vertex_buffers(cmd_buffer, pipeline_is_dirty);
 radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
 radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
  VK_SHADER_STAGE_ALL_GRAPHICS);
--
2.16.3


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Re: [Mesa-dev] [PATCH] radv: disable TC-compat HTILE on Tonga and Iceland

[Samuel Pitoiset]

On 04/05/2018 01:18 PM, Bas Nieuwenhuizen wrote:

On Thu, Apr 5, 2018 at 10:32 AM, Samuel Pitoiset
 wrote:

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_image.c | 5 +
  1 file changed, 5 insertions(+)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index dd3189c67d..44caf0eeae 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -72,6 +72,11 @@ radv_image_is_tc_compat_htile(struct radv_device *device,
 if (device->physical_device->rad_info.chip_class < VI)
 return false;

+   /* TC-compat HTILE seems buggy on Tonga/Iceland. */


Can we please get a reference on what seems buggy about it? This could
very well something that is done incorrectly,s o I'd like something to
check to see if that is fixed.


It's a hardware bug apparently. If you have a Tonga or Iceland card, 
feel free to launch CTS with/without this patch.


I can improve the comment as well.




+   if (device->physical_device->rad_info.family == CHIP_TONGA ||
+   device->physical_device->rad_info.family == CHIP_ICELAND)
+   return false;
+
 if (pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT)
 return false;

--
2.16.3


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Re: [Mesa-dev] [PATCH 1/5] i965/tiled_memcpy: ytiled_to_linear a cache line at a time

[Chris Wilson]

Quoting Scott D Phillips (2018-04-03 21:05:41)
> Similar to the transformation applied to linear_to_ytiled, also align
> each readback from the ytiled source to a cacheline (i.e. transfer a
> whole cacheline from the source before moving on to the next column).
> This will allow us to utilize movntqda (_mm_stream_si128) in a
> subsequent patch to obtain near WB readback performance when accessing
> the uncached ytiled memory, an order of magnitude improvement.

Reviewed-by: Chris Wilson 
-Chris
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[Mesa-dev] [PATCH v2] virgl: disable virgl when no 3D for virtio gpu.

[Lepton Wu]

If users are running mesa under old version of qemu or have turned off
GL at runtime, virtio gpu driver actually doesn't work. Adds a detection
here so mesa can fall back to software rendering.

v2:
 - move detection from loader to virgl (Ilia, Emil)

Signed-off-by: Lepton Wu 
---
 src/gallium/winsys/virgl/drm/virgl_drm_winsys.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c 
b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
index cf3c3bac4b..4198ed7feb 100644
--- a/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
+++ b/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c
@@ -800,8 +800,15 @@ virgl_drm_winsys_create(int drmFD)
 {
struct virgl_drm_winsys *qdws;
int ret;
+   int gl = 0;
struct drm_virtgpu_getparam getparam = {0};
 
+   getparam.param = VIRTGPU_PARAM_3D_FEATURES;
+   getparam.value = (uint64_t)(uintptr_t)
+   ret = drmIoctl(drmFD, DRM_IOCTL_VIRTGPU_GETPARAM, );
+   if (ret < 0 || !gl)
+  return NULL;
+
qdws = CALLOC_STRUCT(virgl_drm_winsys);
if (!qdws)
   return NULL;
@@ -914,6 +921,10 @@ virgl_drm_screen_create(int fd)
   int dup_fd = fcntl(fd, F_DUPFD_CLOEXEC, 3);
 
   vws = virgl_drm_winsys_create(dup_fd);
+  if (!vws) {
+ close(dup_fd);
+ goto unlock;
+  }
 
   pscreen = virgl_create_screen(vws);
   if (pscreen) {
-- 
2.17.0.484.g0c8726318c-goog

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Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

[Mark Janes]

Emil Velikov  writes:

> On 4 April 2018 at 22:50, Mark Janes  wrote:
>> Leo Liu  writes:
>>
>>> On 04/04/2018 12:40 PM, Mark Janes wrote:
 Leo Liu  writes:

> On the CI family, firmware requires the destory command have to be the
> last command in the IB, moving feedback command after destroy is causing
> issues on CI cards, so we have to keep the previous logic that moves
> destroy back to the last command.
>
> But as the original issue fixed previously, with the newer family like 
> Vega10,
> feedback command have to be included inside of the task info command along
> with destroy command.
>
> Fixes: 6d74cb25("radeon/vce: move destroy command before feedback 
> command")
>
> Signed-off-by: Leo Liu 
> Cc: mesa-sta...@lists.freedesktop.org
 These tags seem ambiguous to me.  If this commit fixes a specific
 commit, then the patch should be applied only to stable branches which
 contain that commit.

 However, the mesa-stable CC caused this patch to be applied to 17.3,
 which does *not* contain the broken patch.

 Leo: did you intend for the mesa-stable CC to cause this patch to be
 applied to older stable branches?
>>> I would like to have this patch apply to branches "17.2", "17.3",
>>> "18.0", which got patch titled "radeon/vce: move destroy command before
>>> feedback command"
>>
>> Ok, I understand now.  You cc'd a buggy patch to stable, and the bug was
>> shipped in 17.3.1.
>>
> May I suggest phrasing things less personally. Mistakes happen, so
> let's work in providing suggestions for improvement as opposed to "you
> did X/Y".

Thank you for the feedback.  I was trying to state the facts, but I
understand how this could be read as a criticism.

As you say, mistakes happen -- and when they happen on the stable
branches, there is very little to protect the end users.  Could we
enhance automation to prevent this situation?  For example:

 - bin/.cherry-blacklist lists commits that should never be shipped on
   stable.

 - bisected bugs -> update the blacklist

I can't think of a way to automate that, but it would have highlighted
one of the instance where we shipped a regression in a 17.3 point
release.

> Aside from the normal stable/fixes tag, people can nominate patches by
> sending them to the list [1].
> We had patch authors, other developers and even 'random' members of
> the public to use the last method.
>
> HTH
> Emil
>
> https://www.mesa3d.org/submittingpatches.html#nominations
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[Mesa-dev] [PATCH 1/1] i965: return the fourcc saved in __DRIimage when possible

[James Xiong]

From: "Xiong, James" 

When creating a image from a texture, the image's dri_format is
set to the first plane's format, and used to look up for the
fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to
__DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function
intel_lookup_fourcc():
   { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
instead of the corret one:
   { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
   { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned.

To fix this bug, the image inherits the texture's planar_format that
has the original fourcc; Upon querying, if planar_format is set,
return the saved fourcc; Otherwise fall back to the old way.

v3: add a bug description and "cc mesa-stable" tag (Jason)
  remove abandunt null pointer check (Tapani)
  squash 2 patches into one (James)
v2: fall back to intel_lookup_fourcc() when planar_format is NULL
  (Dongwon & Matt Roper)

Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Xiong, James 
---
 src/mesa/drivers/dri/i965/intel_screen.c | 13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index dcb98da..29cb7ad 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -388,10 +388,16 @@ intel_image_format_lookup(int fourcc)
return NULL;
 }
 
-static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
+static boolean
+intel_image_get_fourcc(__DRIimage *image, int *fourcc)
 {
+   if (image->planar_format) {
+  *fourcc = image->planar_format->fourcc;
+  return true;
+   }
+
for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
-  if (intel_image_formats[i].planes[0].dri_format == dri_format) {
+  if (intel_image_formats[i].planes[0].dri_format == image->dri_format) {
  *fourcc = intel_image_formats[i].fourcc;
  return true;
   }
@@ -578,6 +584,7 @@ intel_create_image_from_texture(__DRIcontext *context, int 
target,
intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
image->dri_format = driGLFormatToImageFormat(image->format);
image->has_depthstencil = iobj->mt->stencil_mt? true : false;
+   image->planar_format = iobj->planar_format;
if (image->dri_format == MESA_FORMAT_NONE) {
   *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
   free(image);
@@ -869,7 +876,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
case __DRI_IMAGE_ATTRIB_FD:
   return !brw_bo_gem_export_to_prime(image->bo, value);
case __DRI_IMAGE_ATTRIB_FOURCC:
-  return intel_lookup_fourcc(image->dri_format, value);
+  return intel_image_get_fourcc(image, value);
case __DRI_IMAGE_ATTRIB_NUM_PLANES:
   if (isl_drm_modifier_has_aux(image->modifier)) {
  assert(!image->planar_format || image->planar_format->nplanes == 1);
-- 
2.7.4

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[Mesa-dev] [Bug 105567] meson/ninja: 1. mesa/vdpau incorrect symlinks in DESTDIR and 2. Ddri-drivers-path Dvdpau-libs-path overrides DESTDIR

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105567

--- Comment #7 from Dylan Baker  ---
1) What is the argument you're providing to -Ddri-drivers-path?

2) It's only supposed to install vdpau symlinks for drivers you've built. When
I run `meson build -Dgallium-drivers=nouveau -Ddri-drivers= -Dvulkan-drivers=
--prefix=/tmp/install; ninja -C build install` I only get vdpau symlinks. Are
you sure there isn't a typo in -Dgallium-drivers?

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Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

[Emil Velikov]

On 5 April 2018 at 19:10, Laura Ekstrand  wrote:
> Emil,
>
> Specifically, what infrastructure do you need?  Gallium is already carrying
> Sphinx around as a dependency.
>
The gallium docs are hosted on readthedocs.org. And I doubt we want to
move the main mesa3d.org website there ;-)
Currently mesa3d.org, most graphics stuff and others are on
freedesktop.org infrastructure.

HTH
Emil
P.S. Can I buy you to use interleaved posting/plain text email, please?
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Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

[Laura Ekstrand]

Emil,

Specifically, what infrastructure do you need?  Gallium is already carrying
Sphinx around as a dependency.

Laura

On Thu, Apr 5, 2018 at 11:07 AM, Emil Velikov 
wrote:

> Hi everyone,
>
> On 5 April 2018 at 01:58, Laura Ekstrand  wrote:
> > I forgot to note that you have to choose space->ignore in the diff
> options
> > on cgit in order to see the easy-to-read git diff.
> >
> I really should have made this more obvious. The key blocker isn't
> about reviewing the patches, but having the required infra to deploy
> it.
>
> Eric E, was planning to look that up, although ETIME and potential
> gitlab move got in the way.
> I'm not sure how we're doing on the latter, but I'm hoping that we
> would be soon.
>
> HTH
> Emil
>
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Re: [Mesa-dev] [PATCH 2/2] i965: return the fourcc saved in __DRIimage

[James Xiong]

On Thu, 5 Apr 2018 20:57:46 +0300
Tapani Pälli  wrote:

> On 05.04.2018 18:43, James Xiong wrote:
> > On Thu, 5 Apr 2018 14:30:02 +0300
> > Tapani Pälli  wrote:
> >   
> >> On 04/05/2018 02:51 AM, James Xiong wrote:  
> >>> From: "Xiong, James" 
> >>>
> >>> The planar_format in __DRIimage contains the original fourcc
> >>> used to create the image, if it's set, return the saved fourcc
> >>> directly; Otherwise fall back to the old way.
> >>>
> >>> Also we should validate the input parameter "value" first as it
> >>> might be NULL based on the SPEC.
> >>>
> >>> v2: fall back to intel_lookup_fourcc() when planar_format is NULL
> >>> (by Dongwon & Matt Roper)
> >>>
> >>> Signed-off-by: Xiong, James 
> >>> ---
> >>>src/mesa/drivers/dri/i965/intel_screen.c | 15 ---
> >>>1 file changed, 12 insertions(+), 3 deletions(-)
> >>>
> >>> diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> >>> b/src/mesa/drivers/dri/i965/intel_screen.c index 7df8bc4..aeecef3
> >>> 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c
> >>> +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> >>> @@ -388,10 +388,16 @@ intel_image_format_lookup(int fourcc)
> >>>   return NULL;
> >>>}
> >>>
> >>> -static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
> >>> +static boolean
> >>> +intel_image_get_fourcc(__DRIimage *image, int *fourcc)
> >>>{
> >>> +   if (image->planar_format) {
> >>> +  *fourcc = image->planar_format->fourcc;
> >>> +  return true;
> >>> +   }
> >>> +
> >>>   for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats);
> >>> i++) {
> >>> -  if (intel_image_formats[i].planes[0].dri_format ==
> >>> dri_format) {
> >>> +  if (intel_image_formats[i].planes[0].dri_format ==
> >>> image->dri_format) { *fourcc = intel_image_formats[i].fourcc;
> >>> return true;
> >>>  }
> >>> @@ -844,6 +850,9 @@ intel_create_image_with_modifiers(__DRIscreen
> >>> *dri_screen, static GLboolean
> >>>intel_query_image(__DRIimage *image, int attrib, int *value)
> >>>{
> >>> +   if (value == NULL)
> >>> +  return false;
> >>> +  
> >>
> >> I would remove this check, we've been fine many years without it.  
> > The function spec does say: ",  and 
> > may be NULL, in which case no value is retrieved."
> > it's better to stick to it and have an extra check than
> > segmentation fault, what do you say?  
> 
> Function modified here 'intel_query_image' is part of DRI interface 
> (dri_interface.h) with no such spec, it is used from many existing 
> places and none of them seem to be passing NULL.
> 
> Now that I know you are using eglExportDMABUFImageMESA, I can also
> see that dri2_export_dma_buf_image_mesa implementation does not call
> this API when 'fds', 'strides' or 'offsets' is NULL, it checks this
> in the implementation before calling.
> 
You are right it's already been checked in the upper level. I will
remove it.
> 
> >>  
> >>>   switch (attrib) {
> >>>   case __DRI_IMAGE_ATTRIB_STRIDE:
> >>>  *value = image->pitch;
> >>> @@ -870,7 +879,7 @@ intel_query_image(__DRIimage *image, int
> >>> attrib, int *value) case __DRI_IMAGE_ATTRIB_FD:
> >>>  return !brw_bo_gem_export_to_prime(image->bo, value);
> >>>   case __DRI_IMAGE_ATTRIB_FOURCC:
> >>> -  return intel_lookup_fourcc(image->dri_format, value);
> >>> +  return intel_image_get_fourcc(image, value);
> >>>   case __DRI_IMAGE_ATTRIB_NUM_PLANES:
> >>>  if (isl_drm_modifier_has_aux(image->modifier)) {
> >>> assert(!image->planar_format ||
> >>> image->planar_format->nplanes == 1);  
> >   
> 
> // Tapani

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Re: [Mesa-dev] [RFC] - Rewrite mesa website in Sphinx

[Emil Velikov]

Hi everyone,

On 5 April 2018 at 01:58, Laura Ekstrand  wrote:
> I forgot to note that you have to choose space->ignore in the diff options
> on cgit in order to see the easy-to-read git diff.
>
I really should have made this more obvious. The key blocker isn't
about reviewing the patches, but having the required infra to deploy
it.

Eric E, was planning to look that up, although ETIME and potential
gitlab move got in the way.
I'm not sure how we're doing on the latter, but I'm hoping that we
would be soon.

HTH
Emil
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Re: [Mesa-dev] [PATCH 2/2] i965: expose MESA_FORMAT_R8G8B8A8_SRGB visual

[Tapani Pälli]

ping .. CC my favourite sRGB reviewer

On 19.03.2018 13:41, Tapani Pälli wrote:

Exposing the visual makes following dEQP tests pass on Android:

dEQP-EGL.functional.wide_color.window__colorspace_srgb
dEQP-EGL.functional.wide_color.pbuffer__colorspace_srgb

Visual is exposed only when DRI_LOADER_CAP_RGBA_ORDERING is set.

Signed-off-by: Tapani Pälli 
---
  src/mesa/drivers/dri/i965/intel_screen.c | 10 +++---
  1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index dfb889221d..4d6829e1f0 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1255,12 +1255,14 @@ intel_query_dma_buf_formats(__DRIscreen *screen, int 
max,
 int i, j = 0;
  
 if (max == 0) {

-  *count = ARRAY_SIZE(intel_image_formats) - 1; /* not SARGB */
+  /* Note, sRGB formats not included. */
+  *count = ARRAY_SIZE(intel_image_formats) - 2;
return true;
 }
  
 for (i = 0; i < (ARRAY_SIZE(intel_image_formats)) && j < max; i++) {

- if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB)
+ if (intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SARGB ||
+ intel_image_formats[i].fourcc == __DRI_IMAGE_FOURCC_SABGR)
 continue;
   formats[j++] = intel_image_formats[i].fourcc;
 }
@@ -2084,6 +2086,8 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
  
/* Required by Android, for HAL_PIXEL_FORMAT_RGBX_. */

MESA_FORMAT_R8G8B8X8_UNORM,
+
+  MESA_FORMAT_R8G8B8A8_SRGB,
 };
  
 /* GLX_SWAP_COPY_OML is not supported due to page flipping. */

@@ -2103,7 +2107,7 @@ intel_screen_make_configs(__DRIscreen *dri_screen)
 if (intel_loader_get_cap(dri_screen, DRI_LOADER_CAP_RGBA_ORDERING))
num_formats = ARRAY_SIZE(formats);
 else
-  num_formats = ARRAY_SIZE(formats) - 2; /* all - RGBA_ORDERING formats */
+  num_formats = ARRAY_SIZE(formats) - 3; /* all - RGBA_ORDERING formats */
  
 /* Shall we expose 10 bpc formats? */

 bool allow_rgb10_configs = driQueryOptionb(>optionCache,


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Re: [Mesa-dev] [PATCH 2/2] i965: return the fourcc saved in __DRIimage

[Tapani Pälli]

On 05.04.2018 18:43, James Xiong wrote:

On Thu, 5 Apr 2018 14:30:02 +0300
Tapani Pälli  wrote:


On 04/05/2018 02:51 AM, James Xiong wrote:

From: "Xiong, James" 

The planar_format in __DRIimage contains the original fourcc
used to create the image, if it's set, return the saved fourcc
directly; Otherwise fall back to the old way.

Also we should validate the input parameter "value" first as it
might be NULL based on the SPEC.

v2: fall back to intel_lookup_fourcc() when planar_format is NULL
(by Dongwon & Matt Roper)

Signed-off-by: Xiong, James 
---
   src/mesa/drivers/dri/i965/intel_screen.c | 15 ---
   1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c index 7df8bc4..aeecef3
100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -388,10 +388,16 @@ intel_image_format_lookup(int fourcc)
  return NULL;
   }
   
-static boolean intel_lookup_fourcc(int dri_format, int *fourcc)

+static boolean
+intel_image_get_fourcc(__DRIimage *image, int *fourcc)
   {
+   if (image->planar_format) {
+  *fourcc = image->planar_format->fourcc;
+  return true;
+   }
+
  for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++)
{
-  if (intel_image_formats[i].planes[0].dri_format ==
dri_format) {
+  if (intel_image_formats[i].planes[0].dri_format ==
image->dri_format) { *fourcc = intel_image_formats[i].fourcc;
return true;
 }
@@ -844,6 +850,9 @@ intel_create_image_with_modifiers(__DRIscreen
*dri_screen, static GLboolean
   intel_query_image(__DRIimage *image, int attrib, int *value)
   {
+   if (value == NULL)
+  return false;
+


I would remove this check, we've been fine many years without it.

The function spec does say: ",  and  may
be NULL, in which case no value is retrieved."
it's better to stick to it and have an extra check than
segmentation fault, what do you say?


Function modified here 'intel_query_image' is part of DRI interface 
(dri_interface.h) with no such spec, it is used from many existing 
places and none of them seem to be passing NULL.


Now that I know you are using eglExportDMABUFImageMESA, I can also see 
that dri2_export_dma_buf_image_mesa implementation does not call this 
API when 'fds', 'strides' or 'offsets' is NULL, it checks this in the 
implementation before calling.






  switch (attrib) {
  case __DRI_IMAGE_ATTRIB_STRIDE:
 *value = image->pitch;
@@ -870,7 +879,7 @@ intel_query_image(__DRIimage *image, int
attrib, int *value) case __DRI_IMAGE_ATTRIB_FD:
 return !brw_bo_gem_export_to_prime(image->bo, value);
  case __DRI_IMAGE_ATTRIB_FOURCC:
-  return intel_lookup_fourcc(image->dri_format, value);
+  return intel_image_get_fourcc(image, value);
  case __DRI_IMAGE_ATTRIB_NUM_PLANES:
 if (isl_drm_modifier_has_aux(image->modifier)) {
assert(!image->planar_format ||
image->planar_format->nplanes == 1);




// Tapani
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Re: [Mesa-dev] [PATCH] anv: Add WSI support for the I915_FORMAT_MOD_Y_TILED_CCS

[Jason Ekstrand]

ping?

On Wed, Feb 21, 2018 at 11:17 AM, Jason Ekstrand 
wrote:

> v2 (Jason Ekstrand):
>  - Return the correct enum values from anv_layout_to_fast_clear_type
>
> v3 (Jason Ekstrand):
>  - Always return ANV_FAST_CLEAR_NONE and leave doing the right thing for
>the patch which adds a modifier which supports fast-clears.
> ---
>  src/intel/vulkan/anv_formats.c |  9 
>  src/intel/vulkan/anv_image.c   | 50 ++
> 
>  2 files changed, 40 insertions(+), 19 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> formats.c
> index 9c52ad5..3c17366 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -671,9 +671,18 @@ get_wsi_format_modifier_properties_list(const struct
> anv_physical_device *physic
>DRM_FORMAT_MOD_LINEAR,
>I915_FORMAT_MOD_X_TILED,
>I915_FORMAT_MOD_Y_TILED,
> +  I915_FORMAT_MOD_Y_TILED_CCS,
> };
>
> for (uint32_t i = 0; i < ARRAY_SIZE(modifiers); i++) {
> +  const struct isl_drm_modifier_info *mod_info =
> + isl_drm_modifier_get_info(modifiers[i]);
> +
> +  if (mod_info->aux_usage == ISL_AUX_USAGE_CCS_E &&
> +  !isl_format_supports_ccs_e(_device->info,
> + anv_format->planes[0].isl_format))
> + continue;
> +
>vk_outarray_append(, mod_props) {
>   mod_props->modifier = modifiers[i];
>   if (isl_drm_modifier_has_aux(modifiers[i]))
> diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
> index a2bae7b..9897e58 100644
> --- a/src/intel/vulkan/anv_image.c
> +++ b/src/intel/vulkan/anv_image.c
> @@ -515,6 +515,7 @@ score_drm_format_mod(uint64_t modifier)
> case DRM_FORMAT_MOD_LINEAR: return 1;
> case I915_FORMAT_MOD_X_TILED: return 2;
> case I915_FORMAT_MOD_Y_TILED: return 3;
> +   case I915_FORMAT_MOD_Y_TILED_CCS: return 4;
> default: unreachable("bad DRM format modifier");
> }
>  }
> @@ -746,8 +747,14 @@ void anv_GetImageSubresourceLayout(
>  VkSubresourceLayout*layout)
>  {
> ANV_FROM_HANDLE(anv_image, image, _image);
> -   const struct anv_surface *surface =
> -  get_surface(image, subresource->aspectMask);
> +
> +   const struct anv_surface *surface;
> +   if (subresource->aspectMask == VK_IMAGE_ASPECT_PLANE_1_BIT_KHR &&
> +   image->drm_format_mod != DRM_FORMAT_MOD_INVALID &&
> +   isl_drm_modifier_has_aux(image->drm_format_mod))
> +  surface = >planes[0].aux_surface;
> +   else
> +  surface = get_surface(image, subresource->aspectMask);
>
> assert(__builtin_popcount(subresource->aspectMask) == 1);
>
> @@ -862,25 +869,20 @@ anv_layout_to_aux_usage(const struct gen_device_info
> * const devinfo,
>}
>
>
> -   case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
> +   case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
>assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
>
> -  /* On SKL+, the render buffer can be decompressed by the
> presentation
> -   * engine. Support for this feature has not yet landed in the wider
> -   * ecosystem. TODO: Update this code when support lands.
> -   *
> -   * From the BDW PRM, Vol 7, Render Target Resolve:
> -   *
> -   *If the MCS is enabled on a non-multisampled render target, the
> -   *render target must be resolved before being used for other
> -   *purposes (display, texture, CPU lock) The clear value from
> -   *SURFACE_STATE is written into pixels in the render target
> -   *indicated as clear in the MCS.
> -   *
> -   * Pre-SKL, the render buffer must be resolved before being used for
> -   * presentation. We can infer that the auxiliary buffer is not used.
> +  /* When handing the image off to the presentation engine, we need to
> +   * ensure that things are properly resolved.  For images with no
> +   * modifier, we assume that they follow the old rules and always
> need
> +   * a full resolve because the PE doesn't understand any form of
> +   * compression.  For images with modifiers, we use the aux usage
> from
> +   * the modifier.
> */
> -  return ISL_AUX_USAGE_NONE;
> +  const struct isl_drm_modifier_info *mod_info =
> + isl_drm_modifier_get_info(image->drm_format_mod);
> +  return mod_info ? mod_info->aux_usage : ISL_AUX_USAGE_NONE;
> +   }
>
>
> /* Rendering Layouts */
> @@ -960,8 +962,18 @@ anv_layout_to_fast_clear_type(const struct
> gen_device_info * const devinfo,
> case VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL:
>return ANV_FAST_CLEAR_ANY;
>
> -   case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR:
> +   case VK_IMAGE_LAYOUT_PRESENT_SRC_KHR: {
> +  assert(image->aspects == VK_IMAGE_ASPECT_COLOR_BIT);
> +#ifndef NDEBUG
> +  /* We do not yet support any modifiers which support clear color so
> we
> +   * just always return NONE.  One day, this will change.

[Mesa-dev] [PATCH] intel/blorp: Assert that we don't re-layout a compressed surface

[Jason Ekstrand]

---
 src/intel/blorp/blorp_blit.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 0757db0..0f9ecb3 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1395,6 +1395,9 @@ blorp_surf_convert_to_single_slice(const struct 
isl_device *isl_dev,
 {
bool ok UNUSED;
 
+   /* It would be insane to try and do this on a compressed surface */
+   assert(info->aux_usage == ISL_AUX_USAGE_NONE);
+
/* Just bail if we have nothing to do. */
if (info->surf.dim == ISL_SURF_DIM_2D &&
info->view.base_level == 0 && info->view.base_array_layer == 0 &&
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH] meson: fix megadriver symlinking

[Dylan Baker]

Quoting Emil Velikov (2018-04-05 07:58:22)
> On 4 April 2018 at 18:45, Dylan Baker  wrote:
> > Which should be relative instead of absolute.
> >
> > Fixes: f7f1b30f81e842db6057591470ce3cb6d4fb2795
> >("meson: extend install_megadrivers script to handle symmlinking")
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105567
> > Signed-off-by: Dylan Baker 
> > ---
> >  bin/install_megadrivers.py | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/bin/install_megadrivers.py b/bin/install_megadrivers.py
> > index 86bfa359188..7931a544bd2 100755
> > --- a/bin/install_megadrivers.py
> > +++ b/bin/install_megadrivers.py
> > @@ -58,7 +58,7 @@ def main():
> >  while ext != '.so':
> >  if os.path.exists(name):
> >  os.unlink(name)
> > -os.symlink(driver, name)
> > +os.symlink(each, name)
> At a later stage, can we update the script to use more obvious names.

Yeah, I thought about that too, but this is fix that should land for 18.0.1, so
I wanted to minimize the churn.

Dylan

> 
> As-is patch does the job and is
> Reviewed-by: Emil Velikov 
> 
> -Emil


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Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon/vce: move feedback command inside of destroy function

[Emil Velikov]

On 4 April 2018 at 22:50, Mark Janes  wrote:
> Leo Liu  writes:
>
>> On 04/04/2018 12:40 PM, Mark Janes wrote:
>>> Leo Liu  writes:
>>>
 On the CI family, firmware requires the destory command have to be the
 last command in the IB, moving feedback command after destroy is causing
 issues on CI cards, so we have to keep the previous logic that moves
 destroy back to the last command.

 But as the original issue fixed previously, with the newer family like 
 Vega10,
 feedback command have to be included inside of the task info command along
 with destroy command.

 Fixes: 6d74cb25("radeon/vce: move destroy command before feedback command")

 Signed-off-by: Leo Liu 
 Cc: mesa-sta...@lists.freedesktop.org
>>> These tags seem ambiguous to me.  If this commit fixes a specific
>>> commit, then the patch should be applied only to stable branches which
>>> contain that commit.
>>>
>>> However, the mesa-stable CC caused this patch to be applied to 17.3,
>>> which does *not* contain the broken patch.
>>>
>>> Leo: did you intend for the mesa-stable CC to cause this patch to be
>>> applied to older stable branches?
>> I would like to have this patch apply to branches "17.2", "17.3",
>> "18.0", which got patch titled "radeon/vce: move destroy command before
>> feedback command"
>
> Ok, I understand now.  You cc'd a buggy patch to stable, and the bug was
> shipped in 17.3.1.
>
May I suggest phrasing things less personally. Mistakes happen, so
let's work in providing suggestions for improvement as opposed to "you
did X/Y".

Aside from the normal stable/fixes tag, people can nominate patches by
sending them to the list [1].
We had patch authors, other developers and even 'random' members of
the public to use the last method.

HTH
Emil

https://www.mesa3d.org/submittingpatches.html#nominations
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[Mesa-dev] [Bug 105846] Assertion failure @ st_atom_array.c:675 when playing Natural Selection 2

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105846

--- Comment #8 from l...@protonmail.ch ---
So I've tested it for a few hours now, and it does not seem to be happening
anymore.

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Re: [Mesa-dev] [PATCH 1/2] mesa: Add GL/GLSL plumbing for ARB_fragment_shader_interlock.

[Francisco Jerez]

Plamena Manolova  writes:

> This extension provides new GLSL built-in functions
> beginInvocationInterlockARB() and endInvocationInterlockARB()
> that delimit a critical section of fragment shader code. For
> pairs of shader invocations with "overlapping" coverage in a
> given pixel, the OpenGL implementation will guarantee that the
> critical section of the fragment shader will be executed for
> only one fragment at a time.
>
> Signed-off-by: Plamena Manolova 
> ---
>  src/compiler/glsl/ast.h  | 10 
>  src/compiler/glsl/ast_to_hir.cpp | 10 
>  src/compiler/glsl/ast_type.cpp   | 30 +++-
>  src/compiler/glsl/builtin_functions.cpp  | 79 
> 
>  src/compiler/glsl/glsl_parser.yy | 46 +++
>  src/compiler/glsl/glsl_parser_extras.cpp | 13 ++
>  src/compiler/glsl/glsl_parser_extras.h   |  7 +++
>  src/compiler/glsl/glsl_to_nir.cpp| 12 +
>  src/compiler/glsl/ir.h   |  2 +
>  src/compiler/glsl/linker.cpp |  8 
>  src/compiler/nir/nir_intrinsics.h|  2 +
>  src/compiler/shader_info.h   |  5 ++
>  src/mesa/main/extensions_table.h |  1 +
>  src/mesa/main/mtypes.h   |  5 ++
>  14 files changed, 229 insertions(+), 1 deletion(-)
>
> diff --git a/src/compiler/glsl/ast.h b/src/compiler/glsl/ast.h
> index a1ec0d566f..319a6a82c1 100644
> --- a/src/compiler/glsl/ast.h
> +++ b/src/compiler/glsl/ast.h
> @@ -620,6 +620,16 @@ struct ast_type_qualifier {
>* Flag set if GL_ARB_post_depth_coverage layout qualifier is used.
>*/
>   unsigned post_depth_coverage:1;
> +
> + /**
> +  * Flags for the layout qualifers added by 
> ARB_fragment_shader_interlock
> +  */
> +
> + unsigned pixel_interlock_ordered:1;
> + unsigned pixel_interlock_unordered:1;
> + unsigned sample_interlock_ordered:1;
> + unsigned sample_interlock_unordered:1;
> +
>   /**
>* Flag set if GL_INTEL_conservartive_rasterization layout qualifier
>* is used.
> diff --git a/src/compiler/glsl/ast_to_hir.cpp 
> b/src/compiler/glsl/ast_to_hir.cpp
> index badfbe6816..2358153c5f 100644
> --- a/src/compiler/glsl/ast_to_hir.cpp
> +++ b/src/compiler/glsl/ast_to_hir.cpp
> @@ -3897,6 +3897,16 @@ apply_layout_qualifier_to_variable(const struct 
> ast_type_qualifier *qual,
>  
> if (state->has_bindless())
>apply_bindless_qualifier_to_variable(qual, var, state, loc);
> +
> +   if (qual->flags.q.pixel_interlock_ordered ||
> +   qual->flags.q.pixel_interlock_unordered ||
> +   qual->flags.q.sample_interlock_ordered ||
> +   qual->flags.q.sample_interlock_unordered) {
> +  _mesa_glsl_error(loc, state, "interlock layout qualifiers: "
> +   "pixel_interlock_ordered, pixel_interlock_unordered, "
> +   "sample_interlock_ordered and 
> sample_interlock_unordered, "
> +   "only valid in fragment shader input layout 
> declaration.");
> +   }
>  }
>  
>  static void
> diff --git a/src/compiler/glsl/ast_type.cpp b/src/compiler/glsl/ast_type.cpp
> index 14ea936f24..49697d3411 100644
> --- a/src/compiler/glsl/ast_type.cpp
> +++ b/src/compiler/glsl/ast_type.cpp
> @@ -637,6 +637,10 @@ ast_type_qualifier::validate_in_qualifier(YYLTYPE *loc,
>valid_in_mask.flags.q.early_fragment_tests = 1;
>valid_in_mask.flags.q.inner_coverage = 1;
>valid_in_mask.flags.q.post_depth_coverage = 1;
> +  valid_in_mask.flags.q.pixel_interlock_ordered = 1;
> +  valid_in_mask.flags.q.pixel_interlock_unordered = 1;
> +  valid_in_mask.flags.q.sample_interlock_ordered = 1;
> +  valid_in_mask.flags.q.sample_interlock_unordered = 1;
>break;
> case MESA_SHADER_COMPUTE:
>valid_in_mask.flags.q.local_size = 7;
> @@ -708,6 +712,26 @@ ast_type_qualifier::merge_into_in_qualifier(YYLTYPE *loc,
>r = false;
> }
>  
> +   if (state->in_qualifier->flags.q.pixel_interlock_ordered) {
> +  state->fs_pixel_interlock_ordered = true;
> +  state->in_qualifier->flags.q.pixel_interlock_ordered = false;
> +   }
> +
> +   if (state->in_qualifier->flags.q.pixel_interlock_unordered) {
> +  state->fs_pixel_interlock_unordered = true;
> +  state->in_qualifier->flags.q.pixel_interlock_unordered = false;
> +   }
> +
> +   if (state->in_qualifier->flags.q.sample_interlock_ordered) {
> +  state->fs_sample_interlock_ordered = true;
> +  state->in_qualifier->flags.q.sample_interlock_ordered = false;
> +   }
> +
> +   if (state->in_qualifier->flags.q.sample_interlock_unordered) {
> +  state->fs_sample_interlock_unordered = true;
> +  state->in_qualifier->flags.q.sample_interlock_unordered = false;
> +   }
> +
> /* We allow the creation of multiple cs_input_layout nodes. Coherence 
> among
>  * all 

Re: [Mesa-dev] [PATCH v3 018/104] nir: Add a deref path helper struct

[Jason Ekstrand]

On Thu, Apr 5, 2018 at 10:06 AM, Caio Marcelo de Oliveira Filho <
caio.olive...@intel.com> wrote:

> Hello,
>
> > +   if (count <= max_short_path_len) {
> > +  /* If we're under max_short_path_len, just use the short path. */
> > +  path->path = head;
> > +  goto done;
> > +   }
> > +
> > +   path->path = ralloc_array(mem_ctx, nir_deref_instr *, count + 1);
> > +   head = tail = path->path + count;
> > +   *tail = NULL;
> > +   for (nir_deref_instr *d = deref; d; d = nir_deref_instr_parent(d))
> > +  *(--head) = d;
>
> What do you think about zeroing the _short_path when we are not using
> it? I'm guessing cases where we don't use _short_path will not be
> common, so it will help highlight them when debugging.
>

We could.  We could also memset it to 0xdeadbeef in debug builds which is
probably better than NULL.


> > +done:
> > +   assert(head == path->path);
> > +   assert(tail == head + count);
> > +   assert((*head)->deref_type == nir_deref_type_var);
>
> This assert access invalid memory if "deref == NULL", but the rest of
> the code is ready for this case. So I suggest either prefixing this
> assert with "(!*head) || ..." or, if the deref == NULL case is not
> useful/expected, assert(deref) in the beginning of the function.
>

It does.  However, I think it should be an error to call this function with
NULL (I can add an assert) and all of the callers assume that the first
path.path[0] will be a variable dereference so we really do want to check
that.
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Re: [Mesa-dev] [PATCH v3 018/104] nir: Add a deref path helper struct

[Caio Marcelo de Oliveira Filho]

Hello,

> +   if (count <= max_short_path_len) {
> +  /* If we're under max_short_path_len, just use the short path. */
> +  path->path = head;
> +  goto done;
> +   }
> +
> +   path->path = ralloc_array(mem_ctx, nir_deref_instr *, count + 1);
> +   head = tail = path->path + count;
> +   *tail = NULL;
> +   for (nir_deref_instr *d = deref; d; d = nir_deref_instr_parent(d))
> +  *(--head) = d;

What do you think about zeroing the _short_path when we are not using
it? I'm guessing cases where we don't use _short_path will not be
common, so it will help highlight them when debugging.


> +done:
> +   assert(head == path->path);
> +   assert(tail == head + count);
> +   assert((*head)->deref_type == nir_deref_type_var);

This assert access invalid memory if "deref == NULL", but the rest of
the code is ready for this case. So I suggest either prefixing this
assert with "(!*head) || ..." or, if the deref == NULL case is not
useful/expected, assert(deref) in the beginning of the function.


Thanks,
Caio
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Re: [Mesa-dev] [PATCH 2/2] i965: Add ARB_fragment_shader_interlock support.

[Francisco Jerez]

Plamena Manolova  writes:

> Adds suppport for ARB_fragment_shader_interlock. We achieve
> the interlock and fragment ordering by issuing a memory fence
> via sendc.
>
> Signed-off-by: Plamena Manolova 
> ---
>  docs/features.txt|  2 +-
>  docs/relnotes/18.1.0.html|  1 +
>  src/intel/compiler/brw_eu.h  |  3 ++-
>  src/intel/compiler/brw_eu_defines.h  |  2 ++
>  src/intel/compiler/brw_eu_emit.c |  7 ---
>  src/intel/compiler/brw_fs_generator.cpp  |  7 ++-
>  src/intel/compiler/brw_fs_nir.cpp| 15 +++
>  src/intel/compiler/brw_shader.cpp|  4 
>  src/intel/compiler/brw_vec4_generator.cpp|  2 +-
>  src/mesa/drivers/dri/i965/intel_extensions.c |  1 +
>  10 files changed, 37 insertions(+), 7 deletions(-)
>
> diff --git a/docs/features.txt b/docs/features.txt
> index 5eae34bf0d..a621251efd 100644
> --- a/docs/features.txt
> +++ b/docs/features.txt
> @@ -297,7 +297,7 @@ Khronos, ARB, and OES extensions that are not part of any 
> OpenGL or OpenGL ES ve
>GL_ARB_cl_event   not started
>GL_ARB_compute_variable_group_sizeDONE (nvc0, radeonsi)
>GL_ARB_ES3_2_compatibilityDONE (i965/gen8+)
> -  GL_ARB_fragment_shader_interlock  not started
> +  GL_ARB_fragment_shader_interlock  DONE (i965)
>GL_ARB_gpu_shader_int64   DONE (i965/gen8+, 
> nvc0, radeonsi, softpipe, llvmpipe)
>GL_ARB_parallel_shader_compilenot started, but 
> Chia-I Wu did some related work in 2014
>GL_ARB_post_depth_coverageDONE (i965)
> diff --git a/docs/relnotes/18.1.0.html b/docs/relnotes/18.1.0.html
> index 1d5201717f..9d8e63855d 100644
> --- a/docs/relnotes/18.1.0.html
> +++ b/docs/relnotes/18.1.0.html
> @@ -51,6 +51,7 @@ Note: some of the new features are only available with 
> certain drivers.
>  GL_EXT_shader_framebuffer_fetch on i965 on desktop GL (GLES was already 
> supported)
>  GL_EXT_shader_framebuffer_fetch_non_coherent on i965
>  Disk shader cache support for i965 enabled by default
> +GL_ARB_fragment_shader_interlock on i965
>  
>  
>  Bug fixes
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index ca72666a55..b2c36d3ea1 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -509,7 +509,8 @@ brw_byte_scattered_write(struct brw_codegen *p,
>  
>  void
>  brw_memory_fence(struct brw_codegen *p,
> - struct brw_reg dst);
> + struct brw_reg dst,
> + uint32_t send_op);
>

The new argument should probably be of type "enum opcode" in order to
avoid losing type information.

>  void
>  brw_pixel_interpolator_query(struct brw_codegen *p,
> diff --git a/src/intel/compiler/brw_eu_defines.h 
> b/src/intel/compiler/brw_eu_defines.h
> index 332d627bc3..2980e98a58 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -480,6 +480,8 @@ enum opcode {
>  
> SHADER_OPCODE_GET_BUFFER_SIZE,
>  
> +   SHADER_OPCODE_INTERLOCK,
> +
> VEC4_OPCODE_MOV_BYTES,
> VEC4_OPCODE_PACK_BYTES,
> VEC4_OPCODE_UNPACK_UNIFORM,
> diff --git a/src/intel/compiler/brw_eu_emit.c 
> b/src/intel/compiler/brw_eu_emit.c
> index f039af56d0..6a57397a41 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -3285,7 +3285,8 @@ brw_set_memory_fence_message(struct brw_codegen *p,
>  
>  void
>  brw_memory_fence(struct brw_codegen *p,
> - struct brw_reg dst)
> + struct brw_reg dst,
> + uint32_t send_op)
>  {
> const struct gen_device_info *devinfo = p->devinfo;
> const bool commit_enable =
> @@ -3301,7 +3302,7 @@ brw_memory_fence(struct brw_codegen *p,
> /* Set dst as destination for dependency tracking, the MEMORY_FENCE
>  * message doesn't write anything back.
>  */
> -   insn = next_insn(p, BRW_OPCODE_SEND);
> +   insn = next_insn(p, send_op);
> dst = retype(dst, BRW_REGISTER_TYPE_UW);
> brw_set_dest(p, insn, dst);
> brw_set_src0(p, insn, dst);
> @@ -3313,7 +3314,7 @@ brw_memory_fence(struct brw_codegen *p,
> * flush it too.  Use a different register so both flushes can be
> * pipelined by the hardware.
> */
> -  insn = next_insn(p, BRW_OPCODE_SEND);
> +  insn = next_insn(p, send_op);
>brw_set_dest(p, insn, offset(dst, 1));
>brw_set_src0(p, insn, offset(dst, 1));
>brw_set_memory_fence_message(p, insn, GEN6_SFID_DATAPORT_RENDER_CACHE,
> diff --git a/src/intel/compiler/brw_fs_generator.cpp 
> b/src/intel/compiler/brw_fs_generator.cpp
> index 0c85eb8e1e..f099d092d1 100644
> --- a/src/intel/compiler/brw_fs_generator.cpp
> +++ 

Re: [Mesa-dev] [PATCH 1/2] i965: init image's planar_format in intel_create_image_from_texture

[James Xiong]

On Thu, 5 Apr 2018 08:56:54 -0700
Jason Ekstrand  wrote:

> On Thu, Apr 5, 2018 at 8:45 AM, James Xiong 
> wrote:
> 
> > On Thu, 5 Apr 2018 08:24:27 -0700
> > Jason Ekstrand  wrote:
> >  
> > > Does this fix a bug?  If so, what?  
> > Jason, yes. I am sorry for the confusion, please see my earlier
> > reply to Tapani.
> >  
> 
> If it fixes a bug then the commit message should include a
> description of the bug fixed.  If the bug is a regression, it should
> have a "Fixes: SHA1" tag indicating where the regression originated
> and if it is a bug that has been around for a very long time, it
> should have a "Cc: mesa-sta...@lists.freedesktop.org" tag.  If the
> bug is filed in bugzilla, it should have a "Bugzilla: " tag.
> 
> --Jason
Thanks for the tip, Jason. I will make the corresponding changes in the
next version.
> 
> 
> 
> > >
> > > On April 4, 2018 16:57:21 James Xiong 
> > > wrote: 
> > > > From: "Xiong, James" 
> > > >
> > > > When creating a image from a texture, initialize the image's
> > > > planar_format with the texture's.
> > > >
> > > > Signed-off-by: Xiong, James 
> > > > ---
> > > > src/mesa/drivers/dri/i965/intel_screen.c | 1 +
> > > > 1 file changed, 1 insertion(+)
> > > >
> > > > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> > > > b/src/mesa/drivers/dri/i965/intel_screen.c
> > > > index dcb98da..7df8bc4 100644
> > > > --- a/src/mesa/drivers/dri/i965/intel_screen.c
> > > > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > > > @@ -578,6 +578,7 @@ intel_create_image_from_texture(__DRIcontext
> > > > *context, int target,
> > > >intel_setup_image_from_mipmap_tree(brw, image, iobj->mt,
> > > > level, zoffset); image->dri_format =
> > > > driGLFormatToImageFormat(image->format);
> > > > image->has_depthstencil = iobj->mt->stencil_mt? true : false;
> > > > +   image->planar_format = iobj->planar_format;
> > > >if (image->dri_format == MESA_FORMAT_NONE) {
> > > >   *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
> > > >   free(image);
> > > > --
> > > > 2.7.4
> > > >
> > > > ___
> > > > mesa-dev mailing list
> > > > mesa-dev@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev  
> > >
> > >
> > >  
> >
> >  

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[Mesa-dev] [Bug 105906] [DRI3] Compiz segfaults in intel_destroy_image()

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105906

Lionel Landwerlin  changed:

   What|Removed |Added

   Assignee|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org
  Component|Drivers/X11 |Drivers/DRI/i965
 QA Contact|mesa-dev@lists.freedesktop. |intel-3d-bugs@lists.freedes
   |org |ktop.org

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[Mesa-dev] [Bug 105906] [DRI3] Compiz segfaults in intel_destroy_image()

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105906

Lionel Landwerlin  changed:

   What|Removed |Added

  Component|Drivers/DRI/i965|Drivers/X11
   Assignee|intel-3d-bugs@lists.freedes |mesa-dev@lists.freedesktop.
   |ktop.org|org
 CC||dan...@fooishbar.org,
   ||l...@collabora.com
 QA Contact|intel-3d-bugs@lists.freedes |mesa-dev@lists.freedesktop.
   |ktop.org|org

--- Comment #1 from Lionel Landwerlin  ---
Looks like a DRI3 issue. Cc Louis-Francis & Daniel who've worked on this
recently.

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Re: [Mesa-dev] [PATCH 1/2] i965: init image's planar_format in intel_create_image_from_texture

[Jason Ekstrand]

On Thu, Apr 5, 2018 at 8:45 AM, James Xiong  wrote:

> On Thu, 5 Apr 2018 08:24:27 -0700
> Jason Ekstrand  wrote:
>
> > Does this fix a bug?  If so, what?
> Jason, yes. I am sorry for the confusion, please see my earlier reply
> to Tapani.
>

If it fixes a bug then the commit message should include a description of
the bug fixed.  If the bug is a regression, it should have a "Fixes: SHA1"
tag indicating where the regression originated and if it is a bug that has
been around for a very long time, it should have a "Cc:
mesa-sta...@lists.freedesktop.org" tag.  If the bug is filed in bugzilla,
it should have a "Bugzilla: " tag.

--Jason



> >
> > On April 4, 2018 16:57:21 James Xiong  wrote:
> >
> > > From: "Xiong, James" 
> > >
> > > When creating a image from a texture, initialize the image's
> > > planar_format with the texture's.
> > >
> > > Signed-off-by: Xiong, James 
> > > ---
> > > src/mesa/drivers/dri/i965/intel_screen.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> > > b/src/mesa/drivers/dri/i965/intel_screen.c
> > > index dcb98da..7df8bc4 100644
> > > --- a/src/mesa/drivers/dri/i965/intel_screen.c
> > > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > > @@ -578,6 +578,7 @@ intel_create_image_from_texture(__DRIcontext
> > > *context, int target,
> > >intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level,
> > > zoffset); image->dri_format =
> > > driGLFormatToImageFormat(image->format); image->has_depthstencil =
> > > iobj->mt->stencil_mt? true : false;
> > > +   image->planar_format = iobj->planar_format;
> > >if (image->dri_format == MESA_FORMAT_NONE) {
> > >   *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
> > >   free(image);
> > > --
> > > 2.7.4
> > >
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> >
> >
> >
>
>
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Re: [Mesa-dev] [PATCH 1/2] i965: init image's planar_format in intel_create_image_from_texture

[James Xiong]

On Thu, 5 Apr 2018 08:24:27 -0700
Jason Ekstrand  wrote:

> Does this fix a bug?  If so, what?
Jason, yes. I am sorry for the confusion, please see my earlier reply
to Tapani.
> 
> On April 4, 2018 16:57:21 James Xiong  wrote:
> 
> > From: "Xiong, James" 
> >
> > When creating a image from a texture, initialize the image's
> > planar_format with the texture's.
> >
> > Signed-off-by: Xiong, James 
> > ---
> > src/mesa/drivers/dri/i965/intel_screen.c | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
> > b/src/mesa/drivers/dri/i965/intel_screen.c
> > index dcb98da..7df8bc4 100644
> > --- a/src/mesa/drivers/dri/i965/intel_screen.c
> > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > @@ -578,6 +578,7 @@ intel_create_image_from_texture(__DRIcontext
> > *context, int target,
> >intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level,
> > zoffset); image->dri_format =
> > driGLFormatToImageFormat(image->format); image->has_depthstencil =
> > iobj->mt->stencil_mt? true : false;
> > +   image->planar_format = iobj->planar_format;
> >if (image->dri_format == MESA_FORMAT_NONE) {
> >   *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
> >   free(image);
> > --
> > 2.7.4
> >
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev  
> 
> 
> 

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Re: [Mesa-dev] [PATCH 2/2] i965: return the fourcc saved in __DRIimage

[James Xiong]

On Thu, 5 Apr 2018 14:30:02 +0300
Tapani Pälli  wrote:

> On 04/05/2018 02:51 AM, James Xiong wrote:
> > From: "Xiong, James" 
> > 
> > The planar_format in __DRIimage contains the original fourcc
> > used to create the image, if it's set, return the saved fourcc
> > directly; Otherwise fall back to the old way.
> > 
> > Also we should validate the input parameter "value" first as it
> > might be NULL based on the SPEC.
> > 
> > v2: fall back to intel_lookup_fourcc() when planar_format is NULL
> >(by Dongwon & Matt Roper)
> > 
> > Signed-off-by: Xiong, James 
> > ---
> >   src/mesa/drivers/dri/i965/intel_screen.c | 15 ---
> >   1 file changed, 12 insertions(+), 3 deletions(-)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
> > b/src/mesa/drivers/dri/i965/intel_screen.c index 7df8bc4..aeecef3
> > 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c
> > +++ b/src/mesa/drivers/dri/i965/intel_screen.c
> > @@ -388,10 +388,16 @@ intel_image_format_lookup(int fourcc)
> >  return NULL;
> >   }
> >   
> > -static boolean intel_lookup_fourcc(int dri_format, int *fourcc)
> > +static boolean
> > +intel_image_get_fourcc(__DRIimage *image, int *fourcc)
> >   {
> > +   if (image->planar_format) {
> > +  *fourcc = image->planar_format->fourcc;
> > +  return true;
> > +   }
> > +
> >  for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++)
> > {
> > -  if (intel_image_formats[i].planes[0].dri_format ==
> > dri_format) {
> > +  if (intel_image_formats[i].planes[0].dri_format ==
> > image->dri_format) { *fourcc = intel_image_formats[i].fourcc;
> >return true;
> > }
> > @@ -844,6 +850,9 @@ intel_create_image_with_modifiers(__DRIscreen
> > *dri_screen, static GLboolean
> >   intel_query_image(__DRIimage *image, int attrib, int *value)
> >   {
> > +   if (value == NULL)
> > +  return false;
> > +  
> 
> I would remove this check, we've been fine many years without it.
The function spec does say: ",  and  may
be NULL, in which case no value is retrieved."
it's better to stick to it and have an extra check than
segmentation fault, what do you say?
> 
> >  switch (attrib) {
> >  case __DRI_IMAGE_ATTRIB_STRIDE:
> > *value = image->pitch;
> > @@ -870,7 +879,7 @@ intel_query_image(__DRIimage *image, int
> > attrib, int *value) case __DRI_IMAGE_ATTRIB_FD:
> > return !brw_bo_gem_export_to_prime(image->bo, value);
> >  case __DRI_IMAGE_ATTRIB_FOURCC:
> > -  return intel_lookup_fourcc(image->dri_format, value);
> > +  return intel_image_get_fourcc(image, value);
> >  case __DRI_IMAGE_ATTRIB_NUM_PLANES:
> > if (isl_drm_modifier_has_aux(image->modifier)) {
> >assert(!image->planar_format ||
> > image->planar_format->nplanes == 1); 

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Re: [Mesa-dev] [PATCH 0/2] wrong fourcc was returned for imported images

[James Xiong]

On Thu, 5 Apr 2018 15:05:26 +0300
Tapani Pälli  wrote:

> Hi;
> 
> On 04/05/2018 02:51 AM, James Xiong wrote:
> > From: "Xiong, James" 
> > 
> > The importer creates an image out of the imported FOURCC_NV12
> > texture, the image's dri_format is set to R8(same as the first
> > plane's format), when it queries the image's fourcc, mesa goes
> > through intel_image_format table and returns FOURCC_R8.  
> 
> Could you explain the use case a bit, I'm not sure I understand how
> this happens. First someone imports dmabufs, creating EGLImage. Then
> a texture is associated with that (glEGLImageTargetTexture2DOES?), is
> it so that then we create yet another EGLImage from that texture or
> am I completely lost here? :)
> 
Sorry for the confusion. 

What actually happened was the exporter 1) calls eglCreateImageKHR()
to create an image from a NV12 texture, 2) calls
eglExportDMABUFImageQueryMESA() but the fourcc_r8 is returned instead
of fourcc_nv12.

Essentially, image->dri_format is the first plane's format, i.e.
__DRI_IMAGE_FORMAT_R8 in our case, when querying fourcc,
intel_lookup_fourcc() gets the following entry from the table
intel_image_formats:
   { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
instead of the corret one:
   { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2,
 { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
   { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },

To fix this, the image should inherit the texture's planar_format which
contains the original fourcc; When the user application queries the
fourcc, we can return the saved fourcc if planar_format is NULL;
otherwise fallback to the original way to look up the fourcc.

> > The solution is to 1) set the image's planar_format using the
> > texture's in function intel_create_image_from_texture(). 2) when
> > queried, return the saved fourcc@planar_format
> > 
> > Xiong, James (2):
> >i965: init image's planar_format in
> > intel_create_image_from_texture i965: return the fourcc saved in
> > __DRIimage
> > 
> >   src/mesa/drivers/dri/i965/intel_screen.c | 16 +---
> >   1 file changed, 13 insertions(+), 3 deletions(-)
> >   

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Re: [Mesa-dev] [PATCH 3/4] radv: rename radv_cmd_buffer_update_vertex_descriptors()

[Bas Nieuwenhuizen]

On Thu, Apr 5, 2018 at 11:42 AM, Samuel Pitoiset
 wrote:
> ... to radv_flush_vertex_buffers().
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 3ae3e33c3b..05610adee8 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1476,7 +1476,8 @@ radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
>  }
>
>  static void
> -radv_cmd_buffer_update_vertex_descriptors(struct radv_cmd_buffer 
> *cmd_buffer, bool pipeline_is_dirty)
> +radv_flush_vertex_buffers(struct radv_cmd_buffer *cmd_buffer,

Can we keep descriptors in there instead of buffers? To keep it clear
it does nothing with the data?

> + bool pipeline_is_dirty)
>  {
> if ((pipeline_is_dirty ||
> (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&
> @@ -1530,7 +1531,7 @@ radv_cmd_buffer_update_vertex_descriptors(struct 
> radv_cmd_buffer *cmd_buffer, bo
>  static void
>  radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, 
> bool pipeline_is_dirty)
>  {
> -   radv_cmd_buffer_update_vertex_descriptors(cmd_buffer, 
> pipeline_is_dirty);
> +   radv_flush_vertex_buffers(cmd_buffer, pipeline_is_dirty);
> radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_ALL_GRAPHICS);
> radv_flush_constants(cmd_buffer, cmd_buffer->state.pipeline,
>  VK_SHADER_STAGE_ALL_GRAPHICS);
> --
> 2.16.3
>
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Re: [Mesa-dev] [PATCH 1/2] i965: init image's planar_format in intel_create_image_from_texture

[Jason Ekstrand]

Does this fix a bug?  If so, what?

On April 4, 2018 16:57:21 James Xiong  wrote:


From: "Xiong, James" 

When creating a image from a texture, initialize the image's planar_format
with the texture's.

Signed-off-by: Xiong, James 
---
src/mesa/drivers/dri/i965/intel_screen.c | 1 +
1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c

index dcb98da..7df8bc4 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -578,6 +578,7 @@ intel_create_image_from_texture(__DRIcontext *context, 
int target,

   intel_setup_image_from_mipmap_tree(brw, image, iobj->mt, level, zoffset);
   image->dri_format = driGLFormatToImageFormat(image->format);
   image->has_depthstencil = iobj->mt->stencil_mt? true : false;
+   image->planar_format = iobj->planar_format;
   if (image->dri_format == MESA_FORMAT_NONE) {
  *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
  free(image);
--
2.7.4

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Re: [Mesa-dev] [RFC PATCH] nir: extend nir_shader_compiler_options with is_scalar

[Christian Gmeiner]

2018-04-05 16:35 GMT+02:00 Rob Clark :
> I'd vote for PIPE_CAP until there is any place inside nir passes were
> we'd want to do something differently.  Since this is just a decision
> in mesa/st I think a cap makes sense..
>

Makes sense.. will go that route - thanks for your comments!

-- 
greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH] meson: fix megadriver symlinking

[Emil Velikov]

On 4 April 2018 at 18:45, Dylan Baker  wrote:
> Which should be relative instead of absolute.
>
> Fixes: f7f1b30f81e842db6057591470ce3cb6d4fb2795
>("meson: extend install_megadrivers script to handle symmlinking")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105567
> Signed-off-by: Dylan Baker 
> ---
>  bin/install_megadrivers.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/bin/install_megadrivers.py b/bin/install_megadrivers.py
> index 86bfa359188..7931a544bd2 100755
> --- a/bin/install_megadrivers.py
> +++ b/bin/install_megadrivers.py
> @@ -58,7 +58,7 @@ def main():
>  while ext != '.so':
>  if os.path.exists(name):
>  os.unlink(name)
> -os.symlink(driver, name)
> +os.symlink(each, name)
At a later stage, can we update the script to use more obvious names.

As-is patch does the job and is
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH] meson: Set .so version for xa like autotools does

[Emil Velikov]

On 4 April 2018 at 18:58, Dylan Baker  wrote:
> Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc
>("meson: build gallium xa state tracker")
> Signed-off-by: Dylan Baker 

Reviewed-by: Emil Velikov 

Please land this as-is, and take a look at the other bits mentioned below.

Thanks
Emil

Skimming through the other version tags:
 - nine - polish
nine_version = '1.0.0' + remove the .join
 - opencl - bug
the meson icd file has ...so.1.0 whereas the autotools one has ...so.1
 - osmesa - bug
the meson pkg file has 8.0.0 whereas the autotools one has 8
 - xvmc,vdpau - bug
missing the version all together
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Re: [Mesa-dev] [RFC PATCH] nir: extend nir_shader_compiler_options with is_scalar

[Rob Clark]

I'd vote for PIPE_CAP until there is any place inside nir passes were
we'd want to do something differently.  Since this is just a decision
in mesa/st I think a cap makes sense..

On Thu, Apr 5, 2018 at 10:25 AM, Jason Ekstrand  wrote:
> I'm not sure if this should be a NIR compiler option or a PIPE_CAP.  On
> Intel hardware, we have both and we handle it ourselves.
>
>
> On April 4, 2018 23:04:36 Christian Gmeiner 
> wrote:
>
>> As not every (upcoming) backend compiler is happy with
>> nir_lower_xxx_to_scalar lowerings do them only if the backend
>> is scalar (and not vec4) based.
>>
>> Signed-off-by: Christian Gmeiner 
>> ---
>> src/amd/vulkan/radv_shader.c| 1 +
>> src/broadcom/compiler/nir_to_vir.c  | 1 +
>> src/compiler/nir/nir.h  | 3 +++
>> src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
>> src/gallium/drivers/radeonsi/si_get.c   | 1 +
>> src/gallium/drivers/vc4/vc4_program.c   | 1 +
>> src/intel/compiler/brw_compiler.c   | 1 +
>> src/mesa/state_tracker/st_glsl_to_nir.cpp   | 8 ++--
>> 8 files changed, 15 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
>> index 171802eede..22f61cb23d 100644
>> --- a/src/amd/vulkan/radv_shader.c
>> +++ b/src/amd/vulkan/radv_shader.c
>> @@ -49,6 +49,7 @@
>> #include "util/string_buffer.h"
>>
>> static const struct nir_shader_compiler_options nir_options = {
>> +   .is_scalar = true,
>> .vertex_id_zero_based = true,
>> .lower_scmp = true,
>> .lower_flrp32 = true,
>> diff --git a/src/broadcom/compiler/nir_to_vir.c
>> b/src/broadcom/compiler/nir_to_vir.c
>> index 595689d244..b4f29554ac 100644
>> --- a/src/broadcom/compiler/nir_to_vir.c
>> +++ b/src/broadcom/compiler/nir_to_vir.c
>> @@ -1876,6 +1876,7 @@ nir_to_vir(struct v3d_compile *c)
>> }
>>
>> const nir_shader_compiler_options v3d_nir_options = {
>> +.is_scalar = true,
>> .lower_all_io_to_temps = true,
>> .lower_extract_byte = true,
>> .lower_extract_word = true,
>> diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
>> index c676331000..4796e3e88c 100644
>> --- a/src/compiler/nir/nir.h
>> +++ b/src/compiler/nir/nir.h
>> @@ -1883,6 +1883,9 @@ typedef struct nir_shader_compiler_options {
>> */
>>bool native_integers;
>>
>> +   /* Indicates that the hw makes use of a scalar ISA */
>> +   bool is_scalar;
>> +
>>/* Indicates that the driver only has zero-based vertex id */
>>bool vertex_id_zero_based;
>>
>> diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> index 0b637bb99b..a921c14565 100644
>> --- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
>> @@ -47,6 +47,7 @@ static const nir_shader_compiler_options options = {
>> .lower_ldexp = true,
>> .fuse_ffma = true,
>> .native_integers = true,
>> +   .is_scalar = true,
>> .vertex_id_zero_based = true,
>> .lower_extract_byte = true,
>> .lower_extract_word = true,
>> diff --git a/src/gallium/drivers/radeonsi/si_get.c
>> b/src/gallium/drivers/radeonsi/si_get.c
>> index e9657602f3..621ff86814 100644
>> --- a/src/gallium/drivers/radeonsi/si_get.c
>> +++ b/src/gallium/drivers/radeonsi/si_get.c
>> @@ -510,6 +510,7 @@ static const struct nir_shader_compiler_options
>> nir_options = {
>> .lower_unpack_unorm_4x8 = true,
>> .lower_extract_byte = true,
>> .lower_extract_word = true,
>> +   .is_scalar = true,
>> .max_unroll_iterations = 32,
>> .native_integers = true,
>> };
>> diff --git a/src/gallium/drivers/vc4/vc4_program.c
>> b/src/gallium/drivers/vc4/vc4_program.c
>> index be80a851d2..1d7d0bdb0a 100644
>> --- a/src/gallium/drivers/vc4/vc4_program.c
>> +++ b/src/gallium/drivers/vc4/vc4_program.c
>> @@ -2191,6 +2191,7 @@ static const nir_shader_compiler_options nir_options
>> = {
>> .lower_ldexp = true,
>> .lower_negate = true,
>> .native_integers = true,
>> +.is_scalar = true,
>> .max_unroll_iterations = 32,
>> };
>>
>> diff --git a/src/intel/compiler/brw_compiler.c
>> b/src/intel/compiler/brw_compiler.c
>> index 9340317492..9794362f5d 100644
>> --- a/src/intel/compiler/brw_compiler.c
>> +++ b/src/intel/compiler/brw_compiler.c
>> @@ -57,6 +57,7 @@
>>.lower_unpack_snorm_4x8 = true,
>> \
>>.lower_unpack_unorm_2x16 = true,
>> \
>>.lower_unpack_unorm_4x8 = true,
>> \
>> +   .is_scalar = true,
>> \
>>.vs_inputs_dual_locations = true,
>> \
>>.max_unroll_iterations = 32
>>
>> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
>> b/src/mesa/state_tracker/st_glsl_to_nir.cpp
>> index 0bd9c4e4e3..9fd64166ae 100644
>> --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
>> +++ 

Re: [Mesa-dev] [PATCH] loader: disable virgl driver when no 3D for virtio

[Emil Velikov]

On 5 April 2018 at 14:45, Ilia Mirkin  wrote:
> Shouldn't this just be handled as in, e.g.,
>
> https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c#n97
>
> i.e. return an error in the driver-specific loader? This create
> function should fail:
>
> https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c#n897
>
Indeed. The radeon and amdgpu drivers also use a similar approach.
Be that to check if the kernel module is too old, or a required
feature is missing.

Keeping the ioctl in virgl_drm_winsys_create, alongside it's brethren
would help with consistency.

-Emil
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Re: [Mesa-dev] [PATCH kmscube 2/4] Pass struct drm to init_gbm()

[Christian Gmeiner]

2018-04-05 15:44 GMT+02:00 Thierry Reding :
> From: Thierry Reding 
>
> This helps cut down on the number of parameters that we need to pass
> around. Subsequent patches will also add more data to struct drm that
> init_gbm() needs to access, so passing in the struct make sure these
> will be available.
>
> Based on work by Lucas Stach .
>
> Signed-off-by: Thierry Reding 

Reviewed-by: Christian Gmeiner 

> ---
>  common.c  | 22 +++---
>  common.h  |  4 ++--
>  kmscube.c |  3 +--
>  3 files changed, 14 insertions(+), 15 deletions(-)
>
> diff --git a/common.c b/common.c
> index faecd4215039..3dcd9bd3d8f4 100644
> --- a/common.c
> +++ b/common.c
> @@ -30,6 +30,7 @@
>  #include 
>
>  #include "common.h"
> +#include "drm-common.h"
>
>  static struct gbm gbm;
>
> @@ -40,25 +41,24 @@ gbm_surface_create_with_modifiers(struct gbm_device *gbm,
>const uint64_t *modifiers,
>const unsigned int count);
>
> -const struct gbm * init_gbm(int drm_fd, int w, int h, uint64_t modifier)
> +const struct gbm * init_gbm(const struct drm *drm, uint64_t modifier)
>  {

Just an idea:
To keep the diffstat smaller it could may help to create local vars like

int w = drm->mode->hdisplay;
int h = drm->mode->vdisplay;

> -   gbm.dev = gbm_create_device(drm_fd);
> +   gbm.dev = gbm_create_device(drm->fd);
> gbm.format = GBM_FORMAT_XRGB;
>
> if (gbm_surface_create_with_modifiers) {
> -   gbm.surface = gbm_surface_create_with_modifiers(gbm.dev, w, h,
> -   gbm.format,
> -   , 1);
> -
> +   gbm.surface = gbm_surface_create_with_modifiers(gbm.dev,
> +   drm->mode->hdisplay, drm->mode->vdisplay,
> +   gbm.format, , 1);
> } else {
> if (modifier != DRM_FORMAT_MOD_LINEAR) {
> fprintf(stderr, "Modifiers requested but support 
> isn't available\n");
> return NULL;
> }
> -   gbm.surface = gbm_surface_create(gbm.dev, w, h,
> -   gbm.format,
> -   GBM_BO_USE_SCANOUT | 
> GBM_BO_USE_RENDERING);
>
> +   gbm.surface = gbm_surface_create(gbm.dev, drm->mode->hdisplay,
> +   drm->mode->vdisplay, gbm.format,
> +   GBM_BO_USE_SCANOUT | GBM_BO_USE_RENDERING);
> }
>
> if (!gbm.surface) {
> @@ -66,8 +66,8 @@ const struct gbm * init_gbm(int drm_fd, int w, int h, 
> uint64_t modifier)
> return NULL;
> }
>
> -   gbm.width = w;
> -   gbm.height = h;
> +   gbm.width = drm->mode->hdisplay;
> +   gbm.height = drm->mode->vdisplay;
>
> return 
>  }
> diff --git a/common.h b/common.h
> index 898010dd546f..8ff1ed3a6aa3 100644
> --- a/common.h
> +++ b/common.h
> @@ -83,8 +83,8 @@ struct gbm {
> int width, height;
>  };
>
> -const struct gbm * init_gbm(int drm_fd, int w, int h, uint64_t modifier);
> -
> +struct drm;
> +const struct gbm *init_gbm(const struct drm *drm, uint64_t modifier);
>
>  struct egl {
> EGLDisplay display;
> diff --git a/kmscube.c b/kmscube.c
> index 87a4205ddc20..b05e57df7faf 100644
> --- a/kmscube.c
> +++ b/kmscube.c
> @@ -130,8 +130,7 @@ int main(int argc, char *argv[])
> return -1;
> }
>
> -   gbm = init_gbm(drm->fd, drm->mode->hdisplay, drm->mode->vdisplay,
> -   modifier);
> +   gbm = init_gbm(drm, modifier);
> if (!gbm) {
> printf("failed to initialize GBM\n");
> return -1;
> --
> 2.16.3
>
> ___
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> mesa-dev@lists.freedesktop.org
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--
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Re: [Mesa-dev] [RFC PATCH] nir: extend nir_shader_compiler_options with is_scalar

[Jason Ekstrand]

I'm not sure if this should be a NIR compiler option or a PIPE_CAP.  On 
Intel hardware, we have both and we handle it ourselves.


On April 4, 2018 23:04:36 Christian Gmeiner  
wrote:



As not every (upcoming) backend compiler is happy with
nir_lower_xxx_to_scalar lowerings do them only if the backend
is scalar (and not vec4) based.

Signed-off-by: Christian Gmeiner 
---
src/amd/vulkan/radv_shader.c| 1 +
src/broadcom/compiler/nir_to_vir.c  | 1 +
src/compiler/nir/nir.h  | 3 +++
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 +
src/gallium/drivers/radeonsi/si_get.c   | 1 +
src/gallium/drivers/vc4/vc4_program.c   | 1 +
src/intel/compiler/brw_compiler.c   | 1 +
src/mesa/state_tracker/st_glsl_to_nir.cpp   | 8 ++--
8 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 171802eede..22f61cb23d 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -49,6 +49,7 @@
#include "util/string_buffer.h"

static const struct nir_shader_compiler_options nir_options = {
+   .is_scalar = true,
.vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp32 = true,
diff --git a/src/broadcom/compiler/nir_to_vir.c 
b/src/broadcom/compiler/nir_to_vir.c

index 595689d244..b4f29554ac 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -1876,6 +1876,7 @@ nir_to_vir(struct v3d_compile *c)
}

const nir_shader_compiler_options v3d_nir_options = {
+.is_scalar = true,
.lower_all_io_to_temps = true,
.lower_extract_byte = true,
.lower_extract_word = true,
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index c676331000..4796e3e88c 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1883,6 +1883,9 @@ typedef struct nir_shader_compiler_options {
*/
   bool native_integers;

+   /* Indicates that the hw makes use of a scalar ISA */
+   bool is_scalar;
+
   /* Indicates that the driver only has zero-based vertex id */
   bool vertex_id_zero_based;

diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c 
b/src/gallium/drivers/freedreno/ir3/ir3_nir.c

index 0b637bb99b..a921c14565 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
@@ -47,6 +47,7 @@ static const nir_shader_compiler_options options = {
.lower_ldexp = true,
.fuse_ffma = true,
.native_integers = true,
+   .is_scalar = true,
.vertex_id_zero_based = true,
.lower_extract_byte = true,
.lower_extract_word = true,
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c

index e9657602f3..621ff86814 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -510,6 +510,7 @@ static const struct nir_shader_compiler_options 
nir_options = {

.lower_unpack_unorm_4x8 = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+   .is_scalar = true,
.max_unroll_iterations = 32,
.native_integers = true,
};
diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c

index be80a851d2..1d7d0bdb0a 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -2191,6 +2191,7 @@ static const nir_shader_compiler_options nir_options = {
.lower_ldexp = true,
.lower_negate = true,
.native_integers = true,
+.is_scalar = true,
.max_unroll_iterations = 32,
};

diff --git a/src/intel/compiler/brw_compiler.c 
b/src/intel/compiler/brw_compiler.c

index 9340317492..9794362f5d 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -57,6 +57,7 @@
   .lower_unpack_snorm_4x8 = true,\
   .lower_unpack_unorm_2x16 = true,   \
   .lower_unpack_unorm_4x8 = true,\
+   .is_scalar = true,  
   \

   .vs_inputs_dual_locations = true,  \
   .max_unroll_iterations = 32

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp

index 0bd9c4e4e3..9fd64166ae 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -262,13 +262,17 @@ st_nir_assign_uniform_locations(struct gl_program *prog,
static void
st_nir_opts(nir_shader *nir)
{
+   const struct nir_shader_compiler_options *options = nir->options;
   bool progress;
   do {
  progress = false;

  NIR_PASS_V(nir, nir_lower_vars_to_ssa);
-  NIR_PASS_V(nir, nir_lower_alu_to_scalar);
-  

Re: [Mesa-dev] [PATCH kmscube 1/4] drm-atomic: Fix indentation

[Christian Gmeiner]

2018-04-05 15:44 GMT+02:00 Thierry Reding :
> From: Thierry Reding 
>
> One of the error returns ended up being indented twice. Fix it.
>
> Signed-off-by: Thierry Reding 

Reviewed-by: Christian Gmeiner 

> ---
>  drm-atomic.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drm-atomic.c b/drm-atomic.c
> index 82531d346d73..99ac33d6a686 100644
> --- a/drm-atomic.c
> +++ b/drm-atomic.c
> @@ -116,7 +116,7 @@ static int drm_atomic_commit(uint32_t fb_id, uint32_t 
> flags)
> if (flags & DRM_MODE_ATOMIC_ALLOW_MODESET) {
> if (add_connector_property(req, drm.connector_id, "CRTC_ID",
> drm.crtc_id) < 0)
> -   return -1;
> +   return -1;
>
> if (drmModeCreatePropertyBlob(drm.fd, drm.mode, 
> sizeof(*drm.mode),
>   _id) != 0)
> --
> 2.16.3
>
> ___
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--
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Re: [Mesa-dev] [PATCH kmscube 3/4] Automatically select modifiers

[Emil Velikov]

On 5 April 2018 at 14:44, Thierry Reding  wrote:
> From: Thierry Reding 
>
> If available, use the formats/modifiers blob from a DRM/KMS device to
> automatically detect which modifiers to use. In the absence of the blob,
> leave it up to the implementation to choose an appropriate format.
>
> Based on work by Lucas Stach .
>
> Signed-off-by: Thierry Reding 
> ---
>  common.c | 10 +
>  common.h |  2 +-
>  drm-atomic.c | 70 
> +++-
>  drm-common.h |  5 -
>  kmscube.c|  8 +--
>  5 files changed, 86 insertions(+), 9 deletions(-)
>
> diff --git a/common.c b/common.c
> index 3dcd9bd3d8f4..a886962ea7b1 100644
> --- a/common.c
> +++ b/common.c
> @@ -41,17 +41,19 @@ gbm_surface_create_with_modifiers(struct gbm_device *gbm,
>const uint64_t *modifiers,
>const unsigned int count);
>
> -const struct gbm * init_gbm(const struct drm *drm, uint64_t modifier)
> +const struct gbm * init_gbm(const struct drm *drm)
>  {
> gbm.dev = gbm_create_device(drm->fd);
> gbm.format = GBM_FORMAT_XRGB;
>
> -   if (gbm_surface_create_with_modifiers) {
> +   if (gbm_surface_create_with_modifiers && drm->num_modifiers > 0) {
> gbm.surface = gbm_surface_create_with_modifiers(gbm.dev,
> drm->mode->hdisplay, drm->mode->vdisplay,
> -   gbm.format, , 1);
> +   gbm.format, drm->modifiers,
> +   drm->num_modifiers);
> } else {
> -   if (modifier != DRM_FORMAT_MOD_LINEAR) {
> +   if (drm->num_modifiers > 0 &&
> +   drm->modifiers[0] != DRM_FORMAT_MOD_LINEAR) {
> fprintf(stderr, "Modifiers requested but support 
> isn't available\n");
> return NULL;
> }
> diff --git a/common.h b/common.h
> index 8ff1ed3a6aa3..bed316786557 100644
> --- a/common.h
> +++ b/common.h
> @@ -84,7 +84,7 @@ struct gbm {
>  };
>
>  struct drm;
> -const struct gbm *init_gbm(const struct drm *drm, uint64_t modifier);
> +const struct gbm *init_gbm(const struct drm *drm);
>
>  struct egl {
> EGLDisplay display;
> diff --git a/drm-atomic.c b/drm-atomic.c
> index 99ac33d6a686..a68f036a9aab 100644
> --- a/drm-atomic.c
> +++ b/drm-atomic.c
> @@ -337,7 +337,66 @@ static int get_plane_id(void)
> return ret;
>  }
>
> -const struct drm * init_drm_atomic(const char *device)
> +static unsigned int
> +get_modifiers(drmModePropertyBlobPtr blob, struct drm_format_modifier 
> **modsp)
> +{
> +   struct drm_format_modifier_blob *data = blob->data;
> +
> +   *modsp = blob->data + data->modifiers_offset;
> +
> +   return data->count_modifiers;
> +}
> +
> +static int
> +drm_atomic_get_modifiers(struct drm *drm)
> +{
> +   unsigned int i, j, format_index = 0;
> +
> +   for (i = 0; i < drm->plane->plane->count_formats; i++) {
> +   if (drm->plane->plane->formats[i] == DRM_FORMAT_XRGB)
Use gbm.format? The {DRM,GBM}_FORMAT defines are identical.

> +   format_index = i;
Shouldn't we bail out if no plane has the requested format?


> @@ -402,6 +464,12 @@ const struct drm * init_drm_atomic(const char *device)
> get_properties(crtc, CRTC, drm.crtc_id);
> get_properties(connector, CONNECTOR, drm.connector_id);
>
> +   if (num_modifiers == 0) {
> +   ret = drm_atomic_get_modifiers();
> +   if (ret < 0)
> +   return NULL;
Just print an {info,error} message and continue. As-is this will break
the (very odd) legacy case.

With the above suggestions (or some clarification) the series is
Reviewed-by: Emil Velikov 

-Emil
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Re: [Mesa-dev] [PATCH] loader: disable virgl driver when no 3D for virtio

[Ilia Mirkin]

Shouldn't this just be handled as in, e.g.,

https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/winsys/nouveau/drm/nouveau_drm_winsys.c#n97

i.e. return an error in the driver-specific loader? This create
function should fail:

https://cgit.freedesktop.org/mesa/mesa/tree/src/gallium/winsys/virgl/drm/virgl_drm_winsys.c#n897

On Thu, Apr 5, 2018 at 1:16 AM, Lepton Wu  wrote:
> If user are running mesa under old version of qemu or have turned off
> GL at runtime, virtio gpu driver actually doesn't work. Adding a detection
> here can make sure same disk image work with both cases.
>
> Signed-off-by: Lepton Wu 
> ---
>  src/loader/loader.c | 21 +
>  1 file changed, 21 insertions(+)
>
> diff --git a/src/loader/loader.c b/src/loader/loader.c
> index 43275484cc..2a689c52d6 100644
> --- a/src/loader/loader.c
> +++ b/src/loader/loader.c
> @@ -381,6 +381,27 @@ out:
> log_(driver ? _LOADER_DEBUG : _LOADER_WARNING,
>   "pci id for fd %d: %04x:%04x, driver %s\n",
>   fd, vendor_id, chip_id, driver);
> +   if (!strcmp(driver, "virtio_gpu")) {
> +  struct drm_virtgpu_getparam {
> + uint64_t param;
> + uint64_t value;
> +  };
> +  #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the 
> hw */
> +  struct drm_virtgpu_getparam args;
> +  uint32_t gl = 0;
> +  args.param = VIRTGPU_PARAM_3D_FEATURES;
> +  args.value = (uint64_t)(uintptr_t)
> +  #define DRM_VIRTGPU_GETPARAM0x03
> +  #define DRM_IOCTL_VIRTGPU_GETPARAM \
> + DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\
> +  struct drm_virtgpu_getparam)
> +  int ret = drmIoctl(fd, DRM_IOCTL_VIRTGPU_GETPARAM, );
> +  if (ret || !gl) {
> + /* Actually there is no virtio_2d driver, mesa will
> +  * fallback to software driver */
> + return strdup("virtio_gpu_2d");
> +  }
> +   }
> return driver;
>  }
>
> --
> 2.17.0.484.g0c8726318c-goog
>
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[Mesa-dev] [PATCH kmscube 3/4] Automatically select modifiers

[Thierry Reding]

From: Thierry Reding 

If available, use the formats/modifiers blob from a DRM/KMS device to
automatically detect which modifiers to use. In the absence of the blob,
leave it up to the implementation to choose an appropriate format.

Based on work by Lucas Stach .

Signed-off-by: Thierry Reding 
---
 common.c | 10 +
 common.h |  2 +-
 drm-atomic.c | 70 +++-
 drm-common.h |  5 -
 kmscube.c|  8 +--
 5 files changed, 86 insertions(+), 9 deletions(-)

diff --git a/common.c b/common.c
index 3dcd9bd3d8f4..a886962ea7b1 100644
--- a/common.c
+++ b/common.c
@@ -41,17 +41,19 @@ gbm_surface_create_with_modifiers(struct gbm_device *gbm,
   const uint64_t *modifiers,
   const unsigned int count);
 
-const struct gbm * init_gbm(const struct drm *drm, uint64_t modifier)
+const struct gbm * init_gbm(const struct drm *drm)
 {
gbm.dev = gbm_create_device(drm->fd);
gbm.format = GBM_FORMAT_XRGB;
 
-   if (gbm_surface_create_with_modifiers) {
+   if (gbm_surface_create_with_modifiers && drm->num_modifiers > 0) {
gbm.surface = gbm_surface_create_with_modifiers(gbm.dev,
drm->mode->hdisplay, drm->mode->vdisplay,
-   gbm.format, , 1);
+   gbm.format, drm->modifiers,
+   drm->num_modifiers);
} else {
-   if (modifier != DRM_FORMAT_MOD_LINEAR) {
+   if (drm->num_modifiers > 0 &&
+   drm->modifiers[0] != DRM_FORMAT_MOD_LINEAR) {
fprintf(stderr, "Modifiers requested but support isn't 
available\n");
return NULL;
}
diff --git a/common.h b/common.h
index 8ff1ed3a6aa3..bed316786557 100644
--- a/common.h
+++ b/common.h
@@ -84,7 +84,7 @@ struct gbm {
 };
 
 struct drm;
-const struct gbm *init_gbm(const struct drm *drm, uint64_t modifier);
+const struct gbm *init_gbm(const struct drm *drm);
 
 struct egl {
EGLDisplay display;
diff --git a/drm-atomic.c b/drm-atomic.c
index 99ac33d6a686..a68f036a9aab 100644
--- a/drm-atomic.c
+++ b/drm-atomic.c
@@ -337,7 +337,66 @@ static int get_plane_id(void)
return ret;
 }
 
-const struct drm * init_drm_atomic(const char *device)
+static unsigned int
+get_modifiers(drmModePropertyBlobPtr blob, struct drm_format_modifier **modsp)
+{
+   struct drm_format_modifier_blob *data = blob->data;
+
+   *modsp = blob->data + data->modifiers_offset;
+
+   return data->count_modifiers;
+}
+
+static int
+drm_atomic_get_modifiers(struct drm *drm)
+{
+   unsigned int i, j, format_index = 0;
+
+   for (i = 0; i < drm->plane->plane->count_formats; i++) {
+   if (drm->plane->plane->formats[i] == DRM_FORMAT_XRGB)
+   format_index = i;
+   }
+
+   for (i = 0; i < drm->plane->props->count_props; i++) {
+   if (!strcmp(drm->plane->props_info[i]->name, "IN_FORMATS")) {
+   struct drm_format_modifier *mods;
+   drmModePropertyBlobPtr blob;
+   unsigned int count;
+
+   blob = drmModeGetPropertyBlob(drm->fd,
+ 
drm->plane->props->prop_values[i]);
+   if (!blob) {
+   printf("failed to get blob for property %s\n",
+  drm->plane->props_info[i]->name);
+   return -ENOMEM;
+   }
+
+   count = get_modifiers(blob, );
+
+   for (j = 0; j < count; j++) {
+   if (mods[j].formats & (1ULL << format_index))
+   drm->num_modifiers++;
+   }
+
+   drm->modifiers = calloc(drm->num_modifiers,
+   sizeof(uint64_t));
+   if (!drm->modifiers) {
+   printf("failed to allocate modifiers\n");
+   return -ENOMEM;
+   }
+
+   for (j = 0; j < count; j++) {
+   if (mods[j].formats & (1ULL << format_index))
+   drm->modifiers[j] = mods[j].modifier;
+   }
+   }
+   }
+
+   return 0;
+}
+
+const struct drm *init_drm_atomic(const char *device, uint64_t *modifiers,
+ unsigned int num_modifiers)
 {
uint32_t plane_id;
int ret;
@@ -346,6 +405,9 @@ const struct drm * init_drm_atomic(const char *device)
if (ret)
return NULL;
 
+   drm.num_modifiers = num_modifiers;
+   

[Mesa-dev] [PATCH kmscube 4/4] drm-atomic: Implement user interruption

[Thierry Reding]

From: Thierry Reding 

In legacy mode, the user can interrupt kmscube by pressing the return
key. Implement the same behaviour for atomic mode.

Signed-off-by: Thierry Reding 
---
 drm-atomic.c | 25 +
 1 file changed, 25 insertions(+)

diff --git a/drm-atomic.c b/drm-atomic.c
index a68f036a9aab..30f978e1d873 100644
--- a/drm-atomic.c
+++ b/drm-atomic.c
@@ -27,6 +27,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "common.h"
 #include "drm-common.h"
@@ -179,6 +180,8 @@ static int atomic_run(const struct gbm *gbm, const struct 
egl *egl)
struct drm_fb *fb;
uint32_t i = 0;
uint32_t flags = DRM_MODE_ATOMIC_NONBLOCK;
+   struct timeval timeout;
+   fd_set fds;
int ret;
 
if (egl_check(egl, eglDupNativeFenceFDANDROID) ||
@@ -274,6 +277,28 @@ static int atomic_run(const struct gbm *gbm, const struct 
egl *egl)
 
/* Allow a modeset change for the first commit only. */
flags &= ~(DRM_MODE_ATOMIC_ALLOW_MODESET);
+
+   /* watch for user interruption */
+   FD_ZERO();
+   FD_SET(0, );
+   memset(, 0, sizeof(timeout));
+
+   ret = select(1, , NULL, NULL, );
+   if (ret < 0) {
+   printf("select() failed: %s\n", strerror(errno));
+   break;
+   }
+
+   /*
+* select() will immediately timeout if there was no user
+* interrupt because of the 0 timeout. However, that's an
+* expected situation, not an error, so we just ignore it
+* here.
+*/
+   if (FD_ISSET(0, )) {
+   printf("user interrupted!\n");
+   break;
+   }
}
 
return ret;
-- 
2.16.3

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[Mesa-dev] [PATCH kmscube 2/4] Pass struct drm to init_gbm()

[Thierry Reding]

From: Thierry Reding 

This helps cut down on the number of parameters that we need to pass
around. Subsequent patches will also add more data to struct drm that
init_gbm() needs to access, so passing in the struct make sure these
will be available.

Based on work by Lucas Stach .

Signed-off-by: Thierry Reding 
---
 common.c  | 22 +++---
 common.h  |  4 ++--
 kmscube.c |  3 +--
 3 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/common.c b/common.c
index faecd4215039..3dcd9bd3d8f4 100644
--- a/common.c
+++ b/common.c
@@ -30,6 +30,7 @@
 #include 
 
 #include "common.h"
+#include "drm-common.h"
 
 static struct gbm gbm;
 
@@ -40,25 +41,24 @@ gbm_surface_create_with_modifiers(struct gbm_device *gbm,
   const uint64_t *modifiers,
   const unsigned int count);
 
-const struct gbm * init_gbm(int drm_fd, int w, int h, uint64_t modifier)
+const struct gbm * init_gbm(const struct drm *drm, uint64_t modifier)
 {
-   gbm.dev = gbm_create_device(drm_fd);
+   gbm.dev = gbm_create_device(drm->fd);
gbm.format = GBM_FORMAT_XRGB;
 
if (gbm_surface_create_with_modifiers) {
-   gbm.surface = gbm_surface_create_with_modifiers(gbm.dev, w, h,
-   gbm.format,
-   , 1);
-
+   gbm.surface = gbm_surface_create_with_modifiers(gbm.dev,
+   drm->mode->hdisplay, drm->mode->vdisplay,
+   gbm.format, , 1);
} else {
if (modifier != DRM_FORMAT_MOD_LINEAR) {
fprintf(stderr, "Modifiers requested but support isn't 
available\n");
return NULL;
}
-   gbm.surface = gbm_surface_create(gbm.dev, w, h,
-   gbm.format,
-   GBM_BO_USE_SCANOUT | 
GBM_BO_USE_RENDERING);
 
+   gbm.surface = gbm_surface_create(gbm.dev, drm->mode->hdisplay,
+   drm->mode->vdisplay, gbm.format,
+   GBM_BO_USE_SCANOUT | GBM_BO_USE_RENDERING);
}
 
if (!gbm.surface) {
@@ -66,8 +66,8 @@ const struct gbm * init_gbm(int drm_fd, int w, int h, 
uint64_t modifier)
return NULL;
}
 
-   gbm.width = w;
-   gbm.height = h;
+   gbm.width = drm->mode->hdisplay;
+   gbm.height = drm->mode->vdisplay;
 
return 
 }
diff --git a/common.h b/common.h
index 898010dd546f..8ff1ed3a6aa3 100644
--- a/common.h
+++ b/common.h
@@ -83,8 +83,8 @@ struct gbm {
int width, height;
 };
 
-const struct gbm * init_gbm(int drm_fd, int w, int h, uint64_t modifier);
-
+struct drm;
+const struct gbm *init_gbm(const struct drm *drm, uint64_t modifier);
 
 struct egl {
EGLDisplay display;
diff --git a/kmscube.c b/kmscube.c
index 87a4205ddc20..b05e57df7faf 100644
--- a/kmscube.c
+++ b/kmscube.c
@@ -130,8 +130,7 @@ int main(int argc, char *argv[])
return -1;
}
 
-   gbm = init_gbm(drm->fd, drm->mode->hdisplay, drm->mode->vdisplay,
-   modifier);
+   gbm = init_gbm(drm, modifier);
if (!gbm) {
printf("failed to initialize GBM\n");
return -1;
-- 
2.16.3

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[Mesa-dev] [PATCH kmscube 1/4] drm-atomic: Fix indentation

[Thierry Reding]

From: Thierry Reding 

One of the error returns ended up being indented twice. Fix it.

Signed-off-by: Thierry Reding 
---
 drm-atomic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drm-atomic.c b/drm-atomic.c
index 82531d346d73..99ac33d6a686 100644
--- a/drm-atomic.c
+++ b/drm-atomic.c
@@ -116,7 +116,7 @@ static int drm_atomic_commit(uint32_t fb_id, uint32_t flags)
if (flags & DRM_MODE_ATOMIC_ALLOW_MODESET) {
if (add_connector_property(req, drm.connector_id, "CRTC_ID",
drm.crtc_id) < 0)
-   return -1;
+   return -1;
 
if (drmModeCreatePropertyBlob(drm.fd, drm.mode, 
sizeof(*drm.mode),
  _id) != 0)
-- 
2.16.3

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[Mesa-dev] [Bug 105901] Warn about mipmap-incomplete texture being used

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105901

--- Comment #2 from Brian Paul  ---
With a debug build of Mesa if you set the MESA_DEBUG env var to
"incomplete_tex" you'll get a warning.  This predates the GL_ARB_debug_output
extension.

It shouldn't be hard to go into the incomplete() function in texobj.c and have
it call _mesa_log_msg() so the incomplete texture gets reported via
GL_ARB_debug_output.

Want to take a stab at it?

We should do the same for FBOs.

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Re: [Mesa-dev] [PATCH] meson: Set .so version for xa like autotools does

[Eric Engestrom]

On Wednesday, 2018-04-04 10:58:29 -0700, Dylan Baker wrote:
> Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc
>("meson: build gallium xa state tracker")
> Signed-off-by: Dylan Baker 

Reviewed-by: Eric Engestrom 

> ---
>  src/gallium/targets/xa/meson.build | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/src/gallium/targets/xa/meson.build 
> b/src/gallium/targets/xa/meson.build
> index ea6e1296dae..733ef54ff85 100644
> --- a/src/gallium/targets/xa/meson.build
> +++ b/src/gallium/targets/xa/meson.build
> @@ -30,6 +30,7 @@ if with_ld_version_script
>xa_link_depends += files('xa.sym')
>  endif
>  
> +_xa_version = '.'.join(xa_version)
>  
>  libxatracker = shared_library(
>'xatracker',
> @@ -49,12 +50,13 @@ libxatracker = shared_library(
>dependencies : [
>  dep_thread, driver_nouveau, driver_i915, driver_svga, driver_freedreno,
>],
> +  version : _xa_version,
>install : true,
>  )
>  
>  pkg.generate(
>name : 'xatracker',
>description : 'Xorg gallium3D acceleration library',
> -  version : '.'.join(xa_version),
> +  version : _xa_version,
>libraries : libxatracker,
>  )
> -- 
> 2.16.3
> 
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Re: [Mesa-dev] [PATCH] meson: fix megadriver symlinking

[Eric Engestrom]

On Wednesday, 2018-04-04 10:45:26 -0700, Dylan Baker wrote:
> Which should be relative instead of absolute.
> 
> Fixes: f7f1b30f81e842db6057591470ce3cb6d4fb2795
>("meson: extend install_megadrivers script to handle symmlinking")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105567
> Signed-off-by: Dylan Baker 

Been using that locally for a couple months:
Reviewed-and-Tested-by: Eric Engestrom 

> ---
>  bin/install_megadrivers.py | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/bin/install_megadrivers.py b/bin/install_megadrivers.py
> index 86bfa359188..7931a544bd2 100755
> --- a/bin/install_megadrivers.py
> +++ b/bin/install_megadrivers.py
> @@ -58,7 +58,7 @@ def main():
>  while ext != '.so':
>  if os.path.exists(name):
>  os.unlink(name)
> -os.symlink(driver, name)
> +os.symlink(each, name)
>  name, ext = os.path.splitext(name)
>  finally:
>  os.chdir(ret)
> -- 
> 2.16.3
> 
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Re: [Mesa-dev] [PATCH 0/2] wrong fourcc was returned for imported images

[Tapani Pälli]

Hi;

On 04/05/2018 02:51 AM, James Xiong wrote:

From: "Xiong, James" 

The importer creates an image out of the imported FOURCC_NV12 texture,
the image's dri_format is set to R8(same as the first plane's format),
when it queries the image's fourcc, mesa goes through intel_image_format
table and returns FOURCC_R8.


Could you explain the use case a bit, I'm not sure I understand how this 
happens. First someone imports dmabufs, creating EGLImage. Then a 
texture is associated with that (glEGLImageTargetTexture2DOES?), is it 
so that then we create yet another EGLImage from that texture or am I 
completely lost here? :)



The solution is to 1) set the image's planar_format using the texture's in
function intel_create_image_from_texture(). 2) when queried, return the
saved fourcc@planar_format

Xiong, James (2):
   i965: init image's planar_format in intel_create_image_from_texture
   i965: return the fourcc saved in __DRIimage

  src/mesa/drivers/dri/i965/intel_screen.c | 16 +---
  1 file changed, 13 insertions(+), 3 deletions(-)


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[Mesa-dev] [Bug 105904] Needed to delete mesa shader cache after driver upgrade for 32 bit wine vulkan programs to work.

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=105904

Bug ID: 105904
   Summary: Needed to delete mesa shader cache after driver
upgrade for 32 bit wine vulkan programs to work.
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: normal
  Priority: medium
 Component: Drivers/Vulkan/radeon
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: daniel.sim...@home.se
QA Contact: mesa-dev@lists.freedesktop.org

After driver update to 18.1~git1804050730.8cd58d~oibaf~b from oibafs ubuntu
repo my 32 bit game that i run with dxvk stopped working.
I tried 64 bit cube.exe from LunarG VulkanSDK which worked, 32 bit cube.exe
from the same SDK didn't work.

Manually deleting shader cache made 32 bit cube.exe and game running with dxvk
work.

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Re: [Mesa-dev] [PATCH 2/2] i965: return the fourcc saved in __DRIimage

[Tapani Pälli]

On 04/05/2018 02:51 AM, James Xiong wrote:

From: "Xiong, James" 

The planar_format in __DRIimage contains the original fourcc
used to create the image, if it's set, return the saved fourcc
directly; Otherwise fall back to the old way.

Also we should validate the input parameter "value" first as it
might be NULL based on the SPEC.

v2: fall back to intel_lookup_fourcc() when planar_format is NULL
   (by Dongwon & Matt Roper)

Signed-off-by: Xiong, James 
---
  src/mesa/drivers/dri/i965/intel_screen.c | 15 ---
  1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 7df8bc4..aeecef3 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -388,10 +388,16 @@ intel_image_format_lookup(int fourcc)
 return NULL;
  }
  
-static boolean intel_lookup_fourcc(int dri_format, int *fourcc)

+static boolean
+intel_image_get_fourcc(__DRIimage *image, int *fourcc)
  {
+   if (image->planar_format) {
+  *fourcc = image->planar_format->fourcc;
+  return true;
+   }
+
 for (unsigned i = 0; i < ARRAY_SIZE(intel_image_formats); i++) {
-  if (intel_image_formats[i].planes[0].dri_format == dri_format) {
+  if (intel_image_formats[i].planes[0].dri_format == image->dri_format) {
   *fourcc = intel_image_formats[i].fourcc;
   return true;
}
@@ -844,6 +850,9 @@ intel_create_image_with_modifiers(__DRIscreen *dri_screen,
  static GLboolean
  intel_query_image(__DRIimage *image, int attrib, int *value)
  {
+   if (value == NULL)
+  return false;
+


I would remove this check, we've been fine many years without it.


 switch (attrib) {
 case __DRI_IMAGE_ATTRIB_STRIDE:
*value = image->pitch;
@@ -870,7 +879,7 @@ intel_query_image(__DRIimage *image, int attrib, int *value)
 case __DRI_IMAGE_ATTRIB_FD:
return !brw_bo_gem_export_to_prime(image->bo, value);
 case __DRI_IMAGE_ATTRIB_FOURCC:
-  return intel_lookup_fourcc(image->dri_format, value);
+  return intel_image_get_fourcc(image, value);
 case __DRI_IMAGE_ATTRIB_NUM_PLANES:
if (isl_drm_modifier_has_aux(image->modifier)) {
   assert(!image->planar_format || image->planar_format->nplanes == 1);


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Re: [Mesa-dev] [PATCH] radv: enable the Polaris small primitive filter control

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Thu, Apr 5, 2018 at 10:27 AM, Samuel Pitoiset
 wrote:
> Enable it directly in the preamble, but do not enable line
> on Polaris10/11/12 because there is a hw bug.
>
> There is possibly an issue when MSAA is off, but this doesn't
> regress any CTS and AMDVLK doesn't have a workaround as well.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/si_cmd_buffer.c | 15 +++
>  1 file changed, 15 insertions(+)
>
> diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c
> index 0970eff103..aed291be35 100644
> --- a/src/amd/vulkan/si_cmd_buffer.c
> +++ b/src/amd/vulkan/si_cmd_buffer.c
> @@ -539,6 +539,21 @@ si_emit_config(struct radv_physical_device 
> *physical_device,
>S_028004_ZPASS_INCREMENT_DISABLE(1));
> }
>
> +   /* Enable the Polaris small primitive filter control.
> +* XXX: There is possibly an issue when MSAA is off (see RadeonSI
> +* has_msaa_sample_loc_bug). But this doesn't seem to regress 
> anything,
> +* and AMDVLK doesn't have a workaround as well.
> +*/
> +   if (physical_device->rad_info.family >= CHIP_POLARIS10) {
> +   unsigned small_prim_filter_cntl =
> +   S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
> +   /* Workaround for a hw line bug. */
> +   
> S_028830_LINE_FILTER_DISABLE(physical_device->rad_info.family <= 
> CHIP_POLARIS12);
> +
> +   radeon_set_context_reg(cs, 
> R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
> +  small_prim_filter_cntl);
> +   }
> +
> si_emit_compute(physical_device, cs);
>  }
>
> --
> 2.16.3
>
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Re: [Mesa-dev] [PATCH] radv: only enable PERFECT_ZPASS_COUNTS for precision occlusion queries

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On Thu, Apr 5, 2018 at 10:27 AM, Samuel Pitoiset
 wrote:
> This unnecessary when the precision bit flag is not set, and this
> might hurt performance. The Vulkan explains that not setting
> VK_QUERY_CONTROL_PRECISE_BIT might be more efficient on some
> implementations.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_cmd_buffer.c |  4 +++-
>  src/amd/vulkan/radv_private.h|  1 +
>  src/amd/vulkan/radv_query.c  | 36 +++-
>  3 files changed, 35 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c 
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 526b618f2a..c0f60ac0d2 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1217,9 +1217,11 @@ void radv_set_db_count_control(struct radv_cmd_buffer 
> *cmd_buffer)
> } else {
> const struct radv_subpass *subpass = 
> cmd_buffer->state.subpass;
> uint32_t sample_rate = subpass ? 
> util_logbase2(subpass->max_sample_count) : 0;
> +   bool perfect = 
> cmd_buffer->state.perfect_occlusion_queries_enabled;
>
> if (cmd_buffer->device->physical_device->rad_info.chip_class 
> >= CIK) {
> -   db_count_control = S_028004_PERFECT_ZPASS_COUNTS(1) |
> +   db_count_control =
> +   S_028004_PERFECT_ZPASS_COUNTS(perfect) |
> S_028004_SAMPLE_RATE(sample_rate) |
> S_028004_ZPASS_ENABLE(1) |
> S_028004_SLICE_EVEN_ENABLE(1) |
> diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
> index ca3beba2d4..9e655af844 100644
> --- a/src/amd/vulkan/radv_private.h
> +++ b/src/amd/vulkan/radv_private.h
> @@ -946,6 +946,7 @@ struct radv_cmd_state {
> uint32_t 
> last_primitive_reset_index;
> enum radv_cmd_flush_bits flush_bits;
> unsigned active_occlusion_queries;
> +   bool 
> perfect_occlusion_queries_enabled;
> floatoffset_scale;
> uint32_t  trace_id;
> uint32_t  last_ia_multi_vgt_param;
> diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
> index cc943d5de0..859a4a1d68 100644
> --- a/src/amd/vulkan/radv_query.c
> +++ b/src/amd/vulkan/radv_query.c
> @@ -1079,7 +1079,8 @@ void radv_CmdResetQueryPool(
>
>  static void emit_begin_query(struct radv_cmd_buffer *cmd_buffer,
>  uint64_t va,
> -VkQueryType query_type)
> +VkQueryType query_type,
> +VkQueryControlFlags flags)
>  {
> struct radeon_winsys_cs *cs = cmd_buffer->cs;
> switch (query_type) {
> @@ -1087,8 +1088,27 @@ static void emit_begin_query(struct radv_cmd_buffer 
> *cmd_buffer,
> radeon_check_space(cmd_buffer->device->ws, cs, 7);
>
> ++cmd_buffer->state.active_occlusion_queries;
> -   if (cmd_buffer->state.active_occlusion_queries == 1)
> +   if (cmd_buffer->state.active_occlusion_queries == 1) {
> +   if (flags & VK_QUERY_CONTROL_PRECISE_BIT) {
> +   /* This is the first occlusion query, enable
> +* the hint if the precision bit is set.
> +*/
> +   
> cmd_buffer->state.perfect_occlusion_queries_enabled = true;
> +   }
> +
> radv_set_db_count_control(cmd_buffer);
> +   } else {
> +   if ((flags & VK_QUERY_CONTROL_PRECISE_BIT) &&
> +   
> !cmd_buffer->state.perfect_occlusion_queries_enabled) {
> +   /* This is not the first query, but this one
> +* needs to enable precision, DB_COUNT_CONTROL
> +* has to be updated accordingly.
> +*/
> +   
> cmd_buffer->state.perfect_occlusion_queries_enabled = true;
> +
> +   radv_set_db_count_control(cmd_buffer);
> +   }
> +   }
>
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | 
> EVENT_INDEX(1));
> @@ -1119,8 +1139,14 @@ static void emit_end_query(struct radv_cmd_buffer 
> *cmd_buffer,
> radeon_check_space(cmd_buffer->device->ws, cs, 14);
>
>