[Mesa-dev] [PATCH 1/2 v2] blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
Jason decided to fake it with a bit of shader math and R32_UNORM RTs.
The only problem is that R32_UNORM isn't renderable either...so we've
just traded one bad format for another.
This patch makes us use R32_UINT instead.
---
src/intel/blorp/blorp_blit.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
v2, now without the (iand value factor).
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index c85ec8543a9..cb07092ae88 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -984,14 +984,14 @@ convert_color(struct nir_builder *b, nir_ssa_def *color,
nir_ssa_def *value;
if (key->dst_format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
- /* The destination image is bound as R32_UNORM but the data needs to be
+ /* The destination image is bound as R32_UINT but the data needs to be
* in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
* top 8 need to be zero. We can accomplish this by simply multiplying
* by a factor to scale things down.
*/
- float factor = (float)((1 << 24) - 1) / (float)UINT32_MAX;
- value = nir_fmul(b, nir_fsat(b, nir_channel(b, color, 0)),
- nir_imm_float(b, factor));
+ unsigned factor = (1 << 24) - 1;
+ value = nir_fsat(b, nir_channel(b, color, 0));
+ value = nir_f2i32(b, nir_fmul(b, value, nir_imm_float(b, factor)));
} else if (key->dst_format == ISL_FORMAT_L8_UNORM_SRGB) {
value = nir_format_linear_to_srgb(b, nir_channel(b, color, 0));
} else if (key->dst_format == ISL_FORMAT_R8G8B8_UNORM_SRGB) {
@@ -1976,7 +1976,7 @@ try_blorp_blit(struct blorp_batch *batch,
isl_format_rgbx_to_rgba(params->dst.view.format);
} else if (params->dst.view.format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
wm_prog_key->dst_format = params->dst.view.format;
- params->dst.view.format = ISL_FORMAT_R32_UNORM;
+ params->dst.view.format = ISL_FORMAT_R32_UINT;
} else if (params->dst.view.format == ISL_FORMAT_A4B4G4R4_UNORM) {
params->dst.view.swizzle =
isl_swizzle_compose(params->dst.view.swizzle,
--
2.18.0
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Re: [Mesa-dev] [PATCH 10/11] mesa: expose EXT_texture_buffer_object
On Fri, Aug 10, 2018 at 9:04 PM, Ian Romanick wrote: > On 08/07/2018 10:42 PM, Marek Olšák wrote: >> From: Marek Olšák >> >> This is needed for exposing the samplerBuffer functions under >> EXT_gpu_shader4. >> >> glTexBufferEXT is defined in glapi, but "make check" fails. >> What am I doing wrong? >> --- >> docs/relnotes/18.3.0.html | 1 + >> src/mesa/main/extensions_table.h| 1 + >> src/mesa/main/tests/dispatch_sanity.cpp | 1 + >> 3 files changed, 3 insertions(+) >> >> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html >> index 786145ad8da..6274c9147a1 100644 >> --- a/docs/relnotes/18.3.0.html >> +++ b/docs/relnotes/18.3.0.html >> @@ -45,20 +45,21 @@ TBD. >> >> >> New features >> >> >> Note: some of the new features are only available with certain drivers. >> >> >> >> GL_AMD_framebuffer_multisample_advanced on radeonsi. >> +GL_EXT_texture_buffer_object on i965, nv50, nvc0, r600, radeonsi. >> >> >> Bug fixes >> >> >> TBD >> >> >> Changes >> >> diff --git a/src/mesa/main/extensions_table.h >> b/src/mesa/main/extensions_table.h >> index bdba49d5380..5eb5c3278e9 100644 >> --- a/src/mesa/main/extensions_table.h >> +++ b/src/mesa/main/extensions_table.h >> @@ -263,20 +263,21 @@ EXT(EXT_shadow_funcs, >> ARB_shadow >> EXT(EXT_stencil_two_side, EXT_stencil_two_side >> , GLL, x , x , x , 2001) >> EXT(EXT_stencil_wrap, dummy_true >> , GLL, x , x , x , 2002) >> EXT(EXT_subtexture , dummy_true >> , GLL, x , x , x , 1995) >> EXT(EXT_tessellation_point_size , ARB_tessellation_shader >> , x , x , x , 31, 2013) >> EXT(EXT_tessellation_shader , ARB_tessellation_shader >> , x , x , x , 31, 2013) >> EXT(EXT_texture , dummy_true >> , GLL, x , x , x , 1996) >> EXT(EXT_texture3D , dummy_true >> , GLL, x , x , x , 1996) >> EXT(EXT_texture_array , EXT_texture_array >> , GLL, GLC, x , x , 2006) >> EXT(EXT_texture_border_clamp, ARB_texture_border_clamp >> , x , x , x , ES2, 2014) >> EXT(EXT_texture_buffer , OES_texture_buffer >> , x , x , x , 31, 2014) >> +EXT(EXT_texture_buffer_object , ARB_texture_buffer_object >> , GLL, GLC, x , x , 2007) > > I doubt we want to actually expose this extension or GL_EXT_gpu_shader4 > in core profile. Do you know of any applications on any platform that > need this? If there are any, I want to shame them. :) What's the issue with the core profile? I'm only adding what our closed driver supports. EXT_gpu_shader4 wouldn't be complete without it. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 00/11] GL_EXT_gpu_shader4
On Fri, Aug 10, 2018 at 9:03 PM, Ian Romanick wrote: > On 08/07/2018 10:41 PM, Marek Olšák wrote: >> Hi, >> >> This adds EXT_gpu_shader4 with its subset EXT_texture_buffer_object. >> >> Some applications that previously required force_glsl_version=130 now >> work without it, because EXT_gpu_shader4 enables a subset of GLSL 1.30. >> >> There are also applications that need the old-style texture functions >> from EXT_gpu_shader4. >> >> I have some tests internally. I'm not sure I wanna write piglits for >> everything (there are about 360 texture functions). A lot of the code >> is shared with GLSL 1.30 anyway. > > There need to at least be compile tests for all of them. It should be > too much effort to write a Python script that generates a few tests that > try a bunch of them at once. Compile tests for some of the other stuff > wouldn't hurt either. It seems like every time we think adding a > billion functions or operators will without tests will be fine, we miss > one or two somehow. > > It also looks like GL_EXT_gpu_shader4 adds a bunch of glFooEXT functions > that are probably all aliases for the glFoo functions in OpenGL 3.0... > are those already wired up? Yes, all aliases are in place. Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/4] vc4: Drop a bunch of duplicated gallium PIPE_CAP default code.
On 08/10/2018 06:20 PM, Eric Anholt wrote:
> Now that we have the util function for the default values, we can get rid
> of the boilerplate.
> ---
> src/gallium/auxiliary/util/u_screen.c | 6 +-
> src/gallium/drivers/vc4/vc4_screen.c | 171 --
> 2 files changed, 1 insertion(+), 176 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_screen.c
> b/src/gallium/auxiliary/util/u_screen.c
> index 18475fcf1377..f74dbb2e0f71 100644
> --- a/src/gallium/auxiliary/util/u_screen.c
> +++ b/src/gallium/auxiliary/util/u_screen.c
> @@ -63,11 +63,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen
> *pscreen,
> case PIPE_CAP_PRIMITIVE_RESTART:
> case PIPE_CAP_INDEP_BLEND_ENABLE:
> case PIPE_CAP_INDEP_BLEND_FUNC:
> - return 0;
> -
> - case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
> - unreachable("driver must implement these.");
> -
> + case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* Enables GL_EXT_texture_array */
> case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
> case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
> case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
> diff --git a/src/gallium/drivers/vc4/vc4_screen.c
> b/src/gallium/drivers/vc4/vc4_screen.c
> index feed9a97f31b..5c8cc9f12d48 100644
> --- a/src/gallium/drivers/vc4/vc4_screen.c
> +++ b/src/gallium/drivers/vc4/vc4_screen.c
> @@ -144,8 +144,6 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum
> pipe_cap param)
> case PIPE_CAP_BLEND_EQUATION_SEPARATE:
> case PIPE_CAP_TEXTURE_MULTISAMPLE:
> case PIPE_CAP_TEXTURE_SWIZZLE:
> -case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
> -case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
> case PIPE_CAP_TEXTURE_BARRIER:
> return 1;
>
> @@ -161,16 +159,10 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum
> pipe_cap param)
> case PIPE_CAP_POINT_SPRITE:
> return 1;
>
> -case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
> -return 256;
> -
> case PIPE_CAP_GLSL_FEATURE_LEVEL:
> case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
> return 120;
Can probably get rid of this too since GLSL 1.20 is the minimum possible
to support in Mesa.
>
> -case PIPE_CAP_MAX_VIEWPORTS:
> -return 1;
> -
> case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
> case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
> return 1;
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[Mesa-dev] [PATCH 1/4] gallium: Add a helper for implementing PIPE_CAP_* default values.
One of the pains of implementing a gallium driver is filling in a million
pipe caps you don't know about yet when you're just starting out. One of
the pains of working on gallium is copy-and-pasting your new PIPE_CAP into
each driver. We can fix both of these by having each driver call into the
default helper from their default case, so that both sides can ignore each
other until they need to.
---
src/gallium/auxiliary/Makefile.sources| 2 +
src/gallium/auxiliary/meson.build | 2 +
src/gallium/auxiliary/util/u_screen.c | 316 ++
src/gallium/auxiliary/util/u_screen.h | 29 ++
src/gallium/drivers/etnaviv/etnaviv_screen.c | 6 +-
.../drivers/freedreno/freedreno_screen.c | 5 +-
src/gallium/drivers/i915/i915_screen.c| 5 +-
src/gallium/drivers/llvmpipe/lp_screen.c | 7 +-
.../drivers/nouveau/nv30/nv30_screen.c| 6 +-
.../drivers/nouveau/nv50/nv50_screen.c| 6 +-
.../drivers/nouveau/nvc0/nvc0_screen.c| 6 +-
src/gallium/drivers/r300/r300_screen.c| 4 +-
src/gallium/drivers/r600/r600_pipe.c | 4 +-
src/gallium/drivers/radeonsi/si_get.c | 5 +-
src/gallium/drivers/softpipe/sp_screen.c | 6 +-
src/gallium/drivers/svga/svga_screen.c| 6 +-
src/gallium/drivers/swr/swr_screen.cpp| 8 +-
src/gallium/drivers/v3d/v3d_screen.c | 4 +-
src/gallium/drivers/vc4/vc4_screen.c | 4 +-
src/gallium/drivers/virgl/virgl_screen.c | 6 +-
20 files changed, 398 insertions(+), 39 deletions(-)
create mode 100644 src/gallium/auxiliary/util/u_screen.c
create mode 100644 src/gallium/auxiliary/util/u_screen.h
diff --git a/src/gallium/auxiliary/Makefile.sources
b/src/gallium/auxiliary/Makefile.sources
index 626cde123afd..d66fa85f798d 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -317,6 +317,8 @@ C_SOURCES := \
util/u_ringbuffer.h \
util/u_sampler.c \
util/u_sampler.h \
+ util/u_screen.c \
+ util/u_screen.h \
util/u_simple_shaders.c \
util/u_simple_shaders.h \
util/u_split_prim.h \
diff --git a/src/gallium/auxiliary/meson.build
b/src/gallium/auxiliary/meson.build
index 98542d7ef3e0..24ad1083ce22 100644
--- a/src/gallium/auxiliary/meson.build
+++ b/src/gallium/auxiliary/meson.build
@@ -337,6 +337,8 @@ files_libgallium = files(
'util/u_ringbuffer.h',
'util/u_sampler.c',
'util/u_sampler.h',
+ 'util/u_screen.c',
+ 'util/u_screen.h',
'util/u_simple_shaders.c',
'util/u_simple_shaders.h',
'util/u_split_prim.h',
diff --git a/src/gallium/auxiliary/util/u_screen.c
b/src/gallium/auxiliary/util/u_screen.c
new file mode 100644
index ..18475fcf1377
--- /dev/null
+++ b/src/gallium/auxiliary/util/u_screen.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright © 2018 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "pipe/p_screen.h"
+#include "util/u_screen.h"
+
+/**
+ * Helper to use from a pipe_screen->get_param() implementation to return
+ * default values for unsupported PIPE_CAPs.
+ *
+ * Call this function from your pipe_screen->get_param() implementation's
+ * default case, so that implementors of new pipe caps don't need to
+ */
+int
+u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
+ enum pipe_cap param)
+{
+ /* Let's keep these sorted by position in p_defines.h. */
+ switch (param) {
+ case PIPE_CAP_NPOT_TEXTURES:
+ case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
+ case PIPE_CAP_ANISOTROPIC_FILTER:
+ case PIPE_CAP_POINT_SPRITE:
+ return 0;
+
+ case PIPE_CAP_MAX_RENDER_TARGETS:
+ return 1;
+
+ case PIPE_CAP_OCCLUSION_QUERY:
+ case PIPE_CAP_QUERY_TIME_ELAPSED:
+ case PIPE_CAP_TEXTURE_SWIZZLE:
+ return 0;
+
+ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ case P
[Mesa-dev] [PATCH 4/4] freedreno: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid of the boilerplate. --- .../drivers/freedreno/freedreno_screen.c | 103 +- 1 file changed, 2 insertions(+), 101 deletions(-) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index b698e36d6e3b..988b623a0b98 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -208,11 +208,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_COMPUTE: return has_compute(screen); - case PIPE_CAP_SHADER_STENCIL_EXPORT: - case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: - case PIPE_CAP_TEXTURE_MIRROR_CLAMP: - case PIPE_CAP_QUERY_MEMORY_INFO: case PIPE_CAP_PCI_GROUP: case PIPE_CAP_PCI_BUS: case PIPE_CAP_PCI_DEVICE: @@ -245,8 +241,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_POLYGON_OFFSET_CLAMP: return is_a5xx(screen); - case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: - return 0; case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: if (is_a3xx(screen)) return 16; if (is_a4xx(screen)) return 32; @@ -294,79 +288,11 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 4; return 0; - /* Unsupported features. */ - case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: - case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: - case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_QUERY_PIPELINE_STATISTICS: - case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: - case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: - case PIPE_CAP_TEXTURE_GATHER_SM5: - case PIPE_CAP_SAMPLE_SHADING: - case PIPE_CAP_TEXTURE_GATHER_OFFSETS: - case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: - case PIPE_CAP_MULTI_DRAW_INDIRECT: - case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: - case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: - case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: - case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: - case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: - case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: - case PIPE_CAP_DEPTH_BOUNDS_TEST: - case PIPE_CAP_TGSI_TXQS: /* TODO if we need this, do it in nir/ir3 backend to avoid breaking precompile: */ case PIPE_CAP_FORCE_PERSAMPLE_INTERP: - case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: - case PIPE_CAP_CLEAR_TEXTURE: - case PIPE_CAP_DRAW_PARAMETERS: - case PIPE_CAP_TGSI_PACK_HALF_FLOAT: - case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: - case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: - case PIPE_CAP_GENERATE_MIPMAP: - case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: - case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR: - case PIPE_CAP_CULL_DISTANCE: - case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: - case PIPE_CAP_TGSI_VOTE: - case PIPE_CAP_MAX_WINDOW_RECTANGLES: - case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED: - case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS: - case PIPE_CAP_TGSI_ARRAY_COMPONENTS: - case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: - case PIPE_CAP_TGSI_FS_FBFETCH: - case PIPE_CAP_TGSI_MUL_ZERO_WINS: - case PIPE_CAP_DOUBLES: - case PIPE_CAP_INT64: - case PIPE_CAP_INT64_DIVMOD: - case PIPE_CAP_TGSI_TEX_TXF_LZ: - case PIPE_CAP_TGSI_CLOCK: - case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: - case PIPE_CAP_TGSI_BALLOT: - case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: - case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX: + return 0; + case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: - case PIPE_CAP_POST_DEPTH_COVERAGE: - case PIPE_CAP_BINDLESS_TEXTURE: - case PIPE_CAP_NIR_SAMPLERS_AS_DEREF: - case PIPE_CAP_QUERY_SO_OVERFLOW: - case PIPE_CAP_MEMOBJ: - case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS: - case PIPE_CAP_TILE_RASTER_ORDER: - case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES: - case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS: - case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET: - case PIPE_CAP_FENCE_SIGNAL: - case PIPE_CAP_CONSTBUF0_FLAGS: - case PIPE_CAP_PACKED_UNIFORMS: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES: - case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES: - case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES: - case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE: - case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS: - case PIPE_CAP_PROGRA
[Mesa-dev] [PATCH 3/4] v3d: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid of the boilerplate. --- src/gallium/drivers/v3d/v3d_screen.c | 147 --- 1 file changed, 147 deletions(-) diff --git a/src/gallium/drivers/v3d/v3d_screen.c b/src/gallium/drivers/v3d/v3d_screen.c index b305dac4b6c9..252ebb379f87 100644 --- a/src/gallium/drivers/v3d/v3d_screen.c +++ b/src/gallium/drivers/v3d/v3d_screen.c @@ -101,11 +101,9 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_SM3: case PIPE_CAP_TEXTURE_QUERY_LOD: case PIPE_CAP_PRIMITIVE_RESTART: -case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: case PIPE_CAP_OCCLUSION_QUERY: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME: -case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION: case PIPE_CAP_COMPUTE: case PIPE_CAP_DRAW_INDIRECT: case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: @@ -128,9 +126,6 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY: return 140; -case PIPE_CAP_MAX_VIEWPORTS: -return 1; - case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: return 1; case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: @@ -151,134 +146,8 @@ v3d_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: return 1; - -/* Stream output. */ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS: return 4; -case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS: -case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS: -return 64; - -case PIPE_CAP_MIN_TEXEL_OFFSET: -case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET: -return -8; -case PIPE_CAP_MAX_TEXEL_OFFSET: -case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET: -return 7; - -/* Unsupported features. */ -case PIPE_CAP_ANISOTROPIC_FILTER: -case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: -case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY: -case PIPE_CAP_CUBE_MAP_ARRAY: -case PIPE_CAP_TEXTURE_MIRROR_CLAMP: -case PIPE_CAP_SEAMLESS_CUBE_MAP: -case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: -case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: -case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: -case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: -case PIPE_CAP_SHADER_STENCIL_EXPORT: -case PIPE_CAP_TGSI_TEXCOORD: -case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: -case PIPE_CAP_CONDITIONAL_RENDER: -case PIPE_CAP_TEXTURE_BARRIER: -case PIPE_CAP_INDEP_BLEND_FUNC: -case PIPE_CAP_DEPTH_CLIP_DISABLE: -case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: -case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: -case PIPE_CAP_USER_VERTEX_BUFFERS: -case PIPE_CAP_QUERY_PIPELINE_STATISTICS: -case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: -case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT: -case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: -case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: -case PIPE_CAP_TEXTURE_GATHER_SM5: -case PIPE_CAP_FAKE_SW_MSAA: -case PIPE_CAP_SAMPLE_SHADING: -case PIPE_CAP_TEXTURE_GATHER_OFFSETS: -case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: -case PIPE_CAP_MAX_VERTEX_STREAMS: -case PIPE_CAP_MULTI_DRAW_INDIRECT: -case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: -case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: -case PIPE_CAP_CONDITIONAL_RENDER_INVERTED: -case PIPE_CAP_SAMPLER_VIEW_TARGET: -case PIPE_CAP_CLIP_HALFZ: -case PIPE_CAP_VERTEXID_NOBASE: -case PIPE_CAP_POLYGON_OFFSET_CLAMP: -case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: -case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: -case PIPE_CAP_DEVICE_RESET_STATUS_QUERY: -case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS: -case PIPE_CAP_TEXTURE_FLOAT_LINEAR: -case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR: -case PIPE_CAP_DEPTH_BOUNDS_TEST: -case PIPE_CAP_TGSI_TXQS: -case PIPE_CAP_FORCE_PERSAMPLE_INTERP: -case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS: -case PIPE_CAP_CLEAR_TEXTURE: -case PIPE_CAP_DRAW_PARAMETERS: -case PIPE_CAP_TGSI_PACK_HALF_FLOAT: -case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL: -case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL: -case PIPE_CAP_INVALIDATE_BUFFER: -case PIPE_CAP_GENERATE_MIPMAP: -case PIPE_CAP_STRING_MARKER: -case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS: -case PIPE_CAP_QUERY_BUFFER_OBJECT: -case PIPE_CAP_QUERY_MEMORY_INFO: -case PIPE_CAP_PCI_GROUP: -case PIPE_CAP_PCI_BUS
[Mesa-dev] [PATCH 0/4] PIPE_CAP default handler
I've been putting off some PIPE_CAPs I've needed to write because each one is such a pain to do, so I went and implemented the thing I've been dreaming of: a single place to define a new pipe cap's default state. Eric Anholt (4): gallium: Add a helper for implementing PIPE_CAP_* default values. vc4: Drop a bunch of duplicated gallium PIPE_CAP default code. v3d: Drop a bunch of duplicated gallium PIPE_CAP default code. freedreno: Drop a bunch of duplicated gallium PIPE_CAP default code. src/gallium/auxiliary/Makefile.sources| 2 + src/gallium/auxiliary/meson.build | 2 + src/gallium/auxiliary/util/u_screen.c | 312 ++ src/gallium/auxiliary/util/u_screen.h | 29 ++ src/gallium/drivers/etnaviv/etnaviv_screen.c | 6 +- .../drivers/freedreno/freedreno_screen.c | 108 +- src/gallium/drivers/i915/i915_screen.c| 5 +- src/gallium/drivers/llvmpipe/lp_screen.c | 7 +- .../drivers/nouveau/nv30/nv30_screen.c| 6 +- .../drivers/nouveau/nv50/nv50_screen.c| 6 +- .../drivers/nouveau/nvc0/nvc0_screen.c| 6 +- src/gallium/drivers/r300/r300_screen.c| 4 +- src/gallium/drivers/r600/r600_pipe.c | 4 +- src/gallium/drivers/radeonsi/si_get.c | 5 +- src/gallium/drivers/softpipe/sp_screen.c | 6 +- src/gallium/drivers/svga/svga_screen.c| 6 +- src/gallium/drivers/swr/swr_screen.cpp| 8 +- src/gallium/drivers/v3d/v3d_screen.c | 151 + src/gallium/drivers/vc4/vc4_screen.c | 175 +- src/gallium/drivers/virgl/virgl_screen.c | 6 +- 20 files changed, 396 insertions(+), 458 deletions(-) create mode 100644 src/gallium/auxiliary/util/u_screen.c create mode 100644 src/gallium/auxiliary/util/u_screen.h -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/4] vc4: Drop a bunch of duplicated gallium PIPE_CAP default code.
Now that we have the util function for the default values, we can get rid
of the boilerplate.
---
src/gallium/auxiliary/util/u_screen.c | 6 +-
src/gallium/drivers/vc4/vc4_screen.c | 171 --
2 files changed, 1 insertion(+), 176 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_screen.c
b/src/gallium/auxiliary/util/u_screen.c
index 18475fcf1377..f74dbb2e0f71 100644
--- a/src/gallium/auxiliary/util/u_screen.c
+++ b/src/gallium/auxiliary/util/u_screen.c
@@ -63,11 +63,7 @@ u_pipe_screen_get_param_defaults(struct pipe_screen *pscreen,
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
- return 0;
-
- case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
- unreachable("driver must implement these.");
-
+ case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS: /* Enables GL_EXT_texture_array */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
diff --git a/src/gallium/drivers/vc4/vc4_screen.c
b/src/gallium/drivers/vc4/vc4_screen.c
index feed9a97f31b..5c8cc9f12d48 100644
--- a/src/gallium/drivers/vc4/vc4_screen.c
+++ b/src/gallium/drivers/vc4/vc4_screen.c
@@ -144,8 +144,6 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_TEXTURE_SWIZZLE:
-case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
-case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_TEXTURE_BARRIER:
return 1;
@@ -161,16 +159,10 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_POINT_SPRITE:
return 1;
-case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
-return 256;
-
case PIPE_CAP_GLSL_FEATURE_LEVEL:
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
return 120;
-case PIPE_CAP_MAX_VIEWPORTS:
-return 1;
-
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
return 1;
@@ -179,143 +171,6 @@ vc4_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
-/* Unsupported features. */
-case PIPE_CAP_ANISOTROPIC_FILTER:
-case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
-case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
-case PIPE_CAP_CUBE_MAP_ARRAY:
-case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
-case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
-case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
-case PIPE_CAP_SEAMLESS_CUBE_MAP:
-case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
-case PIPE_CAP_TGSI_INSTANCEID:
-case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
-case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
-case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
-case PIPE_CAP_COMPUTE:
-case PIPE_CAP_START_INSTANCE:
-case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
-case PIPE_CAP_SHADER_STENCIL_EXPORT:
-case PIPE_CAP_TGSI_TEXCOORD:
-case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
-case PIPE_CAP_CONDITIONAL_RENDER:
-case PIPE_CAP_PRIMITIVE_RESTART:
-case PIPE_CAP_SM3:
-case PIPE_CAP_INDEP_BLEND_ENABLE:
-case PIPE_CAP_INDEP_BLEND_FUNC:
-case PIPE_CAP_DEPTH_CLIP_DISABLE:
-case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
-case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
-case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
-case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
-case PIPE_CAP_USER_VERTEX_BUFFERS:
-case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
-case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
-case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
-case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
-case PIPE_CAP_TEXTURE_GATHER_SM5:
-case PIPE_CAP_FAKE_SW_MSAA:
-case PIPE_CAP_TEXTURE_QUERY_LOD:
-case PIPE_CAP_SAMPLE_SHADING:
-case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
-case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
-case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
-case PIPE_CAP_MAX_TEXEL_OFFSET:
-case PIPE_CAP_MAX_VERTEX_STREAMS:
-case PIPE_CAP_DRAW_INDIRECT:
-case PIPE_CAP_MULTI_DRAW_INDIRECT:
-case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
-case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
-case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
-case PIPE_CAP_SAMPLER_VIEW_TARGET:
-case PIPE_CAP_CLIP_HALFZ:
-case PIPE_CAP_VERTEXID_NOBASE:
-case PIPE_CAP_POLYGON_OFFSET_CLAMP:
-case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
-case PIPE_CAP_RESOURCE_FROM_
Re: [Mesa-dev] [PATCH 10/11] mesa: expose EXT_texture_buffer_object
On 08/07/2018 10:42 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> This is needed for exposing the samplerBuffer functions under
> EXT_gpu_shader4.
>
> glTexBufferEXT is defined in glapi, but "make check" fails.
> What am I doing wrong?
> ---
> docs/relnotes/18.3.0.html | 1 +
> src/mesa/main/extensions_table.h| 1 +
> src/mesa/main/tests/dispatch_sanity.cpp | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/docs/relnotes/18.3.0.html b/docs/relnotes/18.3.0.html
> index 786145ad8da..6274c9147a1 100644
> --- a/docs/relnotes/18.3.0.html
> +++ b/docs/relnotes/18.3.0.html
> @@ -45,20 +45,21 @@ TBD.
>
>
> New features
>
>
> Note: some of the new features are only available with certain drivers.
>
>
>
> GL_AMD_framebuffer_multisample_advanced on radeonsi.
> +GL_EXT_texture_buffer_object on i965, nv50, nvc0, r600, radeonsi.
>
>
> Bug fixes
>
>
> TBD
>
>
> Changes
>
> diff --git a/src/mesa/main/extensions_table.h
> b/src/mesa/main/extensions_table.h
> index bdba49d5380..5eb5c3278e9 100644
> --- a/src/mesa/main/extensions_table.h
> +++ b/src/mesa/main/extensions_table.h
> @@ -263,20 +263,21 @@ EXT(EXT_shadow_funcs, ARB_shadow
> EXT(EXT_stencil_two_side, EXT_stencil_two_side
> , GLL, x , x , x , 2001)
> EXT(EXT_stencil_wrap, dummy_true
> , GLL, x , x , x , 2002)
> EXT(EXT_subtexture , dummy_true
> , GLL, x , x , x , 1995)
> EXT(EXT_tessellation_point_size , ARB_tessellation_shader
> , x , x , x , 31, 2013)
> EXT(EXT_tessellation_shader , ARB_tessellation_shader
> , x , x , x , 31, 2013)
> EXT(EXT_texture , dummy_true
> , GLL, x , x , x , 1996)
> EXT(EXT_texture3D , dummy_true
> , GLL, x , x , x , 1996)
> EXT(EXT_texture_array , EXT_texture_array
> , GLL, GLC, x , x , 2006)
> EXT(EXT_texture_border_clamp, ARB_texture_border_clamp
> , x , x , x , ES2, 2014)
> EXT(EXT_texture_buffer , OES_texture_buffer
> , x , x , x , 31, 2014)
> +EXT(EXT_texture_buffer_object , ARB_texture_buffer_object
> , GLL, GLC, x , x , 2007)
I doubt we want to actually expose this extension or GL_EXT_gpu_shader4
in core profile. Do you know of any applications on any platform that
need this? If there are any, I want to shame them. :)
> EXT(EXT_texture_compression_dxt1, ANGLE_texture_compression_dxt
> , GLL, GLC, ES1, ES2, 2004)
> EXT(EXT_texture_compression_latc, EXT_texture_compression_latc
> , GLL, x , x , x , 2006)
> EXT(EXT_texture_compression_rgtc, ARB_texture_compression_rgtc
> , GLL, GLC, x , x , 2004)
> EXT(EXT_texture_compression_s3tc, EXT_texture_compression_s3tc
> , GLL, GLC, x , x , 2000)
> EXT(EXT_texture_cube_map, ARB_texture_cube_map
> , GLL, x , x , x , 2001)
> EXT(EXT_texture_cube_map_array , OES_texture_cube_map_array
> , x , x , x , 31, 2014)
> EXT(EXT_texture_edge_clamp , dummy_true
> , GLL, x , x , x , 1997)
> EXT(EXT_texture_env_add , dummy_true
> , GLL, x , x , x , 1999)
> EXT(EXT_texture_env_combine , dummy_true
> , GLL, x , x , x , 2000)
> EXT(EXT_texture_env_dot3, EXT_texture_env_dot3
> , GLL, x , x , x , 2000)
> diff --git a/src/mesa/main/tests/dispatch_sanity.cpp
> b/src/mesa/main/tests/dispatch_sanity.cpp
> index 449dd3652cc..a7562b766f3 100644
> --- a/src/mesa/main/tests/dispatch_sanity.cpp
> +++ b/src/mesa/main/tests/dispatch_sanity.cpp
> @@ -499,20 +499,21 @@ const struct function
> common_desktop_functions_possible[] = {
> { "glClearBufferuiv", 30, -1 },
> { "glClearBufferfv", 30, -1 },
> { "glClearBufferfi", 30, -1 },
> { "glGetStringi", 30, -1 },
>
> /* GL 3.1 */
> { "glDrawArraysInstanced", 31, -1 },
> { "glDrawElementsInstanced", 31, -1 },
> { "glPrimitiveRestartIndex", 31, -1 },
> { "glTexBuffer", 31, -1 },
> + { "glTexBufferEXT", 31, -1 },
>
> /* GL_ARB_texture_buffer_range */
> { "glTexBufferRange", 43, -1 },
>
> /* GL_ARB_shader_objects */
> { "glDeleteObjectARB", 31, -1 },
> { "glGetHandleARB", 31, -1 },
> { "glDetachObjectARB", 31, -1 },
> { "glCreateShaderObjectARB", 31, -1 },
> { "glCreateProgramObjectARB", 31, -1 },
>
___
Re: [Mesa-dev] [PATCH 00/11] GL_EXT_gpu_shader4
On 08/07/2018 10:41 PM, Marek Olšák wrote: > Hi, > > This adds EXT_gpu_shader4 with its subset EXT_texture_buffer_object. > > Some applications that previously required force_glsl_version=130 now > work without it, because EXT_gpu_shader4 enables a subset of GLSL 1.30. > > There are also applications that need the old-style texture functions > from EXT_gpu_shader4. > > I have some tests internally. I'm not sure I wanna write piglits for > everything (there are about 360 texture functions). A lot of the code > is shared with GLSL 1.30 anyway. There need to at least be compile tests for all of them. It should be too much effort to write a Python script that generates a few tests that try a bunch of them at once. Compile tests for some of the other stuff wouldn't hurt either. It seems like every time we think adding a billion functions or operators will without tests will be fine, we miss one or two somehow. It also looks like GL_EXT_gpu_shader4 adds a bunch of glFooEXT functions that are probably all aliases for the glFoo functions in OpenGL 3.0... are those already wired up? > The only special additions are "unsigned int" and "truncate". Testing the new constructor syntax and the associated array constructor syntax shouldn't require much effort. It also shouldn't be hard to modify the trunc() tests to be truncate() tests. > The following GLSL code compiles successfully, even though > the "unsigned int" constructor looks weird. > > unsigned int x = unsigned int(gl_Vertex.x); > unsigned int y = 0u; > gl_FrontColor.x = truncate(float(x + y)); > > Please review. > > Thanks, > Marek > ___ > mesa-dev mailing list > mesa-dev@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/mesa-dev > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 04/14] mesa: add ctx->Const.MaxGeometryShaderInvocations
This commit is
Reviewed-by: Ian Romanick
On 08/08/2018 04:55 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> radeonsi wants to report a different value
> ---
> src/compiler/glsl/glsl_parser_extras.cpp | 3 ++-
> src/compiler/glsl/glsl_parser_extras.h | 1 +
> src/mesa/main/context.c | 1 +
> src/mesa/main/get_hash_params.py | 2 +-
> src/mesa/main/mtypes.h | 3 ++-
> 5 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
> b/src/compiler/glsl/glsl_parser_extras.cpp
> index 6d92f24ea22..01ca39fb0cc 100644
> --- a/src/compiler/glsl/glsl_parser_extras.cpp
> +++ b/src/compiler/glsl/glsl_parser_extras.cpp
> @@ -111,20 +111,21 @@ _mesa_glsl_parse_state::_mesa_glsl_parse_state(struct
> gl_context *_ctx,
> this->Const.MaxProgramTexelOffset = ctx->Const.MaxProgramTexelOffset;
>
> this->Const.MaxDrawBuffers = ctx->Const.MaxDrawBuffers;
>
> this->Const.MaxDualSourceDrawBuffers =
> ctx->Const.MaxDualSourceDrawBuffers;
>
> /* 1.50 constants */
> this->Const.MaxVertexOutputComponents =
> ctx->Const.Program[MESA_SHADER_VERTEX].MaxOutputComponents;
> this->Const.MaxGeometryInputComponents =
> ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxInputComponents;
> this->Const.MaxGeometryOutputComponents =
> ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxOutputComponents;
> + this->Const.MaxGeometryShaderInvocations =
> ctx->Const.MaxGeometryShaderInvocations;
> this->Const.MaxFragmentInputComponents =
> ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxInputComponents;
> this->Const.MaxGeometryTextureImageUnits =
> ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxTextureImageUnits;
> this->Const.MaxGeometryOutputVertices =
> ctx->Const.MaxGeometryOutputVertices;
> this->Const.MaxGeometryTotalOutputComponents =
> ctx->Const.MaxGeometryTotalOutputComponents;
> this->Const.MaxGeometryUniformComponents =
> ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxUniformComponents;
>
> this->Const.MaxVertexAtomicCounters =
> ctx->Const.Program[MESA_SHADER_VERTEX].MaxAtomicCounters;
> this->Const.MaxTessControlAtomicCounters =
> ctx->Const.Program[MESA_SHADER_TESS_CTRL].MaxAtomicCounters;
> this->Const.MaxTessEvaluationAtomicCounters =
> ctx->Const.Program[MESA_SHADER_TESS_EVAL].MaxAtomicCounters;
> this->Const.MaxGeometryAtomicCounters =
> ctx->Const.Program[MESA_SHADER_GEOMETRY].MaxAtomicCounters;
> @@ -1810,21 +1811,21 @@ set_shader_inout_layout(struct gl_shader *shader,
>}
>
>shader->info.Geom.Invocations = 0;
>if (state->in_qualifier->flags.q.invocations) {
> unsigned invocations;
> if (state->in_qualifier->invocations->
> process_qualifier_constant(state, "invocations",
>&invocations, false)) {
>
> YYLTYPE loc = state->in_qualifier->invocations->get_location();
> -if (invocations > MAX_GEOMETRY_SHADER_INVOCATIONS) {
> +if (invocations > state->Const.MaxGeometryShaderInvocations) {
> _mesa_glsl_error(&loc, state,
> "invocations (%d) exceeds "
> "GL_MAX_GEOMETRY_SHADER_INVOCATIONS",
> invocations);
> }
> shader->info.Geom.Invocations = invocations;
> }
>}
>break;
>
> diff --git a/src/compiler/glsl/glsl_parser_extras.h
> b/src/compiler/glsl/glsl_parser_extras.h
> index 59a173418b7..b29216f8d32 100644
> --- a/src/compiler/glsl/glsl_parser_extras.h
> +++ b/src/compiler/glsl/glsl_parser_extras.h
> @@ -486,20 +486,21 @@ struct _mesa_glsl_parse_state {
>unsigned MaxDualSourceDrawBuffers;
>
>/* 3.00 ES */
>int MinProgramTexelOffset;
>int MaxProgramTexelOffset;
>
>/* 1.50 */
>unsigned MaxVertexOutputComponents;
>unsigned MaxGeometryInputComponents;
>unsigned MaxGeometryOutputComponents;
> + unsigned MaxGeometryShaderInvocations;
>unsigned MaxFragmentInputComponents;
>unsigned MaxGeometryTextureImageUnits;
>unsigned MaxGeometryOutputVertices;
>unsigned MaxGeometryTotalOutputComponents;
>unsigned MaxGeometryUniformComponents;
>
>/* ARB_shader_atomic_counters */
>unsigned MaxVertexAtomicCounters;
>unsigned MaxTessControlAtomicCounters;
>unsigned MaxTessEvaluationAtomicCounters;
> diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c
> index 0ef8fe32a63..c46d97983e9 100644
> --- a/src/mesa/main/context.c
> +++ b/src/mesa/main/context.c
> @@ -630,20 +630,21 @@ _mesa_init_constants(struct gl_constants *consts,
> gl_api api)
>
> consts->MaxColorAttachments = MAX_COLOR_ATTACHMENTS;
> consts->MaxRenderbufferSize = MAX_RENDERBUFFER_SIZE;
>
> consts->Program[MESA_SHADER_VERTEX].MaxTextureImageUnits =
> MAX_TEX
[Mesa-dev] [PATCH] anv: add VK_EXT_sampler_filter_minmax support
This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.
I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*
---
src/intel/vulkan/anv_device.c | 8
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_formats.c | 6 ++
src/intel/vulkan/genX_state.c | 27 +++
4 files changed, 42 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
break;
}
+ case
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen >=
9;
+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+ }
+
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen
>= 9'),
Extension('VK_EXT_vertex_attribute_divisor', 2, True),
Extension('VK_EXT_post_depth_coverage', 1, 'device->info.gen
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 'device->info.gen
>= 9'),
]
class VkVersion:
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..b0eb4c6afa 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info
*devinfo,
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
+ if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT && devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT |
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info
*devinfo,
if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
+ if (devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..e095cb4cc0 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
[VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
};
+#if GEN_GEN >= 9
+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+ [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+ [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
+ [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
+};
+#endif
+
VkResult genX(CreateSampler)(
VkDevice_device,
const VkSamplerCreateInfo* pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
uint32_t border_color_offset = device->border_colors.offset +
pCreateInfo->borderColor * 64;
+#if GEN_GEN >= 9
+ unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
vk_foreach_struct(ext, pCreateInfo->pNext) {
switch (ext->sType) {
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,16 @@ VkResult genX(CreateSampler)(
sampler->conversion = conversion;
break;
}
+#if GEN_GEN >= 9
+ case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+ (struct VkSamplerReductionModeCreateInfoEXT *) ext;
+ if (sampler_reduction)
+sampler_reduction_mode =
+
vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
+ break;
+ }
+#endif
default:
anv_debug_ignored_stype(ext->sType);
break;
@@ -348,6 +370,11 @@ VkResult genX(CreateSampler)(
.TCXAddressControlMode =
vk_to_gen_tex_address[pCreateInfo->
Re: [Mesa-dev] [Mesa-stable] [PATCH v2 1/2] i965/miptree: Fix can_blit_slice()
On Fri, Aug 10, 2018 at 02:12:55PM -0700, Dylan Baker wrote:
> Quoting Nanley Chery (2018-08-10 10:23:34)
> > Satisfy the BLT engine's row pitch limitation on the destination
> > miptree. The destination miptree is untiled, so its row_pitch will be
> > slightly less than or equal to the source miptree's row_pitch. Use the
> > source miptree's row_pitch in can_blit_slice instead of its blt_pitch.
> >
> > Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> > ("i965/miptree: Use the correct BLT pitch")
>
> For the scripts in stable to pick this up I believe you need a ":", as in
> Fixes: abc123 ("some patch")
>
Thanks. Fixed locally.
-Nanley
> Dylan
>
> >
> > Cc:
> > Reported-by: Dylan Baker
> > ---
> > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++--
> > 1 file changed, 7 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > index a18d5ac3624..d8e823e4826 100644
> > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > @@ -3544,8 +3544,13 @@ static bool
> > can_blit_slice(struct intel_mipmap_tree *mt,
> > unsigned int level, unsigned int slice)
> > {
> > - /* See intel_miptree_blit() for details on the 32k pitch limit. */
> > - if (intel_miptree_blt_pitch(mt) >= 32768)
> > + /* The blit destination is untiled, so its row_pitch will be slightly
> > less
> > +* than or equal to the source's row_pitch. The BLT engine only supports
> > +* linear row pitches up to but not including 32k.
> > +*
> > +* See intel_miptree_blit() for details on the 32k pitch limit.
> > +*/
> > + if (mt->surf.row_pitch >= 32768)
> >return false;
> >
> > return true;
> > --
> > 2.18.0
> >
> > ___
> > mesa-stable mailing list
> > mesa-sta...@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-stable
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Re: [Mesa-dev] [PATCH 1/2] vc4: Wire up core pipe_debug_callback
Rhys Kidd writes: > Signed-off-by: Rhys Kidd Does this actually do anything for us, though? Shouldn't we be hooking up our perf_debug() calls to it? signature.asc Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
On August 10, 2018 13:25:04 Kenneth Graunke wrote:
On Friday, August 10, 2018 8:34:12 AM PDT Jason Ekstrand wrote:
On August 10, 2018 03:19:18 Kenneth Graunke wrote:
The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
Jason decided to fake it with a bit of shader math and R32_UNORM RTs.
The only problem is that R32_UNORM isn't renderable either...so we've
just traded one bad format for another.
This patch makes us use R32_UINT instead.
---
src/intel/blorp/blorp_blit.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index c85ec8543a9..7b49f9afa35 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -984,14 +984,15 @@ convert_color(struct nir_builder *b, nir_ssa_def *color,
nir_ssa_def *value;
if (key->dst_format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
- /* The destination image is bound as R32_UNORM but the data needs to be
+ /* The destination image is bound as R32_UINT but the data needs to be
* in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
* top 8 need to be zero. We can accomplish this by simply multiplying
* by a factor to scale things down.
*/
- float factor = (float)((1 << 24) - 1) / (float)UINT32_MAX;
- value = nir_fmul(b, nir_fsat(b, nir_channel(b, color, 0)),
- nir_imm_float(b, factor));
+ unsigned factor = (1 << 24) - 1;
+ value = nir_fsat(b, nir_channel(b, color, 0));
+ value = nir_fmul(b, value, nir_imm_float(b, factor));
+ value = nir_iand(b, nir_f2i32(b, value), nir_imm_int(b, factor));
Do we really need the and?
Probably not - without it, we'll just leave garbage in the X8 bits
instead of zeroing them. But that's probably fine, unless it affects
HiZ compression somehow? I was mostly borrowing from u_format_zs.c
code to do this without thinking too hard.
That would only matter of mul(sat(x), factor) produces something outside
the range [0, factor+1). I really don't think it's doing anything useful.
--Jason
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[Mesa-dev] [PATCH v3] python: Rework bytes/unicode string handling
In both Python 2 and 3, opening a file without specifying the mode will
open it for reading in text mode ('r').
On Python 2, the read() method of a file object opened in mode 'r' will
return byte strings, while on Python 3 it will return unicode strings.
Explicitly specifying the binary mode ('rb') then decoding the byte
string means we always handle unicode strings on both Python 2 and 3.
Which in turns means all re.match(line) will return unicode strings as
well.
If we also make expandCString return unicode strings, we don't need the
call to the unicode() constructor any more.
We were using the ugettext() method because it always returns unicode
strings in Python 2, contrarily to the gettext() one which returns
byte strings. The ugettext() method doesn't exist on Python 3, so we
must use the right method on each version of Python.
The last hurdles are that Python 3 doesn't let us concatenate unicode
and byte strings directly, and that Python 2's stdout wants encoded byte
strings while Python 3's want unicode strings.
With these changes, the script gives the same output on both Python 2
and 3.
Signed-off-by: Mathieu Bridon
---
src/util/xmlpool/gen_xmlpool.py | 41 +
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/src/util/xmlpool/gen_xmlpool.py b/src/util/xmlpool/gen_xmlpool.py
index b0db183854..327709c7f8 100644
--- a/src/util/xmlpool/gen_xmlpool.py
+++ b/src/util/xmlpool/gen_xmlpool.py
@@ -13,6 +13,12 @@ import sys
import gettext
import re
+
+if sys.version_info < (3, 0):
+gettext_method = 'ugettext'
+else:
+gettext_method = 'gettext'
+
# Path to t_options.h
template_header_path = sys.argv[1]
@@ -60,7 +66,7 @@ def expandCString (s):
octa = False
num = 0
digits = 0
-r = ''
+r = u''
while i < len(s):
if not escape:
if s[i] == '\\':
@@ -128,16 +134,29 @@ def expandMatches (matches, translations, end=None):
if len(matches) == 1 and i < len(translations) and \
not matches[0].expand (r'\7').endswith('\\'):
suffix = ' \\'
-# Expand the description line. Need to use ugettext in order to allow
-# non-ascii unicode chars in the original English descriptions.
-text = escapeCString (trans.ugettext (unicode (expandCString (
-matches[0].expand (r'\5')), "utf-8"))).encode("utf-8")
-print(matches[0].expand (r'\1' + lang + r'\3"' + text + r'"\7') +
suffix)
+text = escapeCString (getattr(trans, gettext_method) (expandCString (
+matches[0].expand (r'\5'
+text = (matches[0].expand (r'\1' + lang + r'\3"' + text + r'"\7') +
suffix)
+
+# In Python 2, stdout expects encoded byte strings, or else it will
+# encode them with the ascii 'codec'
+if sys.version_info.major == 2:
+text = text.encode('utf-8')
+
+print(text)
+
# Expand any subsequent enum lines
for match in matches[1:]:
-text = escapeCString (trans.ugettext (unicode (expandCString (
-match.expand (r'\3')), "utf-8"))).encode("utf-8")
-print(match.expand (r'\1"' + text + r'"\5'))
+text = escapeCString (getattr(trans, gettext_method)
(expandCString (
+match.expand (r'\3'
+text = match.expand (r'\1"' + text + r'"\5')
+
+# In Python 2, stdout expects encoded byte strings, or else it will
+# encode them with the ascii 'codec'
+if sys.version_info.major == 2:
+text = text.encode('utf-8')
+
+print(text)
# Expand description end
if end:
@@ -168,9 +187,11 @@
print("/***\
# Process the options template and generate options.h with all
# translations.
-template = open (template_header_path, "r")
+template = open (template_header_path, "rb")
descMatches = []
for line in template:
+line = line.decode('utf-8')
+
if len(descMatches) > 0:
matchENUM = reENUM.match (line)
matchDESC_END = reDESC_END.match (line)
--
2.17.1
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Re: [Mesa-dev] [Mesa-stable] [PATCH v2 1/2] i965/miptree: Fix can_blit_slice()
Quoting Nanley Chery (2018-08-10 10:23:34)
> Satisfy the BLT engine's row pitch limitation on the destination
> miptree. The destination miptree is untiled, so its row_pitch will be
> slightly less than or equal to the source miptree's row_pitch. Use the
> source miptree's row_pitch in can_blit_slice instead of its blt_pitch.
>
> Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
> ("i965/miptree: Use the correct BLT pitch")
For the scripts in stable to pick this up I believe you need a ":", as in
Fixes: abc123 ("some patch")
Dylan
>
> Cc:
> Reported-by: Dylan Baker
> ---
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> index a18d5ac3624..d8e823e4826 100644
> --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> @@ -3544,8 +3544,13 @@ static bool
> can_blit_slice(struct intel_mipmap_tree *mt,
> unsigned int level, unsigned int slice)
> {
> - /* See intel_miptree_blit() for details on the 32k pitch limit. */
> - if (intel_miptree_blt_pitch(mt) >= 32768)
> + /* The blit destination is untiled, so its row_pitch will be slightly less
> +* than or equal to the source's row_pitch. The BLT engine only supports
> +* linear row pitches up to but not including 32k.
> +*
> +* See intel_miptree_blit() for details on the 32k pitch limit.
> +*/
> + if (mt->surf.row_pitch >= 32768)
>return false;
>
> return true;
> --
> 2.18.0
>
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[Mesa-dev] [Bug 107530] [Regression] widgets rendered black in gtk
https://bugs.freedesktop.org/show_bug.cgi?id=107530 --- Comment #5 from Lionel Landwerlin --- (In reply to Lukas K. from comment #4) > (In reply to Lionel Landwerlin from comment #1) > > What window system is GTK+ using? (Wayland/X11) > X11 1.20.0 > > What's the compositor? > None, but using compton doesn't change anything. > > Seems like this issue is specific to the modesetting driver. Using the > xf86-video-intel driver 1:2.99.917+831+ge7bfc906 works fine. I can reproduce with Xwayland & gnome-shell. Interestingly not with mutter running nested. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v3 2/4] gm107/ir: add support for OP_XMAD on GM107+
On Fri, Aug 10, 2018 at 8:36 PM, Rhys Perry wrote:
> Yeah, "immediate = false;" looks incorrect.
>
> Looking at nvdisasm and the placement of XMAD's various atoms, it seems it
> can only have 16-bit unsigned immediates, so envydis and the patches
> should probably be updated.
>
> As for how multiplication by immediates work with mul/mad -> XMAD
> conversion, the actual conversion should be done before LoadPropagation
> (so it doesn't have to worry about them and it's free of IMUL/IMAD's
> limitations) and the immediates should be propagated when possible later.
>
> After adjusting emitXMAD and TargetNVC0::insnCanLoad, I think the problem
> would be solved.
>
My point was if LoadPropagation would actually load 17+ bit sized
immediates into XMAD
> On Thu, Aug 9, 2018 at 11:32 PM, Karol Herbst wrote:
>> On Mon, Jul 23, 2018 at 12:40 PM, Rhys Perry
>> wrote:
>>> Signed-off-by: Rhys Perry
>>> ---
>>> .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 65
>>> ++
>>> .../nouveau/codegen/nv50_ir_target_gm107.cpp | 6 +-
>>> .../nouveau/codegen/nv50_ir_target_nvc0.cpp| 1 +
>>> 3 files changed, 71 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>>> index 1d31f181e4..c3d7be0f0e 100644
>>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>>> @@ -156,6 +156,7 @@ private:
>>> void emitIMUL();
>>> void emitIMAD();
>>> void emitISCADD();
>>> + void emitXMAD();
>>> void emitIMNMX();
>>> void emitICMP();
>>> void emitISET();
>>> @@ -1892,6 +1893,67 @@ CodeEmitterGM107::emitISCADD()
>>> emitGPR (0x00, insn->def(0));
>>> }
>>>
>>> +void
>>> +CodeEmitterGM107::emitXMAD()
>>> +{
>>> + assert(insn->src(0).getFile() == FILE_GPR);
>>> +
>>> + bool constbuf = false;
>>> + bool psl_mrg = true;
>>> + bool immediate = false;
>>> + if (insn->src(2).getFile() == FILE_MEMORY_CONST) {
>>> + assert(insn->src(1).getFile() == FILE_GPR);
>>> + constbuf = true;
>>> + psl_mrg = false;
>>> + emitInsn(0x5100);
>>> + emitGPR(0x27, insn->src(1));
>>> + emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(2));
>>> + } else if (insn->src(1).getFile() == FILE_MEMORY_CONST) {
>>> + assert(insn->src(2).getFile() == FILE_GPR);
>>> + constbuf = true;
>>> + emitInsn(0x4e00);
>>> + emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(1));
>>> + emitGPR(0x27, insn->src(2));
>>> + } else if (insn->src(1).getFile() == FILE_IMMEDIATE) {
>>> + assert(insn->src(2).getFile() == FILE_GPR);
>>> + assert(!(insn->subOp & NV50_IR_SUBOP_XMAD_H1(1)));
>>> + immediate = false;
>>
>> has to be immediate = true;
>>
>>> + emitInsn(0x3600);
>>> + emitIMMD(0x14, 19, insn->src(1));
>>
>> we can only do 16 bit sized immediates with XMAD I think. I think we
>> also have to adjust the target so that those don't get load
>> propagated? How does this works out for mul/mad -> XMAD conversions
>> anyway? We might want to recheck that we actually do the right thing
>> there actually (or maybe it doesn't come up, still, would be nice to
>> fix it inside the target in case it is actually buggy).
>>
>>> + emitGPR(0x27, insn->src(2));
>>> + } else {
>>> + assert(insn->src(1).getFile() == FILE_GPR);
>>> + assert(insn->src(2).getFile() == FILE_GPR);
>>> + emitInsn(0x5b00);
>>> + emitGPR(0x14, insn->src(1));
>>> + emitGPR(0x27, insn->src(2));
>>> + }
>>> +
>>> + if (psl_mrg)
>>> + emitField(constbuf ? 0x37 : 0x24, 2, insn->subOp & 0x3);
>>> +
>>> + unsigned cmode = (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK);
>>> + cmode >>= NV50_IR_SUBOP_XMAD_CMODE_SHIFT;
>>> + emitField(0x32, constbuf ? 2 : 3, cmode);
>>> +
>>> + emitX(constbuf ? 0x36 : 0x26);
>>> + emitCC(0x2f);
>>> +
>>> + emitGPR(0x0, insn->def(0));
>>> + emitGPR(0x8, insn->src(0));
>>> +
>>> + // source flags
>>> + if (isSignedType(insn->sType)) {
>>> + uint16_t h1s = insn->subOp & NV50_IR_SUBOP_XMAD_H1_MASK;
>>> + emitField(0x30, 2, h1s >> NV50_IR_SUBOP_XMAD_H1_SHIFT);
>>> + }
>>> + emitField(0x35, 1, insn->subOp & NV50_IR_SUBOP_XMAD_H1(0) ? 1 : 0);
>>> + if (!immediate) {
>>> + bool h1 = insn->subOp & NV50_IR_SUBOP_XMAD_H1(1);
>>> + emitField(constbuf ? 0x34 : 0x23, 1, h1);
>>> + }
>>> +}
>>> +
>>> void
>>> CodeEmitterGM107::emitIMNMX()
>>> {
>>> @@ -3266,6 +3328,9 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
>>> case OP_SHLADD:
>>>emitISCADD();
>>>break;
>>> + case OP_XMAD:
>>> + emitXMAD();
>>> + break;
>>> case OP_MIN:
>>> case OP_MAX:
>>>if (isFloatType(insn->dType)) {
>>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
>>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
>
[Mesa-dev] [Bug 107530] [Regression] widgets rendered black in gtk
https://bugs.freedesktop.org/show_bug.cgi?id=107530 --- Comment #4 from Lukas K. --- (In reply to Lionel Landwerlin from comment #1) > What window system is GTK+ using? (Wayland/X11) X11 1.20.0 > What's the compositor? None, but using compton doesn't change anything. Seems like this issue is specific to the modesetting driver. Using the xf86-video-intel driver 1:2.99.917+831+ge7bfc906 works fine. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v3 2/4] gm107/ir: add support for OP_XMAD on GM107+
Yeah, "immediate = false;" looks incorrect.
Looking at nvdisasm and the placement of XMAD's various atoms, it seems it
can only have 16-bit unsigned immediates, so envydis and the patches
should probably be updated.
As for how multiplication by immediates work with mul/mad -> XMAD
conversion, the actual conversion should be done before LoadPropagation
(so it doesn't have to worry about them and it's free of IMUL/IMAD's
limitations) and the immediates should be propagated when possible later.
After adjusting emitXMAD and TargetNVC0::insnCanLoad, I think the problem
would be solved.
On Thu, Aug 9, 2018 at 11:32 PM, Karol Herbst wrote:
> On Mon, Jul 23, 2018 at 12:40 PM, Rhys Perry wrote:
>> Signed-off-by: Rhys Perry
>> ---
>> .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 65
>> ++
>> .../nouveau/codegen/nv50_ir_target_gm107.cpp | 6 +-
>> .../nouveau/codegen/nv50_ir_target_nvc0.cpp| 1 +
>> 3 files changed, 71 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>> index 1d31f181e4..c3d7be0f0e 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
>> @@ -156,6 +156,7 @@ private:
>> void emitIMUL();
>> void emitIMAD();
>> void emitISCADD();
>> + void emitXMAD();
>> void emitIMNMX();
>> void emitICMP();
>> void emitISET();
>> @@ -1892,6 +1893,67 @@ CodeEmitterGM107::emitISCADD()
>> emitGPR (0x00, insn->def(0));
>> }
>>
>> +void
>> +CodeEmitterGM107::emitXMAD()
>> +{
>> + assert(insn->src(0).getFile() == FILE_GPR);
>> +
>> + bool constbuf = false;
>> + bool psl_mrg = true;
>> + bool immediate = false;
>> + if (insn->src(2).getFile() == FILE_MEMORY_CONST) {
>> + assert(insn->src(1).getFile() == FILE_GPR);
>> + constbuf = true;
>> + psl_mrg = false;
>> + emitInsn(0x5100);
>> + emitGPR(0x27, insn->src(1));
>> + emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(2));
>> + } else if (insn->src(1).getFile() == FILE_MEMORY_CONST) {
>> + assert(insn->src(2).getFile() == FILE_GPR);
>> + constbuf = true;
>> + emitInsn(0x4e00);
>> + emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(1));
>> + emitGPR(0x27, insn->src(2));
>> + } else if (insn->src(1).getFile() == FILE_IMMEDIATE) {
>> + assert(insn->src(2).getFile() == FILE_GPR);
>> + assert(!(insn->subOp & NV50_IR_SUBOP_XMAD_H1(1)));
>> + immediate = false;
>
> has to be immediate = true;
>
>> + emitInsn(0x3600);
>> + emitIMMD(0x14, 19, insn->src(1));
>
> we can only do 16 bit sized immediates with XMAD I think. I think we
> also have to adjust the target so that those don't get load
> propagated? How does this works out for mul/mad -> XMAD conversions
> anyway? We might want to recheck that we actually do the right thing
> there actually (or maybe it doesn't come up, still, would be nice to
> fix it inside the target in case it is actually buggy).
>
>> + emitGPR(0x27, insn->src(2));
>> + } else {
>> + assert(insn->src(1).getFile() == FILE_GPR);
>> + assert(insn->src(2).getFile() == FILE_GPR);
>> + emitInsn(0x5b00);
>> + emitGPR(0x14, insn->src(1));
>> + emitGPR(0x27, insn->src(2));
>> + }
>> +
>> + if (psl_mrg)
>> + emitField(constbuf ? 0x37 : 0x24, 2, insn->subOp & 0x3);
>> +
>> + unsigned cmode = (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK);
>> + cmode >>= NV50_IR_SUBOP_XMAD_CMODE_SHIFT;
>> + emitField(0x32, constbuf ? 2 : 3, cmode);
>> +
>> + emitX(constbuf ? 0x36 : 0x26);
>> + emitCC(0x2f);
>> +
>> + emitGPR(0x0, insn->def(0));
>> + emitGPR(0x8, insn->src(0));
>> +
>> + // source flags
>> + if (isSignedType(insn->sType)) {
>> + uint16_t h1s = insn->subOp & NV50_IR_SUBOP_XMAD_H1_MASK;
>> + emitField(0x30, 2, h1s >> NV50_IR_SUBOP_XMAD_H1_SHIFT);
>> + }
>> + emitField(0x35, 1, insn->subOp & NV50_IR_SUBOP_XMAD_H1(0) ? 1 : 0);
>> + if (!immediate) {
>> + bool h1 = insn->subOp & NV50_IR_SUBOP_XMAD_H1(1);
>> + emitField(constbuf ? 0x34 : 0x23, 1, h1);
>> + }
>> +}
>> +
>> void
>> CodeEmitterGM107::emitIMNMX()
>> {
>> @@ -3266,6 +3328,9 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
>> case OP_SHLADD:
>>emitISCADD();
>>break;
>> + case OP_XMAD:
>> + emitXMAD();
>> + break;
>> case OP_MIN:
>> case OP_MAX:
>>if (isFloatType(insn->dType)) {
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
>> index 7293fb27dd..bb1c234c43 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
>> @@ -60,8 +60,11 @@ TargetGM107::isOpSupported(operation op, DataType ty)
>> const
>> case OP_SQRT:
[Mesa-dev] [PATCH 3/3] radeonsi: enable 1 missing PS_SU perf counter on Polaris
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_perfcounter.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c
b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 43bf887b774..c4f6e164fb5 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -370,21 +370,21 @@ static struct si_pc_block groups_CIK[] = {
{ &cik_CPC, 22 },
};
static struct si_pc_block groups_VI[] = {
{ &cik_CB, 405},
{ &cik_CPF, 19 },
{ &cik_DB, 257},
{ &cik_GRBM, 34 },
{ &cik_GRBMSE, 15 },
- { &cik_PA_SU, 153 },
+ { &cik_PA_SU, 154 },
{ &cik_PA_SC, 397 },
{ &cik_SPI, 197 },
{ &cik_SQ, 273 },
{ &cik_SX, 34 },
{ &cik_TA, 119, 16 },
{ &cik_TCA, 35, 2 },
{ &cik_TCC, 192},
{ &cik_TD, 55, 16 },
{ &cik_TCP, 180, 16 },
{ &cik_GDS, 121 },
--
2.17.1
___
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[Mesa-dev] [PATCH 2/3] radeonsi: use radeon_info::name
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_get.c | 49 ++
src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
src/gallium/drivers/radeonsi/si_pipe.h | 1 -
3 files changed, 12 insertions(+), 40 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_get.c
b/src/gallium/drivers/radeonsi/si_get.c
index 6e804797bab..d9b3a31356c 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -47,50 +47,20 @@ static const char *si_get_device_vendor(struct pipe_screen
*pscreen)
return "AMD";
}
static const char *si_get_marketing_name(struct radeon_winsys *ws)
{
if (!ws->get_chip_name)
return NULL;
return ws->get_chip_name(ws);
}
-const char *si_get_family_name(const struct si_screen *sscreen)
-{
- switch (sscreen->info.family) {
- case CHIP_TAHITI: return "AMD TAHITI";
- case CHIP_PITCAIRN: return "AMD PITCAIRN";
- case CHIP_VERDE: return "AMD CAPE VERDE";
- case CHIP_OLAND: return "AMD OLAND";
- case CHIP_HAINAN: return "AMD HAINAN";
- case CHIP_BONAIRE: return "AMD BONAIRE";
- case CHIP_KAVERI: return "AMD KAVERI";
- case CHIP_KABINI: return "AMD KABINI";
- case CHIP_HAWAII: return "AMD HAWAII";
- case CHIP_MULLINS: return "AMD MULLINS";
- case CHIP_TONGA: return "AMD TONGA";
- case CHIP_ICELAND: return "AMD ICELAND";
- case CHIP_CARRIZO: return "AMD CARRIZO";
- case CHIP_FIJI: return "AMD FIJI";
- case CHIP_STONEY: return "AMD STONEY";
- case CHIP_POLARIS10: return "AMD POLARIS10";
- case CHIP_POLARIS11: return "AMD POLARIS11";
- case CHIP_POLARIS12: return "AMD POLARIS12";
- case CHIP_VEGAM: return "AMD VEGAM";
- case CHIP_VEGA10: return "AMD VEGA10";
- case CHIP_VEGA12: return "AMD VEGA12";
- case CHIP_VEGA20: return "AMD VEGA20";
- case CHIP_RAVEN: return "AMD RAVEN";
- default: return "AMD unknown";
- }
-}
-
static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
switch (param) {
/* Supported features (boolean caps). */
case PIPE_CAP_ACCELERATED:
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
@@ -949,38 +919,41 @@ static void si_query_memory_info(struct pipe_screen
*screen,
static struct disk_cache *si_get_disk_shader_cache(struct pipe_screen *pscreen)
{
struct si_screen *sscreen = (struct si_screen*)pscreen;
return sscreen->disk_shader_cache;
}
static void si_init_renderer_string(struct si_screen *sscreen)
{
struct radeon_winsys *ws = sscreen->ws;
- char family_name[32] = {}, kernel_version[128] = {};
+ char first_name[256], second_name[32] = {}, kernel_version[128] = {};
struct utsname uname_data;
- const char *chip_name = si_get_marketing_name(ws);
+ const char *marketing_name = si_get_marketing_name(ws);
- if (chip_name)
- snprintf(family_name, sizeof(family_name), "%s, ",
-si_get_family_name(sscreen) + 4);
- else
- chip_name = si_get_family_name(sscreen);
+ if (marketing_name) {
+ snprintf(first_name, sizeof(first_name), "%s", marketing_name);
+ snprintf(second_name, sizeof(second_name), "%s, ",
+sscreen->info.name);
+ } else {
+ snprintf(first_name, sizeof(first_name), "AMD %s",
+sscreen->info.name);
+ }
if (uname(&uname_data) == 0)
snprintf(kernel_version, sizeof(kernel_version),
", %s", uname_data.release);
snprintf(sscreen->renderer_string, sizeof(sscreen->renderer_string),
"%s (%sDRM %i.%i.%i%s, LLVM %i.%i.%i)",
-chip_name, family_name, sscreen->info.drm_major,
+first_name, second_name, sscreen->info.drm_major,
sscreen->info.drm_minor, sscreen->info.drm_patchlevel,
kernel_version,
(HAVE_LLVM >> 8) & 0xff,
HAVE_LLVM & 0xff,
MESA_LLVM_VERSION_PATCH);
}
void si_init_screen_get_functions(struct si_screen *sscreen)
{
sscreen->b.get_name = si_get_name;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 3ca53dfed7c..13fcf1f3aea 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -775,21 +775,21 @@ static void si_disk_cache_create(struct si_screen
*sscreen)
uint64_t shader_debug_flags = sscreen->debug_flags &
ALL_FLAGS;
/* Add the high bits of 32-bit addresses, which affects
[Mesa-dev] [PATCH 1/3] ac: add radeon_info::name
From: Marek Olšák
---
src/amd/common/ac_gpu_info.c | 6 +-
src/amd/common/ac_gpu_info.h | 1 +
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 7 ++-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 40441ec0c67..8705d878f9a 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -294,21 +294,25 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
* allocations can fail or cause buffer movement failures in
the kernel.
*/
info->max_alloc_size = MAX2(info->vram_size * 0.9,
info->gart_size * 0.7);
}
/* Set chip identification. */
info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
info->vce_harvest_config = amdinfo->vce_harvest_config;
switch (info->pci_id) {
-#define CHIPSET(pci_id, cfamily) case pci_id: info->family = CHIP_##cfamily;
break;
+#define CHIPSET(pci_id, cfamily) \
+ case pci_id: \
+ info->family = CHIP_##cfamily; \
+ info->name = #cfamily; \
+ break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
default:
fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
return false;
}
if (info->family >= CHIP_VEGA10)
info->chip_class = GFX9;
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index f6e09d2e13c..a897496da48 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -40,20 +40,21 @@ typedef struct amdgpu_device *amdgpu_device_handle;
struct amdgpu_gpu_info;
struct radeon_info {
/* PCI info: domain:bus:dev:func */
uint32_tpci_domain;
uint32_tpci_bus;
uint32_tpci_dev;
uint32_tpci_func;
/* Device info. */
+ const char *name;
uint32_tpci_id;
enum radeon_family family;
enum chip_class chip_class;
uint32_tnum_compute_rings;
uint32_tnum_sdma_rings;
uint32_tclock_crystal_freq;
uint32_ttcc_cache_line_size;
/* Memory info. */
uint32_tpte_fragment_size;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 491e8e159f4..f8702e7c601 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -175,21 +175,26 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
/* Check PCI ID. */
switch (ws->info.pci_id) {
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family =
CHIP_##cfamily; ws->gen = DRV_R300; break;
#include "pci_ids/r300_pci_ids.h"
#undef CHIPSET
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family =
CHIP_##cfamily; ws->gen = DRV_R600; break;
#include "pci_ids/r600_pci_ids.h"
#undef CHIPSET
-#define CHIPSET(pci_id, cfamily) case pci_id: ws->info.family =
CHIP_##cfamily; ws->gen = DRV_SI; break;
+#define CHIPSET(pci_id, cfamily) \
+case pci_id: \
+ws->info.family = CHIP_##cfamily; \
+ws->info.name = #cfamily; \
+ws->gen = DRV_SI; \
+break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
default:
fprintf(stderr, "radeon: Invalid PCI ID.\n");
return false;
}
switch (ws->info.family) {
default:
--
2.17.1
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Re: [Mesa-dev] [PATCH 1/2] blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
On Friday, August 10, 2018 8:34:12 AM PDT Jason Ekstrand wrote:
> On August 10, 2018 03:19:18 Kenneth Graunke wrote:
>
> > The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
> > Jason decided to fake it with a bit of shader math and R32_UNORM RTs.
> >
> > The only problem is that R32_UNORM isn't renderable either...so we've
> > just traded one bad format for another.
> >
> > This patch makes us use R32_UINT instead.
> > ---
> > src/intel/blorp/blorp_blit.c | 11 ++-
> > 1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
> > index c85ec8543a9..7b49f9afa35 100644
> > --- a/src/intel/blorp/blorp_blit.c
> > +++ b/src/intel/blorp/blorp_blit.c
> > @@ -984,14 +984,15 @@ convert_color(struct nir_builder *b, nir_ssa_def
> > *color,
> >nir_ssa_def *value;
> >
> >if (key->dst_format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
> > - /* The destination image is bound as R32_UNORM but the data needs to
> > be
> > + /* The destination image is bound as R32_UINT but the data needs to
> > be
> >* in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and
> > the
> >* top 8 need to be zero. We can accomplish this by simply
> > multiplying
> >* by a factor to scale things down.
> >*/
> > - float factor = (float)((1 << 24) - 1) / (float)UINT32_MAX;
> > - value = nir_fmul(b, nir_fsat(b, nir_channel(b, color, 0)),
> > - nir_imm_float(b, factor));
> > + unsigned factor = (1 << 24) - 1;
> > + value = nir_fsat(b, nir_channel(b, color, 0));
> > + value = nir_fmul(b, value, nir_imm_float(b, factor));
> > + value = nir_iand(b, nir_f2i32(b, value), nir_imm_int(b, factor));
>
> Do we really need the and?
Probably not - without it, we'll just leave garbage in the X8 bits
instead of zeroing them. But that's probably fine, unless it affects
HiZ compression somehow? I was mostly borrowing from u_format_zs.c
code to do this without thinking too hard.
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[Mesa-dev] [PATCH 02/14] mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES
From: Marek Olšák same number as our closed GL driver v2: don't use MaxArrayLockSize --- src/mesa/main/config.h | 3 +++ src/mesa/main/get_hash_params.py | 4 ++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h index 6a2f766222a..6f514650009 100644 --- a/src/mesa/main/config.h +++ b/src/mesa/main/config.h @@ -134,20 +134,23 @@ /** Maximum number of viewports supported with ARB_viewport_array */ #define MAX_VIEWPORTS 16 /** Maximum number of window rectangles supported with EXT_window_rectangles */ #define MAX_WINDOW_RECTANGLES 8 /** Maximum size for CVA. May be overridden by the drivers. */ #define MAX_ARRAY_LOCK_SIZE 3000 +/** For GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES. */ +#define MAX_ELEMENTS_VERTICES_INDICES (512 * 1024 * 1024) + /** Subpixel precision for antialiasing, window coordinate snapping */ #define SUB_PIXEL_BITS 4 /** For GL_ARB_texture_compression */ #define MAX_COMPRESSED_TEXTURE_FORMATS 25 /** For GL_EXT_texture_filter_anisotropic */ #define MAX_TEXTURE_MAX_ANISOTROPY 16.0 /** For GL_EXT_texture_lod_bias (typically MAX_TEXTURE_LEVELS - 1) */ diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py index 5c672a33123..03409daa8e7 100644 --- a/src/mesa/main/get_hash_params.py +++ b/src/mesa/main/get_hash_params.py @@ -12,22 +12,22 @@ descriptor=[ [ "DEPTH_CLEAR_VALUE", "CONTEXT_FIELD(Depth.Clear, TYPE_DOUBLEN), NO_EXTRA" ], [ "DEPTH_FUNC", "CONTEXT_ENUM16(Depth.Func), NO_EXTRA" ], [ "DEPTH_RANGE", "LOC_CUSTOM, TYPE_DOUBLEN_2, 0, NO_EXTRA" ], [ "DEPTH_TEST", "CONTEXT_BOOL(Depth.Test), NO_EXTRA" ], [ "DEPTH_WRITEMASK", "CONTEXT_BOOL(Depth.Mask), NO_EXTRA" ], [ "DITHER", "CONTEXT_BOOL(Color.DitherFlag), NO_EXTRA" ], [ "FRONT_FACE", "CONTEXT_ENUM16(Polygon.FrontFace), NO_EXTRA" ], [ "GREEN_BITS", "BUFFER_INT(Visual.greenBits), extra_new_buffers" ], [ "LINE_WIDTH", "CONTEXT_FLOAT(Line.Width), NO_EXTRA" ], [ "ALIASED_LINE_WIDTH_RANGE", "CONTEXT_FLOAT2(Const.MinLineWidth), NO_EXTRA" ], - [ "MAX_ELEMENTS_VERTICES", "CONTEXT_INT(Const.MaxArrayLockSize), NO_EXTRA" ], - [ "MAX_ELEMENTS_INDICES", "CONTEXT_INT(Const.MaxArrayLockSize), NO_EXTRA" ], + [ "MAX_ELEMENTS_VERTICES", "CONST(MAX_ELEMENTS_VERTICES_INDICES), NO_EXTRA" ], + [ "MAX_ELEMENTS_INDICES", "CONST(MAX_ELEMENTS_VERTICES_INDICES), NO_EXTRA" ], [ "MAX_TEXTURE_SIZE", "LOC_CUSTOM, TYPE_INT, offsetof(struct gl_context, Const.MaxTextureLevels), NO_EXTRA" ], [ "MAX_VIEWPORT_DIMS", "CONTEXT_INT2(Const.MaxViewportWidth), NO_EXTRA" ], [ "PACK_ALIGNMENT", "CONTEXT_INT(Pack.Alignment), NO_EXTRA" ], [ "ALIASED_POINT_SIZE_RANGE", "CONTEXT_FLOAT2(Const.MinPointSize), NO_EXTRA" ], [ "POLYGON_OFFSET_FACTOR", "CONTEXT_FLOAT(Polygon.OffsetFactor ), NO_EXTRA" ], [ "POLYGON_OFFSET_UNITS", "CONTEXT_FLOAT(Polygon.OffsetUnits ), NO_EXTRA" ], [ "POLYGON_OFFSET_FILL", "CONTEXT_BOOL(Polygon.OffsetFill), NO_EXTRA" ], [ "RED_BITS", "BUFFER_INT(Visual.redBits), extra_new_buffers" ], [ "SCISSOR_BOX", "LOC_CUSTOM, TYPE_INT_4, 0, NO_EXTRA" ], [ "SCISSOR_TEST", "LOC_CUSTOM, TYPE_BOOLEAN, NO_OFFSET, NO_EXTRA" ], -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [1/2] loader: add loader_open_name(..)
On 10 August 2018 at 13:25, Martin Fuzzey wrote: > Hi Christian, > > On 01/08/18 23:07, Christian Gmeiner wrote: >> >> Add an improved drmOpenWithType(..) clone which fixes some serious >> flaws. Some highlights: >> - using busid works only with PCI devices >> - open() w/o O_CLOEXEC >> - when build w/o udev - it creates a node: mkdir, chown(root), chmod, >> mknod >> - calls back into Xserver/DDX module >> - last but no least - borderline hacks with massive documentation [1] >> to keep this running. >> >> Signed-off-by: Christian Gmeiner > > > Why do this in mesa rather than fixing (or adding a new version if necessary > for backwards compatibility) to the libdrm code? > By fixing the libdrm code, we'll break old users - something that is a no-go for open-source projects. I've been slowly chipping on libdrm3 for far too long. Sadly it's not the most enjoyable thing to hack on in one's spare time. FWIW, Christian's second take on the topic is here [1]. HTH Emil [1] https://patchwork.freedesktop.org/series/47923/ ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] nv50/ir: silence partitionLoadStore() unused function warning
Move this now-unused function into the existing comment block, which was its
only prior use.
../../../../../src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp:2645:1:
warning:
unused function 'partitionLoadStore' [-Wunused-function]
partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
Fixes: 86e4440361 ("nouveau: codegen: Disable more old resource handling code")
Signed-off-by: Rhys Kidd
Cc: Hans de Goede
Cc: Samuel Pitoiset
---
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 2f9bcc1f34..c6e69ff123 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2640,7 +2640,7 @@ Converter::getResourceCoords(std::vector
&coords, int r, int s)
coords[0] = mkOp1v(OP_MOV, TYPE_U32, getScratch(4, FILE_ADDRESS),
coords[0]);
}
-*/
+
static inline int
partitionLoadStore(uint8_t comp[2], uint8_t size[2], uint8_t mask)
{
@@ -2665,7 +2665,7 @@ partitionLoadStore(uint8_t comp[2], uint8_t size[2],
uint8_t mask)
}
return n + 1;
}
-
+*/
void
Converter::getImageCoords(std::vector &coords, int s)
{
--
2.17.1
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Re: [Mesa-dev] [PATCH] intel/decoder: fix the possible out of bounds group_iter
On Fri, Aug 10, 2018 at 05:37:12PM +0100, Lionel Landwerlin wrote:
> Andrey also opened a bug about this issue :
> https://bugs.freedesktop.org/show_bug.cgi?id=107544
>
> It feels like it should be fixed on master though. get_length() shouldn't
> return -1 for structs anymore.
> We should probably return 1 at end of get_length() so that the decoder
> prints out "unknown instruction".
> That would help spot potential errors and updates needed to genxml.
Yeah, that makes sense. I saw the we were doing the check for length < 0
somewhere else so it seemed reasonable to check for that, considering we
can return -1, but I agree that printing "unknown instruction" would be
better.
> -
> Lionel
>
>
> On 10/08/18 16:48, Rafael Antognolli wrote:
> > On Thu, Aug 09, 2018 at 03:00:30PM +0300, andrey simiklit wrote:
> > > Hi,
> > >
> > > Sorry I missed the main thought here.
> > > The "gen_group_get_length" function returns int
> > > but the "iter_group_offset_bits" function returns uint32_t
> > > So uint32_t(int(-32)) = 0xFFE0U and it looks like unexpected behavior
> > > for
> > > me:
> > > iter_group_offset_bits(iter, iter->group_iter + 1) < 0xFFE0U;
> > That's fine, I think the original commit message is good enough to
> > understand this change. Feel free to add this extra bit too if you want,
> > but I don't think it's needed.
> >
> > Reviewed-by: Rafael Antognolli
> >
> > > Regards,
> > > Andrii.
> > >
> > > On Thu, Aug 9, 2018 at 2:35 PM, Andrii Simiklit
> > > wrote:
> > >
> > > The "gen_group_get_length" function can return a negative value
> > > and it can lead to the out of bounds group_iter.
> > >
> > > Signed-off-by: Andrii Simiklit
> > > ---
> > > src/intel/common/gen_decoder.c | 6 --
> > > 1 file changed, 4 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/src/intel/common/gen_decoder.c
> > > b/src/intel/common/gen_decoder
> > > .c
> > > index ec0a486..f09bd87 100644
> > > --- a/src/intel/common/gen_decoder.c
> > > +++ b/src/intel/common/gen_decoder.c
> > > @@ -803,8 +803,10 @@ static bool
> > > iter_more_groups(const struct gen_field_iterator *iter)
> > > {
> > > if (iter->group->variable) {
> > > - return iter_group_offset_bits(iter, iter->group_iter + 1) <
> > > - (gen_group_get_length(iter->group, iter->p) * 32);
> > > + const int length = gen_group_get_length(iter->group, iter->p);
> > > + return length > 0 &&
> > > + iter_group_offset_bits(iter, iter->group_iter + 1) <
> > > + (length * 32);
> > > } else {
> > > return (iter->group_iter + 1) < iter->group->group_count ||
> > >iter->group->next != NULL;
> > > --
> > > 2.7.4
> > >
> > >
> > >
>
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[Mesa-dev] [PATCH v2 2/2] intel/isl: Avoid tiling some 16K-wide render targets
Fix rendering issues on BDW and SKL.
Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
Fixes the following regressions seen
exclusively on SKL:
* KHR-GL46.texture_barrier_ARB.disjoint-texels
* KHR-GL46.texture_barrier_ARB.overlapping-texels
* KHR-GL46.texture_barrier.disjoint-texels
* KHR-GL46.texture_barrier.overlapping-texels
and both on BDW and SKL:
* GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners
* GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners
v2: Note the fixed tests (Andres).
Don't cause failures with multisampled surfaces (Andres).
Don't hamper SKL GT4 (Ken).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107359
Cc:
---
src/intel/isl/isl_gen7.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/src/intel/isl/isl_gen7.c b/src/intel/isl/isl_gen7.c
index 4fa9851233f..a9db21fba52 100644
--- a/src/intel/isl/isl_gen7.c
+++ b/src/intel/isl/isl_gen7.c
@@ -294,6 +294,29 @@ isl_gen6_filter_tiling(const struct isl_device *dev,
*/
if (ISL_DEV_GEN(dev) < 7 && isl_format_get_layout(info->format)->bpb >= 128)
*flags &= ~ISL_TILING_Y0_BIT;
+
+ /* From the BDW and SKL PRMs, Volume 2d,
+* RENDER_SURFACE_STATE::Width - Programming Notes:
+*
+* A known issue exists if a primitive is rendered to the first 2 rows and
+* last 2 columns of a 16K width surface. If any geometry is drawn inside
+* this square it will be copied to column X=2 and X=3 (arrangement on Y
+* position will stay the same). If any geometry exceeds the boundaries of
+* this 2x2 region it will be drawn normally. The issue also only occurs
+* if the surface has TileMode != Linear.
+*
+* [Internal documentation notes that this issue isn't present on SKL GT4.]
+* To prevent this rendering corruption, only allow linear tiling for
+* surfaces with widths greater than 16K-2 pixels.
+*
+* TODO: Is this an issue for multisampled surfaces as well?
+*/
+ if (info->width > 16382 && info->samples == 1 &&
+ info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT &&
+ (ISL_DEV_GEN(dev) == 8 ||
+(dev->info->is_skylake && dev->info->gt != 4))) {
+ *flags &= ISL_TILING_LINEAR_BIT;
+ }
}
void
--
2.18.0
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[Mesa-dev] [PATCH v2 1/2] i965/miptree: Fix can_blit_slice()
Satisfy the BLT engine's row pitch limitation on the destination
miptree. The destination miptree is untiled, so its row_pitch will be
slightly less than or equal to the source miptree's row_pitch. Use the
source miptree's row_pitch in can_blit_slice instead of its blt_pitch.
Fixes 0288fe8d0417730bdd5b3477130dd1dc32bdbcd3
("i965/miptree: Use the correct BLT pitch")
Cc:
Reported-by: Dylan Baker
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index a18d5ac3624..d8e823e4826 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -3544,8 +3544,13 @@ static bool
can_blit_slice(struct intel_mipmap_tree *mt,
unsigned int level, unsigned int slice)
{
- /* See intel_miptree_blit() for details on the 32k pitch limit. */
- if (intel_miptree_blt_pitch(mt) >= 32768)
+ /* The blit destination is untiled, so its row_pitch will be slightly less
+* than or equal to the source's row_pitch. The BLT engine only supports
+* linear row pitches up to but not including 32k.
+*
+* See intel_miptree_blit() for details on the 32k pitch limit.
+*/
+ if (mt->surf.row_pitch >= 32768)
return false;
return true;
--
2.18.0
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[Mesa-dev] Mesa 18.1.6 Release Notice
Hi list, Due to a busy week and a slip of my mind I didn't get out the announcement for 18.1.6 on Wednesday. Therefore, I'm planning to make the release Monday August 13th, at or around 10AM PDT. It's been another busy cycle for 18.1, currently we have: - 40 Queued - 0 Nominated - 0 Rejected All merge conflicts have already been followed up with the original patch authors. Please see the staging/18.1 branch if you are interested in which patches are queued for the release Dylan signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] v3d: Wire up core pipe_debug_callback
Signed-off-by: Rhys Kidd
---
src/gallium/drivers/v3d/v3d_context.c | 13 +
src/gallium/drivers/v3d/v3d_context.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/src/gallium/drivers/v3d/v3d_context.c
b/src/gallium/drivers/v3d/v3d_context.c
index 2fd2fa0bbf..0737713e8b 100644
--- a/src/gallium/drivers/v3d/v3d_context.c
+++ b/src/gallium/drivers/v3d/v3d_context.c
@@ -66,6 +66,18 @@ v3d_pipe_flush(struct pipe_context *pctx, struct
pipe_fence_handle **fence,
}
}
+static void
+v3d_set_debug_callback(struct pipe_context *pctx,
+ const struct pipe_debug_callback *cb)
+{
+struct v3d_context *v3d = v3d_context(pctx);
+
+if (cb)
+v3d->debug = *cb;
+else
+memset(&v3d->debug, 0, sizeof(v3d->debug));
+}
+
static void
v3d_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
{
@@ -138,6 +150,7 @@ v3d_context_create(struct pipe_screen *pscreen, void *priv,
unsigned flags)
pctx->priv = priv;
pctx->destroy = v3d_context_destroy;
pctx->flush = v3d_pipe_flush;
+pctx->set_debug_callback = v3d_set_debug_callback;
pctx->invalidate_resource = v3d_invalidate_resource;
if (screen->devinfo.ver >= 41) {
diff --git a/src/gallium/drivers/v3d/v3d_context.h
b/src/gallium/drivers/v3d/v3d_context.h
index f6720e2ca9..536ef61d0c 100644
--- a/src/gallium/drivers/v3d/v3d_context.h
+++ b/src/gallium/drivers/v3d/v3d_context.h
@@ -425,6 +425,7 @@ struct v3d_context {
struct v3d_vertexbuf_stateobj vertexbuf;
struct v3d_streamout_stateobj streamout;
struct v3d_bo *current_oq;
+struct pipe_debug_callback debug;
/** @} */
};
--
2.17.1
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[Mesa-dev] [PATCH 1/2] vc4: Wire up core pipe_debug_callback
Signed-off-by: Rhys Kidd
---
src/gallium/drivers/vc4/vc4_context.c | 13 +
src/gallium/drivers/vc4/vc4_context.h | 1 +
2 files changed, 14 insertions(+)
diff --git a/src/gallium/drivers/vc4/vc4_context.c
b/src/gallium/drivers/vc4/vc4_context.c
index 9ff39c2655..6f91d0567c 100644
--- a/src/gallium/drivers/vc4/vc4_context.c
+++ b/src/gallium/drivers/vc4/vc4_context.c
@@ -85,6 +85,18 @@ vc4_texture_barrier(struct pipe_context *pctx, unsigned
flags)
vc4_flush(pctx);
}
+static void
+vc4_set_debug_callback(struct pipe_context *pctx,
+ const struct pipe_debug_callback *cb)
+{
+struct vc4_context *vc4 = vc4_context(pctx);
+
+if (cb)
+vc4->debug = *cb;
+else
+memset(&vc4->debug, 0, sizeof(vc4->debug));
+}
+
static void
vc4_invalidate_resource(struct pipe_context *pctx, struct pipe_resource *prsc)
{
@@ -165,6 +177,7 @@ vc4_context_create(struct pipe_screen *pscreen, void *priv,
unsigned flags)
pctx->priv = priv;
pctx->destroy = vc4_context_destroy;
pctx->flush = vc4_pipe_flush;
+pctx->set_debug_callback = vc4_set_debug_callback;
pctx->invalidate_resource = vc4_invalidate_resource;
pctx->texture_barrier = vc4_texture_barrier;
diff --git a/src/gallium/drivers/vc4/vc4_context.h
b/src/gallium/drivers/vc4/vc4_context.h
index ce8bcffac0..c162f19ba1 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -405,6 +405,7 @@ struct vc4_context {
struct pipe_viewport_state viewport;
struct vc4_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
struct vc4_vertexbuf_stateobj vertexbuf;
+struct pipe_debug_callback debug;
struct vc4_hwperfmon *perfmon;
/** @} */
--
2.17.1
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Re: [Mesa-dev] [PATCH] intel/decoder: fix the possible out of bounds group_iter
Andrey also opened a bug about this issue :
https://bugs.freedesktop.org/show_bug.cgi?id=107544
It feels like it should be fixed on master though. get_length()
shouldn't return -1 for structs anymore.
We should probably return 1 at end of get_length() so that the decoder
prints out "unknown instruction".
That would help spot potential errors and updates needed to genxml.
-
Lionel
On 10/08/18 16:48, Rafael Antognolli wrote:
On Thu, Aug 09, 2018 at 03:00:30PM +0300, andrey simiklit wrote:
Hi,
Sorry I missed the main thought here.
The "gen_group_get_length" function returns int
but the "iter_group_offset_bits" function returns uint32_t
So uint32_t(int(-32)) = 0xFFE0U and it looks like unexpected behavior for
me:
iter_group_offset_bits(iter, iter->group_iter + 1) < 0xFFE0U;
That's fine, I think the original commit message is good enough to
understand this change. Feel free to add this extra bit too if you want,
but I don't think it's needed.
Reviewed-by: Rafael Antognolli
Regards,
Andrii.
On Thu, Aug 9, 2018 at 2:35 PM, Andrii Simiklit
wrote:
The "gen_group_get_length" function can return a negative value
and it can lead to the out of bounds group_iter.
Signed-off-by: Andrii Simiklit
---
src/intel/common/gen_decoder.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder
.c
index ec0a486..f09bd87 100644
--- a/src/intel/common/gen_decoder.c
+++ b/src/intel/common/gen_decoder.c
@@ -803,8 +803,10 @@ static bool
iter_more_groups(const struct gen_field_iterator *iter)
{
if (iter->group->variable) {
- return iter_group_offset_bits(iter, iter->group_iter + 1) <
- (gen_group_get_length(iter->group, iter->p) * 32);
+ const int length = gen_group_get_length(iter->group, iter->p);
+ return length > 0 &&
+ iter_group_offset_bits(iter, iter->group_iter + 1) <
+ (length * 32);
} else {
return (iter->group_iter + 1) < iter->group->group_count ||
iter->group->next != NULL;
--
2.7.4
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Re: [Mesa-dev] [PATCH v3 1/4] nv50/ir: add preliminary support for OP_XMAD
I don't think so.
On Wed, Aug 8, 2018 at 11:27 PM, Karol Herbst wrote:
> On Mon, Jul 23, 2018 at 12:40 PM, Rhys Perry wrote:
>> Signed-off-by: Rhys Perry
>> ---
>> src/gallium/drivers/nouveau/codegen/nv50_ir.h | 26
>> ++
>> .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 18 +--
>> .../drivers/nouveau/codegen/nv50_ir_print.cpp | 19
>> .../drivers/nouveau/codegen/nv50_ir_target.cpp | 7 +++---
>> .../nouveau/codegen/nv50_ir_target_gm107.cpp | 1 +
>> .../nouveau/codegen/nv50_ir_target_nv50.cpp| 1 +
>> .../nouveau/codegen/nv50_ir_target_nvc0.cpp| 15 +
>> 7 files changed, 82 insertions(+), 5 deletions(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
>> index 0b220cc48d..13822a08c3 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
>> @@ -58,6 +58,9 @@ enum operation
>> OP_FMA,
>> OP_SAD, // abs(src0 - src1) + src2
>> OP_SHLADD,
>> + // extended multiply-add (GM107+), does a lot of things.
>> + // see envytools for detailed documentation
>> + OP_XMAD,
>> OP_ABS,
>> OP_NEG,
>> OP_NOT,
>> @@ -256,6 +259,29 @@ enum operation
>> #define NV50_IR_SUBOP_MINMAX_MED 2
>> #define NV50_IR_SUBOP_MINMAX_HIGH 3
>>
>> +// xmad(src0, src1, 0) << 16 + src2
>> +#define NV50_IR_SUBOP_XMAD_PSL (1 << 0)
>> +// (xmad(src0, src1, src2) & 0x) | (src1 << 16)
>> +#define NV50_IR_SUBOP_XMAD_MRG (1 << 1)
>> +// xmad(src0, src1, src2.lo)
>> +#define NV50_IR_SUBOP_XMAD_CLO (1 << 2)
>> +// xmad(src0, src1, src2.hi)
>> +#define NV50_IR_SUBOP_XMAD_CHI (2 << 2)
>> +// if both operands to the multiplication are non-zero, subtract 65536 for
>> each
>> +// negative operand
>> +#define NV50_IR_SUBOP_XMAD_CSFU (3 << 2)
>> +// xmad(src0, src1, src2) + src1 << 16
>> +#define NV50_IR_SUBOP_XMAD_CBCC (4 << 2)
>> +#define NV50_IR_SUBOP_XMAD_CMODE_SHIFT 2
>> +#define NV50_IR_SUBOP_XMAD_CMODE_MASK uint16_t(0x7 <<
>> NV50_IR_SUBOP_XMAD_CMODE_SHIFT)
>> +
>> +// use the high 16 bits instead of the low 16 bits for the multiplication.
>> +// if the instruction's sType is signed, sign extend the operand from 16
>> bits
>> +// to 32 before multiplication.
>> +#define NV50_IR_SUBOP_XMAD_H1_SHIFT 5
>> +#define NV50_IR_SUBOP_XMAD_H1(i) (1 << (NV50_IR_SUBOP_XMAD_H1_SHIFT + (i)))
>> +#define NV50_IR_SUBOP_XMAD_H1_MASK uint16_t(0x3 <<
>> NV50_IR_SUBOP_XMAD_H1_SHIFT)
>
> is the uint16_t really needed?
>
>> +
>> enum DataType
>> {
>> TYPE_NONE,
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> index 16022e6f23..6deea7a360 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
>> @@ -191,9 +191,17 @@ void
>> LoadPropagation::checkSwapSrc01(Instruction *insn)
>> {
>> const Target *targ = prog->getTarget();
>> - if (!targ->getOpInfo(insn).commutative)
>> - if (insn->op != OP_SET && insn->op != OP_SLCT && insn->op != OP_SUB)
>> + if (!targ->getOpInfo(insn).commutative) {
>> + if (insn->op != OP_SET && insn->op != OP_SLCT &&
>> + insn->op != OP_SUB && insn->op != OP_XMAD)
>> return;
>> + // XMAD is only commutative if both the CBCC and MRG flags are not
>> set.
>> + if (insn->op == OP_XMAD &&
>> + (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK) ==
>> NV50_IR_SUBOP_XMAD_CBCC)
>> + return;
>> + if (insn->op == OP_XMAD && (insn->subOp & NV50_IR_SUBOP_XMAD_MRG))
>> + return;
>> + }
>> if (insn->src(1).getFile() != FILE_GPR)
>>return;
>> // This is the special OP_SET used for alphatesting, we can't reverse its
>> @@ -236,6 +244,12 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
>> if (insn->op == OP_SUB) {
>>insn->src(0).mod = insn->src(0).mod ^ Modifier(NV50_IR_MOD_NEG);
>>insn->src(1).mod = insn->src(1).mod ^ Modifier(NV50_IR_MOD_NEG);
>> + } else
>> + if (insn->op == OP_XMAD) {
>> + // swap h1 flags
>> + uint16_t h1 = (insn->subOp >> 1 & NV50_IR_SUBOP_XMAD_H1(0)) |
>> +(insn->subOp << 1 & NV50_IR_SUBOP_XMAD_H1(1));
>> + insn->subOp = (insn->subOp & ~NV50_IR_SUBOP_XMAD_H1_MASK) | h1;
>> }
>> }
>>
>> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
>> b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
>> index ee3506fbae..7eab8b8d70 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
>> @@ -86,6 +86,7 @@ const char *operationStr[OP_LAST + 1] =
>> "fma",
>> "sad",
>> "shladd",
>> + "xmad",
>> "abs",
>> "neg",
>> "not",
>> @@ -240,6 +241,11 @@ static const char *barOpStr[] =
>> "sync", "arrive", "red and", "red or", "red
Re: [Mesa-dev] [PATCH] intel/decoder: fix the possible out of bounds group_iter
On Thu, Aug 09, 2018 at 03:00:30PM +0300, andrey simiklit wrote:
> Hi,
>
> Sorry I missed the main thought here.
> The "gen_group_get_length" function returns int
> but the "iter_group_offset_bits" function returns uint32_t
> So uint32_t(int(-32)) = 0xFFE0U and it looks like unexpected behavior for
> me:
> iter_group_offset_bits(iter, iter->group_iter + 1) < 0xFFE0U;
That's fine, I think the original commit message is good enough to
understand this change. Feel free to add this extra bit too if you want,
but I don't think it's needed.
Reviewed-by: Rafael Antognolli
> Regards,
> Andrii.
>
> On Thu, Aug 9, 2018 at 2:35 PM, Andrii Simiklit
> wrote:
>
> The "gen_group_get_length" function can return a negative value
> and it can lead to the out of bounds group_iter.
>
> Signed-off-by: Andrii Simiklit
> ---
> src/intel/common/gen_decoder.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/src/intel/common/gen_decoder.c b/src/intel/common/gen_decoder
> .c
> index ec0a486..f09bd87 100644
> --- a/src/intel/common/gen_decoder.c
> +++ b/src/intel/common/gen_decoder.c
> @@ -803,8 +803,10 @@ static bool
> iter_more_groups(const struct gen_field_iterator *iter)
> {
> if (iter->group->variable) {
> - return iter_group_offset_bits(iter, iter->group_iter + 1) <
> - (gen_group_get_length(iter->group, iter->p) * 32);
> + const int length = gen_group_get_length(iter->group, iter->p);
> + return length > 0 &&
> + iter_group_offset_bits(iter, iter->group_iter + 1) <
> + (length * 32);
> } else {
>return (iter->group_iter + 1) < iter->group->group_count ||
> iter->group->next != NULL;
> --
> 2.7.4
>
>
>
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Re: [Mesa-dev] [PATCH 05/10] nir/lower_samplers: don't assume a deref for both texture and sampler srcs
On August 9, 2018 07:44:51 Alejandro Piñeiro wrote:
After commit "nir: Use derefs in nir_lower_samplers"
(75286c2d083cdbdfb202a93349e567df0441d5f7) assumes one deref for both
the texture and the sampler. However there are cases (on OpenGL, using
ARB_gl_spirv) where SPIR-V is not providing a sampler, like for
texture query levels ops. Although we could make spirv_to_nir to
provide a sampler deref for those cases, it is not really needed, and
wrong from the Vulkan point of view.
This patch fixes the following (borrowed) tests run on SPIR-V mode:
arb_compute_shader/execution/basic-texelFetch.shader_test
arb_gpu_shader5/execution/sampler_array_indexing/fs-simple-texture-size.shader_test
arb_texture_query_levels/execution/fs-baselevel.shader_test
arb_texture_query_levels/execution/fs-maxlevel.shader_test
arb_texture_query_levels/execution/fs-miptree.shader_test
arb_texture_query_levels/execution/fs-nomips.shader_test
arb_texture_query_levels/execution/vs-baselevel.shader_test
arb_texture_query_levels/execution/vs-maxlevel.shader_test
arb_texture_query_levels/execution/vs-miptree.shader_test
arb_texture_query_levels/execution/vs-nomips.shader_test
glsl-1.30/execution/fs-textureSize-compare.shader_test
---
src/compiler/glsl/gl_nir_lower_samplers.c | 83 ---
1 file changed, 55 insertions(+), 28 deletions(-)
diff --git a/src/compiler/glsl/gl_nir_lower_samplers.c
b/src/compiler/glsl/gl_nir_lower_samplers.c
index 43fe318a835..1b50b10d345 100644
--- a/src/compiler/glsl/gl_nir_lower_samplers.c
+++ b/src/compiler/glsl/gl_nir_lower_samplers.c
@@ -103,48 +103,75 @@ calc_sampler_offsets(nir_builder *b, nir_ssa_def *ptr,
shader_program->data->UniformStorage[location].opaque[stage].index;
}
+static void
+lower_tex_src_to_offset(nir_builder *b,
+nir_tex_instr *instr, unsigned src_idx,
+unsigned *index, unsigned *array_size,
+const struct gl_shader_program *shader_program)
+{
+ nir_ssa_def *indirect;
+ unsigned base_offset, array_elements;
+ nir_tex_src *src = &instr->src[src_idx];
+ bool is_sampler = src->src_type == nir_tex_src_sampler_deref;
+
+ calc_sampler_offsets(b, src->src.ssa, shader_program, &base_offset,
+&indirect, &array_elements);
We can likely roll lower_tex_src_to_offset and calc_sampler_offsets
together. May make things a bit better.
+ if (indirect) {
+ nir_instr_rewrite_src(&instr->instr, &src->src,
+nir_src_for_ssa(indirect));
+
+ src->src_type = is_sampler ?
+ nir_tex_src_sampler_offset :
+ nir_tex_src_texture_offset;
+
+ instr->texture_array_size = array_elements;
+ } else {
+ nir_tex_instr_remove_src(instr, src_idx);
+ }
+
+ if (index)
+ *index = base_offset;
+
+ if (array_size)
+ *array_size = array_elements;
+}
+
static bool
lower_sampler(nir_builder *b, nir_tex_instr *instr,
const struct gl_shader_program *shader_program)
{
int texture_idx =
nir_tex_instr_src_index(instr, nir_tex_src_texture_deref);
- int sampler_idx =
- nir_tex_instr_src_index(instr, nir_tex_src_sampler_deref);
- if (texture_idx < 0)
- return false;
+ if (texture_idx >= 0) {
+ unsigned texture_index;
+ unsigned texture_array_size;
- assert(texture_idx >= 0 && sampler_idx >= 0);
- assert(instr->src[texture_idx].src.is_ssa);
- assert(instr->src[sampler_idx].src.is_ssa);
- assert(instr->src[texture_idx].src.ssa == instr->src[sampler_idx].src.ssa);
+ b->cursor = nir_before_instr(&instr->instr);
- b->cursor = nir_before_instr(&instr->instr);
+ lower_tex_src_to_offset(b, instr, texture_idx,
+ &texture_index, &texture_array_size,
+ shader_program);
- unsigned base_offset, array_elements;
- nir_ssa_def *indirect;
- calc_sampler_offsets(b, instr->src[texture_idx].src.ssa, shader_program,
-&base_offset, &indirect, &array_elements);
+ instr->texture_index = texture_index;
+ instr->texture_array_size = texture_array_size;
Can we pass these into lower_tex_src_to_offset directly?
+ }
- instr->texture_index = base_offset;
- instr->sampler_index = base_offset;
- if (indirect) {
- nir_instr_rewrite_src(&instr->instr, &instr->src[texture_idx].src,
-nir_src_for_ssa(indirect));
- instr->src[texture_idx].src_type = nir_tex_src_texture_offset;
- nir_instr_rewrite_src(&instr->instr, &instr->src[sampler_idx].src,
-nir_src_for_ssa(indirect));
- instr->src[sampler_idx].src_type = nir_tex_src_sampler_offset;
+ int sampler_idx =
+ nir_tex_instr_src_index(instr, nir_tex_src_sampler_deref);
- instr->texture_array_size = array_elements;
- } else {
- nir_tex_instr_remove_src(instr, texture_idx);
- /* The sampler index may have changed */
-
Re: [Mesa-dev] [PATCH 1/2] blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
On August 10, 2018 03:19:18 Kenneth Graunke wrote:
The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
Jason decided to fake it with a bit of shader math and R32_UNORM RTs.
The only problem is that R32_UNORM isn't renderable either...so we've
just traded one bad format for another.
This patch makes us use R32_UINT instead.
---
src/intel/blorp/blorp_blit.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index c85ec8543a9..7b49f9afa35 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -984,14 +984,15 @@ convert_color(struct nir_builder *b, nir_ssa_def *color,
nir_ssa_def *value;
if (key->dst_format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
- /* The destination image is bound as R32_UNORM but the data needs to be
+ /* The destination image is bound as R32_UINT but the data needs to be
* in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
* top 8 need to be zero. We can accomplish this by simply multiplying
* by a factor to scale things down.
*/
- float factor = (float)((1 << 24) - 1) / (float)UINT32_MAX;
- value = nir_fmul(b, nir_fsat(b, nir_channel(b, color, 0)),
- nir_imm_float(b, factor));
+ unsigned factor = (1 << 24) - 1;
+ value = nir_fsat(b, nir_channel(b, color, 0));
+ value = nir_fmul(b, value, nir_imm_float(b, factor));
+ value = nir_iand(b, nir_f2i32(b, value), nir_imm_int(b, factor));
Do we really need the and?
} else if (key->dst_format == ISL_FORMAT_L8_UNORM_SRGB) {
value = nir_format_linear_to_srgb(b, nir_channel(b, color, 0));
} else if (key->dst_format == ISL_FORMAT_R8G8B8_UNORM_SRGB) {
@@ -1976,7 +1977,7 @@ try_blorp_blit(struct blorp_batch *batch,
isl_format_rgbx_to_rgba(params->dst.view.format);
} else if (params->dst.view.format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
wm_prog_key->dst_format = params->dst.view.format;
- params->dst.view.format = ISL_FORMAT_R32_UNORM;
+ params->dst.view.format = ISL_FORMAT_R32_UINT;
} else if (params->dst.view.format == ISL_FORMAT_A4B4G4R4_UNORM) {
params->dst.view.swizzle =
isl_swizzle_compose(params->dst.view.swizzle,
--
2.18.0
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[Mesa-dev] [Bug 107530] [Regression] widgets rendered black in gtk
https://bugs.freedesktop.org/show_bug.cgi?id=107530 --- Comment #3 from Marina Chernish --- Created attachment 141038 --> https://bugs.freedesktop.org/attachment.cgi?id=141038&action=edit OpenGL area -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107530] [Regression] widgets rendered black in gtk
https://bugs.freedesktop.org/show_bug.cgi?id=107530 --- Comment #2 from Marina Chernish --- Hi Lukas, I've tried to reproduce it on following configuration: OS: Linux ubuntu 4.15.0-29-generic #31-Ubuntu SMP Tue Jul 17 15:39:52 UTC 2018 x86_64 x86_64 x86_64 GNU/Linux Device: Mesa DRI Intel(R) Haswell Mobile (0x416) CPU: Intel Core i5-4300M Display: server: X.Org 1.19.6 resolution: 1600x900~60Hz Mesa 18.1.5 (git-711035e355) also have gtk3 3.22.30 installed and glarea looks good without any black fillouts (see attachment). What else device types (DRI) have you observed this issue on? Possibly some other installed applications/libraries could make some influence? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v3] Gallium/tgsi: Correct signdness of return value of bit operations
Reviewed-by: Roland Scheidegger Am 10.08.2018 um 15:04 schrieb Gert Wollny: > From: Gert Wollny > > The GLSL operations findLSB, findMSB, and countBits always return > a signed integer type. Let TGSI reflect this. > > v2: Properly set values in infer_(src|dst)_type (Thanks Roland > Schneidegger for pointing out problems with my 1st approach) > v2: Set values in the common infer_type code path, and only add > the correct source type for UMSB (Roland Schneidegger) > > Signed-off-by: Gert Wollny > --- > src/gallium/auxiliary/tgsi/tgsi_info.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c > b/src/gallium/auxiliary/tgsi/tgsi_info.c > index bbe1a21e43..d249b956ed 100644 > --- a/src/gallium/auxiliary/tgsi/tgsi_info.c > +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c > @@ -150,9 +150,6 @@ tgsi_opcode_infer_type(enum tgsi_opcode opcode) > case TGSI_OPCODE_UBFE: > case TGSI_OPCODE_BFI: > case TGSI_OPCODE_BREV: > - case TGSI_OPCODE_POPC: > - case TGSI_OPCODE_LSB: > - case TGSI_OPCODE_UMSB: > case TGSI_OPCODE_IMG2HND: > case TGSI_OPCODE_SAMP2HND: >return TGSI_TYPE_UNSIGNED; > @@ -188,6 +185,9 @@ tgsi_opcode_infer_type(enum tgsi_opcode opcode) > case TGSI_OPCODE_U64SGE: > case TGSI_OPCODE_I64SLT: > case TGSI_OPCODE_I64SGE: > + case TGSI_OPCODE_LSB: > + case TGSI_OPCODE_POPC: > + case TGSI_OPCODE_UMSB: >return TGSI_TYPE_SIGNED; > case TGSI_OPCODE_DADD: > case TGSI_OPCODE_DABS: > @@ -269,6 +269,7 @@ tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint > src_idx) > case TGSI_OPCODE_UP2H: > case TGSI_OPCODE_U2I64: > case TGSI_OPCODE_MEMBAR: > + case TGSI_OPCODE_UMSB: >return TGSI_TYPE_UNSIGNED; > case TGSI_OPCODE_IMUL_HI: > case TGSI_OPCODE_I2F: > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107530] [Regression] widgets rendered black in gtk
https://bugs.freedesktop.org/show_bug.cgi?id=107530 Lionel Landwerlin changed: What|Removed |Added Status|NEW |NEEDINFO --- Comment #1 from Lionel Landwerlin --- What window system is GTK+ using? (Wayland/X11) What's the compositor? Thanks! -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 02/14] mesa: bump GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES
Hi Marek, On Thursday, 9 August 2018 01:55:11 CEST Marek Olšák wrote: > From: Marek Olšák > > same number as our closed GL driver > --- > src/mesa/main/config.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/src/mesa/main/config.h b/src/mesa/main/config.h > index 6a2f766222a..fdf90d8956f 100644 > --- a/src/mesa/main/config.h > +++ b/src/mesa/main/config.h > @@ -131,22 +131,22 @@ > * used almost everywhere else. > */ > #define MAX_TEXTURE_UNITS ((MAX_TEXTURE_COORD_UNITS > > MAX_TEXTURE_IMAGE_UNITS) ? MAX_TEXTURE_COORD_UNITS : MAX_TEXTURE_IMAGE_UNITS) > > /** Maximum number of viewports supported with ARB_viewport_array */ > #define MAX_VIEWPORTS 16 > > /** Maximum number of window rectangles supported with EXT_window_rectangles > */ > #define MAX_WINDOW_RECTANGLES 8 > > -/** Maximum size for CVA. May be overridden by the drivers. */ > -#define MAX_ARRAY_LOCK_SIZE 3000 > +/** Default for GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES. */ > +#define MAX_ARRAY_LOCK_SIZE (512 * 1024 * 1024) While I really appreciate to return something sensible at max GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES, I think that extending gl_constants::MaxArrayLockSize breaks some drivers using tnl. The gl_constants::MaxArrayLockSize value is given to a lot of _tnl_init_vertices calls that allocates an array of size gl_constants::MaxArrayLockSize*. That one probably fails in a too large malloc with the new constant. May be you can introduce a new value in gl_constants that is used for GL_MAX_ELEMENTS_INDICES and GL_MAX_ELEMENTS_VERTICES. Alternatively, you may look for drivers using _tnl_init_vertices and leave those drivers values of gl_constants::MaxArrayLockSize at a reasonable size for tnl drivers. ... or some other solution not blowing up tnl drivers. best Mathias > > /** Subpixel precision for antialiasing, window coordinate snapping */ > #define SUB_PIXEL_BITS 4 > > /** For GL_ARB_texture_compression */ > #define MAX_COMPRESSED_TEXTURE_FORMATS 25 > > /** For GL_EXT_texture_filter_anisotropic */ > #define MAX_TEXTURE_MAX_ANISOTROPY 16.0 > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] compiler: add SYSTEM_VALUE_VARYING_COORD
Used internally in freedreno/ir3 for the vec2 value that hw passes to shader to use as coordinate for bary.f (varying fetch) instruction. This is not the same as SYSTEM_VALUE_FRAG_COORD. Signed-off-by: Rob Clark --- Up until now, we'd been hard-coding the location of this value (ie. to r0.xy), mostly because originally in the early a3xx days I didn't know which bits could configure this value (blob was always using r0.xy so in cmdstream traces it always showed up as 0's). But starting with a6xx, the address register aliases r0.x, which kinda throws a monkey-wrench in the existing scheme of hard-coding. The good news is that I know the bits to configure this value for a3xx-a6xx. So I'm shifting over to handling this like a sysval. src/compiler/shader_enums.c| 1 + src/compiler/shader_enums.h| 6 ++ src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 + 3 files changed, 8 insertions(+) diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c index a874083a0b7..0210b503d3f 100644 --- a/src/compiler/shader_enums.c +++ b/src/compiler/shader_enums.c @@ -244,6 +244,7 @@ gl_system_value_name(gl_system_value sysval) ENUM(SYSTEM_VALUE_DEVICE_INDEX), ENUM(SYSTEM_VALUE_VIEW_INDEX), ENUM(SYSTEM_VALUE_VERTEX_CNT), + ENUM(SYSTEM_VALUE_VARYING_COORD), }; STATIC_ASSERT(ARRAY_SIZE(names) == SYSTEM_VALUE_MAX); return NAME(sysval); diff --git a/src/compiler/shader_enums.h b/src/compiler/shader_enums.h index f8e22925f35..5c36f55283c 100644 --- a/src/compiler/shader_enums.h +++ b/src/compiler/shader_enums.h @@ -601,6 +601,12 @@ typedef enum */ SYSTEM_VALUE_VERTEX_CNT, + /** +* Driver internal varying-coord, used for varying-fetch instructions. +* Not externally visible. +*/ + SYSTEM_VALUE_VARYING_COORD, + SYSTEM_VALUE_MAX /**< Number of values */ } gl_system_value; diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index aec53309172..ec79a7f4918 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -5601,6 +5601,7 @@ _mesa_sysval_to_semantic(unsigned sysval) case SYSTEM_VALUE_LOCAL_INVOCATION_INDEX: case SYSTEM_VALUE_GLOBAL_INVOCATION_ID: case SYSTEM_VALUE_VERTEX_CNT: + case SYSTEM_VALUE_VARYING_COORD: default: assert(!"Unexpected SYSTEM_VALUE_ enum"); return TGSI_SEMANTIC_COUNT; -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH shader-db] run: simplify filename handling
Maybe set out_filename = NULL (might not be initialized on Linux by default, according to manpage). Either way : Reviewed-by: Lionel Landwerlin On 10/08/18 13:21, Eric Engestrom wrote: Compiler wasn't happy about strncpy() depending on the source's length and not the target's, but this whole thing can be simplified by simply using asprintf() (which is already used in this file, so no #include necessary). run.c: In function ‘main._omp_fn.0’: run.c:964:21: warning: ‘strncpy’ specified bound depends on the length of the source argument [-Wstringop-overflow=] strncpy(out_filename, current_shader_name, ^~ strlen(current_shader_name) + 1); Signed-off-by: Eric Engestrom --- run.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/run.c b/run.c index 200c0f4d6ffb1a2be467..43f1bf5bdd5f160e86fd 100644 --- a/run.c +++ b/run.c @@ -959,11 +959,8 @@ main(int argc, char **argv) continue; } -char *out_filename = malloc(strlen(current_shader_name) + 5); - -strncpy(out_filename, current_shader_name, -strlen(current_shader_name) + 1); -out_filename = strcat(out_filename, ".bin"); +char *out_filename; +asprintf(&out_filename, "%s.bin", current_shader_name); fp = fopen(out_filename, "wb"); fprintf(stdout, ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v3] Gallium/tgsi: Correct signdness of return value of bit operations
From: Gert Wollny The GLSL operations findLSB, findMSB, and countBits always return a signed integer type. Let TGSI reflect this. v2: Properly set values in infer_(src|dst)_type (Thanks Roland Schneidegger for pointing out problems with my 1st approach) v2: Set values in the common infer_type code path, and only add the correct source type for UMSB (Roland Schneidegger) Signed-off-by: Gert Wollny --- src/gallium/auxiliary/tgsi/tgsi_info.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c b/src/gallium/auxiliary/tgsi/tgsi_info.c index bbe1a21e43..d249b956ed 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_info.c +++ b/src/gallium/auxiliary/tgsi/tgsi_info.c @@ -150,9 +150,6 @@ tgsi_opcode_infer_type(enum tgsi_opcode opcode) case TGSI_OPCODE_UBFE: case TGSI_OPCODE_BFI: case TGSI_OPCODE_BREV: - case TGSI_OPCODE_POPC: - case TGSI_OPCODE_LSB: - case TGSI_OPCODE_UMSB: case TGSI_OPCODE_IMG2HND: case TGSI_OPCODE_SAMP2HND: return TGSI_TYPE_UNSIGNED; @@ -188,6 +185,9 @@ tgsi_opcode_infer_type(enum tgsi_opcode opcode) case TGSI_OPCODE_U64SGE: case TGSI_OPCODE_I64SLT: case TGSI_OPCODE_I64SGE: + case TGSI_OPCODE_LSB: + case TGSI_OPCODE_POPC: + case TGSI_OPCODE_UMSB: return TGSI_TYPE_SIGNED; case TGSI_OPCODE_DADD: case TGSI_OPCODE_DABS: @@ -269,6 +269,7 @@ tgsi_opcode_infer_src_type(enum tgsi_opcode opcode, uint src_idx) case TGSI_OPCODE_UP2H: case TGSI_OPCODE_U2I64: case TGSI_OPCODE_MEMBAR: + case TGSI_OPCODE_UMSB: return TGSI_TYPE_UNSIGNED; case TGSI_OPCODE_IMUL_HI: case TGSI_OPCODE_I2F: -- 2.16.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] freedreno: a2xx: ir2 update
()
On Tue, Jul 24, 2018 at 9:00 AM Jonathan Marek wrote:
>
> this patch brings a number of changes to ir2:
> -ir2 now generates CF clauses as necessary during assembly. this simplifies
> fd2_program/fd2_compiler and is necessary to implement optimization passes
> -ir2 now has separate vector/scalar instructions. this will make it easier
> to implementing scheduling of scalar+vector instructions together. dst_reg
> is also now seperate from src registers instead of a single list
> -ir2 now implements register allocation. this makes it possible to compile
> shaders which have more than 64 TGSI registers
> -ir2 now implements the following optimizations: removal of IN/OUT MOV
> instructions generated by TGSI and removal of unused instructions when
> some exports are disabled
> -ir2 now allows full 8-bit index for constants
> -ir2_alloc no longer allocates 4 times too many bytes
>
So, this might be easier to review if it was split up a bit better
into multiple patches.
That said, I think I'll merge it as is, mostly because you folks are
the main ones using and working on a2xx currently, and it isn't
something that would break a3xx+.
However, a few recommendations for the future:
1) you probably want to start running piglit and/or deqp_gles2.
(Piglit has better desktop gl coverage, deqp has better gles coverage.
Not sure whether you care more about gl or gles.) Due to feature
level of a2xx (and because, iirc, I didn't start running piglit much
until a3xx), I guess there will be a lot of skips and fails, but main
thing you want to watch for is tests that transition pass->fail..
piglit-summary.py can compare before/after piglit runs. (Not really
sure how to do that best with deqp, but you can use piglit to run deqp
tests.)
2) shader-db is good for measuring the effect of compiler changes
across a bunch of shaders. Probably worth wiring up shaderdb traces
for a2xx, see dump_shader_info() in ir3_shader.c for example. I
suppose you could use the same format for the traces and re-use
fd-report.py in the shader-db tree to parse before/after results.
(That script could probably use some improvements, like splitting
VS/FS results.. I guess I'll do that next time I work up the courage
to hack on python.)
3) seems like eventually you'll want to stop re-inventing
register_allocate.[ch].. perhaps it is overkill for a2xx, I guess
there wasn't anything complicated like multiple register banks or
conflicting register classes. So maybe this is fine for now.
BR,
-R
> Signed-off-by: Jonathan Marek
> ---
> .../drivers/freedreno/a2xx/fd2_compiler.c | 210 ++---
> .../drivers/freedreno/a2xx/fd2_program.c | 75 +-
> .../drivers/freedreno/a2xx/instr-a2xx.h | 28 +-
> src/gallium/drivers/freedreno/a2xx/ir-a2xx.c | 734 +++---
> src/gallium/drivers/freedreno/a2xx/ir-a2xx.h | 113 +--
> 5 files changed, 615 insertions(+), 545 deletions(-)
>
> diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> index 3ad47f9850..12f9a1ce0a 100644
> --- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> +++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
> @@ -93,9 +93,6 @@ struct fd2_compile_context {
> unsigned position, psize;
>
> uint64_t need_sync;
> -
> - /* current exec CF instruction */
> - struct ir2_cf *cf;
> };
>
> static int
> @@ -130,7 +127,6 @@ compile_init(struct fd2_compile_context *ctx, struct
> fd_program_stateobj *prog,
>
> ctx->prog = prog;
> ctx->so = so;
> - ctx->cf = NULL;
> ctx->pred_depth = 0;
>
> ret = tgsi_parse_init(&ctx->parser, so->tokens);
> @@ -236,15 +232,6 @@ compile_free(struct fd2_compile_context *ctx)
> tgsi_parse_free(&ctx->parser);
> }
>
> -static struct ir2_cf *
> -next_exec_cf(struct fd2_compile_context *ctx)
> -{
> - struct ir2_cf *cf = ctx->cf;
> - if (!cf || cf->exec.instrs_count >= ARRAY_SIZE(ctx->cf->exec.instrs))
> - ctx->cf = cf = ir2_cf_create(ctx->so->ir, EXEC);
> - return cf;
> -}
> -
> static void
> compile_vtx_fetch(struct fd2_compile_context *ctx)
> {
> @@ -252,13 +239,13 @@ compile_vtx_fetch(struct fd2_compile_context *ctx)
> int i;
> for (i = 0; i < ctx->num_regs[TGSI_FILE_INPUT]; i++) {
> struct ir2_instruction *instr = ir2_instr_create(
> - next_exec_cf(ctx), IR2_FETCH);
> + ctx->so->ir, IR2_FETCH);
> instr->fetch.opc = VTX_FETCH;
>
> ctx->need_sync |= 1 << (i+1);
>
> - ir2_reg_create(instr, i+1, "xyzw", 0);
> - ir2_reg_create(instr, 0, "x", 0);
> + ir2_dst_create(instr, i+1, "xyzw", 0);
> + ir2_reg_create(instr, 0, "x", IR2_REG_INPUT);
>
> if (i == 0)
> instr->sync = true;
> @@ -266,7 +253,6 @@ compile_vtx_fetch(struct fd2_compile_context *ctx)
Re: [Mesa-dev] [1/2] loader: add loader_open_name(..)
Hi Christian,
On 01/08/18 23:07, Christian Gmeiner wrote:
Add an improved drmOpenWithType(..) clone which fixes some serious
flaws. Some highlights:
- using busid works only with PCI devices
- open() w/o O_CLOEXEC
- when build w/o udev - it creates a node: mkdir, chown(root), chmod, mknod
- calls back into Xserver/DDX module
- last but no least - borderline hacks with massive documentation [1]
to keep this running.
Signed-off-by: Christian Gmeiner
Why do this in mesa rather than fixing (or adding a new version if
necessary for backwards compatibility) to the libdrm code?
mesa is not the only place that we need to find the node path based on a
driver name to avoid hard coding or putting brittle paths in config files.
There is at least drm_hwcomposer as well for Android and probably others.
(drm_hwc currently uses a hard coded path overridable by a system property):
property_get("hwc.drm.device", path, "/dev/dri/card0");
Regards,
Martin
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[Mesa-dev] [PATCH shader-db] run: simplify filename handling
Compiler wasn't happy about strncpy() depending on the source's length and not the target's, but this whole thing can be simplified by simply using asprintf() (which is already used in this file, so no #include necessary). run.c: In function ‘main._omp_fn.0’: run.c:964:21: warning: ‘strncpy’ specified bound depends on the length of the source argument [-Wstringop-overflow=] strncpy(out_filename, current_shader_name, ^~ strlen(current_shader_name) + 1); Signed-off-by: Eric Engestrom --- run.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/run.c b/run.c index 200c0f4d6ffb1a2be467..43f1bf5bdd5f160e86fd 100644 --- a/run.c +++ b/run.c @@ -959,11 +959,8 @@ main(int argc, char **argv) continue; } -char *out_filename = malloc(strlen(current_shader_name) + 5); - -strncpy(out_filename, current_shader_name, -strlen(current_shader_name) + 1); -out_filename = strcat(out_filename, ".bin"); +char *out_filename; +asprintf(&out_filename, "%s.bin", current_shader_name); fp = fopen(out_filename, "wb"); fprintf(stdout, -- Cheers, Eric ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] i915/swrast vertex array regression
Hi Ville,
> Looks like
> "vid_gl20" "0"
> is needed to reproduce the issue.
Thanks! Now I can observe the problem!
And the attached patch seems to fix what I can observe here.
Does the attached patch also fix the problem with the
older intel chip you originally reported?
Thanks!
MathiasFrom 68e921478c8c38a13b7258e0d3f1f235709dcfe9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Mathias=20Fr=C3=B6hlich?=
Date: Fri, 10 Aug 2018 11:37:43 +0200
Subject: [PATCH] tnl: Fix green gun regression in xonotic.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Signed-off-by: Mathias Fröhlich
---
src/mesa/tnl/t_split_copy.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/tnl/t_split_copy.c b/src/mesa/tnl/t_split_copy.c
index cbb7eb409f..085ae9a28c 100644
--- a/src/mesa/tnl/t_split_copy.c
+++ b/src/mesa/tnl/t_split_copy.c
@@ -531,7 +531,7 @@ replay_init(struct copy_context *copy)
for (offset = 0, i = 0; i < copy->nr_varying; i++) {
const struct tnl_vertex_array *src = copy->varying[i].array;
const struct gl_array_attributes *srcattr = src->VertexAttrib;
- struct tnl_vertex_array *dst = ©->dstarray[i];
+ struct tnl_vertex_array *dst = ©->dstarray[copy->varying[i].attr];
struct gl_vertex_buffer_binding *dstbind = ©->varying[i].dstbinding;
struct gl_array_attributes *dstattr = ©->varying[i].dstattribs;
--
2.17.1
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[Mesa-dev] [Bug 106833] glLinkProgram is expected to fail when vertex attribute aliasing happens on ES3.0 context or later
https://bugs.freedesktop.org/show_bug.cgi?id=106833 --- Comment #7 from Yang Gu --- Yang is OOO from Aug 10 to 19. Please expect slow response. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 106833] glLinkProgram is expected to fail when vertex attribute aliasing happens on ES3.0 context or later
https://bugs.freedesktop.org/show_bug.cgi?id=106833 Tapani Pälli changed: What|Removed |Added Attachment #140052|0 |1 is obsolete|| --- Comment #6 from Tapani Pälli --- Created attachment 141034 --> https://bugs.freedesktop.org/attachment.cgi?id=141034&action=edit possible fix v2 Here's a fixed version .. it's not nice though but we should do something along these lines, perhaps have a separate lighter weight pass. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/2] blorp: Properly handle Z24X8 blits.
One of the reasons we didn't notice that R24_UNORM_X8_TYPELESS
destinations were broken was that an earlier layer was swapping it
out for B8G8R8A8_UNORM. That made Z24X8 -> Z24X8 blits work.
However, R32_FLOAT -> R24_UNORM_X8_TYPELESS was still totally broken.
The old code only considered one format at a time, without thinking
that format conversion may need to occur.
This patch moves the translation out to a place where it can consider
both formats. If both are Z24X8, we continue using B8G8R8A8_UNORM to
avoid having to do shader math workarounds. If we have a Z24X8
destination, but a non-matching source, we use our shader hacks to
actually render to it properly.
---
src/intel/blorp/blorp.c | 12
src/intel/blorp/blorp_blit.c | 11 +++
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index c36ec703b18..ffe26076e16 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -75,18 +75,6 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
if (format == ISL_FORMAT_UNSUPPORTED)
format = surf->surf->format;
- if (format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
- /* Unfortunately, ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as
- * a render target, which would prevent us from blitting to 24-bit
- * depth. The miptree consists of 32 bits per pixel, arranged as 24-bit
- * depth values interleaved with 8 "don't care" bits. Since depth
- * values don't require any blending, it doesn't matter how we interpret
- * the bit pattern as long as we copy the right amount of data, so just
- * map it as 8-bit BGRA.
- */
- format = ISL_FORMAT_B8G8R8A8_UNORM;
- }
-
info->surf = *surf->surf;
info->addr = surf->addr;
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 7b49f9afa35..3b84e634bd9 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -2241,6 +2241,17 @@ blorp_blit(struct blorp_batch *batch,
}
}
+ /* ISL_FORMAT_R24_UNORM_X8_TYPELESS it isn't supported as a render target,
+* which requires shader math to render to it. Blitting Z24X8 to Z24X8
+* is fairly common though, so we'd like to avoid it. Since we don't need
+* to blend depth values, we can simply pick a renderable format with the
+* right number of bits-per-pixel, like 8-bit BGRA.
+*/
+ if (dst_surf->surf->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS &&
+ src_surf->surf->format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
+ src_format = dst_format = ISL_FORMAT_B8G8R8A8_UNORM;
+ }
+
brw_blorp_surface_info_init(batch->blorp, ¶ms.src, src_surf, src_level,
src_layer, src_format, false);
brw_blorp_surface_info_init(batch->blorp, ¶ms.dst, dst_surf, dst_level,
--
2.18.0
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[Mesa-dev] [PATCH 1/2] blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
The hardware doesn't support rendering to R24_UNORM_X8_TYPELESS, so
Jason decided to fake it with a bit of shader math and R32_UNORM RTs.
The only problem is that R32_UNORM isn't renderable either...so we've
just traded one bad format for another.
This patch makes us use R32_UINT instead.
---
src/intel/blorp/blorp_blit.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index c85ec8543a9..7b49f9afa35 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -984,14 +984,15 @@ convert_color(struct nir_builder *b, nir_ssa_def *color,
nir_ssa_def *value;
if (key->dst_format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
- /* The destination image is bound as R32_UNORM but the data needs to be
+ /* The destination image is bound as R32_UINT but the data needs to be
* in R24_UNORM_X8_TYPELESS. The bottom 24 are the actual data and the
* top 8 need to be zero. We can accomplish this by simply multiplying
* by a factor to scale things down.
*/
- float factor = (float)((1 << 24) - 1) / (float)UINT32_MAX;
- value = nir_fmul(b, nir_fsat(b, nir_channel(b, color, 0)),
- nir_imm_float(b, factor));
+ unsigned factor = (1 << 24) - 1;
+ value = nir_fsat(b, nir_channel(b, color, 0));
+ value = nir_fmul(b, value, nir_imm_float(b, factor));
+ value = nir_iand(b, nir_f2i32(b, value), nir_imm_int(b, factor));
} else if (key->dst_format == ISL_FORMAT_L8_UNORM_SRGB) {
value = nir_format_linear_to_srgb(b, nir_channel(b, color, 0));
} else if (key->dst_format == ISL_FORMAT_R8G8B8_UNORM_SRGB) {
@@ -1976,7 +1977,7 @@ try_blorp_blit(struct blorp_batch *batch,
isl_format_rgbx_to_rgba(params->dst.view.format);
} else if (params->dst.view.format == ISL_FORMAT_R24_UNORM_X8_TYPELESS) {
wm_prog_key->dst_format = params->dst.view.format;
- params->dst.view.format = ISL_FORMAT_R32_UNORM;
+ params->dst.view.format = ISL_FORMAT_R32_UINT;
} else if (params->dst.view.format == ISL_FORMAT_A4B4G4R4_UNORM) {
params->dst.view.swizzle =
isl_swizzle_compose(params->dst.view.swizzle,
--
2.18.0
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Re: [Mesa-dev] [PATCH 05/10] nir/lower_samplers: don't assume a deref for both texture and sampler srcs
Hi Jason, I'm CCing you for this one as you basically provided the
pseudocode I used as reference. So I assume that you already know what's
going on, hoping that would make the review easier.
On 09/08/18 15:43, Alejandro Piñeiro wrote:
> After commit "nir: Use derefs in nir_lower_samplers"
> (75286c2d083cdbdfb202a93349e567df0441d5f7) assumes one deref for both
> the texture and the sampler. However there are cases (on OpenGL, using
> ARB_gl_spirv) where SPIR-V is not providing a sampler, like for
> texture query levels ops. Although we could make spirv_to_nir to
> provide a sampler deref for those cases, it is not really needed, and
> wrong from the Vulkan point of view.
>
> This patch fixes the following (borrowed) tests run on SPIR-V mode:
> arb_compute_shader/execution/basic-texelFetch.shader_test
>
> arb_gpu_shader5/execution/sampler_array_indexing/fs-simple-texture-size.shader_test
> arb_texture_query_levels/execution/fs-baselevel.shader_test
> arb_texture_query_levels/execution/fs-maxlevel.shader_test
> arb_texture_query_levels/execution/fs-miptree.shader_test
> arb_texture_query_levels/execution/fs-nomips.shader_test
> arb_texture_query_levels/execution/vs-baselevel.shader_test
> arb_texture_query_levels/execution/vs-maxlevel.shader_test
> arb_texture_query_levels/execution/vs-miptree.shader_test
> arb_texture_query_levels/execution/vs-nomips.shader_test
> glsl-1.30/execution/fs-textureSize-compare.shader_test
> ---
> src/compiler/glsl/gl_nir_lower_samplers.c | 83
> ---
> 1 file changed, 55 insertions(+), 28 deletions(-)
>
> diff --git a/src/compiler/glsl/gl_nir_lower_samplers.c
> b/src/compiler/glsl/gl_nir_lower_samplers.c
> index 43fe318a835..1b50b10d345 100644
> --- a/src/compiler/glsl/gl_nir_lower_samplers.c
> +++ b/src/compiler/glsl/gl_nir_lower_samplers.c
> @@ -103,48 +103,75 @@ calc_sampler_offsets(nir_builder *b, nir_ssa_def *ptr,
>shader_program->data->UniformStorage[location].opaque[stage].index;
> }
>
> +static void
> +lower_tex_src_to_offset(nir_builder *b,
> +nir_tex_instr *instr, unsigned src_idx,
> +unsigned *index, unsigned *array_size,
> +const struct gl_shader_program *shader_program)
> +{
> + nir_ssa_def *indirect;
> + unsigned base_offset, array_elements;
> + nir_tex_src *src = &instr->src[src_idx];
> + bool is_sampler = src->src_type == nir_tex_src_sampler_deref;
> +
> + calc_sampler_offsets(b, src->src.ssa, shader_program, &base_offset,
> +&indirect, &array_elements);
> + if (indirect) {
> + nir_instr_rewrite_src(&instr->instr, &src->src,
> +nir_src_for_ssa(indirect));
> +
> + src->src_type = is_sampler ?
> + nir_tex_src_sampler_offset :
> + nir_tex_src_texture_offset;
> +
> + instr->texture_array_size = array_elements;
> + } else {
> + nir_tex_instr_remove_src(instr, src_idx);
> + }
> +
> + if (index)
> + *index = base_offset;
> +
> + if (array_size)
> + *array_size = array_elements;
> +}
> +
> static bool
> lower_sampler(nir_builder *b, nir_tex_instr *instr,
>const struct gl_shader_program *shader_program)
> {
> int texture_idx =
>nir_tex_instr_src_index(instr, nir_tex_src_texture_deref);
> - int sampler_idx =
> - nir_tex_instr_src_index(instr, nir_tex_src_sampler_deref);
>
> - if (texture_idx < 0)
> - return false;
> + if (texture_idx >= 0) {
> + unsigned texture_index;
> + unsigned texture_array_size;
>
> - assert(texture_idx >= 0 && sampler_idx >= 0);
> - assert(instr->src[texture_idx].src.is_ssa);
> - assert(instr->src[sampler_idx].src.is_ssa);
> - assert(instr->src[texture_idx].src.ssa ==
> instr->src[sampler_idx].src.ssa);
> + b->cursor = nir_before_instr(&instr->instr);
>
> - b->cursor = nir_before_instr(&instr->instr);
> + lower_tex_src_to_offset(b, instr, texture_idx,
> + &texture_index, &texture_array_size,
> + shader_program);
>
> - unsigned base_offset, array_elements;
> - nir_ssa_def *indirect;
> - calc_sampler_offsets(b, instr->src[texture_idx].src.ssa, shader_program,
> -&base_offset, &indirect, &array_elements);
> + instr->texture_index = texture_index;
> + instr->texture_array_size = texture_array_size;
> + }
>
> - instr->texture_index = base_offset;
> - instr->sampler_index = base_offset;
> - if (indirect) {
> - nir_instr_rewrite_src(&instr->instr, &instr->src[texture_idx].src,
> -nir_src_for_ssa(indirect));
> - instr->src[texture_idx].src_type = nir_tex_src_texture_offset;
> - nir_instr_rewrite_src(&instr->instr, &instr->src[sampler_idx].src,
> -nir_src_for_ssa(indirect));
> - instr->src[sampler_idx].src_type = nir_tex_src_sampler_offset;
Re: [Mesa-dev] [PATCH v3 08/48] meson: fix dl detection on non cygwin windows
On Thursday, 2018-08-09 10:32:35 -0700, Dylan Baker wrote:
> Quoting Eric Engestrom (2018-08-09 08:36:55)
> > On Monday, 2018-08-06 17:50:48 -0700, Dylan Baker wrote:
> > > ---
> > > meson.build | 4 ++--
> > > 1 file changed, 2 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/meson.build b/meson.build
> > > index c7dd5ddfec6..788021c05e9 100644
> > > --- a/meson.build
> > > +++ b/meson.build
> > > @@ -1027,9 +1027,9 @@ endif
> > > if cc.has_function('dlopen')
> >
> > This check is not needed on windows, is it? It will always fail afaict.
> >
> > How about this?
> > if host == windows or cc.has_function(dlopen)
> >
> > >dep_dl = null_dep
> > > else
> > > - dep_dl = cc.find_library('dl')
> > > + dep_dl = cc.find_library('dl', required : host_machine.system() !=
> > > 'windows')
> > > endif
> > > -if cc.has_function('dladdr', dependencies : dep_dl)
> > > +if host_machine.system() != 'windows' and cc.has_function('dladdr',
> > > dependencies : dep_dl)
> > ># This is really only required for megadrivers
> > >pre_args += '-DHAVE_DLADDR'
> > > endif
>
> How about:
> # check for dl support
> dep_dl = null_dep
> if host_machine.system() != 'windows'
> if not cc.has_function('dlopen')
> dep_dl = cc.find_library('dl')
> endif
> if cc.has_function('dladdr', dependencies : dep_dl)
> # This is really only required for megadrivers
> pre_args += '-DHAVE_DLADDR'
> endif
> endif
Even better :)
Consider it r-b
>
> >
> > With that, 1-4 and 7-8 are:
> > Reviewed-by: Eric Engestrom
> >
> > > --
> > > 2.18.0
> > >
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [Bug 107524] Broken packDouble2x32 at llvmpipe
https://bugs.freedesktop.org/show_bug.cgi?id=107524 --- Comment #3 from Matwey V. Kornilov --- Created attachment 141033 --> https://bugs.freedesktop.org/attachment.cgi?id=141033&action=edit shader_run test Attached is what are you looking for. It passes at Intel and fails at llvmpipe. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
