Re: [Mesa-dev] [RFC PATCH] nir: call nir_validate_shader in debug but not debugoptimized builds
Please, no. You could make a case for changing the default in
debugoptimized builds (which I would still be against) but we should
definitely still compile it. Why is it so hard to set NIR_VALIDATE=0 when
you really care about compiler times?
--Jason
On May 10, 2019 20:15:56 Marek Olšák wrote:
From: Marek Olšák
This reverts commit 7b85b9b8773b119360a31b66b321ae560a77cb6d.
---
src/compiler/nir/nir.h | 8
src/compiler/nir/nir_metadata.c | 2 +-
src/compiler/nir/nir_validate.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 8441c9f26c5..6ee733efa75 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -35,23 +35,23 @@
#include "util/ralloc.h"
#include "util/set.h"
#include "util/bitscan.h"
#include "util/bitset.h"
#include "util/macros.h"
#include "compiler/nir_types.h"
#include "compiler/shader_enums.h"
#include "compiler/shader_info.h"
#include
-#ifndef NDEBUG
+#ifdef DEBUG
#include "util/debug.h"
-#endif /* NDEBUG */
+#endif /* DEBUG */
#include "nir_opcodes.h"
#if defined(_WIN32) && !defined(snprintf)
#define snprintf _snprintf
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -2875,21 +2875,21 @@ void nir_print_instr(const nir_instr *instr, FILE *fp);
void nir_print_deref(const nir_deref_instr *deref, FILE *fp);
nir_shader *nir_shader_clone(void *mem_ctx, const nir_shader *s);
nir_function_impl *nir_function_impl_clone(nir_shader *shader,
const nir_function_impl *fi);
nir_constant *nir_constant_clone(const nir_constant *c, nir_variable *var);
nir_variable *nir_variable_clone(const nir_variable *c, nir_shader *shader);
nir_shader *nir_shader_serialize_deserialize(void *mem_ctx, nir_shader *s);
-#ifndef NDEBUG
+#ifdef DEBUG
void nir_validate_shader(nir_shader *shader, const char *when);
void nir_metadata_set_validation_flag(nir_shader *shader);
void nir_metadata_check_validation_flag(nir_shader *shader);
static inline bool
should_skip_nir(const char *name)
{
static const char *list = NULL;
if (!list) {
/* Comma separated list of names to skip. */
@@ -2934,21 +2934,21 @@ should_print_nir(void)
return should_print;
}
#else
static inline void nir_validate_shader(nir_shader *shader, const char
*when) { (void) shader; (void)when; }
static inline void nir_metadata_set_validation_flag(nir_shader *shader) {
(void) shader; }
static inline void nir_metadata_check_validation_flag(nir_shader *shader) {
(void) shader; }
static inline bool should_skip_nir(UNUSED const char *pass_name) { return
false; }
static inline bool should_clone_nir(void) { return false; }
static inline bool should_serialize_deserialize_nir(void) { return false; }
static inline bool should_print_nir(void) { return false; }
-#endif /* NDEBUG */
+#endif /* DEBUG */
#define _PASS(pass, nir, do_pass) do { \
if (should_skip_nir(#pass)) { \
printf("skipping %s\n", #pass);\
break; \
} \
do_pass \
nir_validate_shader(nir, "after " #pass); \
if (should_clone_nir()) { \
nir_shader *clone = nir_shader_clone(ralloc_parent(nir), nir); \
diff --git a/src/compiler/nir/nir_metadata.c b/src/compiler/nir/nir_metadata.c
index e681ba34f75..f71cf432b70 100644
--- a/src/compiler/nir/nir_metadata.c
+++ b/src/compiler/nir/nir_metadata.c
@@ -52,21 +52,21 @@ nir_metadata_require(nir_function_impl *impl,
nir_metadata required, ...)
impl->valid_metadata |= required;
}
void
nir_metadata_preserve(nir_function_impl *impl, nir_metadata preserved)
{
impl->valid_metadata &= preserved;
}
-#ifndef NDEBUG
+#ifdef DEBUG
/**
* Make sure passes properly invalidate metadata (part 1).
*
* Call this before running a pass to set a bogus metadata flag, which will
* only be preserved if the pass forgets to call nir_metadata_preserve().
*/
void
nir_metadata_set_validation_flag(nir_shader *shader)
{
nir_foreach_function(function, shader) {
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 7746c391abc..a57b78e97c0 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -29,21 +29,21 @@
#include "c11/threads.h"
#include
/*
* This file checks for invalid IR indicating a bug somewhere in the compiler.
*/
/* Since this file is just a pile of asserts, don't bother compiling it if
* we're not building a debug build.
*/
-#ifndef NDEBUG
+#ifdef DEBUG
/*
* Per-register validation state.
*/
typedef struct {
/*
* equivalent to the uses and defs in nir_register, but built up by the
* validator. At the end, we verify that the sets have the same
[Mesa-dev] [RFC PATCH] nir: call nir_validate_shader in debug but not debugoptimized builds
From: Marek Olšák
This reverts commit 7b85b9b8773b119360a31b66b321ae560a77cb6d.
---
src/compiler/nir/nir.h | 8
src/compiler/nir/nir_metadata.c | 2 +-
src/compiler/nir/nir_validate.c | 2 +-
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 8441c9f26c5..6ee733efa75 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -35,23 +35,23 @@
#include "util/ralloc.h"
#include "util/set.h"
#include "util/bitscan.h"
#include "util/bitset.h"
#include "util/macros.h"
#include "compiler/nir_types.h"
#include "compiler/shader_enums.h"
#include "compiler/shader_info.h"
#include
-#ifndef NDEBUG
+#ifdef DEBUG
#include "util/debug.h"
-#endif /* NDEBUG */
+#endif /* DEBUG */
#include "nir_opcodes.h"
#if defined(_WIN32) && !defined(snprintf)
#define snprintf _snprintf
#endif
#ifdef __cplusplus
extern "C" {
#endif
@@ -2875,21 +2875,21 @@ void nir_print_instr(const nir_instr *instr, FILE *fp);
void nir_print_deref(const nir_deref_instr *deref, FILE *fp);
nir_shader *nir_shader_clone(void *mem_ctx, const nir_shader *s);
nir_function_impl *nir_function_impl_clone(nir_shader *shader,
const nir_function_impl *fi);
nir_constant *nir_constant_clone(const nir_constant *c, nir_variable *var);
nir_variable *nir_variable_clone(const nir_variable *c, nir_shader *shader);
nir_shader *nir_shader_serialize_deserialize(void *mem_ctx, nir_shader *s);
-#ifndef NDEBUG
+#ifdef DEBUG
void nir_validate_shader(nir_shader *shader, const char *when);
void nir_metadata_set_validation_flag(nir_shader *shader);
void nir_metadata_check_validation_flag(nir_shader *shader);
static inline bool
should_skip_nir(const char *name)
{
static const char *list = NULL;
if (!list) {
/* Comma separated list of names to skip. */
@@ -2934,21 +2934,21 @@ should_print_nir(void)
return should_print;
}
#else
static inline void nir_validate_shader(nir_shader *shader, const char *when) {
(void) shader; (void)when; }
static inline void nir_metadata_set_validation_flag(nir_shader *shader) {
(void) shader; }
static inline void nir_metadata_check_validation_flag(nir_shader *shader) {
(void) shader; }
static inline bool should_skip_nir(UNUSED const char *pass_name) { return
false; }
static inline bool should_clone_nir(void) { return false; }
static inline bool should_serialize_deserialize_nir(void) { return false; }
static inline bool should_print_nir(void) { return false; }
-#endif /* NDEBUG */
+#endif /* DEBUG */
#define _PASS(pass, nir, do_pass) do { \
if (should_skip_nir(#pass)) { \
printf("skipping %s\n", #pass);\
break; \
} \
do_pass \
nir_validate_shader(nir, "after " #pass); \
if (should_clone_nir()) { \
nir_shader *clone = nir_shader_clone(ralloc_parent(nir), nir); \
diff --git a/src/compiler/nir/nir_metadata.c b/src/compiler/nir/nir_metadata.c
index e681ba34f75..f71cf432b70 100644
--- a/src/compiler/nir/nir_metadata.c
+++ b/src/compiler/nir/nir_metadata.c
@@ -52,21 +52,21 @@ nir_metadata_require(nir_function_impl *impl, nir_metadata
required, ...)
impl->valid_metadata |= required;
}
void
nir_metadata_preserve(nir_function_impl *impl, nir_metadata preserved)
{
impl->valid_metadata &= preserved;
}
-#ifndef NDEBUG
+#ifdef DEBUG
/**
* Make sure passes properly invalidate metadata (part 1).
*
* Call this before running a pass to set a bogus metadata flag, which will
* only be preserved if the pass forgets to call nir_metadata_preserve().
*/
void
nir_metadata_set_validation_flag(nir_shader *shader)
{
nir_foreach_function(function, shader) {
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 7746c391abc..a57b78e97c0 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -29,21 +29,21 @@
#include "c11/threads.h"
#include
/*
* This file checks for invalid IR indicating a bug somewhere in the compiler.
*/
/* Since this file is just a pile of asserts, don't bother compiling it if
* we're not building a debug build.
*/
-#ifndef NDEBUG
+#ifdef DEBUG
/*
* Per-register validation state.
*/
typedef struct {
/*
* equivalent to the uses and defs in nir_register, but built up by the
* validator. At the end, we verify that the sets have the same entries.
*/
--
2.17.1
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Re: [Mesa-dev] nir_opt_copy_prop_vars doing the wrong thing
We have unit tests for that pass. Maybe you could write one which
exercises the issue? It'd help in debugging.
On Thu, May 9, 2019 at 8:12 PM Dave Airlie wrote:
> I've got a bunch of cases where copy prop vars is getting things wrong
> around casts, it finds a store to an vec2 but ends up with the
> writemask staying at 0x3 but the item being store being a single
> 64-bit.
>
> Debug is attached below.
>
> Dave.
>
> nir_lower_memcpy_deref
> shader: MESA_SHADER_KERNEL
> local-size: 0, 0, 0 (variable)
> shared-size: 1
> inputs: 16
> outputs: 0
> uniforms: 0
> shared: 0
> decl_var shader_in INTERP_MODE_NONE uint64_t @0 (0.x, 0, 0)
> decl_var shader_in INTERP_MODE_NONE uint64_t @1 (1.x, 8, 0)
> decl_function __wrapped_vload2_private (0 params)
>
> impl __wrapped_vload2_private {
> decl_var INTERP_MODE_NONE uint[3] @2
> block block_0:
> /* preds: */
> vec1 64 ssa_0 = deref_var &@0 (shader_in uint64_t)
> vec1 64 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */
> vec1 64 ssa_2 = deref_var &@1 (shader_in uint64_t)
> vec1 64 ssa_3 = intrinsic load_deref (ssa_2) (0) /* access=0 */
> vec1 64 ssa_4 = load_const (0x 0 /* 0.00 */)
> vec1 64 ssa_5 = load_const (0x 0 /* 0.00 */)
> vec1 64 ssa_6 = deref_cast (uint *)ssa_1 (global uint)
> vec1 64 ssa_7 = deref_cast (uvec2 *)ssa_3 (global uvec2)
> vec1 32 ssa_8 = intrinsic load_deref (ssa_6) (0) /* access=0 */
> vec1 64 ssa_9 = deref_var &@2 (function_temp uint[3])
> vec1 64 ssa_10 = deref_cast (uint[3] *)ssa_9 (function_temp uint[3])
> vec1 64 ssa_11 = load_const (0x 0 /* 0.00 */)
> vec1 64 ssa_13 = load_const (0x 0 /* 0.00 */)
> vec1 64 ssa_14 = deref_array &(*ssa_9)[0] (function_temp uint) /*
> &@2[0] */
> intrinsic store_deref (ssa_14, ssa_8) (1, 0) /* wrmask=x */ /*
> access=0 */
> vec1 64 ssa_15 = deref_cast (uint *)ssa_1 (global uint)
> vec1 64 ssa_16 = load_const (0x 1 /* 0.00 */)
> vec1 64 ssa_17 = deref_ptr_as_array &(*ssa_15)[1] (global uint) /*
> &(*(uint *)ssa_1)[1] */
> vec1 32 ssa_18 = intrinsic load_deref (ssa_17) (0) /* access=0 */
> vec1 64 ssa_19 = deref_var &@2 (function_temp uint[3])
> vec1 64 ssa_20 = deref_cast (uint[3] *)ssa_19 (function_temp uint[3])
> vec1 64 ssa_21 = load_const (0x 0 /* 0.00 */)
> vec1 64 ssa_23 = load_const (0x 1 /* 0.00 */)
> vec1 64 ssa_24 = deref_array &(*ssa_19)[1] (function_temp uint) /*
> &@2[1] */
> intrinsic store_deref (ssa_24, ssa_18) (1, 0) /* wrmask=x */ /*
> access=0 */
> vec1 64 ssa_25 = deref_cast (uint *)ssa_1 (global uint)
> vec1 64 ssa_26 = load_const (0x 2 /* 0.00 */)
> vec1 64 ssa_27 = deref_ptr_as_array &(*ssa_25)[2] (global uint) /*
> &(*(uint *)ssa_1)[2] */
> vec1 32 ssa_28 = intrinsic load_deref (ssa_27) (0) /* access=0 */
> vec1 64 ssa_29 = deref_var &@2 (function_temp uint[3])
> vec1 64 ssa_30 = deref_cast (uint[3] *)ssa_29 (function_temp uint[3])
> vec1 64 ssa_31 = load_const (0x 0 /* 0.00 */)
> vec1 64 ssa_33 = load_const (0x 2 /* 0.00 */)
> vec1 64 ssa_34 = deref_array &(*ssa_29)[2] (function_temp uint) /*
> &@2[2] */
> intrinsic store_deref (ssa_34, ssa_28) (1, 0) /* wrmask=x */ /*
> access=0 */
> vec1 64 ssa_35 = deref_cast (uvec2 *)ssa_14 (function_temp uvec2)
> vec2 32 ssa_37 = intrinsic load_deref (ssa_35) (0) /* access=0 */
> intrinsic store_deref (ssa_7, ssa_37) (3, 0) /* wrmask=xy */ /*
> access=0 */
> vec1 64 ssa_38 = deref_cast (uvec2 *)ssa_24 (function_temp uvec2)
> vec2 32 ssa_40 = intrinsic load_deref (ssa_38) (0) /* access=0 */
> vec1 64 ssa_41 = deref_cast (uvec2 *)ssa_3 (global uvec2)
> vec1 64 ssa_42 = load_const (0x 1 /* 0.00 */)
> vec1 64 ssa_43 = deref_ptr_as_array &(*ssa_41)[1] (global uvec2)
> /* &(*(uvec2 *)ssa_3)[1] */
> intrinsic store_deref (ssa_43, ssa_40) (3, 0) /* wrmask=xy */ /*
> access=0 */
> /* succs: block_1 */
> block block_1:
> }
>
> nir_opt_copy_prop_vars
> ## nir_copy_prop_vars_impl for __wrapped_vload2_private
> # block0
>
> vec1 64 ssa_0 = deref_var (shader_in uint64_t)
> vec1 64 ssa_1 = intrinsic load_deref (ssa_0) (0) /* access=0 */
> uint64_t unnamed: ssa_1
>
> vec1 64 ssa_2 = deref_var (shader_in uint64_t)
> vec1 64 ssa_3 = intrinsic load_deref (ssa_2) (0) /* access=0 */
> uint64_t unnamed: ssa_1
> uint64_t unnamed: ssa_3
>
> vec1 64 ssa_6 = deref_cast (uint *)ssa_1 (global uint)
> vec1 64 ssa_7 = deref_cast (uvec2 *)ssa_3 (global uvec2)
> vec1 32 ssa_8 = intrinsic load_deref (ssa_6) (0) /* access=0 */
> uint64_t unnamed: ssa_1
> uint64_t unnamed: ssa_3
> uint (uint *)ssa_1: ssa_8
>
> vec1 64 ssa_9 = deref_var (function_temp uint[3])
> vec1 64 ssa_10 = deref_cast (uint[3] *)ssa_9
Re: [Mesa-dev] [PATCH v3 1/2] nir: Add is_non_scalar_swizzle search helper
Reviewed-by: Jason Ekstrand
On Fri, May 10, 2019 at 12:59 PM Alyssa Rosenzweig
wrote:
> This allows algebraic optimizations to check if the argument accesses
> multiple distinct components of a vector. So a swizzle like "xyz" will
> return true, but "yyy" will return false, as will a scalar. This can be
> useful for optimizations on vector processors, where a scalar
> swizzle can be handled in one clock (replicated a scalar channel) but a
> non-scalar swizzle requires multiple scalarized operations. In these
> cases, it is useful to optimize differently based on whether the swizzle
> is non-scalar.
>
> For my use case, csel on Midgard requires a scalar condition, so this
> allows csel to be lowered only with a vector condition.
>
> Signed-off-by: Alyssa Rosenzweig
> Cc: Jason Ekstrand
> Cc: Ilia Mirkin
> ---
> src/compiler/nir/nir_search_helpers.h | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/src/compiler/nir/nir_search_helpers.h
> b/src/compiler/nir/nir_search_helpers.h
> index 1624508993d..8e26739a3ce 100644
> --- a/src/compiler/nir/nir_search_helpers.h
> +++ b/src/compiler/nir/nir_search_helpers.h
> @@ -143,6 +143,23 @@ is_not_const(nir_alu_instr *instr, unsigned src,
> UNUSED unsigned num_components,
> return !nir_src_is_const(instr->src[src].src);
> }
>
> +/* I.e. the vector's swizzle actually accesses multiple channels. True for
> + * xyzw, false for , false for w */
> +
> +static inline bool
> +is_non_scalar_swizzle(nir_alu_instr *instr, UNUSED unsigned src,
> + unsigned num_components, const uint8_t *swizzle)
> +{
> + unsigned first_component = swizzle[0];
> +
> + for (unsigned i = 1; i < num_components; ++i) {
> + if (swizzle[i] != first_component)
> + return true;
> + }
> +
> + return false;
> +}
> +
> static inline bool
> is_used_more_than_once(nir_alu_instr *instr)
> {
> --
> 2.20.1
>
>
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[Mesa-dev] [Bug 110625] [TRACKER] Mesa 19.1 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=110625 Clayton Craft changed: What|Removed |Added Depends on||110357 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=110357 [Bug 110357] [REGRESSION] [BISECTED] [OpenGL CTS] cts-runner --type=gl46 fails in new attempted "41" configuration -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110625] [TRACKER] Mesa 19.1 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=110625 Clayton Craft changed: What|Removed |Added Depends on||110302 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=110302 [Bug 110302] [bisected][regression] piglit egl-create-pbuffer-surface and egl-gl-colorspace regressions -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] intel/tools: Fix build with glibc < 2.27.
glibc < 2.27 defines OVERFLOW in /usr/include/math.h.
This patch fixes this build error.
In file included from ../include/c99_math.h:37:0,
from ../src/util/u_math.h:44,
from ../src/mesa/main/macros.h:35,
from ../src/intel/compiler/brw_reg.h:47,
from ../src/intel/tools/i965_asm.h:32,
from ../src/intel/tools/i965_gram.y:29:
src/intel/tools/i965_gram.tab.c:562:5: error: expected identifier before
numeric constant
OVERFLOW = 412,
^
Fixes: 70308a5a8a80 ("intel/tools: New i965 instruction assembler tool")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110656
Signed-off-by: Vinson Lee
Acked-by: Eric Engestrom
---
src/intel/tools/i965_asm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/intel/tools/i965_asm.h b/src/intel/tools/i965_asm.h
index 7027f4e..dd29208 100644
--- a/src/intel/tools/i965_asm.h
+++ b/src/intel/tools/i965_asm.h
@@ -36,6 +36,9 @@
#include "compiler/brw_eu.h"
#include "dev/gen_device_info.h"
+/* glibc < 2.27 defines OVERFLOW in /usr/include/math.h. */
+#undef OVERFLOW
+
void yyerror (char *);
int yyparse(void);
int yylex(void);
--
2.7.4
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[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 --- Comment #6 from tempel.jul...@gmail.com --- Created attachment 144229 --> https://bugs.freedesktop.org/attachment.cgi?id=144229=edit renderdoc capture part 6/6 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110663] threads_posix.h:96: undefined reference to `pthread_once'
https://bugs.freedesktop.org/show_bug.cgi?id=110663 Bug ID: 110663 Summary: threads_posix.h:96: undefined reference to `pthread_once' Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Mesa core Assignee: mesa-dev@lists.freedesktop.org Reporter: v...@freedesktop.org QA Contact: mesa-dev@lists.freedesktop.org meson builddir -Ddri-drivers='' -Dbuild-tests=true -Dgallium-drivers=swrast -Dplatforms=x11 -Dvulkan-drivers='' FAILED: src/gallium/tests/trivial/quad-tex ccache c++ -o src/gallium/tests/trivial/quad-tex 'src/gallium/tests/trivial/quad-tex@exe/quad-tex.c.o' -Wl,--no-undefined -Wl,--as-needed -Wl,--start-group src/util/libmesa_util.a src/gallium/auxiliary/libgallium.a src/compiler/glsl/libglsl.a src/compiler/glsl/glcpp/libglcpp.a src/compiler/nir/libnir.a src/compiler/libcompiler.a src/gallium/auxiliary/pipe-loader/libpipe_loader_dynamic.a src/loader/libloader.a src/util/libxmlconfig.a -lz -lm -Wl,--end-group -ldrm -L/usr/lib/llvm-6.0/lib -lLLVM-6.0 -lunwind -ldl -lm -lsensors -lz -lm -ldrm -ldrm -lexpat -lm -lz -lm src/util/libmesa_util.a(u_cpu_detect.c.o): In function `call_once': ../include/c11/threads_posix.h:96: undefined reference to `pthread_once' -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 --- Comment #5 from tempel.jul...@gmail.com --- Created attachment 144228 --> https://bugs.freedesktop.org/attachment.cgi?id=144228=edit renderdoc capture part 5 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 --- Comment #4 from tempel.jul...@gmail.com --- Created attachment 144227 --> https://bugs.freedesktop.org/attachment.cgi?id=144227=edit renderdoc capture part 4 -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 --- Comment #3 from tempel.jul...@gmail.com --- Created attachment 144226 --> https://bugs.freedesktop.org/attachment.cgi?id=144226=edit renderdoc capture part 3 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 --- Comment #2 from tempel.jul...@gmail.com --- Created attachment 144225 --> https://bugs.freedesktop.org/attachment.cgi?id=144225=edit renderdoc capture part 2 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] intel/tools: Fix build with glibc < 2.27.
On 2019-05-10 at 19:28, Vinson Lee wrote:
> glibc < 2.27 defines OVERFLOW in /usr/include/math.h.
>
> This patch fixes this build error.
>
> In file included from ../include/c99_math.h:37:0,
> from ../src/util/u_math.h:44,
> from ../src/mesa/main/macros.h:35,
> from ../src/intel/compiler/brw_reg.h:47,
> from ../src/intel/tools/i965_asm.h:32,
> from ../src/intel/tools/i965_gram.y:29:
> src/intel/tools/i965_gram.tab.c:562:5: error: expected identifier
> before numeric constant
> OVERFLOW = 412,
> ^
>
> Fixes: 70308a5a8a80 ("intel/tools: New i965 instruction assembler tool")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110656
> Signed-off-by: Vinson Lee
> ---
> src/intel/tools/i965_asm.h | 4
> 1 file changed, 4 insertions(+)
>
> diff --git a/src/intel/tools/i965_asm.h b/src/intel/tools/i965_asm.h
> index 7027f4e..0519ba5 100644
> --- a/src/intel/tools/i965_asm.h
> +++ b/src/intel/tools/i965_asm.h
> @@ -36,6 +36,10 @@
> #include "compiler/brw_eu.h"
> #include "dev/gen_device_info.h"
>
> +#ifdef OVERFLOW
> +#undef OVERFLOW
> +#endif
You don't need the #ifdef, you can just #undef.
Can you add the first line of the commit message as an online comment here?
Acked-by: Eric Engestrom
> +
> void yyerror (char *);
> int yyparse(void);
> int yylex(void);
> --
> 2.7.4
>
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[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 --- Comment #1 from tempel.jul...@gmail.com --- Created attachment 144224 --> https://bugs.freedesktop.org/attachment.cgi?id=144224=edit renderdoc capture part 1 -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110662] shadow artifacts in Assassin's Creed: Unity
https://bugs.freedesktop.org/show_bug.cgi?id=110662 Bug ID: 110662 Summary: shadow artifacts in Assassin's Creed: Unity Product: Mesa Version: git Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: normal Priority: medium Component: Drivers/Vulkan/radeon Assignee: mesa-dev@lists.freedesktop.org Reporter: tempel.jul...@gmail.com QA Contact: mesa-dev@lists.freedesktop.org Especially in interiors like this, there are "holes" and stripe artifacts in shadow maps: https://abload.de/img/screenshot_20190510_24djhr.png They also wander and change shape in motion, making the corruption quite perceivable. The issue does not occur with proprietary amdvlk driver (open amdvlk hangs) and neither on Windows with DX11. Using Nvidia PCSS GameWorks effect mitigates or stops the issue, but it's very expensive. Uploading renderdoc capture right now. Latest git-master versions of dxvk and mesa were used. -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] st/mesa: fix 2 crashes in st_tgsi_lower_yuv
On Fri, May 10, 2019 at 1:29 PM Marek Olšák wrote:
>
> From: Marek Olšák
>
> src/mesa/state_tracker/st_tgsi_lower_yuv.c:68: void reg_dst(struct
> tgsi_full_dst_register *, const struct tgsi_full_dst_register *, unsigned
> int): assertion "dst->Register.WriteMask" failed
>
> The second crash was due to insufficient allocated size for TGSI
> instructions.
I might have split this into two patches, but either way you can add my:
Reviewed-by: Rob Clark
>
> Cc: 19.0 19.1
> ---
> src/mesa/state_tracker/st_tgsi_lower_yuv.c | 48 +-
> 1 file changed, 28 insertions(+), 20 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_tgsi_lower_yuv.c
> b/src/mesa/state_tracker/st_tgsi_lower_yuv.c
> index 6acd173adc9..73437ddda70 100644
> --- a/src/mesa/state_tracker/st_tgsi_lower_yuv.c
> +++ b/src/mesa/state_tracker/st_tgsi_lower_yuv.c
> @@ -262,45 +262,53 @@ yuv_to_rgb(struct tgsi_transform_context *tctx,
> inst.Instruction.Saturate = 0;
> inst.Instruction.NumDstRegs = 1;
> inst.Instruction.NumSrcRegs = 2;
> reg_dst([0], >tmp[A].dst, TGSI_WRITEMASK_XYZ);
> reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, _));
> reg_src([1], >imm[3], SWIZ(X, Y, Z, _));
> inst.Src[1].Register.Negate = 1;
> tctx->emit_instruction(tctx, );
>
> /* DP3 dst.x, tmpA, imm[0] */
> - inst = dp3_instruction();
> - reg_dst([0], dst, TGSI_WRITEMASK_X);
> - reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
> - reg_src([1], >imm[0], SWIZ(X, Y, Z, W));
> - tctx->emit_instruction(tctx, );
> + if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
> + inst = dp3_instruction();
> + reg_dst([0], dst, TGSI_WRITEMASK_X);
> + reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
> + reg_src([1], >imm[0], SWIZ(X, Y, Z, W));
> + tctx->emit_instruction(tctx, );
> + }
>
> /* DP3 dst.y, tmpA, imm[1] */
> - inst = dp3_instruction();
> - reg_dst([0], dst, TGSI_WRITEMASK_Y);
> - reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
> - reg_src([1], >imm[1], SWIZ(X, Y, Z, W));
> - tctx->emit_instruction(tctx, );
> + if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
> + inst = dp3_instruction();
> + reg_dst([0], dst, TGSI_WRITEMASK_Y);
> + reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
> + reg_src([1], >imm[1], SWIZ(X, Y, Z, W));
> + tctx->emit_instruction(tctx, );
> + }
>
> /* DP3 dst.z, tmpA, imm[2] */
> - inst = dp3_instruction();
> - reg_dst([0], dst, TGSI_WRITEMASK_Z);
> - reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
> - reg_src([1], >imm[2], SWIZ(X, Y, Z, W));
> - tctx->emit_instruction(tctx, );
> + if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) {
> + inst = dp3_instruction();
> + reg_dst([0], dst, TGSI_WRITEMASK_Z);
> + reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
> + reg_src([1], >imm[2], SWIZ(X, Y, Z, W));
> + tctx->emit_instruction(tctx, );
> + }
>
> /* MOV dst.w, imm[0].x */
> - inst = mov_instruction();
> - reg_dst([0], dst, TGSI_WRITEMASK_W);
> - reg_src([0], >imm[3], SWIZ(_, _, _, W));
> - tctx->emit_instruction(tctx, );
> + if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
> + inst = mov_instruction();
> + reg_dst([0], dst, TGSI_WRITEMASK_W);
> + reg_src([0], >imm[3], SWIZ(_, _, _, W));
> + tctx->emit_instruction(tctx, );
> + }
> }
>
> static void
> lower_nv12(struct tgsi_transform_context *tctx,
> struct tgsi_full_instruction *originst)
> {
> struct tgsi_yuv_transform *ctx = tgsi_yuv_transform(tctx);
> struct tgsi_full_instruction inst;
> struct tgsi_full_src_register *coord = >Src[0];
> unsigned samp = originst->Src[1].Register.Index;
> @@ -427,21 +435,21 @@ st_tgsi_lower_yuv(const struct tgsi_token *tokens,
> unsigned free_slots,
> memset(, 0, sizeof(ctx));
> ctx.base.transform_instruction = transform_instr;
> ctx.free_slots = free_slots;
> ctx.lower_nv12 = lower_nv12;
> ctx.lower_iyuv = lower_iyuv;
> tgsi_scan_shader(tokens, );
>
> /* TODO better job of figuring out how many extra tokens we need..
> * this is a pain about tgsi_transform :-/
> */
> - newlen = tgsi_num_tokens(tokens) + 120;
> + newlen = tgsi_num_tokens(tokens) + 300;
> newtoks = tgsi_alloc_tokens(newlen);
> if (!newtoks)
>return NULL;
>
> tgsi_transform_shader(tokens, newtoks, newlen, );
>
> // tgsi_dump(newtoks, 0);
> // debug_printf("\n");
>
> return newtoks;
> --
> 2.17.1
>
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[Mesa-dev] [PATCH] st/mesa: fix 2 crashes in st_tgsi_lower_yuv
From: Marek Olšák
src/mesa/state_tracker/st_tgsi_lower_yuv.c:68: void reg_dst(struct
tgsi_full_dst_register *, const struct tgsi_full_dst_register *, unsigned
int): assertion "dst->Register.WriteMask" failed
The second crash was due to insufficient allocated size for TGSI
instructions.
Cc: 19.0 19.1
---
src/mesa/state_tracker/st_tgsi_lower_yuv.c | 48 +-
1 file changed, 28 insertions(+), 20 deletions(-)
diff --git a/src/mesa/state_tracker/st_tgsi_lower_yuv.c
b/src/mesa/state_tracker/st_tgsi_lower_yuv.c
index 6acd173adc9..73437ddda70 100644
--- a/src/mesa/state_tracker/st_tgsi_lower_yuv.c
+++ b/src/mesa/state_tracker/st_tgsi_lower_yuv.c
@@ -262,45 +262,53 @@ yuv_to_rgb(struct tgsi_transform_context *tctx,
inst.Instruction.Saturate = 0;
inst.Instruction.NumDstRegs = 1;
inst.Instruction.NumSrcRegs = 2;
reg_dst([0], >tmp[A].dst, TGSI_WRITEMASK_XYZ);
reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, _));
reg_src([1], >imm[3], SWIZ(X, Y, Z, _));
inst.Src[1].Register.Negate = 1;
tctx->emit_instruction(tctx, );
/* DP3 dst.x, tmpA, imm[0] */
- inst = dp3_instruction();
- reg_dst([0], dst, TGSI_WRITEMASK_X);
- reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
- reg_src([1], >imm[0], SWIZ(X, Y, Z, W));
- tctx->emit_instruction(tctx, );
+ if (dst->Register.WriteMask & TGSI_WRITEMASK_X) {
+ inst = dp3_instruction();
+ reg_dst([0], dst, TGSI_WRITEMASK_X);
+ reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
+ reg_src([1], >imm[0], SWIZ(X, Y, Z, W));
+ tctx->emit_instruction(tctx, );
+ }
/* DP3 dst.y, tmpA, imm[1] */
- inst = dp3_instruction();
- reg_dst([0], dst, TGSI_WRITEMASK_Y);
- reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
- reg_src([1], >imm[1], SWIZ(X, Y, Z, W));
- tctx->emit_instruction(tctx, );
+ if (dst->Register.WriteMask & TGSI_WRITEMASK_Y) {
+ inst = dp3_instruction();
+ reg_dst([0], dst, TGSI_WRITEMASK_Y);
+ reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
+ reg_src([1], >imm[1], SWIZ(X, Y, Z, W));
+ tctx->emit_instruction(tctx, );
+ }
/* DP3 dst.z, tmpA, imm[2] */
- inst = dp3_instruction();
- reg_dst([0], dst, TGSI_WRITEMASK_Z);
- reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
- reg_src([1], >imm[2], SWIZ(X, Y, Z, W));
- tctx->emit_instruction(tctx, );
+ if (dst->Register.WriteMask & TGSI_WRITEMASK_Z) {
+ inst = dp3_instruction();
+ reg_dst([0], dst, TGSI_WRITEMASK_Z);
+ reg_src([0], >tmp[A].src, SWIZ(X, Y, Z, W));
+ reg_src([1], >imm[2], SWIZ(X, Y, Z, W));
+ tctx->emit_instruction(tctx, );
+ }
/* MOV dst.w, imm[0].x */
- inst = mov_instruction();
- reg_dst([0], dst, TGSI_WRITEMASK_W);
- reg_src([0], >imm[3], SWIZ(_, _, _, W));
- tctx->emit_instruction(tctx, );
+ if (dst->Register.WriteMask & TGSI_WRITEMASK_W) {
+ inst = mov_instruction();
+ reg_dst([0], dst, TGSI_WRITEMASK_W);
+ reg_src([0], >imm[3], SWIZ(_, _, _, W));
+ tctx->emit_instruction(tctx, );
+ }
}
static void
lower_nv12(struct tgsi_transform_context *tctx,
struct tgsi_full_instruction *originst)
{
struct tgsi_yuv_transform *ctx = tgsi_yuv_transform(tctx);
struct tgsi_full_instruction inst;
struct tgsi_full_src_register *coord = >Src[0];
unsigned samp = originst->Src[1].Register.Index;
@@ -427,21 +435,21 @@ st_tgsi_lower_yuv(const struct tgsi_token *tokens,
unsigned free_slots,
memset(, 0, sizeof(ctx));
ctx.base.transform_instruction = transform_instr;
ctx.free_slots = free_slots;
ctx.lower_nv12 = lower_nv12;
ctx.lower_iyuv = lower_iyuv;
tgsi_scan_shader(tokens, );
/* TODO better job of figuring out how many extra tokens we need..
* this is a pain about tgsi_transform :-/
*/
- newlen = tgsi_num_tokens(tokens) + 120;
+ newlen = tgsi_num_tokens(tokens) + 300;
newtoks = tgsi_alloc_tokens(newlen);
if (!newtoks)
return NULL;
tgsi_transform_shader(tokens, newtoks, newlen, );
// tgsi_dump(newtoks, 0);
// debug_printf("\n");
return newtoks;
--
2.17.1
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Re: [Mesa-dev] [PATCH] radv: clear vertex bindings while resetting command buffer
Reviewed-by: Bas Nieuwenhuizen
Fixes: 5010436e09f "radv: bail out when binding the same vertex buffers"
I'll push after running it through the testsuite.
Thanks!
On Fri, May 10, 2019 at 9:38 PM Józef Kucia wrote:
>
> Only vertex inputs accessed by vertex shader must have valid buffers
> bound.
>
> Signed-off-by: Józef Kucia
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index b04c998fac2e..890662841d21 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -301,7 +301,6 @@ radv_cmd_buffer_destroy(struct radv_cmd_buffer
> *cmd_buffer)
> static VkResult
> radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
> {
> -
> cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
>
> list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
> @@ -326,6 +325,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
>
> cmd_buffer->record_result = VK_SUCCESS;
>
> + memset(cmd_buffer->vertex_bindings, 0,
> sizeof(cmd_buffer->vertex_bindings));
> +
> for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
> cmd_buffer->descriptors[i].dirty = 0;
> cmd_buffer->descriptors[i].valid = 0;
> --
> 2.21.0
>
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[Mesa-dev] [PATCH] radv: clear vertex bindings while resetting command buffer
Only vertex inputs accessed by vertex shader must have valid buffers
bound.
Signed-off-by: Józef Kucia
---
src/amd/vulkan/radv_cmd_buffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index b04c998fac2e..890662841d21 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -301,7 +301,6 @@ radv_cmd_buffer_destroy(struct radv_cmd_buffer *cmd_buffer)
static VkResult
radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
{
-
cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);
list_for_each_entry_safe(struct radv_cmd_buffer_upload, up,
@@ -326,6 +325,8 @@ radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)
cmd_buffer->record_result = VK_SUCCESS;
+ memset(cmd_buffer->vertex_bindings, 0,
sizeof(cmd_buffer->vertex_bindings));
+
for (unsigned i = 0; i < VK_PIPELINE_BIND_POINT_RANGE_SIZE; i++) {
cmd_buffer->descriptors[i].dirty = 0;
cmd_buffer->descriptors[i].valid = 0;
--
2.21.0
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Re: [Mesa-dev] [RFC PATCH 03/17] eir: add live ranges pass
On Fri, May 10, 2019 at 12:28 PM Rob Clark wrote:
>
> On Fri, May 10, 2019 at 7:43 AM Connor Abbott wrote:
> >
> > On Fri, May 10, 2019 at 11:47 AM Connor Abbott wrote:
> > >
> > >
> > > This way of representing liveness, and then using a coloring register
> > > allocator, is a common anti-pattern in Mesa, that was initially copied
> > > from i965 which dates back to before we knew any better. I really
> > > don't want to see it spread to yet another driver :(.
> > >
> > > Representing live ranges like this is imprecise. If I have a program like
> > > this:
> > >
> > > foo = ...
> > > if (...) {
> > >bar = ...
> > >... = bar; /* last use of "bar" */
> > > }
> > > ... = foo;
> >
> > Whoops, that should actually read:
> >
> > foo = ...
> > if (...) {
> >bar = ...
> >... = bar; /* last use of "bar" */
> > } else {
> >... = foo;
> > }
>
> hmm, my mind is a bit rusty on the live-range analysis, but foo and
> bar do interfere in the if() side of the if/else..
>
> I thought the case we didn't handle properly was more like a loop:
>
> foo = ...
> for (..) {
>bar = foo;
>... stuff .. foo not live here..
>foo = ...
> }
> ... = foo
>
> where we end up considering foo live during the entire body of the
> loop even though it isn't really. I guess it is the same case as:
>
> foo = ...
> if () {
>bar = foo;
>...
>foo = ...
> }
> ... = foo;
>
hmm, maybe I mis-read your example (damn gmail hiding quotes).. I
guess last use of bar is in the else block, so we are saying the same
(or similar) thing?
BR,
-R
> BR,
> -R
>
> >
> > >
> > > Then it will say that foo and bar interfere, even when they don't.
> > >
> > > Now, this approximation does make things a bit simpler. But, it turns
> > > out that if you're willing to make it, then the interference graph is
> > > trivially colorable via a simple linear-time algorithm. This is the
> > > basis of "linear-scan" register allocators, including the one in LLVM.
> > > If you want to go down this route, you can, but this hybrid is just
> > > useless as it gives you the worst of both worlds.
> > >
> > > If you want to properly build up the interference graph, it's actually
> > > not that hard. After doing the inter-basic-block liveness analysis,
> > > for each block, you initialize a bitset to the live-out bitset. Then
> > > you walk the block backwards, updating it at each instruction exactly
> > > as in liveness analysis, so that it always represents the live
> > > registers before each instruction. Then you add interferences between
> > > all of the live registers and the register(s) defined at the
> > > instruction.
> > >
> > > One last pitfall I'll mention is that in the real world, you'll also
> > > need to use reachability. If you have something like
> > >
> > > if (...)
> > >foo = ... /* only definition of "foo" */
> > >
> > > ... = foo;
> > >
> > > where foo is only partially defined, then the liveness of foo will
> > > "leak" through the if. To fix this you need to consider what's called
> > > "reachability," i.e. something is only live if, in addition to
> > > potentially being used sometime later, it is reachable (potentially
> > > defined sometime earlier). Reachability analysis is exactly like
> > > liveness analysis, but everything is backwards. i965 does this
> > > properly nowadays, and the change had a huge effect on spilling/RA.
> > >
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [RFC PATCH 03/17] eir: add live ranges pass
On Fri, May 10, 2019 at 7:43 AM Connor Abbott wrote:
>
> On Fri, May 10, 2019 at 11:47 AM Connor Abbott wrote:
> >
> >
> > This way of representing liveness, and then using a coloring register
> > allocator, is a common anti-pattern in Mesa, that was initially copied
> > from i965 which dates back to before we knew any better. I really
> > don't want to see it spread to yet another driver :(.
> >
> > Representing live ranges like this is imprecise. If I have a program like
> > this:
> >
> > foo = ...
> > if (...) {
> >bar = ...
> >... = bar; /* last use of "bar" */
> > }
> > ... = foo;
>
> Whoops, that should actually read:
>
> foo = ...
> if (...) {
>bar = ...
>... = bar; /* last use of "bar" */
> } else {
>... = foo;
> }
hmm, my mind is a bit rusty on the live-range analysis, but foo and
bar do interfere in the if() side of the if/else..
I thought the case we didn't handle properly was more like a loop:
foo = ...
for (..) {
bar = foo;
... stuff .. foo not live here..
foo = ...
}
... = foo
where we end up considering foo live during the entire body of the
loop even though it isn't really. I guess it is the same case as:
foo = ...
if () {
bar = foo;
...
foo = ...
}
... = foo;
BR,
-R
>
> >
> > Then it will say that foo and bar interfere, even when they don't.
> >
> > Now, this approximation does make things a bit simpler. But, it turns
> > out that if you're willing to make it, then the interference graph is
> > trivially colorable via a simple linear-time algorithm. This is the
> > basis of "linear-scan" register allocators, including the one in LLVM.
> > If you want to go down this route, you can, but this hybrid is just
> > useless as it gives you the worst of both worlds.
> >
> > If you want to properly build up the interference graph, it's actually
> > not that hard. After doing the inter-basic-block liveness analysis,
> > for each block, you initialize a bitset to the live-out bitset. Then
> > you walk the block backwards, updating it at each instruction exactly
> > as in liveness analysis, so that it always represents the live
> > registers before each instruction. Then you add interferences between
> > all of the live registers and the register(s) defined at the
> > instruction.
> >
> > One last pitfall I'll mention is that in the real world, you'll also
> > need to use reachability. If you have something like
> >
> > if (...)
> >foo = ... /* only definition of "foo" */
> >
> > ... = foo;
> >
> > where foo is only partially defined, then the liveness of foo will
> > "leak" through the if. To fix this you need to consider what's called
> > "reachability," i.e. something is only live if, in addition to
> > potentially being used sometime later, it is reachable (potentially
> > defined sometime earlier). Reachability analysis is exactly like
> > liveness analysis, but everything is backwards. i965 does this
> > properly nowadays, and the change had a huge effect on spilling/RA.
> >
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[Mesa-dev] [PATCH] intel/tools: Fix build with glibc < 2.27.
glibc < 2.27 defines OVERFLOW in /usr/include/math.h.
This patch fixes this build error.
In file included from ../include/c99_math.h:37:0,
from ../src/util/u_math.h:44,
from ../src/mesa/main/macros.h:35,
from ../src/intel/compiler/brw_reg.h:47,
from ../src/intel/tools/i965_asm.h:32,
from ../src/intel/tools/i965_gram.y:29:
src/intel/tools/i965_gram.tab.c:562:5: error: expected identifier before
numeric constant
OVERFLOW = 412,
^
Fixes: 70308a5a8a80 ("intel/tools: New i965 instruction assembler tool")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110656
Signed-off-by: Vinson Lee
---
src/intel/tools/i965_asm.h | 4
1 file changed, 4 insertions(+)
diff --git a/src/intel/tools/i965_asm.h b/src/intel/tools/i965_asm.h
index 7027f4e..0519ba5 100644
--- a/src/intel/tools/i965_asm.h
+++ b/src/intel/tools/i965_asm.h
@@ -36,6 +36,10 @@
#include "compiler/brw_eu.h"
#include "dev/gen_device_info.h"
+#ifdef OVERFLOW
+#undef OVERFLOW
+#endif
+
void yyerror (char *);
int yyparse(void);
int yylex(void);
--
2.7.4
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[Mesa-dev] [PATCH v3 1/2] nir: Add is_non_scalar_swizzle search helper
This allows algebraic optimizations to check if the argument accesses
multiple distinct components of a vector. So a swizzle like "xyz" will
return true, but "yyy" will return false, as will a scalar. This can be
useful for optimizations on vector processors, where a scalar
swizzle can be handled in one clock (replicated a scalar channel) but a
non-scalar swizzle requires multiple scalarized operations. In these
cases, it is useful to optimize differently based on whether the swizzle
is non-scalar.
For my use case, csel on Midgard requires a scalar condition, so this
allows csel to be lowered only with a vector condition.
Signed-off-by: Alyssa Rosenzweig
Cc: Jason Ekstrand
Cc: Ilia Mirkin
---
src/compiler/nir/nir_search_helpers.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/compiler/nir/nir_search_helpers.h
b/src/compiler/nir/nir_search_helpers.h
index 1624508993d..8e26739a3ce 100644
--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -143,6 +143,23 @@ is_not_const(nir_alu_instr *instr, unsigned src, UNUSED
unsigned num_components,
return !nir_src_is_const(instr->src[src].src);
}
+/* I.e. the vector's swizzle actually accesses multiple channels. True for
+ * xyzw, false for , false for w */
+
+static inline bool
+is_non_scalar_swizzle(nir_alu_instr *instr, UNUSED unsigned src,
+ unsigned num_components, const uint8_t *swizzle)
+{
+ unsigned first_component = swizzle[0];
+
+ for (unsigned i = 1; i < num_components; ++i) {
+ if (swizzle[i] != first_component)
+ return true;
+ }
+
+ return false;
+}
+
static inline bool
is_used_more_than_once(nir_alu_instr *instr)
{
--
2.20.1
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[Mesa-dev] [PATCH v3 2/2] panfrost/midgard: Cleanup csel lowering
Signed-off-by: Alyssa Rosenzweig
---
.../panfrost/midgard/midgard_compile.c| 151 +++---
.../panfrost/midgard/midgard_nir_algebraic.py | 12 +-
2 files changed, 37 insertions(+), 126 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 25316cab053..4ed36c53dfc 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -715,58 +715,6 @@ midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr
*alu)
nir_ssa_def_rewrite_uses(>dest.dest.ssa, nir_src_for_ssa(sum));
}
-/* Lower csel with mixed condition channels to mulitple csel instructions. For
- * context, the csel ops on Midgard are vector in *outputs*, but not in
- * *conditions*. So, if the condition is e.g. , a single op can select a
- * vec4. But if the condition is e.g. xyzw, four ops are needed as the ISA
- * can't cope with the divergent channels.*/
-
-static void
-midgard_nir_lower_mixed_csel_body(nir_builder *b, nir_alu_instr *alu)
-{
-if (alu->op != nir_op_bcsel)
-return;
-
-b->cursor = nir_before_instr(>instr);
-
-/* Must be run before registering */
-assert(alu->dest.dest.is_ssa);
-
-/* Check for mixed condition */
-
-unsigned comp = alu->src[0].swizzle[0];
-unsigned nr_components = alu->dest.dest.ssa.num_components;
-
-bool mixed = false;
-
-for (unsigned c = 1; c < nr_components; ++c)
-mixed |= (alu->src[0].swizzle[c] != comp);
-
-if (!mixed)
-return;
-
-/* We're mixed, so lower */
-
-assert(nr_components <= 4);
-nir_ssa_def *results[4];
-
-nir_ssa_def *cond = nir_ssa_for_alu_src(b, alu, 0);
-nir_ssa_def *choice0 = nir_ssa_for_alu_src(b, alu, 1);
-nir_ssa_def *choice1 = nir_ssa_for_alu_src(b, alu, 2);
-
-for (unsigned c = 0; c < nr_components; ++c) {
-results[c] = nir_bcsel(b,
-nir_channel(b, cond, c),
-nir_channel(b, choice0, c),
-nir_channel(b, choice1, c));
-}
-
-/* Replace with our scalarized version */
-
-nir_ssa_def *result = nir_vec(b, results, nr_components);
-nir_ssa_def_rewrite_uses(>dest.dest.ssa, nir_src_for_ssa(result));
-}
-
static int
midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
{
@@ -851,36 +799,6 @@ midgard_nir_lower_fdot2(nir_shader *shader)
return progress;
}
-static bool
-midgard_nir_lower_mixed_csel(nir_shader *shader)
-{
-bool progress = false;
-
-nir_foreach_function(function, shader) {
-if (!function->impl) continue;
-
-nir_builder _b;
-nir_builder *b = &_b;
-nir_builder_init(b, function->impl);
-
-nir_foreach_block(block, function->impl) {
-nir_foreach_instr_safe(instr, block) {
-if (instr->type != nir_instr_type_alu)
continue;
-
-nir_alu_instr *alu = nir_instr_as_alu(instr);
-midgard_nir_lower_mixed_csel_body(b, alu);
-
-progress |= true;
-}
-}
-
-nir_metadata_preserve(function->impl, nir_metadata_block_index
| nir_metadata_dominance);
-
-}
-
-return progress;
-}
-
static void
optimise_nir(nir_shader *nir)
{
@@ -892,7 +810,6 @@ optimise_nir(nir_shader *nir)
NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
-NIR_PASS(progress, nir, midgard_nir_lower_mixed_csel);
nir_lower_tex_options lower_tex_options = {
.lower_rect = true
@@ -957,6 +874,11 @@ optimise_nir(nir_shader *nir)
} while (progress);
NIR_PASS(progress, nir, nir_opt_algebraic_late);
+
+/* We implement booleans as 32-bit 0/~0 */
+NIR_PASS(progress, nir, nir_lower_bool_to_int32);
+
+/* Now that booleans are lowered, we can run out late opts */
NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
/* Lower mods for float ops only. Integer ops don't support modifiers
@@ -967,9 +889,6 @@ optimise_nir(nir_shader *nir)
NIR_PASS(progress, nir, nir_copy_prop);
NIR_PASS(progress, nir, nir_opt_dce);
-/* We implement booleans as 32-bit 0/~0 */
-NIR_PASS(progress, nir, nir_lower_bool_to_int32);
-
/* Take us out of SSA */
NIR_PASS(progress, nir, nir_lower_locals_to_regs);
NIR_PASS(progress, nir, nir_convert_from_ssa, true);
@@ -1189,7 +1108,6 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
case nir_op_##nir: \
op =
Re: [Mesa-dev] [RFC 2/2] mesa: Android: enable altxmlconfig for O+
Hi Sumit, I haven't looked too closely at this, but there are a couple of things right away that jumped out to me. I've noted them inline below Quoting Sumit Semwal (2019-05-09 23:02:57) > Android version O and later would like to use altxmlconfig > instead of libexpat based parsing. > > We enable altxmlconfig instead of xmlconfig.c for Android O+. > > Change-Id: Iaa51b2a1e9c16a1fdf6f120104429b19dc68f9eb Please do not include "Change-Id:" tags, we don't use them in mesa. > Signed-off-by: Sumit Semwal > --- > src/gallium/targets/dri/Android.mk | 8 +++- > src/mesa/drivers/dri/Android.mk| 12 +--- > src/util/Android.mk| 12 +--- > src/util/Makefile.sources | 2 +- > 4 files changed, 14 insertions(+), 20 deletions(-) > > diff --git a/src/gallium/targets/dri/Android.mk > b/src/gallium/targets/dri/Android.mk > index 10b27a80ef3e..da462ac1230d 100644 > --- a/src/gallium/targets/dri/Android.mk > +++ b/src/gallium/targets/dri/Android.mk > @@ -44,11 +44,9 @@ LOCAL_SHARED_LIBRARIES := \ > libglapi \ > libz > > -# If Android version >=8 MESA should static link libexpat else should > dynamic link > -ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) > -LOCAL_STATIC_LIBRARIES := \ > - libexpat > -else > +# If Android version <8 MESA should dynamic link libexpat > +# version >= 8 would use altxmlconfig instead > +ifneq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) > LOCAL_SHARED_LIBRARIES += \ > libexpat > endif > diff --git a/src/mesa/drivers/dri/Android.mk b/src/mesa/drivers/dri/Android.mk > index 60c8476a38a7..eefcb2475c6b 100644 > --- a/src/mesa/drivers/dri/Android.mk > +++ b/src/mesa/drivers/dri/Android.mk > @@ -53,13 +53,11 @@ MESA_DRI_SHARED_LIBRARIES := \ > liblog \ > libz > > -# If Android version >=8 MESA should static link libexpat else should > dynamic link > -ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) > -MESA_DRI_WHOLE_STATIC_LIBRARIES += \ > - libexpat > -else > -MESA_DRI_SHARED_LIBRARIES += \ > - libexpat > +# If Android version <8 MESA should dynamic link libexpat > +# version >= 8 would use altxmlconfig instead > +ifneq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) > +LOCAL_SHARED_LIBRARIES += \ > +libexpat > endif > > #--- > diff --git a/src/util/Android.mk b/src/util/Android.mk > index 6d770ca95756..c8cfdae91e6a 100644 > --- a/src/util/Android.mk > +++ b/src/util/Android.mk > @@ -41,13 +41,11 @@ LOCAL_C_INCLUDES := \ > $(MESA_TOP)/src/gallium/include \ > $(MESA_TOP)/src/gallium/auxiliary > > -# If Android version >=8 MESA should static link libexpat else should > dynamic link > -ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) > -LOCAL_STATIC_LIBRARIES := \ > - libexpat > -else > -LOCAL_SHARED_LIBRARIES := \ > - libexpat > +# If Android version <8 MESA should dynamic link libexpat > +# version >= 8 would use altxmlconfig instead > +ifneq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) > +LOCAL_SHARED_LIBRARIES += \ > +libexpat > endif > > LOCAL_MODULE := libmesa_util > diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources > index ad8c56d3d1b7..617cc272d340 100644 > --- a/src/util/Makefile.sources > +++ b/src/util/Makefile.sources > @@ -88,5 +88,5 @@ MESA_UTIL_GENERATED_FILES = \ > format_srgb.c > > XMLCONFIG_FILES := \ > - xmlconfig.c \ > + altxmlconfig.c \ > xmlconfig.h Even though we've deleted autotools, scons still uses the Makefile.sources, have you run a scons build on Linux to make sure that things are still working correctly? Dylan signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2 1/2] nir: Add is_divergent_vector search helper
Oh, forgot to amend the message itself, thank you :) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] swrast: Rename blend_func->swrast_blend_func
Thank you. I'm so sorry for the inconvenience... I've learned my CI lesson ;) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] swrast: Rename blend_func->swrast_blend_func
On Fri, May 10, 2019 at 09:25:06AM -0700, Caio Marcelo de Oliveira Filho wrote:
> On Fri, May 10, 2019 at 04:22:05PM +, Alyssa Rosenzweig wrote:
> > This avoids a conflict with the new (driver-agnostic) blend_func enum in
> > shader_enum.h, which broke the build of swrast (and i965 by extension).
> >
> > My apologies :(
> >
> > Signed-off-by: Alyssa Rosenzweig
> > Fixes: f41be53a ("compiler: Add enums for blend state")
> > Cc: Caio Marcelo de Oliveira Filho
> > ---
>
> Reviewed-by: Caio Marcelo de Oliveira Filho
Pushed!
Caio
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Re: [Mesa-dev] [PATCH] swrast: Rename blend_func->swrast_blend_func
On Fri, May 10, 2019 at 04:22:05PM +, Alyssa Rosenzweig wrote:
> This avoids a conflict with the new (driver-agnostic) blend_func enum in
> shader_enum.h, which broke the build of swrast (and i965 by extension).
>
> My apologies :(
>
> Signed-off-by: Alyssa Rosenzweig
> Fixes: f41be53a ("compiler: Add enums for blend state")
> Cc: Caio Marcelo de Oliveira Filho
> ---
Reviewed-by: Caio Marcelo de Oliveira Filho
Caio
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Re: [Mesa-dev] [PATCH v2 1/2] nir: Add is_divergent_vector search helper
Perhaps change the subject?
On Fri, May 10, 2019 at 12:08 PM Alyssa Rosenzweig wrote:
>
> This allows algebraic optimizations to check if the argument accesses
> multiple distinct components of a vector. So a swizzle like "xyz" will
> return true, but "yyy" will return false, as will a scalar. This can be
> useful for optimizations on vector processors, where a convergent
> swizzle can be done in one clock (replicating as if a scalar) but a
> divergent one must be scalarized. In these cases, it is useful to
> optimize differently based on whether the swizzle diverges. (Use case is
> the "csel" condition on Midgard).
I might rephrase it as
"""
csel on Midgard requires a scalar condition, so add a function to
enable lowering csel for cases where the condition is non-scalar.
"""
Your call. (But either way, get rid of the divergent/convergent references.)
>
> Signed-off-by: Alyssa Rosenzweig
> Cc: Jason Ekstrand
> Cc: Ilia Mirkin
> ---
> src/compiler/nir/nir_search_helpers.h | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/src/compiler/nir/nir_search_helpers.h
> b/src/compiler/nir/nir_search_helpers.h
> index 1624508993d..8e26739a3ce 100644
> --- a/src/compiler/nir/nir_search_helpers.h
> +++ b/src/compiler/nir/nir_search_helpers.h
> @@ -143,6 +143,23 @@ is_not_const(nir_alu_instr *instr, unsigned src, UNUSED
> unsigned num_components,
> return !nir_src_is_const(instr->src[src].src);
> }
>
> +/* I.e. the vector's swizzle actually accesses multiple channels. True for
> + * xyzw, false for , false for w */
> +
> +static inline bool
> +is_non_scalar_swizzle(nir_alu_instr *instr, UNUSED unsigned src,
> + unsigned num_components, const uint8_t *swizzle)
> +{
> + unsigned first_component = swizzle[0];
> +
> + for (unsigned i = 1; i < num_components; ++i) {
> + if (swizzle[i] != first_component)
> + return true;
> + }
> +
> + return false;
> +}
> +
> static inline bool
> is_used_more_than_once(nir_alu_instr *instr)
> {
> --
> 2.20.1
>
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[Mesa-dev] [PATCH] swrast: Rename blend_func->swrast_blend_func
This avoids a conflict with the new (driver-agnostic) blend_func enum in
shader_enum.h, which broke the build of swrast (and i965 by extension).
My apologies :(
Signed-off-by: Alyssa Rosenzweig
Fixes: f41be53a ("compiler: Add enums for blend state")
Cc: Caio Marcelo de Oliveira Filho
---
src/mesa/swrast/s_context.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/swrast/s_context.h b/src/mesa/swrast/s_context.h
index 49c30a3de3b..dd700183c88 100644
--- a/src/mesa/swrast/s_context.h
+++ b/src/mesa/swrast/s_context.h
@@ -57,10 +57,10 @@ typedef void (*texture_sample_func)(struct gl_context *ctx,
GLuint n, const GLfloat texcoords[][4],
const GLfloat lambda[], GLfloat rgba[][4]);
-typedef void (*blend_func)(struct gl_context *ctx, GLuint n,
- const GLubyte mask[],
- GLvoid *src, const GLvoid *dst,
- GLenum chanType);
+typedef void (*swrast_blend_func)(struct gl_context *ctx, GLuint n,
+ const GLubyte mask[],
+ GLvoid *src, const GLvoid *dst,
+ GLenum chanType);
typedef void (*swrast_point_func)( struct gl_context *ctx, const SWvertex *);
@@ -310,7 +310,7 @@ typedef struct
/** Internal hooks, kept up to date by the same mechanism as above.
*/
- blend_func BlendFunc;
+ swrast_blend_func BlendFunc;
texture_sample_func TextureSample[MAX_COMBINED_TEXTURE_IMAGE_UNITS];
/** Buffer for saving the sampled texture colors.
--
2.20.1
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[Mesa-dev] [PATCH v2 2/2] panfrost/midgard: Cleanup csel lowering
Signed-off-by: Alyssa Rosenzweig
---
.../panfrost/midgard/midgard_compile.c| 151 +++---
.../panfrost/midgard/midgard_nir_algebraic.py | 12 +-
2 files changed, 37 insertions(+), 126 deletions(-)
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 25316cab053..4ed36c53dfc 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -715,58 +715,6 @@ midgard_nir_lower_fdot2_body(nir_builder *b, nir_alu_instr
*alu)
nir_ssa_def_rewrite_uses(>dest.dest.ssa, nir_src_for_ssa(sum));
}
-/* Lower csel with mixed condition channels to mulitple csel instructions. For
- * context, the csel ops on Midgard are vector in *outputs*, but not in
- * *conditions*. So, if the condition is e.g. , a single op can select a
- * vec4. But if the condition is e.g. xyzw, four ops are needed as the ISA
- * can't cope with the divergent channels.*/
-
-static void
-midgard_nir_lower_mixed_csel_body(nir_builder *b, nir_alu_instr *alu)
-{
-if (alu->op != nir_op_bcsel)
-return;
-
-b->cursor = nir_before_instr(>instr);
-
-/* Must be run before registering */
-assert(alu->dest.dest.is_ssa);
-
-/* Check for mixed condition */
-
-unsigned comp = alu->src[0].swizzle[0];
-unsigned nr_components = alu->dest.dest.ssa.num_components;
-
-bool mixed = false;
-
-for (unsigned c = 1; c < nr_components; ++c)
-mixed |= (alu->src[0].swizzle[c] != comp);
-
-if (!mixed)
-return;
-
-/* We're mixed, so lower */
-
-assert(nr_components <= 4);
-nir_ssa_def *results[4];
-
-nir_ssa_def *cond = nir_ssa_for_alu_src(b, alu, 0);
-nir_ssa_def *choice0 = nir_ssa_for_alu_src(b, alu, 1);
-nir_ssa_def *choice1 = nir_ssa_for_alu_src(b, alu, 2);
-
-for (unsigned c = 0; c < nr_components; ++c) {
-results[c] = nir_bcsel(b,
-nir_channel(b, cond, c),
-nir_channel(b, choice0, c),
-nir_channel(b, choice1, c));
-}
-
-/* Replace with our scalarized version */
-
-nir_ssa_def *result = nir_vec(b, results, nr_components);
-nir_ssa_def_rewrite_uses(>dest.dest.ssa, nir_src_for_ssa(result));
-}
-
static int
midgard_nir_sysval_for_intrinsic(nir_intrinsic_instr *instr)
{
@@ -851,36 +799,6 @@ midgard_nir_lower_fdot2(nir_shader *shader)
return progress;
}
-static bool
-midgard_nir_lower_mixed_csel(nir_shader *shader)
-{
-bool progress = false;
-
-nir_foreach_function(function, shader) {
-if (!function->impl) continue;
-
-nir_builder _b;
-nir_builder *b = &_b;
-nir_builder_init(b, function->impl);
-
-nir_foreach_block(block, function->impl) {
-nir_foreach_instr_safe(instr, block) {
-if (instr->type != nir_instr_type_alu)
continue;
-
-nir_alu_instr *alu = nir_instr_as_alu(instr);
-midgard_nir_lower_mixed_csel_body(b, alu);
-
-progress |= true;
-}
-}
-
-nir_metadata_preserve(function->impl, nir_metadata_block_index
| nir_metadata_dominance);
-
-}
-
-return progress;
-}
-
static void
optimise_nir(nir_shader *nir)
{
@@ -892,7 +810,6 @@ optimise_nir(nir_shader *nir)
NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
NIR_PASS(progress, nir, midgard_nir_lower_fdot2);
-NIR_PASS(progress, nir, midgard_nir_lower_mixed_csel);
nir_lower_tex_options lower_tex_options = {
.lower_rect = true
@@ -957,6 +874,11 @@ optimise_nir(nir_shader *nir)
} while (progress);
NIR_PASS(progress, nir, nir_opt_algebraic_late);
+
+/* We implement booleans as 32-bit 0/~0 */
+NIR_PASS(progress, nir, nir_lower_bool_to_int32);
+
+/* Now that booleans are lowered, we can run out late opts */
NIR_PASS(progress, nir, midgard_nir_lower_algebraic_late);
/* Lower mods for float ops only. Integer ops don't support modifiers
@@ -967,9 +889,6 @@ optimise_nir(nir_shader *nir)
NIR_PASS(progress, nir, nir_copy_prop);
NIR_PASS(progress, nir, nir_opt_dce);
-/* We implement booleans as 32-bit 0/~0 */
-NIR_PASS(progress, nir, nir_lower_bool_to_int32);
-
/* Take us out of SSA */
NIR_PASS(progress, nir, nir_lower_locals_to_regs);
NIR_PASS(progress, nir, nir_convert_from_ssa, true);
@@ -1189,7 +1108,6 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
case nir_op_##nir: \
op =
[Mesa-dev] [PATCH v2 1/2] nir: Add is_divergent_vector search helper
This allows algebraic optimizations to check if the argument accesses
multiple distinct components of a vector. So a swizzle like "xyz" will
return true, but "yyy" will return false, as will a scalar. This can be
useful for optimizations on vector processors, where a convergent
swizzle can be done in one clock (replicating as if a scalar) but a
divergent one must be scalarized. In these cases, it is useful to
optimize differently based on whether the swizzle diverges. (Use case is
the "csel" condition on Midgard).
Signed-off-by: Alyssa Rosenzweig
Cc: Jason Ekstrand
Cc: Ilia Mirkin
---
src/compiler/nir/nir_search_helpers.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/compiler/nir/nir_search_helpers.h
b/src/compiler/nir/nir_search_helpers.h
index 1624508993d..8e26739a3ce 100644
--- a/src/compiler/nir/nir_search_helpers.h
+++ b/src/compiler/nir/nir_search_helpers.h
@@ -143,6 +143,23 @@ is_not_const(nir_alu_instr *instr, unsigned src, UNUSED
unsigned num_components,
return !nir_src_is_const(instr->src[src].src);
}
+/* I.e. the vector's swizzle actually accesses multiple channels. True for
+ * xyzw, false for , false for w */
+
+static inline bool
+is_non_scalar_swizzle(nir_alu_instr *instr, UNUSED unsigned src,
+ unsigned num_components, const uint8_t *swizzle)
+{
+ unsigned first_component = swizzle[0];
+
+ for (unsigned i = 1; i < num_components; ++i) {
+ if (swizzle[i] != first_component)
+ return true;
+ }
+
+ return false;
+}
+
static inline bool
is_used_more_than_once(nir_alu_instr *instr)
{
--
2.20.1
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Re: [Mesa-dev] [RFC PATCH 03/17] eir: add live ranges pass
On Fri, May 10, 2019 at 5:47 AM Connor Abbott wrote:
>
> On Fri, May 10, 2019 at 11:09 AM Christian Gmeiner
> wrote:
> >
> > Signed-off-by: Christian Gmeiner
> > ---
> > src/etnaviv/compiler/eir.h| 3 +
> > src/etnaviv/compiler/eir_live_variables.c | 258 ++
> > src/etnaviv/compiler/meson.build | 1 +
> > .../compiler/tests/eir_live_variables.cpp | 162 +++
> > src/etnaviv/compiler/tests/meson.build| 11 +
> > 5 files changed, 435 insertions(+)
> > create mode 100644 src/etnaviv/compiler/eir_live_variables.c
> > create mode 100644 src/etnaviv/compiler/tests/eir_live_variables.cpp
> >
> > diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
> > index a05b12de94b..38c6af4e07e 100644
> > --- a/src/etnaviv/compiler/eir.h
> > +++ b/src/etnaviv/compiler/eir.h
> > @@ -151,6 +151,9 @@ struct eir
> > /* keep track of number of allocated uniforms */
> > struct util_dynarray uniform_alloc;
> > unsigned uniform_offset;
> > +
> > + /* Live ranges of temp registers */
> > + int *temp_start, *temp_end;
>
> This way of representing liveness, and then using a coloring register
> allocator, is a common anti-pattern in Mesa, that was initially copied
> from i965 which dates back to before we knew any better. I really
> don't want to see it spread to yet another driver :(.
>
> Representing live ranges like this is imprecise. If I have a program like
> this:
>
> foo = ...
> if (...) {
>bar = ...
>... = bar; /* last use of "bar" */
> }
> ... = foo;
>
> Then it will say that foo and bar interfere, even when they don't.
>
> Now, this approximation does make things a bit simpler. But, it turns
> out that if you're willing to make it, then the interference graph is
> trivially colorable via a simple linear-time algorithm. This is the
> basis of "linear-scan" register allocators, including the one in LLVM.
> If you want to go down this route, you can, but this hybrid is just
> useless as it gives you the worst of both worlds.
>
> If you want to properly build up the interference graph, it's actually
> not that hard. After doing the inter-basic-block liveness analysis,
> for each block, you initialize a bitset to the live-out bitset. Then
> you walk the block backwards, updating it at each instruction exactly
> as in liveness analysis, so that it always represents the live
> registers before each instruction. Then you add interferences between
> all of the live registers and the register(s) defined at the
> instruction.
>
> One last pitfall I'll mention is that in the real world, you'll also
> need to use reachability. If you have something like
>
> if (...)
>foo = ... /* only definition of "foo" */
>
> ... = foo;
>
> where foo is only partially defined, then the liveness of foo will
> "leak" through the if. To fix this you need to consider what's called
> "reachability," i.e. something is only live if, in addition to
> potentially being used sometime later, it is reachable (potentially
> defined sometime earlier). Reachability analysis is exactly like
> liveness analysis, but everything is backwards. i965 does this
> properly nowadays, and the change had a huge effect on spilling/RA.
One more word on the reachability thing... watch out for code like
while() {
use(foo);
if ()
foo = bar;
more code that doesn't use foo
}
In SSA, this becomes like
foo1 = undef
while() {
foo = phi(foo1, foo2)
use(foo)
if ()
foo2 = bar
more code that doesn't use foo2
}
And so you have to extend the live range of foo2 until the end of the
loop. This becomes even more fun with various nested control flow
scenarios. (I haven't reviewed whether this series handles this sort
of thing appropriately, but Connor's comment reminded me of it.)
-ilia
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Re: [Mesa-dev] [RFC PATCH 03/17] eir: add live ranges pass
On Fri, May 10, 2019 at 11:47 AM Connor Abbott wrote:
>
>
> This way of representing liveness, and then using a coloring register
> allocator, is a common anti-pattern in Mesa, that was initially copied
> from i965 which dates back to before we knew any better. I really
> don't want to see it spread to yet another driver :(.
>
> Representing live ranges like this is imprecise. If I have a program like
> this:
>
> foo = ...
> if (...) {
>bar = ...
>... = bar; /* last use of "bar" */
> }
> ... = foo;
Whoops, that should actually read:
foo = ...
if (...) {
bar = ...
... = bar; /* last use of "bar" */
} else {
... = foo;
}
>
> Then it will say that foo and bar interfere, even when they don't.
>
> Now, this approximation does make things a bit simpler. But, it turns
> out that if you're willing to make it, then the interference graph is
> trivially colorable via a simple linear-time algorithm. This is the
> basis of "linear-scan" register allocators, including the one in LLVM.
> If you want to go down this route, you can, but this hybrid is just
> useless as it gives you the worst of both worlds.
>
> If you want to properly build up the interference graph, it's actually
> not that hard. After doing the inter-basic-block liveness analysis,
> for each block, you initialize a bitset to the live-out bitset. Then
> you walk the block backwards, updating it at each instruction exactly
> as in liveness analysis, so that it always represents the live
> registers before each instruction. Then you add interferences between
> all of the live registers and the register(s) defined at the
> instruction.
>
> One last pitfall I'll mention is that in the real world, you'll also
> need to use reachability. If you have something like
>
> if (...)
>foo = ... /* only definition of "foo" */
>
> ... = foo;
>
> where foo is only partially defined, then the liveness of foo will
> "leak" through the if. To fix this you need to consider what's called
> "reachability," i.e. something is only live if, in addition to
> potentially being used sometime later, it is reachable (potentially
> defined sometime earlier). Reachability analysis is exactly like
> liveness analysis, but everything is backwards. i965 does this
> properly nowadays, and the change had a huge effect on spilling/RA.
>
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[Mesa-dev] [Bug 110345] Unrecoverable GPU crash with DiRT 4
https://bugs.freedesktop.org/show_bug.cgi?id=110345 --- Comment #22 from Samuel Pitoiset --- Created attachment 144219 --> https://bugs.freedesktop.org/attachment.cgi?id=144219=edit force wd switch on eop Does the attached patch help? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 110345] Unrecoverable GPU crash with DiRT 4
https://bugs.freedesktop.org/show_bug.cgi?id=110345 --- Comment #21 from Samuel Pitoiset --- Can you attach the output of "RADV_DEBUG=info vulkaninfo" please? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 109822] Texture holes in simple vulkan examples.
https://bugs.freedesktop.org/show_bug.cgi?id=109822 Samuel Pitoiset changed: What|Removed |Added Status|NEEDINFO|RESOLVED Resolution|--- |NOTOURBUG --- Comment #5 from Samuel Pitoiset --- Closing, feel free to re-open if your issue still happens after fixing the build and after checking with Vulkan validation layers. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 109599] small shadows are not drawn in various games (shadow map bias issue?)
https://bugs.freedesktop.org/show_bug.cgi?id=109599 Samuel Pitoiset changed: What|Removed |Added Resolution|--- |NOTABUG Status|NEW |RESOLVED --- Comment #29 from Samuel Pitoiset --- No because it's not a bug. Per the Vulkan spec "26.11.3. Depth Bias": "depthBiasSlopeFactor scales the maximum depth slope of the polygon, and depthBiasConstantFactor scales an implementation-dependent constant that relates to the usable resolution of the depth buffer." and, "The minimum resolvable difference r is an implementation-dependent parameter that depends on the depth buffer representation." That means, it might render differently based on that implementation-dependent parameter. Note that it likely renders something different with NVIDIA as well. Closing as we can't do anything. Thanks for the report! -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [RFC PATCH 03/17] eir: add live ranges pass
On Fri, May 10, 2019 at 11:09 AM Christian Gmeiner
wrote:
>
> Signed-off-by: Christian Gmeiner
> ---
> src/etnaviv/compiler/eir.h| 3 +
> src/etnaviv/compiler/eir_live_variables.c | 258 ++
> src/etnaviv/compiler/meson.build | 1 +
> .../compiler/tests/eir_live_variables.cpp | 162 +++
> src/etnaviv/compiler/tests/meson.build| 11 +
> 5 files changed, 435 insertions(+)
> create mode 100644 src/etnaviv/compiler/eir_live_variables.c
> create mode 100644 src/etnaviv/compiler/tests/eir_live_variables.cpp
>
> diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
> index a05b12de94b..38c6af4e07e 100644
> --- a/src/etnaviv/compiler/eir.h
> +++ b/src/etnaviv/compiler/eir.h
> @@ -151,6 +151,9 @@ struct eir
> /* keep track of number of allocated uniforms */
> struct util_dynarray uniform_alloc;
> unsigned uniform_offset;
> +
> + /* Live ranges of temp registers */
> + int *temp_start, *temp_end;
This way of representing liveness, and then using a coloring register
allocator, is a common anti-pattern in Mesa, that was initially copied
from i965 which dates back to before we knew any better. I really
don't want to see it spread to yet another driver :(.
Representing live ranges like this is imprecise. If I have a program like this:
foo = ...
if (...) {
bar = ...
... = bar; /* last use of "bar" */
}
... = foo;
Then it will say that foo and bar interfere, even when they don't.
Now, this approximation does make things a bit simpler. But, it turns
out that if you're willing to make it, then the interference graph is
trivially colorable via a simple linear-time algorithm. This is the
basis of "linear-scan" register allocators, including the one in LLVM.
If you want to go down this route, you can, but this hybrid is just
useless as it gives you the worst of both worlds.
If you want to properly build up the interference graph, it's actually
not that hard. After doing the inter-basic-block liveness analysis,
for each block, you initialize a bitset to the live-out bitset. Then
you walk the block backwards, updating it at each instruction exactly
as in liveness analysis, so that it always represents the live
registers before each instruction. Then you add interferences between
all of the live registers and the register(s) defined at the
instruction.
One last pitfall I'll mention is that in the real world, you'll also
need to use reachability. If you have something like
if (...)
foo = ... /* only definition of "foo" */
... = foo;
where foo is only partially defined, then the liveness of foo will
"leak" through the if. To fix this you need to consider what's called
"reachability," i.e. something is only live if, in addition to
potentially being used sometime later, it is reachable (potentially
defined sometime earlier). Reachability analysis is exactly like
liveness analysis, but everything is backwards. i965 does this
properly nowadays, and the change had a huge effect on spilling/RA.
> };
>
> struct eir_info {
> diff --git a/src/etnaviv/compiler/eir_live_variables.c
> b/src/etnaviv/compiler/eir_live_variables.c
> new file mode 100644
> index 000..fe94e7a2a3d
> --- /dev/null
> +++ b/src/etnaviv/compiler/eir_live_variables.c
> @@ -0,0 +1,258 @@
> +/*
> + * Copyright (c) 2018 Etnaviv Project
> + * Copyright (C) 2018 Zodiac Inflight Innovations
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sub license,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *Christian Gmeiner
> + */
> +
> +#include "eir.h"
> +#include "util/bitset.h"
> +#include "util/ralloc.h"
> +#include "util/u_math.h"
> +
> +#define MAX_INSTRUCTION (1 << 30)
> +
> +struct block_data {
> + BITSET_WORD *def;
> + BITSET_WORD *use;
> + BITSET_WORD *livein;
> + BITSET_WORD *liveout;
> + int start_ip, end_ip;
> +};
> +
> +/* Returns the variable index
[Mesa-dev] [RFC PATCH 00/17] An other look at nir
There has been interest in NIR support for etnaviv for a while, for the obvious reasons: gaining access to common optimizations, better support for non-trivial code transformations, better register allocation, and the promise of OpenCL and SPIR-V support in the future. This time I give it a try with a completly different architecture compared to the one pengutronix has choosen. - https://patchwork.freedesktop.org/series/44282/ My main goal was to have all the needed tools like assembler, disasm, linker and ofc the compiler living outside of the gallium driver. This opens the door for easier testing of the different components and - if somebody dreams loud - vulkan. I have choosen to go with an own backend ir called: *drumroll* eir It is a basic block based one with some nice to haves. I have studied every backend-compiler mesa have and have choosen the (best) parts from them. eir provides stuff like: - legalization - optimizations - register allocator - unit tests Why I have not choosen to do it directly in nir? Not that easy to answer but nir is a really fast moving target and nobody can tell where the road goes. nir might translate well enought to hw ISA now but maybe in the situation gets harder with newer GPUs and some core nir changes. For instance, at the moment on thing that might need worked around is the fact that nir can't represent (jump_if x CND y). ISA wise there are some improvements possible like on GC3000 it is possible to provide immediate values inline for source arguments for other instructions than control flow instructions. Oh before I forget it - this RFC is based on top of: "etnaviv: add low level ISA library" - https://gitlab.freedesktop.org/mesa/mesa/merge_requests/848 I am sending out this RFC to get feedback on the design I have choosen. I am not sure how the future nir based compiler infrastrucutre will look like but I am hoping for the best. Keep in mind that the nir compiler does something but most of the time the wrong thing. I only target GC2000 for the moment as it is still my main dev gpu. Weeks ago I have started to track deqp and piglit problems and to address them - so dont even try to use it. The last thing I want to say - lot of you might know that I am working on this thing for a while now and never had any ready-to-send patches, but I have a good explanation. - nir is moving really fast and it takes time to sync my downstream with upstream. - I only hack/work on etnaviv one day a week. - Cleaning up the git history after a long hack day (with refactorings etc.) takes time. - It takes time to upstream nir changes if you need to respin it. - I spend some of my etnaviv time with other topic like linear texturing support, etc2 texture patching, some other RE stuff and ofc I try my best to review other patches in the area of etnaviv. So it comes down to my limted time and the big architectural changes I have done with unit tests and real shader compiles on the targets. At the moment I am not sure how to move on form this point. Thanks PS: You can find this changes here too https://github.com/austriancoder/mesa/commits/eir-v3 Christian Gmeiner (17): etnaviv: add basic block based backend ir: eir eir: add legalization eir: add live ranges pass eir: add virtual register classes eir: implement actual register allocator eir: add nir optimization loop eir: add eir_print(..) eir: add nir compiler and all its infrastructure etnaviv: become independed of the used compiler backend etnaviv: hook-up eir into gallium driver etnaviv: add eir_compiler etnaviv: add debug option to report NIR as supported and preferred shader IR etnaviv: enable nir paths eir: add nir alu to scalar lowering pass eir: make use of eir_nir_lower_alu_to_scalar(..) eir: add optimization 'framework' eir: add peephole optimization src/etnaviv/compiler/eir.c| 239 src/etnaviv/compiler/eir.h| 523 + src/etnaviv/compiler/eir_compiler.c | 61 + src/etnaviv/compiler/eir_compiler.h | 70 ++ src/etnaviv/compiler/eir_compiler_nir.c | 1041 + src/etnaviv/compiler/eir_legalize.c | 177 +++ src/etnaviv/compiler/eir_live_variables.c | 258 src/etnaviv/compiler/eir_nir.c| 133 +++ src/etnaviv/compiler/eir_nir.h| 43 + .../compiler/eir_nir_lower_alu_to_scalar.c| 131 +++ src/etnaviv/compiler/eir_opt_peephole.c | 63 + src/etnaviv/compiler/eir_optimize.c | 50 + src/etnaviv/compiler/eir_optimize.h | 36 + src/etnaviv/compiler/eir_print.c | 222 src/etnaviv/compiler/eir_register_allocate.c | 353 ++ src/etnaviv/compiler/eir_shader.c | 312 + src/etnaviv/compiler/eir_shader.h | 203 src/etnaviv/compiler/eir_uniform.c| 108 ++ src/etnaviv/compiler/meson.build | 52 +
[Mesa-dev] [RFC PATCH 08/17] eir: add nir compiler and all its infrastructure
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir_compiler.c | 61 ++
src/etnaviv/compiler/eir_compiler.h | 29 +
src/etnaviv/compiler/eir_compiler_nir.c | 1035 +++
src/etnaviv/compiler/eir_shader.c | 312 +++
src/etnaviv/compiler/eir_shader.h | 203 +
src/etnaviv/compiler/meson.build|4 +
6 files changed, 1644 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_compiler.c
create mode 100644 src/etnaviv/compiler/eir_compiler_nir.c
create mode 100644 src/etnaviv/compiler/eir_shader.c
create mode 100644 src/etnaviv/compiler/eir_shader.h
diff --git a/src/etnaviv/compiler/eir_compiler.c
b/src/etnaviv/compiler/eir_compiler.c
new file mode 100644
index 000..386dcd0b0bc
--- /dev/null
+++ b/src/etnaviv/compiler/eir_compiler.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir.h"
+#include "eir_compiler.h"
+#include "util/ralloc.h"
+#include "util/u_debug.h"
+
+static const struct debug_named_value shader_debug_options[] = {
+ {"disasm", EIR_DBG_DISASM, "Dump NIR and etnaviv shader disassembly"},
+ {"optmsgs", EIR_DBG_OPTMSGS,"Enable optimizer debug messages"},
+ DEBUG_NAMED_VALUE_END
+};
+
+DEBUG_GET_ONCE_FLAGS_OPTION(eir_compiler_debug, "EIR_COMPILER_DEBUG",
shader_debug_options, 0)
+
+enum eir_compiler_debug eir_compiler_debug = 0;
+
+struct eir_compiler *
+eir_compiler_create(void)
+{
+ struct eir_compiler *compiler = rzalloc(NULL, struct eir_compiler);
+
+ if (!compiler)
+ return NULL;
+
+ eir_compiler_debug = debug_get_option_eir_compiler_debug();
+ compiler->set = eir_ra_alloc_reg_set(compiler);
+
+ return compiler;
+}
+
+void
+eir_compiler_free(const struct eir_compiler *compiler)
+{
+ ralloc_free((void *)compiler);
+}
diff --git a/src/etnaviv/compiler/eir_compiler.h
b/src/etnaviv/compiler/eir_compiler.h
index 5c5412e4773..645ee6a0db2 100644
--- a/src/etnaviv/compiler/eir_compiler.h
+++ b/src/etnaviv/compiler/eir_compiler.h
@@ -28,7 +28,21 @@
#ifndef H_EIR_COMPILER
#define H_EIR_COMPILER
+#include
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
struct eir_ra_reg_set;
+struct eir_shader_variant;
+
+enum eir_compiler_debug {
+ EIR_DBG_DISASM = (1 << 0),
+ EIR_DBG_OPTMSGS = (1 << 1),
+};
+
+extern enum eir_compiler_debug eir_compiler_debug;
/**
* Compiler state saved across compiler invocations, for any expensive global
@@ -36,6 +50,21 @@ struct eir_ra_reg_set;
*/
struct eir_compiler {
struct eir_ra_reg_set *set;
+ uint32_t shader_count;
};
+struct eir_compiler *
+eir_compiler_create(void);
+
+void
+eir_compiler_free(const struct eir_compiler *compiler);
+
+int
+eir_compile_shader_nir(struct eir_compiler *compiler,
+ struct eir_shader_variant *v);
+
+#ifdef __cplusplus
+}
+#endif
+
#endif // H_EIR_COMPILER
diff --git a/src/etnaviv/compiler/eir_compiler_nir.c
b/src/etnaviv/compiler/eir_compiler_nir.c
new file mode 100644
index 000..862f34390e0
--- /dev/null
+++ b/src/etnaviv/compiler/eir_compiler_nir.c
@@ -0,0 +1,1035 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or
[Mesa-dev] [RFC PATCH 15/17] eir: make use of eir_nir_lower_alu_to_scalar(..)
Signed-off-by: Christian Gmeiner --- src/etnaviv/compiler/eir_nir.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/etnaviv/compiler/eir_nir.c b/src/etnaviv/compiler/eir_nir.c index 6e75f2c5fd8..a579037a667 100644 --- a/src/etnaviv/compiler/eir_nir.c +++ b/src/etnaviv/compiler/eir_nir.c @@ -102,6 +102,8 @@ eir_optimize_nir(struct nir_shader *s) OPT_V(s, nir_lower_global_vars_to_local); OPT_V(s, nir_lower_regs_to_ssa); + OPT_V(s, eir_nir_lower_alu_to_scalar); + OPT_V(s, nir_opt_algebraic); eir_optimize_loop(s); -- 2.21.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC PATCH 07/17] eir: add eir_print(..)
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.h | 3 +
src/etnaviv/compiler/eir_print.c | 222 +++
src/etnaviv/compiler/meson.build | 1 +
3 files changed, 226 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_print.c
diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
index bbde10cde08..1b67edab559 100644
--- a/src/etnaviv/compiler/eir.h
+++ b/src/etnaviv/compiler/eir.h
@@ -309,6 +309,9 @@ eir_ra_alloc_reg_set(void *memctx);
bool
eir_register_allocate(struct eir *ir, gl_shader_stage type, struct
eir_compiler *compiler);
+void
+eir_print(struct eir *ir);
+
uint32_t *
eir_assemble(const struct eir *ir, struct eir_info *info);
diff --git a/src/etnaviv/compiler/eir_print.c b/src/etnaviv/compiler/eir_print.c
new file mode 100644
index 000..e4e11d5de19
--- /dev/null
+++ b/src/etnaviv/compiler/eir_print.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include
+
+#include "eir.h"
+#include "etnaviv/gc/gc_disasm.h"
+
+static void
+tab(struct gc_string *string, const unsigned lvl)
+{
+ for (unsigned i = 0; i < lvl; i++)
+ gc_string_append(string, "\t");
+}
+
+static void
+print_a(struct gc_string *string, const struct eir *ir, unsigned ip, bool
start)
+{
+ const int num = util_dynarray_num_elements(>reg_alloc, unsigned);
+ const int num_components = num * 4;
+ int *data;
+
+ if (start)
+ data = ir->temp_start;
+ else
+ data = ir->temp_end;
+
+ for (int i = 0; i < num_components; i = i + 4) {
+ unsigned comp = 0;
+
+ for (int j = 0; j < 4; j++)
+ if (data[i + j] == ip)
+comp |= 1 << j;
+
+ if (comp == 0)
+ continue;
+
+ if (start)
+ gc_string_append(string, "S%4d", i / 4);
+ else
+ gc_string_append(string, "E%4d", i / 4);
+
+ gc_decode_components(string, comp);
+ gc_string_append(string, " ");
+ }
+
+ gc_string_append(string, "");
+}
+
+static void
+print_live_ranges(struct gc_string *string, const struct eir *ir,
+ unsigned ip)
+{
+ print_a(string, ir, ip, true);
+ print_a(string, ir, ip, false);
+}
+
+static void
+print_register(struct gc_string *string, const struct eir_register *reg)
+{
+ switch (reg->type) {
+ case EIR_REG_TEMP:
+ gc_string_append(string, "t%d", reg->index);
+ break;
+ case EIR_REG_UNIFORM:
+ gc_string_append(string, "u%d", reg->index);
+ break;
+ case EIR_REG_UNDEF:
+ unreachable("undef??");
+ break;
+ default:
+ unreachable("oops");
+ break;
+ }
+}
+
+static void
+print_dst(struct gc_string *string, const struct eir_register *reg)
+{
+ print_register(string, reg);
+ gc_decode_components(string, reg->writemask);
+ gc_string_append(string, " ");
+}
+
+static void
+print_src(struct gc_string *string, const struct eir_register *reg)
+{
+ if (reg->abs)
+ gc_string_append(string, "|");
+
+ print_register(string, reg);
+ gc_decode_swiz(string, reg->swizzle);
+
+ if (reg->abs)
+ gc_string_append(string, "|");
+
+ gc_string_append(string, " ");
+}
+
+static void
+print_alu(struct gc_string *string, struct eir_instruction *inst)
+{
+ for (unsigned i = 0; i < gc_op_num_src(inst->gc.opcode); i++)
+ print_src(string, >src[i]);
+}
+
+static void
+print_branch(struct gc_string *string, struct eir_instruction *inst)
+{
+ print_src(string, >src[0]);
+ print_src(string, >src[1]);
+ gc_string_append(string, "block %u", inst->block->successors[0]->num);
+}
+
+static void
+print_sampler(struct gc_string *string, struct eir_instruction *inst)
+{
+ const struct eir_register *tex = >src[0];
+
+ gc_string_append(string, "tex%u", tex->index);
+
[Mesa-dev] [RFC PATCH 01/17] etnaviv: add basic block based backend ir: eir
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.c | 239 ++
src/etnaviv/compiler/eir.h | 499
src/etnaviv/compiler/eir_uniform.c | 108 +
src/etnaviv/compiler/meson.build| 38 ++
src/etnaviv/compiler/tests/eir_assemble.cpp | 114 +
src/etnaviv/compiler/tests/eir_uniform.cpp | 324 +
src/etnaviv/compiler/tests/meson.build | 44 ++
src/etnaviv/meson.build | 1 +
8 files changed, 1367 insertions(+)
create mode 100644 src/etnaviv/compiler/eir.c
create mode 100644 src/etnaviv/compiler/eir.h
create mode 100644 src/etnaviv/compiler/eir_uniform.c
create mode 100644 src/etnaviv/compiler/meson.build
create mode 100644 src/etnaviv/compiler/tests/eir_assemble.cpp
create mode 100644 src/etnaviv/compiler/tests/eir_uniform.cpp
create mode 100644 src/etnaviv/compiler/tests/meson.build
diff --git a/src/etnaviv/compiler/eir.c b/src/etnaviv/compiler/eir.c
new file mode 100644
index 000..398ae7443c5
--- /dev/null
+++ b/src/etnaviv/compiler/eir.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir.h"
+#include
+#include
+#include "util/ralloc.h"
+
+struct eir *
+eir_create(void)
+{
+ struct eir *ir = rzalloc(NULL, struct eir);
+
+ list_inithead(>block_list);
+ util_dynarray_init(>reg_alloc, ir);
+ util_dynarray_init(>uniform_alloc, ir);
+
+ return ir;
+}
+
+void
+eir_destroy(struct eir *ir)
+{
+ assert(ir);
+ util_dynarray_fini(>reg_alloc);
+ util_dynarray_fini(>uniform_alloc);
+ ralloc_free(ir);
+}
+
+struct eir_block *
+eir_block_create(struct eir *ir)
+{
+ assert(ir);
+ struct eir_block *block = rzalloc(ir, struct eir_block);
+
+ block->ir = ir;
+ block->num = ir->blocks++;
+ list_inithead(>node);
+ list_inithead(>instr_list);
+
+ list_addtail(>node, >block_list);
+
+ return block;
+}
+
+struct eir_instruction *
+eir_instruction_create(struct eir_block *block, enum gc_op opc)
+{
+ assert(block);
+ struct eir_instruction *instr = rzalloc(block, struct eir_instruction);
+
+ instr->block = block;
+ list_addtail(>node, >instr_list);
+
+ instr->gc.opcode = opc;
+
+ return instr;
+}
+
+struct eir_register
+eir_temp_register(struct eir *ir, unsigned num_components)
+{
+ assert(num_components >= 1 && num_components <= 4);
+
+ struct eir_register reg = {
+ .type = EIR_REG_TEMP,
+ .index = util_dynarray_num_elements(>reg_alloc, unsigned),
+ };
+
+ util_dynarray_append(>reg_alloc, unsigned, num_components);
+
+ return reg;
+}
+
+void
+eir_link_blocks(struct eir_block *predecessor, struct eir_block *successor)
+{
+ assert(predecessor);
+ assert(successor);
+
+ if (predecessor->successors[0]) {
+ assert(!predecessor->successors[1]);
+ predecessor->successors[1] = successor;
+ } else {
+ predecessor->successors[0] = successor;
+ }
+}
+
+static void
+convert_sampler(const struct eir_register *eir, struct gc_instr_sampler
*sampler)
+{
+ assert(eir->type == EIR_REG_SAMPLER);
+
+ sampler->id = eir->index;
+ sampler->swiz = eir->swizzle;
+ sampler->amode = GC_ADDRESSING_MODE_DIRECT;
+}
+
+static void
+convert_src(const struct eir_register *eir, struct gc_instr_src *gc)
+{
+ assert(!gc->use);
+ assert(eir->type != EIR_REG_UNDEF);
+ assert(eir->type != EIR_REG_SAMPLER);
+
+ gc->use = true;
+ gc->reg = eir->index;
+ gc->abs = eir->abs;
+ gc->neg = eir->neg;
+ gc->swiz = eir->swizzle;
+
+ switch (eir->type) {
+ case EIR_REG_TEMP:
+ gc->rgroup = GC_REGISTER_GROUP_TEMP;
+ break;
+
+ case EIR_REG_UNIFORM:
+ gc->rgroup = GC_REGISTER_GROUP_UNIFORM;
+ break;
+
+ default:
+ unreachable("unhandled type");
+ }
[Mesa-dev] [RFC PATCH 03/17] eir: add live ranges pass
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.h| 3 +
src/etnaviv/compiler/eir_live_variables.c | 258 ++
src/etnaviv/compiler/meson.build | 1 +
.../compiler/tests/eir_live_variables.cpp | 162 +++
src/etnaviv/compiler/tests/meson.build| 11 +
5 files changed, 435 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_live_variables.c
create mode 100644 src/etnaviv/compiler/tests/eir_live_variables.cpp
diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
index a05b12de94b..38c6af4e07e 100644
--- a/src/etnaviv/compiler/eir.h
+++ b/src/etnaviv/compiler/eir.h
@@ -151,6 +151,9 @@ struct eir
/* keep track of number of allocated uniforms */
struct util_dynarray uniform_alloc;
unsigned uniform_offset;
+
+ /* Live ranges of temp registers */
+ int *temp_start, *temp_end;
};
struct eir_info {
diff --git a/src/etnaviv/compiler/eir_live_variables.c
b/src/etnaviv/compiler/eir_live_variables.c
new file mode 100644
index 000..fe94e7a2a3d
--- /dev/null
+++ b/src/etnaviv/compiler/eir_live_variables.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir.h"
+#include "util/bitset.h"
+#include "util/ralloc.h"
+#include "util/u_math.h"
+
+#define MAX_INSTRUCTION (1 << 30)
+
+struct block_data {
+ BITSET_WORD *def;
+ BITSET_WORD *use;
+ BITSET_WORD *livein;
+ BITSET_WORD *liveout;
+ int start_ip, end_ip;
+};
+
+/* Returns the variable index for the c-th component of register reg. */
+static inline unsigned
+var_from_reg(unsigned reg, unsigned c)
+{
+ assert(c < 4);
+ return (reg * 4) + c;
+}
+
+static void
+setup_use(struct eir_block *block, const struct eir_register *src, int ip)
+{
+ const struct eir *ir = block->ir;
+ struct block_data *bd = block->data;
+
+ if (src->type != EIR_REG_TEMP)
+ return;
+
+ /* The use[] bitset marks when the block makes
+* use of a variable without having completely
+* defined that variable within the block.
+*/
+
+ const unsigned swiz_comp[4] = {
+ /* x */ src->swizzle & 0x3,
+ /* y */ (src->swizzle & 0x0C) >> 2,
+ /* z */ (src->swizzle & 0x30) >> 4,
+ /* w */ (src->swizzle & 0xc0) >> 6,
+ };
+
+ for (unsigned c = 0; c < 4; c++) {
+ const unsigned var = var_from_reg(src->index, swiz_comp[c]);
+
+ ir->temp_start[var] = MIN2(ir->temp_start[var], ip);
+ ir->temp_end[var] = ip;
+
+ if (!BITSET_TEST(bd->def, var))
+ BITSET_SET(bd->use, var);
+ }
+}
+
+static inline void
+setup_def(struct eir_block *block, const struct eir_register *dst, int ip)
+{
+ const struct eir *ir = block->ir;
+ struct block_data *bd = block->data;
+
+ for (unsigned c = 0; c < 4; c++) {
+ if (dst->writemask & (1 << c)) {
+ const unsigned var = var_from_reg(dst->index, c);
+
+ ir->temp_start[var] = MIN2(ir->temp_start[var], ip);
+ ir->temp_end[var] = ip;
+
+ BITSET_SET(bd->def, var);
+ }
+ }
+}
+
+static void
+setup_def_use(struct eir *ir)
+{
+ int ip = 0;
+
+ eir_for_each_block(block, ir) {
+ struct block_data *bd = block->data;
+ bd->start_ip = ip;
+
+ eir_for_each_inst(instr, block) {
+ const struct gc_instr *gc = >gc;
+
+ for (unsigned i = 0; i < gc_op_num_src(gc->opcode); i++)
+setup_use(block, >src[i], ip);
+
+ if (gc_op_has_dst(gc->opcode))
+setup_def(block, >dst, ip);
+
+ ip++;
+ }
+ bd->end_ip = ip;
+ }
+}
+
+static bool
+compute_live_variables(struct eir *ir, unsigned bitset_words)
+{
+ bool progress = false;
+
+ eir_for_each_block_rev(block, ir) {
+ struct block_data *bd = block->data;
+
+ /* update
[Mesa-dev] [RFC PATCH 06/17] eir: add nir optimization loop
This change adds the eir_optimize_nir(..) function which gets used
to optimize and transform a nir shader for our needs.
Besides this there are some other nir helpers for compiler options
and tgsi handling.
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir_nir.c | 131 +++
src/etnaviv/compiler/eir_nir.h | 40 ++
src/etnaviv/compiler/meson.build | 2 +
3 files changed, 173 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_nir.c
create mode 100644 src/etnaviv/compiler/eir_nir.h
diff --git a/src/etnaviv/compiler/eir_nir.c b/src/etnaviv/compiler/eir_nir.c
new file mode 100644
index 000..6e75f2c5fd8
--- /dev/null
+++ b/src/etnaviv/compiler/eir_nir.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir_nir.h"
+#include "compiler/nir/nir.h"
+
+static const nir_shader_compiler_options options = {
+ .lower_all_io_to_temps = true,
+ .fdot_replicates = true,
+ .fuse_ffma = true,
+ .lower_sub = true,
+ .lower_fpow = true,
+ .lower_flrp32 = true,
+ .lower_ftrunc = true,
+ .max_unroll_iterations = 32
+};
+
+const struct nir_shader_compiler_options *
+eir_get_compiler_options(void)
+{
+ return
+}
+
+#define OPT(nir, pass, ...) ({ \
+ bool this_progress = false; \
+ NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
+ this_progress; \
+})
+
+#define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
+
+static void
+eir_optimize_loop(struct nir_shader *s)
+{
+ bool progress;
+ do {
+ progress = false;
+
+ OPT_V(s, nir_lower_vars_to_ssa);
+ progress |= OPT(s, nir_opt_copy_prop_vars);
+ progress |= OPT(s, nir_copy_prop);
+ progress |= OPT(s, nir_opt_dce);
+ progress |= OPT(s, nir_opt_cse);
+ progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
+ progress |= OPT(s, nir_opt_intrinsics);
+ progress |= OPT(s, nir_opt_algebraic);
+ progress |= OPT(s, nir_opt_constant_folding);
+ progress |= OPT(s, nir_opt_dead_cf);
+ if (OPT(s, nir_opt_trivial_continues)) {
+ progress |= true;
+ /* If nir_opt_trivial_continues makes progress, then we need to clean
+ * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
+ * to make progress.
+ */
+ OPT(s, nir_copy_prop);
+ OPT(s, nir_opt_dce);
+ }
+ progress |= OPT(s, nir_opt_if, false);
+
+ if (s->options->max_unroll_iterations)
+ progress |= OPT(s, nir_opt_loop_unroll, 0);
+
+ progress |= OPT(s, nir_opt_remove_phis);
+ progress |= OPT(s, nir_opt_undef);
+
+ } while (progress);
+}
+
+struct nir_shader *
+eir_optimize_nir(struct nir_shader *s)
+{
+ struct nir_lower_tex_options tex_options = {
+ .lower_txp = ~0,
+ .lower_rect = true,
+ };
+
+ OPT_V(s, nir_lower_tex, _options);
+ OPT_V(s, nir_lower_global_vars_to_local);
+ OPT_V(s, nir_lower_regs_to_ssa);
+
+ OPT_V(s, nir_opt_algebraic);
+
+ eir_optimize_loop(s);
+
+ OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
+
+ OPT_V(s, nir_opt_algebraic_late);
+
+ OPT_V(s, nir_lower_to_source_mods, nir_lower_all_source_mods);
+ OPT_V(s, nir_copy_prop);
+ OPT_V(s, nir_opt_dce);
+ OPT_V(s, nir_opt_move_comparisons);
+
+ OPT_V(s, nir_lower_bool_to_float);
+ OPT_V(s, nir_lower_int_to_float);
+ OPT_V(s, nir_lower_locals_to_regs);
+ OPT_V(s, nir_convert_from_ssa, true);
+ OPT_V(s, nir_move_vec_src_uses_to_dest);
+ OPT_V(s, nir_lower_vec_to_movs);
+
+ /* TODO: nir_lower_vec_to_movs can generate imov's */
+ OPT_V(s, nir_lower_bool_to_float);
+
+ nir_sweep(s);
+
+ return s;
+}
diff
[Mesa-dev] [RFC PATCH 11/17] etnaviv: add eir_compiler
Signed-off-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/eir_cmdline.c | 189 ++
src/gallium/drivers/etnaviv/meson.build | 20 +++
2 files changed, 209 insertions(+)
create mode 100644 src/gallium/drivers/etnaviv/eir_cmdline.c
diff --git a/src/gallium/drivers/etnaviv/eir_cmdline.c
b/src/gallium/drivers/etnaviv/eir_cmdline.c
new file mode 100644
index 000..f888a649050
--- /dev/null
+++ b/src/gallium/drivers/etnaviv/eir_cmdline.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2017 Etnaviv Project
+ * Copyright (C) 2017 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Rob Clark
+ *Christian Gmeiner
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "main/mtypes.h"
+
+#include "compiler/eir_compiler.h"
+#include "compiler/eir_nir.h"
+#include "compiler/eir_shader.h"
+#include "compiler/glsl/standalone.h"
+#include "compiler/glsl/glsl_to_nir.h"
+
+#include "etnaviv_eir.h"
+
+#include "tgsi/tgsi_parse.h"
+#include "tgsi/tgsi_text.h"
+
+#include "util/u_debug.h"
+
+int st_glsl_type_size(const struct glsl_type *type);
+
+static nir_shader *
+load_glsl(const char *filename, gl_shader_stage stage)
+{
+ static const struct standalone_options options = {
+ .glsl_version = 120,
+ .do_link = true,
+ };
+ static struct gl_context local_ctx;
+ struct gl_shader_program *prog;
+
+ prog = standalone_compile_shader(, 1, (char * const*),
_ctx);
+ if (!prog)
+ errx(1, "couldn't parse `%s'", filename);
+
+ nir_shader *nir = glsl_to_nir(_ctx, prog, stage,
eir_get_compiler_options());
+
+ standalone_compiler_cleanup(prog);
+
+ return nir;
+}
+
+static int
+read_file(const char *filename, void **ptr, size_t *size)
+{
+ int fd, ret;
+ struct stat st;
+
+ *ptr = MAP_FAILED;
+
+ fd = open(filename, O_RDONLY);
+ if (fd == -1) {
+ warnx("couldn't open `%s'", filename);
+ return 1;
+ }
+
+ ret = fstat(fd, );
+ if (ret)
+ errx(1, "couldn't stat `%s'", filename);
+
+ *size = st.st_size;
+ *ptr = mmap(NULL, st.st_size, PROT_READ, MAP_SHARED, fd, 0);
+ if (*ptr == MAP_FAILED)
+ errx(1, "couldn't map `%s'", filename);
+
+ close(fd);
+
+ return 0;
+}
+
+static void
+print_usage(void)
+{
+ printf("Usage: etnaviv_compiler [OPTIONS]... \n");
+ printf("--verbose - verbose compiler/debug messages\n");
+ printf("--frag-rb-swap- swap rb in color output (FRAG)\n");
+ printf("--help- show this message\n");
+}
+
+int main(int argc, char **argv)
+{
+ int ret, n = 1;
+ const char *filename;
+ struct eir_shader_key key = {};
+ void *ptr;
+ size_t size;
+ bool verbose = false;
+
+ while (n < argc) {
+ if (!strcmp(argv[n], "--verbose")) {
+ verbose = true;
+ n++;
+ continue;
+ }
+
+ if (!strcmp(argv[n], "--frag-rb-swap")) {
+ debug_printf(" %s", argv[n]);
+ key.frag_rb_swap = true;
+ n++;
+ continue;
+ }
+
+ if (!strcmp(argv[n], "--help")) {
+ print_usage();
+ return 0;
+ }
+
+ break;
+ }
+
+ filename = argv[n];
+
+ ret = read_file(filename, , );
+ if (ret) {
+ print_usage();
+ return ret;
+ }
+
+ debug_printf("%s\n", (char *)ptr);
+ nir_shader *nir;
+ const char *ext = rindex(filename, '.');
+
+ if (strcmp(ext, ".tgsi") == 0) {
+ struct tgsi_token toks[65536];
+
+ if (!tgsi_text_translate(ptr, toks, ARRAY_SIZE(toks)))
+ errx(1, "could not parse `%s'", filename);
+
+ nir = eir_tgsi_to_nir(toks, NULL);
+ } else if (strcmp(ext, ".frag") == 0) {
+ nir = load_glsl(filename, MESA_SHADER_FRAGMENT);
+ } else if (strcmp(ext, ".vert") == 0) {
+ nir = load_glsl(filename, MESA_SHADER_VERTEX);
+ } else {
+ print_usage();
+ return -1;
[Mesa-dev] [RFC PATCH 17/17] eir: add peephole optimization
Some created shaders can contain instructions like:
mov t0 t0
This simple pass removes that kind of mov instructions.
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir_opt_peephole.c | 63 +
src/etnaviv/compiler/eir_optimize.c | 4 +-
src/etnaviv/compiler/eir_optimize.h | 5 ++
src/etnaviv/compiler/meson.build| 1 +
4 files changed, 72 insertions(+), 1 deletion(-)
create mode 100644 src/etnaviv/compiler/eir_opt_peephole.c
diff --git a/src/etnaviv/compiler/eir_opt_peephole.c
b/src/etnaviv/compiler/eir_opt_peephole.c
new file mode 100644
index 000..a8cf848d652
--- /dev/null
+++ b/src/etnaviv/compiler/eir_opt_peephole.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019 Etnaviv Project
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir.h"
+#include "eir_optimize.h"
+
+static bool
+eir_opt_peephole_impl(struct eir_instruction *instr)
+{
+ /* remove "mov t0 t0" as seen with bin/gl-2.0-vertex-attr-0 */
+
+ if (instr->gc.opcode != GC_MOV)
+ return false;
+
+ if (instr->src[0].index != instr->dst.index)
+ return false;
+
+ if (instr->dst.writemask != (INST_COMPS_X | INST_COMPS_Y | INST_COMPS_Z |
INST_COMPS_W))
+ return false;
+
+ if (instr->src[0].swizzle != INST_SWIZ_IDENTITY)
+ return false;
+
+ list_del(>node);
+
+ return true;
+}
+
+bool
+eir_opt_peephole(struct eir *ir)
+{
+ bool progress = false;
+
+ eir_for_each_block(block, ir)
+ eir_for_each_inst_safe(inst, block)
+ progress |= eir_opt_peephole_impl(inst);
+
+ return progress;
+}
diff --git a/src/etnaviv/compiler/eir_optimize.c
b/src/etnaviv/compiler/eir_optimize.c
index 6eae8e9c9ec..695ef76001a 100644
--- a/src/etnaviv/compiler/eir_optimize.c
+++ b/src/etnaviv/compiler/eir_optimize.c
@@ -44,5 +44,7 @@
void
eir_optimize(struct eir *ir)
{
- const bool print_opt_debug = true;
+ const bool print_opt_debug = false;
+
+ OPTPASS(eir_opt_peephole);
}
diff --git a/src/etnaviv/compiler/eir_optimize.h
b/src/etnaviv/compiler/eir_optimize.h
index b840a273c25..ecc9e44713c 100644
--- a/src/etnaviv/compiler/eir_optimize.h
+++ b/src/etnaviv/compiler/eir_optimize.h
@@ -28,4 +28,9 @@
#ifndef H_EIR_OPTIMIZE
#define H_EIR_OPTIMIZE
+struct eir;
+
+bool
+eir_opt_peephole(struct eir *ir);
+
#endif // H_EIR_OPTIMIZE
diff --git a/src/etnaviv/compiler/meson.build b/src/etnaviv/compiler/meson.build
index 8343e6b91ad..f43e868208a 100644
--- a/src/etnaviv/compiler/meson.build
+++ b/src/etnaviv/compiler/meson.build
@@ -31,6 +31,7 @@ libetnaviv_compiler_files = files(
'eir_nir_lower_alu_to_scalar.c',
'eir_nir.c',
'eir_nir.h',
+ 'eir_opt_peephole.c',
'eir_optimize.c',
'eir_print.c',
'eir_register_allocate.c',
--
2.21.0
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC PATCH 16/17] eir: add optimization 'framework'
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.h | 3 ++
src/etnaviv/compiler/eir_compiler_nir.c | 6
src/etnaviv/compiler/eir_optimize.c | 48 +
src/etnaviv/compiler/eir_optimize.h | 31
src/etnaviv/compiler/meson.build| 1 +
5 files changed, 89 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_optimize.c
create mode 100644 src/etnaviv/compiler/eir_optimize.h
diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
index 1b67edab559..f46d12b822a 100644
--- a/src/etnaviv/compiler/eir.h
+++ b/src/etnaviv/compiler/eir.h
@@ -294,6 +294,9 @@ eir_assign_output(struct eir *ir, unsigned idx, unsigned
slot, unsigned ncomp)
void
eir_legalize(struct eir *ir);
+void
+eir_optimize(struct eir *ir);
+
void
eir_calculate_live_intervals(struct eir *ir);
diff --git a/src/etnaviv/compiler/eir_compiler_nir.c
b/src/etnaviv/compiler/eir_compiler_nir.c
index 862f34390e0..4dbbd5e8f0a 100644
--- a/src/etnaviv/compiler/eir_compiler_nir.c
+++ b/src/etnaviv/compiler/eir_compiler_nir.c
@@ -991,6 +991,12 @@ eir_compile_shader_nir(struct eir_compiler *compiler,
eir_print(ctx->ir);
}
+ eir_optimize(ctx->ir);
+ if (eir_compiler_debug & EIR_DBG_OPTMSGS) {
+ printf("AFTER eir_optimize:\n");
+ eir_print(ctx->ir);
+ }
+
eir_legalize(ctx->ir);
if (eir_compiler_debug & EIR_DBG_OPTMSGS) {
printf("AFTER legalization:\n");
diff --git a/src/etnaviv/compiler/eir_optimize.c
b/src/etnaviv/compiler/eir_optimize.c
new file mode 100644
index 000..6eae8e9c9ec
--- /dev/null
+++ b/src/etnaviv/compiler/eir_optimize.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2019 Etnaviv Project
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir.h"
+#include "eir_optimize.h"
+#include
+
+#define OPTPASS(func) \
+ do { \
+ bool stage_progress = func(ir); \
+ if (stage_progress) {\
+if (print_opt_debug) {\
+ fprintf(stderr,\
+ "EIR opt pass %s progress\n", \
+ #func);\
+} \
+ }\
+ } while (0)
+
+void
+eir_optimize(struct eir *ir)
+{
+ const bool print_opt_debug = true;
+}
diff --git a/src/etnaviv/compiler/eir_optimize.h
b/src/etnaviv/compiler/eir_optimize.h
new file mode 100644
index 000..b840a273c25
--- /dev/null
+++ b/src/etnaviv/compiler/eir_optimize.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2019 Etnaviv Project
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
[Mesa-dev] [RFC PATCH 12/17] etnaviv: add debug option to report NIR as supported and preferred shader IR
Add a debug option ETNA_MESA_DEBUG="nir" that will cause the etnaviv
gallium pipe driver to advertise support and preference for NIR shaders.
Signed-off-by: Philipp Zabel
Signed-off-by: Michael Tretter
---
src/gallium/drivers/etnaviv/etnaviv_debug.h | 3 +++
src/gallium/drivers/etnaviv/etnaviv_screen.c | 11 +--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_debug.h
b/src/gallium/drivers/etnaviv/etnaviv_debug.h
index 4051e95dd5f..8dacf6b2433 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_debug.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_debug.h
@@ -54,6 +54,9 @@
#define ETNA_DBG_SHADERDB0x80 /* dump program compile information
*/
#define ETNA_DBG_NO_SINGLEBUF0x100 /* disable single buffer feature */
+/* Experimental features */
+#define ETNA_DBG_NIR 0x1000 /* Enable NIR compiler */
+
extern int etna_mesa_debug; /* set in etna_screen.c from ETNA_DEBUG */
#define DBG_ENABLED(flag) unlikely(etna_mesa_debug & (flag))
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 641ee80948c..3e151e75159 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -69,6 +69,7 @@ static const struct debug_named_value debug_options[] = {
{"cflush_all", ETNA_DBG_CFLUSH_ALL, "Flush every cache before state
update"},
{"msaa2x", ETNA_DBG_MSAA_2X, "Force 2x msaa"},
{"msaa4x", ETNA_DBG_MSAA_4X, "Force 4x msaa"},
+ {"nir",ETNA_DBG_NIR, "Enable experimental NIR compiler"},
{"flush_all", ETNA_DBG_FLUSH_ALL, "Flush after every rendered
primitive"},
{"zero", ETNA_DBG_ZERO, "Zero all resources after allocation"},
{"draw_stall", ETNA_DBG_DRAW_STALL, "Stall FE/PE after each rendered
primitive"},
@@ -486,7 +487,10 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
? screen->specs.fragment_sampler_count
: screen->specs.vertex_sampler_count;
case PIPE_SHADER_CAP_PREFERRED_IR:
- return PIPE_SHADER_IR_TGSI;
+ if (etna_mesa_debug & ETNA_DBG_NIR)
+ return PIPE_SHADER_IR_NIR;
+ else
+ return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 4096;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
@@ -496,7 +500,10 @@ etna_screen_get_shader_param(struct pipe_screen *pscreen,
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return false;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return 0;
+ if (etna_mesa_debug & ETNA_DBG_NIR)
+ return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR);
+ else
+ return (1 << PIPE_SHADER_IR_TGSI);
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
--
2.21.0
___
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[Mesa-dev] [RFC PATCH 14/17] eir: add nir alu to scalar lowering pass
Some operations are scalar and need special treatment. Those
are exp and log2.
dst := exp2(src2.x)
dst := log2(src2.x)
The result is broadcasted over all active destination components.
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir_nir.h| 3 +
.../compiler/eir_nir_lower_alu_to_scalar.c| 131 ++
src/etnaviv/compiler/meson.build | 1 +
3 files changed, 135 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_nir_lower_alu_to_scalar.c
diff --git a/src/etnaviv/compiler/eir_nir.h b/src/etnaviv/compiler/eir_nir.h
index 0ba5fa8e6a3..cd21cae38e4 100644
--- a/src/etnaviv/compiler/eir_nir.h
+++ b/src/etnaviv/compiler/eir_nir.h
@@ -37,4 +37,7 @@ eir_get_compiler_options(void);
struct nir_shader *
eir_optimize_nir(struct nir_shader *s);
+void
+eir_nir_lower_alu_to_scalar(struct nir_shader *shader);
+
#endif // H_EIR_NIR
diff --git a/src/etnaviv/compiler/eir_nir_lower_alu_to_scalar.c
b/src/etnaviv/compiler/eir_nir_lower_alu_to_scalar.c
new file mode 100644
index 000..8dc264d083f
--- /dev/null
+++ b/src/etnaviv/compiler/eir_nir_lower_alu_to_scalar.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2019 Etnaviv Project
+ * Copyright (C) 2019 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir_nir.h"
+#include "nir.h"
+#include "nir_builder.h"
+
+/** @file eir_nir_lower_to_scalar.c
+ *
+ * Replaces nir alu operations with individual per-channel operations.
+ */
+
+static void
+nir_alu_ssa_dest_init(nir_alu_instr *instr, unsigned num_components,
+ unsigned bit_size)
+{
+ nir_ssa_dest_init(>instr, >dest.dest, num_components,
+ bit_size, NULL);
+ instr->dest.write_mask = (1 << num_components) - 1;
+}
+
+static nir_ssa_def *
+replace(nir_builder *b, nir_alu_instr *instr)
+{
+ unsigned num_src = nir_op_infos[instr->op].num_inputs;
+ unsigned num_components = instr->dest.dest.ssa.num_components;
+ nir_ssa_def *comps[NIR_MAX_VEC_COMPONENTS] = { NULL };
+ unsigned i, chan;
+
+ for (chan = 0; chan < NIR_MAX_VEC_COMPONENTS; chan++) {
+ if (!(instr->dest.write_mask & (1 << chan)))
+ continue;
+
+ nir_alu_instr *lower = nir_alu_instr_create(b->shader, instr->op);
+ for (i = 0; i < num_src; i++) {
+ /* We only handle same-size-as-dest (input_sizes[] == 0) or scalar
+ * args (input_sizes[] == 1).
+ */
+ assert(nir_op_infos[instr->op].input_sizes[i] < 2);
+ unsigned src_chan = (nir_op_infos[instr->op].input_sizes[i] == 1 ?
+ 0 : chan);
+
+ nir_alu_src_copy(>src[i], >src[i], lower);
+ for (int j = 0; j < NIR_MAX_VEC_COMPONENTS; j++)
+lower->src[i].swizzle[j] = instr->src[i].swizzle[src_chan];
+ }
+
+ nir_alu_ssa_dest_init(lower, 1, instr->dest.dest.ssa.bit_size);
+ lower->dest.saturate = instr->dest.saturate;
+ comps[chan] = >dest.dest.ssa;
+ lower->exact = instr->exact;
+
+ nir_builder_instr_insert(b, >instr);
+ }
+
+ return nir_vec(b, comps, num_components);
+}
+
+static void
+lower_alu_to_scalar_impl(nir_function_impl *impl)
+{
+ bool progress = false;
+
+ nir_builder b;
+ nir_builder_init(, impl);
+
+ nir_foreach_block(block, impl) {
+ nir_foreach_instr_safe(instr, block) {
+ if (instr->type != nir_instr_type_alu)
+continue;
+
+ nir_alu_instr *alu_instr = nir_instr_as_alu(instr);
+ nir_ssa_def *vec;
+
+ b.cursor = nir_before_instr(instr);
+
+ switch (alu_instr->op) {
+ case nir_op_fexp2:
+/* fall-through */
+ case nir_op_flog2:
+vec = replace(, alu_instr);
+break;
+ default:
+continue;
+ }
+
+ nir_ssa_def_rewrite_uses(_instr->dest.dest.ssa,
[Mesa-dev] [RFC PATCH 13/17] etnaviv: enable nir paths
Signed-off-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/etnaviv_context.c | 23 ++--
src/gallium/drivers/etnaviv/etnaviv_shader.c | 55 +--
2 files changed, 68 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c
b/src/gallium/drivers/etnaviv/etnaviv_context.c
index d78d8941087..3b764f0111b 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -25,6 +25,8 @@
*Christian Gmeiner
*/
+#include "etnaviv_eir.h" /* TODO: fix problems with COMPARE_FUNC_NEVER */
+
#include "etnaviv_context.h"
#include "etnaviv_blend.h"
@@ -466,12 +468,21 @@ etna_context_create(struct pipe_screen *pscreen, void
*priv, unsigned flags)
etna_texture_init(pctx);
etna_transfer_init(pctx);
- ctx->uniform_dirty_flags = etna_uniform_dirty_flags;
- ctx->uniforms_write = etna_uniforms_write;
- ctx->uniforms_const_count = etna_uniforms_const_count;
- ctx->create_shader_variant = etna_shader_variant;
- ctx->shader_link = etna_shader_link;
- ctx->shader_update_vertex = etna_shader_update_vertex;
+ if (etna_mesa_debug & ETNA_DBG_NIR) {
+ ctx->uniform_dirty_flags = eir_uniform_dirty_flags;
+ ctx->uniforms_write = eir_uniforms_write;
+ ctx->uniforms_const_count = eir_uniforms_const_count;
+ ctx->create_shader_variant = eir_shader_variant;
+ ctx->shader_link = eir_link_shaders;
+ ctx->shader_update_vertex = eir_shader_update_vertex;
+ } else {
+ ctx->uniform_dirty_flags = etna_uniform_dirty_flags;
+ ctx->uniforms_write = etna_uniforms_write;
+ ctx->uniforms_const_count = etna_uniforms_const_count;
+ ctx->create_shader_variant = etna_shader_variant;
+ ctx->shader_link = etna_shader_link;
+ ctx->shader_update_vertex = etna_shader_update_vertex;
+ }
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_shader.c
b/src/gallium/drivers/etnaviv/etnaviv_shader.c
index 34c546c3c66..cec27dcb2f8 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_shader.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_shader.c
@@ -24,6 +24,7 @@
*Wladimir J. van der Laan
*/
+#include "etnaviv_eir.h"
#include "etnaviv_shader.h"
#include "etnaviv_compiler.h"
@@ -36,6 +37,44 @@
#include "util/u_math.h"
#include "util/u_memory.h"
+static struct eir_shader *
+create_shader_stateobj(struct pipe_context *pctx, const struct
pipe_shader_state *cso,
+ gl_shader_stage type)
+{
+ struct etna_context *ctx = etna_context(pctx);
+ struct eir_compiler *compiler = ctx->screen->compiler;
+
+ return eir_shader_create(compiler, cso, type, >debug, pctx->screen);
+}
+
+static void *
+etna_fs_state_create(struct pipe_context *pctx, const struct pipe_shader_state
*cso)
+{
+ return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
+}
+
+static void
+etna_fs_state_delete(struct pipe_context *pctx, void *hwcso)
+{
+ struct eir_shader *so = hwcso;
+
+ eir_shader_destroy(so);
+}
+
+static void *
+etna_vs_state_create(struct pipe_context *pctx, const struct pipe_shader_state
*cso)
+{
+ return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
+}
+
+static void
+etna_vs_state_delete(struct pipe_context *pctx, void *hwcso)
+{
+ struct eir_shader *so = hwcso;
+
+ eir_shader_destroy(so);
+}
+
/* Upload shader code to bo, if not already done */
static bool etna_icache_upload_shader(struct etna_context *ctx, struct
etna_shader_variant *v)
{
@@ -459,10 +498,18 @@ etna_bind_vs_state(struct pipe_context *pctx, void *hwcso)
void
etna_shader_init(struct pipe_context *pctx)
{
- pctx->create_fs_state = etna_create_shader_state;
+ if (etna_mesa_debug & ETNA_DBG_NIR) {
+ pctx->create_fs_state = etna_fs_state_create;
+ pctx->delete_fs_state = etna_fs_state_delete;
+ pctx->create_vs_state = etna_vs_state_create;
+ pctx->delete_vs_state = etna_vs_state_delete;
+ } else {
+ pctx->create_fs_state = etna_create_shader_state;
+ pctx->delete_fs_state = etna_delete_shader_state;
+ pctx->create_vs_state = etna_create_shader_state;
+ pctx->delete_vs_state = etna_delete_shader_state;
+ }
+
pctx->bind_fs_state = etna_bind_fs_state;
- pctx->delete_fs_state = etna_delete_shader_state;
- pctx->create_vs_state = etna_create_shader_state;
pctx->bind_vs_state = etna_bind_vs_state;
- pctx->delete_vs_state = etna_delete_shader_state;
}
--
2.21.0
___
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[Mesa-dev] [RFC PATCH 09/17] etnaviv: become independed of the used compiler backend
This change preps etnaviv to be able to swap the used compiler
backend easily. It takes care of uniform stuff and the actual
creation of shader variants. In the long run - if one backend
won - we can remove this again.
Signed-off-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/etnaviv_context.c | 16
src/gallium/drivers/etnaviv/etnaviv_context.h | 18 +-
src/gallium/drivers/etnaviv/etnaviv_emit.c| 16
src/gallium/drivers/etnaviv/etnaviv_shader.c | 5 +++--
src/gallium/drivers/etnaviv/etnaviv_shader.h | 4 ++--
src/gallium/drivers/etnaviv/etnaviv_state.c | 16 ++--
.../drivers/etnaviv/etnaviv_uniforms.c| 19 ++-
.../drivers/etnaviv/etnaviv_uniforms.h| 8 +++-
8 files changed, 81 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c
b/src/gallium/drivers/etnaviv/etnaviv_context.c
index a59338490b6..d78d8941087 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.c
@@ -44,6 +44,7 @@
#include "etnaviv_texture.h"
#include "etnaviv_transfer.h"
#include "etnaviv_translate.h"
+#include "etnaviv_uniforms.h"
#include "etnaviv_zsa.h"
#include "pipe/p_context.h"
@@ -119,9 +120,9 @@ etna_update_state_for_draw(struct etna_context *ctx, const
struct pipe_draw_info
static bool
etna_get_vs(struct etna_context *ctx, struct etna_shader_key key)
{
- const struct etna_shader_variant *old = ctx->shader.vs;
+ const void *old = ctx->shader.vs;
- ctx->shader.vs = etna_shader_variant(ctx->shader.bind_vs, key, >debug);
+ ctx->shader.vs = ctx->create_shader_variant(ctx->shader.bind_vs, key,
>debug);
if (!ctx->shader.vs)
return false;
@@ -135,9 +136,9 @@ etna_get_vs(struct etna_context *ctx, struct
etna_shader_key key)
static bool
etna_get_fs(struct etna_context *ctx, struct etna_shader_key key)
{
- const struct etna_shader_variant *old = ctx->shader.fs;
+ const void *old = ctx->shader.fs;
- ctx->shader.fs = etna_shader_variant(ctx->shader.bind_fs, key, >debug);
+ ctx->shader.fs = ctx->create_shader_variant(ctx->shader.bind_fs, key,
>debug);
if (!ctx->shader.fs)
return false;
@@ -465,6 +466,13 @@ etna_context_create(struct pipe_screen *pscreen, void
*priv, unsigned flags)
etna_texture_init(pctx);
etna_transfer_init(pctx);
+ ctx->uniform_dirty_flags = etna_uniform_dirty_flags;
+ ctx->uniforms_write = etna_uniforms_write;
+ ctx->uniforms_const_count = etna_uniforms_const_count;
+ ctx->create_shader_variant = etna_shader_variant;
+ ctx->shader_link = etna_shader_link;
+ ctx->shader_update_vertex = etna_shader_update_vertex;
+
ctx->blitter = util_blitter_create(pctx);
if (!ctx->blitter)
goto fail;
diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h
b/src/gallium/drivers/etnaviv/etnaviv_context.h
index a79d739100d..a20f3d6cf79 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_context.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_context.h
@@ -31,6 +31,7 @@
#include
#include "etnaviv_resource.h"
+#include "etnaviv_shader.h"
#include "etnaviv_tiling.h"
#include "indices/u_primconvert.h"
#include "pipe/p_context.h"
@@ -82,7 +83,7 @@ struct etna_vertexbuf_state {
struct etna_shader_state {
void *bind_vs, *bind_fs;
- struct etna_shader_variant *vs, *fs;
+ void *vs, *fs;
};
enum etna_immediate_contents {
@@ -191,6 +192,21 @@ struct etna_context {
struct etna_bo *dummy_rt;
struct etna_reloc dummy_rt_reloc;
+
+ /* abstraction to support different compilers backends */
+ uint32_t (*uniform_dirty_flags)(const void *sobj);
+ void (*uniforms_write)(const struct etna_context *ctx,
+ const void *sobj,
+ struct pipe_constant_buffer *cb,
+ uint32_t *uniforms,
+ unsigned *size);
+ uint32_t (*uniforms_const_count)(const void *sobj);
+
+ void *(*create_shader_variant)(void *shader,
+ struct etna_shader_key key,
+ struct pipe_debug_callback *debug);
+ bool (*shader_link)(struct etna_context *ctx);
+ bool (*shader_update_vertex)(struct etna_context *ctx);
};
static inline struct etna_context *
diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c
b/src/gallium/drivers/etnaviv/etnaviv_emit.c
index ed7b7ee3cb8..f6f2d83e607 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
@@ -105,8 +105,8 @@ required_stream_size(struct etna_context *ctx)
size += ctx->vertex_elements->num_elements + 1;
/* uniforms - worst case (2 words per uniform load) */
- size += ctx->shader.vs->uniforms.const_count * 2;
- size += ctx->shader.fs->uniforms.const_count * 2;
+ size += ctx->uniforms_const_count(ctx->shader.vs) * 2;
+ size += ctx->uniforms_const_count(ctx->shader.fs) * 2;
/*
[Mesa-dev] [RFC PATCH 02/17] eir: add legalization
- if shader is empty add a NOP instruction
- avoid multiple uniform src for alu ops
- resolve jump target
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.h | 3 +
src/etnaviv/compiler/eir_legalize.c | 177
src/etnaviv/compiler/meson.build| 1 +
src/etnaviv/compiler/tests/eir_legalize.cpp | 136 +++
src/etnaviv/compiler/tests/meson.build | 10 ++
5 files changed, 327 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_legalize.c
create mode 100644 src/etnaviv/compiler/tests/eir_legalize.cpp
diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
index e2185b004f1..a05b12de94b 100644
--- a/src/etnaviv/compiler/eir.h
+++ b/src/etnaviv/compiler/eir.h
@@ -282,6 +282,9 @@ eir_assign_output(struct eir *ir, unsigned idx, unsigned
slot, unsigned ncomp)
ir->num_outputs = MAX2(ir->num_outputs, idx + 1);
}
+void
+eir_legalize(struct eir *ir);
+
void
eir_calculate_live_intervals(struct eir *ir);
diff --git a/src/etnaviv/compiler/eir_legalize.c
b/src/etnaviv/compiler/eir_legalize.c
new file mode 100644
index 000..94f5c2bd12b
--- /dev/null
+++ b/src/etnaviv/compiler/eir_legalize.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "eir.h"
+#include "etnaviv/gc/gc_instr.h"
+
+static int
+invalid_uniform_usage(const struct eir_instruction *inst)
+{
+ const struct gc_instr *gc = >gc;
+ int invalid = 0;
+ bool first_uniform = true;
+ int index;
+
+ if (gc->type != GC_OP_TYPE_ALU)
+ return 0;
+
+ for (unsigned i = 0; i < gc_op_num_src(gc->opcode); i++) {
+ const struct eir_register *src = >src[i];
+
+ if (src->type != EIR_REG_UNIFORM)
+ continue;
+
+ if (first_uniform) {
+ index = src->index;
+ first_uniform = false;
+ continue;
+ }
+
+ if (src->index == index)
+ continue;
+
+ invalid |= 1 << i;
+ }
+
+ return invalid;
+}
+
+static void
+legalize_uniform_usage(struct eir_block *block, struct eir_instruction *inst)
+{
+ /*
+ * The hardware does not allow two or more different uniform registers to be
used as
+ * sources in the same ALU instruction. Emit mov instructions to temporary
registers
+ * for all but one uniform register in this case.
+ */
+ int mask = invalid_uniform_usage(inst);
+
+ while (mask) {
+ const int i = ffs(mask) - 1;
+ struct eir_register *src = >src[i];
+ struct eir_register tmp = eir_temp_register(block->ir, 4);
+
+ tmp.writemask = 0xf; /* TODO */
+
+ eir_MOV(block, , src);
+ src->type = EIR_REG_TEMP;
+ src->index = tmp.index;
+
+ mask &= ~(1 << i);
+ }
+}
+
+static void
+legalize_block(struct eir_block *block)
+{
+ struct list_head instr_list;
+
+ /*
+* Remove all the instructions from the list, we'll be adding
+* them back in as we go
+*/
+ list_replace(>instr_list, _list);
+ list_inithead(>instr_list);
+
+ list_for_each_entry_safe (struct eir_instruction, inst, _list, node) {
+ legalize_uniform_usage(block, inst);
+ list_addtail(>node, >instr_list);
+ }
+}
+
+struct block_data {
+ unsigned start_ip;
+ unsigned end_ip;
+};
+
+static void
+resolve_jumps(struct eir *ir)
+{
+ void *mem_ctx = ralloc_context(NULL);
+ unsigned ip = 0;
+ assert(mem_ctx);
+
+ eir_for_each_block(block, ir) {
+ struct block_data *bd = rzalloc(mem_ctx, struct block_data);
+
+ assert(bd);
+ assert(!block->data);
+ block->data = bd;
+
+ /* determine start and end IP for this block */
+ bd->start_ip = ip;
+ eir_for_each_inst(inst, block) {
+ ip++;
+ }
+ bd->end_ip = ip;
+ }
+
+ eir_for_each_block(block, ir) {
+ const
[Mesa-dev] [RFC PATCH 05/17] eir: implement actual register allocator
Some unit tests would be great.
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.h | 10 +-
src/etnaviv/compiler/eir_register_allocate.c | 176 ++-
2 files changed, 184 insertions(+), 2 deletions(-)
diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
index f2652863de6..bbde10cde08 100644
--- a/src/etnaviv/compiler/eir.h
+++ b/src/etnaviv/compiler/eir.h
@@ -29,6 +29,7 @@
#define H_EIR
#include
+#include "compiler/shader_enums.h"
#include "util/list.h"
#include "util/u_dynarray.h"
#include "util/u_math.h"
@@ -40,6 +41,7 @@ extern "C"{
struct eir;
struct eir_block;
+struct eir_compiler;
struct eir_ra_reg_set;
struct eir_register
@@ -149,10 +151,13 @@ struct eir
* and the used components per register */
struct util_dynarray reg_alloc;
- /* keep track of number of allocated uniforms */
+ /* keep track of number of allocated uniforms - pre RA */
struct util_dynarray uniform_alloc;
unsigned uniform_offset;
+ /* total used temp register - post RA */
+ unsigned num_temps;
+
/* Live ranges of temp registers */
int *temp_start, *temp_end;
};
@@ -301,6 +306,9 @@ eir_temp_range_end(const struct eir* ir, unsigned n);
struct eir_ra_reg_set *
eir_ra_alloc_reg_set(void *memctx);
+bool
+eir_register_allocate(struct eir *ir, gl_shader_stage type, struct
eir_compiler *compiler);
+
uint32_t *
eir_assemble(const struct eir *ir, struct eir_info *info);
diff --git a/src/etnaviv/compiler/eir_register_allocate.c
b/src/etnaviv/compiler/eir_register_allocate.c
index 332d686add9..e02fc37a5ef 100644
--- a/src/etnaviv/compiler/eir_register_allocate.c
+++ b/src/etnaviv/compiler/eir_register_allocate.c
@@ -164,7 +164,7 @@ eir_ra_alloc_reg_set(void *memctx)
}
}
- unsigned int **q_values = ralloc_array(set, unsigned *,
EIR_NUM_REG_CLASSES);
+ unsigned int **q_values = ralloc_array(set, unsigned *,
EIR_NUM_REG_CLASSES);
for (int i = 0; i < EIR_NUM_REG_CLASSES; i++) {
q_values[i] = rzalloc_array(q_values, unsigned, EIR_NUM_REG_CLASSES);
for (int j = 0; j < EIR_NUM_REG_CLASSES; j++)
@@ -177,3 +177,177 @@ eir_ra_alloc_reg_set(void *memctx)
return set;
}
+
+static bool
+interferes(const struct eir *ir, int a, int b)
+{
+ return !((eir_temp_range_end(ir, a) <= eir_temp_range_start(ir, b)) ||
+(eir_temp_range_end(ir, b) <= eir_temp_range_start(ir, a)));
+}
+
+static inline void
+reswizzle(struct eir_register *reg, int virt_reg)
+{
+ static const unsigned swizzle[EIR_NUM_REG_TYPES] = {
+ INST_SWIZ(0, 1, 2, 3), /* XYZW */
+ INST_SWIZ(0, 1, 2, 2), /* XYZ */
+ INST_SWIZ(0, 1, 3, 3), /* XYW */
+ INST_SWIZ(0, 2, 3, 3), /* XZW */
+ INST_SWIZ(1, 2, 3, 3), /* YZW */
+ INST_SWIZ(0, 1, 1, 1), /* XY */
+ INST_SWIZ(0, 2, 2, 2), /* XZ */
+ INST_SWIZ(0, 3, 3, 3), /* XW */
+ INST_SWIZ(1, 2, 2, 2), /* YZ */
+ INST_SWIZ(1, 3, 3, 3), /* YW */
+ INST_SWIZ(2, 3, 3, 3), /* ZW */
+ INST_SWIZ(0, 0, 0, 0), /* X */
+ INST_SWIZ(1, 1, 1 ,1), /* Y */
+ INST_SWIZ(2, 2, 2, 2), /* Z */
+ INST_SWIZ(3, 3, 3, 3), /* W */
+ };
+
+ const int type = eir_reg_get_type(virt_reg);
+ reg->swizzle = swizzle[type];
+}
+
+static unsigned inline
+result(struct ra_graph *g, unsigned reg)
+{
+ const int virt_reg = ra_get_node_reg(g, reg);
+
+ return etna_reg_get_base(virt_reg);
+}
+
+static void
+assign(struct eir_register *reg, struct ra_graph *g, unsigned *num_temps)
+{
+ if (reg->type != EIR_REG_TEMP)
+ return;
+
+ const int virt_reg = ra_get_node_reg(g, reg->index);
+
+ /*
+* convert virtual register back to hw register
+* and change swizzle if needed
+*/
+ reg->index = etna_reg_get_base(virt_reg);
+
+ if (eir_reg_get_type(virt_reg) != EIR_REG_CLASS_VEC4)
+ reswizzle(reg, virt_reg);
+
+ *num_temps = MAX2(*num_temps, reg->index + 1);
+}
+
+bool
+eir_register_allocate(struct eir *ir, gl_shader_stage type, struct
eir_compiler *compiler)
+{
+ int num = util_dynarray_num_elements(>reg_alloc, unsigned);
+
+ if (num == 0)
+ return true;
+
+ int frag_varying_pos = -1;
+
+ if (type == MESA_SHADER_FRAGMENT) {
+ for (unsigned i = 0; i < ir->num_inputs; i++) {
+ if (ir->inputs[i].slot == VARYING_SLOT_POS) {
+frag_varying_pos = i;
+break;
+ }
+ }
+
+ /* allocate one extra register for hardwired t0 register */
+ if (frag_varying_pos == -1) {
+ num++;
+ frag_varying_pos = num - 1;
+ }
+ }
+
+ struct ra_graph *g = ra_alloc_interference_graph(compiler->set->regs, num);
+ unsigned num_temps = 0;
+
+ assert(g);
+ assert(ir->temp_start);
+ assert(ir->temp_end);
+
+ unsigned i = 0;
+ util_dynarray_foreach(>reg_alloc, unsigned, num_components) {
+ switch (*num_components) {
+ case 1:
+ ra_set_node_class(g, i,
compiler->set->class[EIR_REG_CLASS_VIRT_SCALAR]);
+ break;
[Mesa-dev] [RFC PATCH 04/17] eir: add virtual register classes
Since all threads share a global temporary vec4 register file, it is
important to reduce temporary register use of shaders.
Using source swizzles and destination write mask of ALU operations we
can layer smaller virtual registers on top of the physical base
registers that overlap with their base register and partially with each
other:
++-+-+-+
|VEC4| VEC3 |VEC2 | SCALAR |
++-+-+-+
| X | X X X | X X X | X |
| Y | Y Y Y | Y Y Y | Y |
| Z | Z Z Z | Z Z Z | Z |
| W | W W W | W W W | W |
++-+-+-+
There are four possible virtual vec3 registers that leave the remaining
component usable as a scalar virtual register, six possible vec2
registers, and four possible scalar registers that only use a single
component.
Signed-off-by: Philipp Zabel
Signed-off-by: Michael Tretter
Signed-off-by: Christian Gmeiner
---
src/etnaviv/compiler/eir.h | 4 +
src/etnaviv/compiler/eir_compiler.h | 41 +
src/etnaviv/compiler/eir_register_allocate.c | 179 +++
src/etnaviv/compiler/meson.build | 2 +
4 files changed, 226 insertions(+)
create mode 100644 src/etnaviv/compiler/eir_compiler.h
create mode 100644 src/etnaviv/compiler/eir_register_allocate.c
diff --git a/src/etnaviv/compiler/eir.h b/src/etnaviv/compiler/eir.h
index 38c6af4e07e..f2652863de6 100644
--- a/src/etnaviv/compiler/eir.h
+++ b/src/etnaviv/compiler/eir.h
@@ -40,6 +40,7 @@ extern "C"{
struct eir;
struct eir_block;
+struct eir_ra_reg_set;
struct eir_register
{
@@ -297,6 +298,9 @@ eir_temp_range_start(const struct eir* ir, unsigned n);
int
eir_temp_range_end(const struct eir* ir, unsigned n);
+struct eir_ra_reg_set *
+eir_ra_alloc_reg_set(void *memctx);
+
uint32_t *
eir_assemble(const struct eir *ir, struct eir_info *info);
diff --git a/src/etnaviv/compiler/eir_compiler.h
b/src/etnaviv/compiler/eir_compiler.h
new file mode 100644
index 000..5c5412e4773
--- /dev/null
+++ b/src/etnaviv/compiler/eir_compiler.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#ifndef H_EIR_COMPILER
+#define H_EIR_COMPILER
+
+struct eir_ra_reg_set;
+
+/**
+ * Compiler state saved across compiler invocations, for any expensive global
+ * setup.
+ */
+struct eir_compiler {
+ struct eir_ra_reg_set *set;
+};
+
+#endif // H_EIR_COMPILER
diff --git a/src/etnaviv/compiler/eir_register_allocate.c
b/src/etnaviv/compiler/eir_register_allocate.c
new file mode 100644
index 000..332d686add9
--- /dev/null
+++ b/src/etnaviv/compiler/eir_register_allocate.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ *
[Mesa-dev] [RFC PATCH 10/17] etnaviv: hook-up eir into gallium driver
Signed-off-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/Makefile.sources | 2 +
src/gallium/drivers/etnaviv/etnaviv_eir.c| 454 +++
src/gallium/drivers/etnaviv/etnaviv_eir.h| 71 +++
src/gallium/drivers/etnaviv/etnaviv_screen.c | 15 +
src/gallium/drivers/etnaviv/etnaviv_screen.h | 2 +
src/gallium/drivers/etnaviv/meson.build | 8 +-
6 files changed, 549 insertions(+), 3 deletions(-)
create mode 100644 src/gallium/drivers/etnaviv/etnaviv_eir.c
create mode 100644 src/gallium/drivers/etnaviv/etnaviv_eir.h
diff --git a/src/gallium/drivers/etnaviv/Makefile.sources
b/src/gallium/drivers/etnaviv/Makefile.sources
index 01e7e49a38a..62e65fb6c5e 100644
--- a/src/gallium/drivers/etnaviv/Makefile.sources
+++ b/src/gallium/drivers/etnaviv/Makefile.sources
@@ -23,6 +23,8 @@ C_SOURCES := \
etnaviv_debug.h \
etnaviv_disasm.c \
etnaviv_disasm.h \
+ etnaviv_eir.c \
+ etnaviv_eir.h \
etnaviv_emit.c \
etnaviv_emit.h \
etnaviv_etc2.c \
diff --git a/src/gallium/drivers/etnaviv/etnaviv_eir.c
b/src/gallium/drivers/etnaviv/etnaviv_eir.c
new file mode 100644
index 000..6914f83f5fc
--- /dev/null
+++ b/src/gallium/drivers/etnaviv/etnaviv_eir.c
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) 2018 Etnaviv Project
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Christian Gmeiner
+ */
+
+#include "etnaviv_eir.h"
+
+#include "etnaviv_context.h"
+#include "etnaviv_debug.h"
+#include "etnaviv_util.h"
+#include "nir/tgsi_to_nir.h"
+#include "tgsi/tgsi_dump.h"
+#include "util/u_debug.h"
+#include "util/u_memory.h"
+#include "etnaviv/compiler/eir_compiler.h"
+#include "etnaviv/compiler/eir_nir.h"
+#include "etnaviv/compiler/eir_shader.h"
+#include "pipe/p_state.h"
+
+static void
+dump_shader_info(struct eir_shader_variant *v, struct pipe_debug_callback
*debug)
+{
+ if (!unlikely(etna_mesa_debug & ETNA_DBG_SHADERDB))
+ return;
+
+ pipe_debug_message(debug, SHADER_INFO, "\n"
+ "SHADER-DB: %s prog %d/%d: %u instructions %u temps\n"
+ "SHADER-DB: %s prog %d/%d: %u immediates %u consts\n"
+ "SHADER-DB: %s prog %d/%d: %u loops\n",
+ gl_shader_stage_name(v->shader->type),
+ v->shader->id, v->id,
+ v->info.sizedwords,
+ v->num_temps,
+ gl_shader_stage_name(v->shader->type),
+ v->shader->id, v->id,
+ util_dynarray_num_elements(>uniforms, struct eir_uniform_data),
+ v->const_size,
+ gl_shader_stage_name(v->shader->type),
+ v->shader->id, v->id,
+ v->num_loops);
+}
+
+struct eir_shader *
+eir_shader_create(struct eir_compiler *compiler,
+ const struct pipe_shader_state *cso,
+ gl_shader_stage type,
+ struct pipe_debug_callback *debug,
+ struct pipe_screen *screen)
+{
+ struct nir_shader *nir;
+
+ assert(compiler);
+
+ if (cso->type == PIPE_SHADER_IR_NIR) {
+ /* we take ownership of the reference */
+ nir = cso->ir.nir;
+ } else {
+ debug_assert(cso->type == PIPE_SHADER_IR_TGSI);
+
+ if (eir_compiler_debug & EIR_DBG_DISASM)
+ tgsi_dump(cso->tokens, 0);
+
+ nir = eir_tgsi_to_nir(cso->tokens, screen);
+ }
+
+ struct eir_shader *shader = eir_shader_from_nir(compiler, nir);
+
+ if (etna_mesa_debug & ETNA_DBG_SHADERDB) {
+ /* if shader-db run, create a standard variant immediately
+ * (as otherwise nothing will trigger the shader to be
+ * actually compiled)
+ */
+ static struct etna_shader_key key;
+ memset(, 0, sizeof(key));
+ eir_shader_variant(shader, key, debug);
+ }
+
+ return shader;
+}
+
+void *
+eir_shader_variant(void *s,
+ struct etna_shader_key key,
+ struct pipe_debug_callback *debug)
+{
+
[Mesa-dev] About EVOC 2019 project ideas
Hello Dear Sir, My name is Shubham Verma. I am a B tech 2nd-year I.T. student I would like to look into working with X.Org for the Endless Vacation of Code program 2019 this summer. I have just recently started learning and looking into the contributions that I can make to GitHub issues. As this is my first EVOC I wanted to know what other things I have to do to be part of an organization. I mentioned my interest and project on which I want to work on below, have a look at that and tell me what will be good for me. I want to work on the project of Mesa and OpenMAX under the guidance of yours and I want to know that which project of Mesa and OpenMAX in the idea list is not selected by any student . I would be grateful if you can tell me if there's anything else that I could do which would be appreciated. Any further guidance or inputs would certainly be of great help. Thank you! ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC 1/2] mesa: utils: provide alternate default config mechanism
Core mesa uses libexpat to parse default configuration information
stored as xml in header files. This potentially allows userspaces to
supply their own configuration information, without a need to rebuild.
However, for userspaces that don't want or need to allow external
configuration, libexpat adds an un-necessary dependency.
This patch provides an alternate, static configuration for the
current defaults parsed for mesa core. This is a simple lookup with
the same current internal API as src/util/xmlconfig.c.
Change-Id: I81cf3817c4a6856a4b156646cf585e0152f93e02
Signed-off-by: Sumit Semwal
---
src/util/altxmlconfig.c | 261
1 file changed, 261 insertions(+)
create mode 100644 src/util/altxmlconfig.c
diff --git a/src/util/altxmlconfig.c b/src/util/altxmlconfig.c
new file mode 100644
index ..418e5ba7408b
--- /dev/null
+++ b/src/util/altxmlconfig.c
@@ -0,0 +1,261 @@
+/*
+ * XML DRI configuration shim for libexpat independent xmlconfig
+ * Copyright (C) 2019 Sumit Semwal, Linaro Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * FELIX KUEHLING, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
+ * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+/**
+ * \file altxmlconfig.c
+ * \brief libexpat independent xml config shim layer, for userspaces that don't
+ * wish to use libexpat
+ * \author Sumit Semwal
+ */
+#include
+#include "xmlconfig.h"
+
+#define ALT_XML_MAX_OPTIONS 32
+/*
+ * For dri_util.c
+ */
+struct driOptionRange _iRange_0_3 = {
+ .start._int = 0,
+ .end._int = 3
+};
+
+struct driOptionRange _iRange_0_32 = {
+ .start._int = 0,
+ .end._int = 32
+};
+
+struct driOptionRange _iRange_0_1 = {
+ .start._int = 0,
+ .end._int = 1
+};
+
+struct driOptionRange _iRange_0_999 = {
+ .start._int = 0,
+ .end._int = 999
+};
+
+/*
+ * For src/gallium/auxiliary/pipe-loader/pipe_loader.c
+ */
+
+
+static struct driOptionInfo _info [ALT_XML_MAX_OPTIONS] = {
+ {"vblank_mode", DRI_ENUM, &_iRange_0_3, 1},
+ {"pp_celshade", DRI_ENUM, &_iRange_0_1, 1},
+ {"pp_nored", DRI_ENUM, &_iRange_0_1, 1},
+ {"pp_nogreen", DRI_ENUM, &_iRange_0_1, 1},
+ {"pp_noblue", DRI_ENUM, &_iRange_0_1, 1},
+ {"pp_jimenezmlaa", DRI_ENUM, &_iRange_0_32, 1},
+ {"pp_jimenezmlaa_color", DRI_ENUM, &_iRange_0_32, 1},
+ {"force_glsl_version", DRI_ENUM, &_iRange_0_999, 1},
+ {"mesa_glthread", DRI_BOOL, NULL, 0},
+ {"mesa_no_error", DRI_BOOL, NULL, 0},
+ {"glx_disable_ext_buffer_age", DRI_BOOL, NULL, 0},
+ {"glx_disable_oml_sync_control", DRI_BOOL, NULL, 0},
+ {"force_glsl_extensions_warn", DRI_BOOL, NULL, 0},
+ {"disable_glsl_line_continuations", DRI_BOOL, NULL, 0},
+ {"disable_blend_func_extended", DRI_BOOL, NULL, 0},
+ {"disable_shader_bit_encoding", DRI_BOOL, NULL, 0},
+ {"allow_glsl_extension_directive_midshader", DRI_BOOL, NULL, 0},
+ {"allow_glsl_builtin_variable_redeclaration", DRI_BOOL, NULL,
0},
+ {"allow_glsl_cross_stage_interpolation_mismatch", DRI_BOOL,
NULL, 0},
+ {"allow_higher_compat_version", DRI_BOOL, NULL, 0},
+ {"force_glsl_abs_sqrt", DRI_BOOL, NULL, 0},
+ {"glsl_correct_derivatives_after_discard", DRI_BOOL, NULL, 0},
+ {"always_have_depth_buffer", DRI_BOOL, NULL, 0},
+ {"glsl_zero_init", DRI_BOOL, NULL, 0},
+ {"allow_rgb10_configs", DRI_BOOL, NULL, 0},
+ {"device_id", DRI_STRING, NULL, 0 },
+ {"allow_glsl_layout_qualifier_on_function_parameters",
DRI_BOOL, NULL, 0},
+ {"allow_glsl_builtin_const_expression", DRI_BOOL, NULL, 0},
+ {"allow_glsl_relaxed_es", DRI_BOOL, NULL, 0},
+ {"force_compat_profile", DRI_BOOL, NULL, 0},
+
[Mesa-dev] [RFC 0/2] Alternate default config mechanism
Mesa uses libexpat for many configuration parsing needs; however some userspaces like Android may not want to use libexpat for various reasons - eg some might restrict reading of any config xml files from filesystems. This patchset proposes a simple lookup mechanism for the default values as per current core mesa, keeping the same mesa-internal API as existing xmlconfig.c. Note: This RFC doesn't change mesa drivers that directly use libexpat API - vc4 and intel gen decoder. If these drivers need Android to be enabled for them, I request help from the experts there. For building and testing this on current AOSP/master, I have two hack patches - one provides empty dummy declarations for the XML* API in use in gen_decoder, while the other disables vc4 decoder functionality. These can be found at [1]. These have been built and boot-tested to UI on dragonboard. [1]: https://git.linaro.org/people/sumit.semwal/aosp/external/mesa3d.git/log/?h=expat_wip Sumit Semwal (2): mesa: utils: provide alternate default config mechanism mesa: Android: enable altxmlconfig for O+ src/gallium/targets/dri/Android.mk | 8 +- src/mesa/drivers/dri/Android.mk| 12 +- src/util/Android.mk| 12 +- src/util/Makefile.sources | 2 +- src/util/altxmlconfig.c| 261 + 5 files changed, 275 insertions(+), 20 deletions(-) create mode 100644 src/util/altxmlconfig.c -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [RFC 2/2] mesa: Android: enable altxmlconfig for O+
Android version O and later would like to use altxmlconfig instead of libexpat based parsing. We enable altxmlconfig instead of xmlconfig.c for Android O+. Change-Id: Iaa51b2a1e9c16a1fdf6f120104429b19dc68f9eb Signed-off-by: Sumit Semwal --- src/gallium/targets/dri/Android.mk | 8 +++- src/mesa/drivers/dri/Android.mk| 12 +--- src/util/Android.mk| 12 +--- src/util/Makefile.sources | 2 +- 4 files changed, 14 insertions(+), 20 deletions(-) diff --git a/src/gallium/targets/dri/Android.mk b/src/gallium/targets/dri/Android.mk index 10b27a80ef3e..da462ac1230d 100644 --- a/src/gallium/targets/dri/Android.mk +++ b/src/gallium/targets/dri/Android.mk @@ -44,11 +44,9 @@ LOCAL_SHARED_LIBRARIES := \ libglapi \ libz -# If Android version >=8 MESA should static link libexpat else should dynamic link -ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) -LOCAL_STATIC_LIBRARIES := \ - libexpat -else +# If Android version <8 MESA should dynamic link libexpat +# version >= 8 would use altxmlconfig instead +ifneq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) LOCAL_SHARED_LIBRARIES += \ libexpat endif diff --git a/src/mesa/drivers/dri/Android.mk b/src/mesa/drivers/dri/Android.mk index 60c8476a38a7..eefcb2475c6b 100644 --- a/src/mesa/drivers/dri/Android.mk +++ b/src/mesa/drivers/dri/Android.mk @@ -53,13 +53,11 @@ MESA_DRI_SHARED_LIBRARIES := \ liblog \ libz -# If Android version >=8 MESA should static link libexpat else should dynamic link -ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) -MESA_DRI_WHOLE_STATIC_LIBRARIES += \ - libexpat -else -MESA_DRI_SHARED_LIBRARIES += \ - libexpat +# If Android version <8 MESA should dynamic link libexpat +# version >= 8 would use altxmlconfig instead +ifneq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_SHARED_LIBRARIES += \ +libexpat endif #--- diff --git a/src/util/Android.mk b/src/util/Android.mk index 6d770ca95756..c8cfdae91e6a 100644 --- a/src/util/Android.mk +++ b/src/util/Android.mk @@ -41,13 +41,11 @@ LOCAL_C_INCLUDES := \ $(MESA_TOP)/src/gallium/include \ $(MESA_TOP)/src/gallium/auxiliary -# If Android version >=8 MESA should static link libexpat else should dynamic link -ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) -LOCAL_STATIC_LIBRARIES := \ - libexpat -else -LOCAL_SHARED_LIBRARIES := \ - libexpat +# If Android version <8 MESA should dynamic link libexpat +# version >= 8 would use altxmlconfig instead +ifneq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_SHARED_LIBRARIES += \ +libexpat endif LOCAL_MODULE := libmesa_util diff --git a/src/util/Makefile.sources b/src/util/Makefile.sources index ad8c56d3d1b7..617cc272d340 100644 --- a/src/util/Makefile.sources +++ b/src/util/Makefile.sources @@ -88,5 +88,5 @@ MESA_UTIL_GENERATED_FILES = \ format_srgb.c XMLCONFIG_FILES := \ - xmlconfig.c \ + altxmlconfig.c \ xmlconfig.h -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
