[Mesa-dev] [Bug 111039] [radv] - Persona 5 in RPCS3 emulator has glitches when using hardware fp16 (LLVM 9)

2019-07-08 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=111039

--- Comment #3 from Andrew Sheldon  ---
I've been informed that ACO doesn't support this feature yet, so it doesn't
actually "work" with that compiler, it's just falling back to the non-native
form.

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[Mesa-dev] [Bug 111039] [radv] - Persona 5 in RPCS3 emulator has glitches when using hardware fp16 (LLVM 9)

2019-07-08 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=111039

--- Comment #2 from Andrew Sheldon  ---
I should add that the bug doesn't occur with the ACO compiler.

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[Mesa-dev] [Bug 111039] [radv] - Persona 5 in RPCS3 emulator has glitches when using hardware fp16 (LLVM 9)

2019-07-08 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=111039

--- Comment #1 from Andrew Sheldon  ---
Created attachment 144730
  --> https://bugs.freedesktop.org/attachment.cgi?id=144730=edit
Renderdoc capture

Renderdoc capture. I'm not sure how helpful it will be since I can't reproduce
the bug when renderdoc is running, but maybe it will help see what the
game/emulator is doing.

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Re: [Mesa-dev] [PATCH] nir/lower_io_to_temporaries: Fix hash table leak

2019-07-08 Thread Timothy Arceri 

Reviewed-by: Timothy Arceri 

On 9/7/19 2:20 am, Connor Abbott wrote:

Fixes: c45f5db527252384395e55fb1149b673ec7b5fa8 ("nir/lower_io_to_temporaries: 
Handle interpolation intrinsics")
---
Whoops...

  src/compiler/nir/nir_lower_io_to_temporaries.c | 2 ++
  1 file changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir_lower_io_to_temporaries.c 
b/src/compiler/nir/nir_lower_io_to_temporaries.c
index c865c7de10c..f92489b9d51 100644
--- a/src/compiler/nir/nir_lower_io_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_io_to_temporaries.c
@@ -364,4 +364,6 @@ nir_lower_io_to_temporaries(nir_shader *shader, 
nir_function_impl *entrypoint,
 exec_list_append(>globals, _outputs);
  
 nir_fixup_deref_modes(shader);

+
+   _mesa_hash_table_destroy(state.input_map, NULL);
  }


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[Mesa-dev] [AppVeyor] mesa master #11788 completed

2019-07-08 Thread AppVeyor 


Build mesa 11788 completed



Commit a72351cc76 by Lionel Landwerlin on 7/8/2019 1:00 PM:

vulkan/overlay: fix crash on freeing NULL command buffer\n\nIt is legal to call vkFreeCommandBuffers() on NULL command buffers.\n\nThis fix requires eb41ce1b012f24 ("util/hash_table: Properly handle\nthe NULL key in hash_table_u64").\n\nSigned-off-by: Lionel Landwerlin \nFixes: 4438188f492e1f ("vulkan/overlay: record stats in command buffers and accumulate on exec/submit")\nReviewed-by: Bas Nieuwenhuizen 


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[Mesa-dev] [AppVeyor] mesa use-utils-functions2 #11787 failed

2019-07-08 Thread AppVeyor 



Build mesa 11787 failed


Commit 56ff535989 by Dylan Baker on 9/14/2018 7:57 PM:

remove final imports.h bits\n\nThis moves the fi_types to a new mesa_private.h and removes the\nimports.c file. The vast majority of this patch is just removing\npound includes of imports.h and fixing up the recursive includes.\n\nv2: - remove duplicate addition


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[Mesa-dev] [AppVeyor] mesa master #11786 completed

2019-07-08 Thread AppVeyor 


Build mesa 11786 completed



Commit 6271d16320 by Lionel Landwerlin on 7/8/2019 7:30 AM:

vulkan: bump headers & registry to 1.1.114\n\nSigned-off-by: Lionel Landwerlin \nReviewed-by: Eric Engestrom 


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[Mesa-dev] [AppVeyor] mesa use-utils-functions2 #11785 failed

2019-07-08 Thread AppVeyor 



Build mesa 11785 failed


Commit fc0a7b3663 by Dylan Baker on 9/14/2018 7:57 PM:

remove final imports.h bits\n\nThis moves the fi_types to a new mesa_private.h and removes the\nimports.c file. The vast majority of this patch is just removing\npound includes of imports.h and fixing up the recursive includes.\n\nv2: - remove duplicate addition


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Re: [Mesa-dev] [PATCH] nvc0: remove nvc0_program.tp.input_patch_size

2019-07-08 Thread Ilia Mirkin 
Reviewed-by: Ilia Mirkin 

The tcp input patch size is not a compile-time value, and even if it
were, not sure where we'd use it. The tep input patch size is set at
compile time, but in the code you're removing, we set it to ~0
anyways.

On Mon, Jul 8, 2019 at 3:22 PM Karol Herbst  wrote:
>
> right now that's dead code
>
> Signed-off-by: Karol Herbst 
> ---
>  src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 -
>  src/gallium/drivers/nouveau/nvc0/nvc0_program.c  | 4 
>  src/gallium/drivers/nouveau/nvc0/nvc0_program.h  | 1 -
>  3 files changed, 6 deletions(-)
>
> diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
> b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> index 7c835ceab8d..95b3d633ee6 100644
> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
> @@ -123,7 +123,6 @@ struct nv50_ir_prog_info
>   bool usesDrawParameters;
>} vp;
>struct {
> - uint8_t inputPatchSize;
>   uint8_t outputPatchSize;
>   uint8_t partitioning;/* PIPE_TESS_PART */
>   int8_t winding;  /* +1 (clockwise) / -1 (counter-clockwise) 
> */
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> index 1ff9f19f139..180b31ea893 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
> @@ -343,8 +343,6 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct 
> nv50_ir_prog_info *info)
>  {
> unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
>
> -   tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
> -
> if (info->numPatchConstants)
>opcs = 8 + info->numPatchConstants * 4;
>
> @@ -374,8 +372,6 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct 
> nv50_ir_prog_info *info)
>  static int
>  nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
>  {
> -   tep->tp.input_patch_size = ~0;
> -
> tep->hdr[0] = 0x20061 | (3 << 10);
> tep->hdr[4] = 0xff000;
>
> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h 
> b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
> index b73822ea9f7..183b14a42c2 100644
> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
> @@ -54,7 +54,6 @@ struct nvc0_program {
> } fp;
> struct {
>uint32_t tess_mode; /* ~0 if defined by the other stage */
> -  uint32_t input_patch_size;
> } tp;
> struct {
>uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
> --
> 2.21.0
>
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[Mesa-dev] [PATCH] nvc0: remove nvc0_program.tp.input_patch_size

2019-07-08 Thread Karol Herbst 
right now that's dead code

Signed-off-by: Karol Herbst 
---
 src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h | 1 -
 src/gallium/drivers/nouveau/nvc0/nvc0_program.c  | 4 
 src/gallium/drivers/nouveau/nvc0/nvc0_program.h  | 1 -
 3 files changed, 6 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index 7c835ceab8d..95b3d633ee6 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -123,7 +123,6 @@ struct nv50_ir_prog_info
  bool usesDrawParameters;
   } vp;
   struct {
- uint8_t inputPatchSize;
  uint8_t outputPatchSize;
  uint8_t partitioning;/* PIPE_TESS_PART */
  int8_t winding;  /* +1 (clockwise) / -1 (counter-clockwise) */
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 1ff9f19f139..180b31ea893 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -343,8 +343,6 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct 
nv50_ir_prog_info *info)
 {
unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
 
-   tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
-
if (info->numPatchConstants)
   opcs = 8 + info->numPatchConstants * 4;
 
@@ -374,8 +372,6 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct 
nv50_ir_prog_info *info)
 static int
 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 {
-   tep->tp.input_patch_size = ~0;
-
tep->hdr[0] = 0x20061 | (3 << 10);
tep->hdr[4] = 0xff000;
 
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
index b73822ea9f7..183b14a42c2 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.h
@@ -54,7 +54,6 @@ struct nvc0_program {
} fp;
struct {
   uint32_t tess_mode; /* ~0 if defined by the other stage */
-  uint32_t input_patch_size;
} tp;
struct {
   uint32_t lmem_size; /* local memory (TGSI PRIVATE resource) size */
-- 
2.21.0

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Re: [Mesa-dev] [PATCH] gallium: switch boolean -> bool at the interface definitions

2019-07-08 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek
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Re: [Mesa-dev] [PATCH] gallium: remove boolean from state tracker APIs

2019-07-08 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek
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Re: [Mesa-dev] [PATCH 3/3] android: amd/addrlib: add gfx10 support

2019-07-08 Thread Marek Olšák 
For the series:

Acked-by: Marek Olšák 

Marek

On Sat, Jul 6, 2019 at 4:17 PM Mauro Rossi  wrote:

> Fix the following building error:
>
> external/mesa/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp:35:10:
> fatal error: 'gfx10_gb_reg.h' file not found
>  ^~~~
> 1 error generated.
>
> Fixes: 78cdf9a ("amd/addrlib: add gfx10 support")
> Signed-off-by: Mauro Rossi 
> ---
>  src/amd/Android.addrlib.mk | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/src/amd/Android.addrlib.mk b/src/amd/Android.addrlib.mk
> index 428fe19b20..eec78fc8bf 100644
> --- a/src/amd/Android.addrlib.mk
> +++ b/src/amd/Android.addrlib.mk
> @@ -37,6 +37,7 @@ LOCAL_C_INCLUDES := \
> $(MESA_TOP)/src/amd/addrlib/src \
> $(MESA_TOP)/src/amd/addrlib/src/core \
> $(MESA_TOP)/src/amd/addrlib/src/chip/gfx9 \
> +   $(MESA_TOP)/src/amd/addrlib/src/chip/gfx10 \
> $(MESA_TOP)/src/amd/addrlib/src/chip/r800
>
>  LOCAL_EXPORT_C_INCLUDE_DIRS := \
> --
> 2.20.1
>
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Re: [Mesa-dev] [PATCH] ac: select the GFX ring when halting waves with UMR on GFX10

2019-07-08 Thread Marek Olšák 
Reviewed-by: Marek Olšák 

Marek

On Sun, Jul 7, 2019 at 1:32 PM Samuel Pitoiset 
wrote:

> GFX10 has two rings, so UMR want to know which one to halt.
> Select the first one by default.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/common/ac_debug.c   | 9 ++---
>  src/amd/common/ac_debug.h   | 3 ++-
>  src/amd/vulkan/radv_debug.c | 3 ++-
>  src/gallium/drivers/radeonsi/si_debug.c | 2 +-
>  4 files changed, 11 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
> index e4cb6a13a3a..1632106fdb9 100644
> --- a/src/amd/common/ac_debug.c
> +++ b/src/amd/common/ac_debug.c
> @@ -769,12 +769,15 @@ static int compare_wave(const void *p1, const void
> *p2)
>  }
>
>  /* Return wave information. "waves" should be a large enough array. */
> -unsigned ac_get_wave_info(struct ac_wave_info
> waves[AC_MAX_WAVES_PER_CHIP])
> +unsigned ac_get_wave_info(enum chip_class chip_class,
> + struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP])
>  {
> -   char line[2000];
> +   char line[2000], cmd[128];
> unsigned num_waves = 0;
>
> -   FILE *p = popen("umr -O halt_waves -wa", "r");
> +   sprintf(cmd, "umr -O halt_waves -wa %s", chip_class >= GFX10 ?
> "gfx_0.0.0" : "gfx");
> +
> +   FILE *p = popen(cmd, "r");
> if (!p)
> return 0;
>
> diff --git a/src/amd/common/ac_debug.h b/src/amd/common/ac_debug.h
> index 23343fe1304..0d5c1dd9eac 100644
> --- a/src/amd/common/ac_debug.h
> +++ b/src/amd/common/ac_debug.h
> @@ -64,6 +64,7 @@ void ac_parse_ib(FILE *f, uint32_t *ib, int num_dw,
> const int *trace_ids,
>  bool ac_vm_fault_occured(enum chip_class chip_class,
>  uint64_t *old_dmesg_timestamp, uint64_t
> *out_addr);
>
> -unsigned ac_get_wave_info(struct ac_wave_info
> waves[AC_MAX_WAVES_PER_CHIP]);
> +unsigned ac_get_wave_info(enum chip_class chip_class,
> + struct ac_wave_info
> waves[AC_MAX_WAVES_PER_CHIP]);
>
>  #endif
> diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
> index 2f661c0208f..42296745543 100644
> --- a/src/amd/vulkan/radv_debug.c
> +++ b/src/amd/vulkan/radv_debug.c
> @@ -445,7 +445,8 @@ radv_dump_annotated_shaders(struct radv_pipeline
> *pipeline,
> VkShaderStageFlagBits active_stages, FILE *f)
>  {
> struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
> -   unsigned num_waves = ac_get_wave_info(waves);
> +   enum chip_class chip_class =
> pipeline->device->physical_device->rad_info.chip_class;
> +   unsigned num_waves = ac_get_wave_info(chip_class, waves);
>
> fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
> "\n\n", num_waves);
> diff --git a/src/gallium/drivers/radeonsi/si_debug.c
> b/src/gallium/drivers/radeonsi/si_debug.c
> index c9c78733099..8265159c0d0 100644
> --- a/src/gallium/drivers/radeonsi/si_debug.c
> +++ b/src/gallium/drivers/radeonsi/si_debug.c
> @@ -1080,7 +1080,7 @@ static void si_print_annotated_shader(struct
> si_shader *shader,
>  static void si_dump_annotated_shaders(struct si_context *sctx, FILE *f)
>  {
> struct ac_wave_info waves[AC_MAX_WAVES_PER_CHIP];
> -   unsigned num_waves = ac_get_wave_info(waves);
> +   unsigned num_waves = ac_get_wave_info(sctx->chip_class, waves);
>
> fprintf(f, COLOR_CYAN "The number of active waves = %u" COLOR_RESET
> "\n\n", num_waves);
> --
> 2.22.0
>
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[Mesa-dev] [Bug 110735] Meson can't find 32-bit libXvMCW in non-standard path

2019-07-08 Thread bugzilla-daemon 
https://bugs.freedesktop.org/show_bug.cgi?id=110735

--- Comment #6 from Dylan Baker  ---
I started thinking about this over the weekend, and realized that all of this
work-arounding a lack of a .pc file for libxvmcw is silly, we should just add a
pkg-config file so this is less painful:
https://gitlab.freedesktop.org/xorg/lib/libxvmc/merge_requests/2

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[Mesa-dev] [PATCH] nir/lower_io_to_temporaries: Fix hash table leak

2019-07-08 Thread Connor Abbott 
Fixes: c45f5db527252384395e55fb1149b673ec7b5fa8 ("nir/lower_io_to_temporaries: 
Handle interpolation intrinsics")
---
Whoops...

 src/compiler/nir/nir_lower_io_to_temporaries.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/compiler/nir/nir_lower_io_to_temporaries.c 
b/src/compiler/nir/nir_lower_io_to_temporaries.c
index c865c7de10c..f92489b9d51 100644
--- a/src/compiler/nir/nir_lower_io_to_temporaries.c
+++ b/src/compiler/nir/nir_lower_io_to_temporaries.c
@@ -364,4 +364,6 @@ nir_lower_io_to_temporaries(nir_shader *shader, 
nir_function_impl *entrypoint,
exec_list_append(>globals, _outputs);
 
nir_fixup_deref_modes(shader);
+
+   _mesa_hash_table_destroy(state.input_map, NULL);
 }
-- 
2.17.2

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[Mesa-dev] [PATCH 37/42] panfrost: Implement ES3-format writeout

2019-07-08 Thread Alyssa Rosenzweig 
We add support for writing out (via a blend shader):

   - RGBA4
   - RGB10_A2_UNORM
   - RGB10_A2_UINT
   - RGB5_A1_UNORM
   - R11G11B10_FLOAT

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_nir_algebraic.py |   2 +
 .../panfrost/midgard/nir_lower_framebuffer.c  | 113 +-
 src/gallium/drivers/panfrost/pan_blending.c   |   3 -
 src/gallium/drivers/panfrost/pan_mfbd.c   |  19 ++-
 4 files changed, 129 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py 
b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
index 951b4b23241..faf83364c3a 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
+++ b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
@@ -60,6 +60,8 @@ converts = [
 
 # Totally redundant
 (('~f2f16', ('f2f32', 'a@16')), a),
+
+(('pack_half_2x16_split', 'a@32', 'b@32'), ('ior', ('ishl', ('i2i32', 
('f2f16', b)), 16), ('i2i32', ('f2f16', a,
 ]
 
 # Midgard scales fsin/fcos arguments by pi.
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index fddd8e3f12a..b0a8cd66259 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -39,6 +39,7 @@
 
 #include "compiler/nir/nir.h"
 #include "compiler/nir/nir_builder.h"
+#include "compiler/nir/nir_format_convert.h"
 #include "nir_lower_blend.h"
 #include "util/u_format.h"
 
@@ -72,6 +73,85 @@ nir_unorm8_to_float(nir_builder *b, nir_ssa_def *c_native)
return scaled;
 }
 
+/* Converters for UNORM4 formats, packing the final result into 16-bit */
+
+static nir_ssa_def *
+nir_float_to_unorm4(nir_builder *b, nir_ssa_def *c_float)
+{
+   /* First, we degrade quality to fp16; we don't need the extra bits */
+   nir_ssa_def *degraded = nir_f2f16(b, c_float);
+
+   /* Scale from [0, 1] to [0, 15.0] */
+   nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, degraded), 15.0);
+
+   /* Next, we type convert to u16 */
+   nir_ssa_def *converted = nir_f2u16(b,
+nir_fround_even(b, scaled));
+
+   /* In u16 land, we now need to pack */
+   nir_ssa_def *cr = nir_channel(b, converted, 0);
+   nir_ssa_def *cg = nir_channel(b, converted, 1);
+   nir_ssa_def *cb = nir_channel(b, converted, 2);
+   nir_ssa_def *ca = nir_channel(b, converted, 3);
+
+   nir_ssa_def *pack =
+  nir_ior(b,
+nir_ior(b, cr, nir_ishl(b, cg, nir_imm_int(b, 4))),
+nir_ior(b, nir_ishl(b, cb, nir_imm_int(b, 8)), nir_ishl(b, ca, 
nir_imm_int(b, 12;
+
+   return pack;
+}
+
+static nir_ssa_def *
+nir_float_to_rgb10a2(nir_builder *b, nir_ssa_def *c_float, bool normalize)
+{
+   nir_ssa_def *converted = c_float;
+
+   if (normalize) {
+  nir_ssa_def *scaled = nir_fmul(b, nir_fsat(b, c_float),
+nir_imm_vec4(b, 1023.0, 1023.0, 1023.0, 3.0));
+
+  converted = nir_f2u32(b,
+   nir_fround_even(b, scaled));
+   }
+
+   nir_ssa_def *cr = nir_channel(b, converted, 0);
+   nir_ssa_def *cg = nir_channel(b, converted, 1);
+   nir_ssa_def *cb = nir_channel(b, converted, 2);
+   nir_ssa_def *ca = nir_channel(b, converted, 3);
+
+   nir_ssa_def *pack =
+  nir_ior(b,
+nir_ior(b, cr, nir_ishl(b, cg, nir_imm_int(b, 10))),
+nir_ior(b, nir_ishl(b, cb, nir_imm_int(b, 20)), nir_ishl(b, ca, 
nir_imm_int(b, 30;
+
+   return pack;
+}
+
+static nir_ssa_def *
+nir_float_to_rgb5a1(nir_builder *b, nir_ssa_def *c_float)
+{
+   nir_ssa_def *degraded = nir_f2f16(b, c_float);
+
+   nir_ssa_def *scaled = nir_fmul(b, nir_fsat(b, degraded),
+ nir_imm_vec4_16(b, 31.0, 31.0, 31.0, 1.0));
+
+   nir_ssa_def *converted = nir_f2u16(b,
+nir_fround_even(b, scaled));
+
+   nir_ssa_def *cr = nir_channel(b, converted, 0);
+   nir_ssa_def *cg = nir_channel(b, converted, 1);
+   nir_ssa_def *cb = nir_channel(b, converted, 2);
+   nir_ssa_def *ca = nir_channel(b, converted, 3);
+
+   nir_ssa_def *pack =
+  nir_ior(b,
+nir_ior(b, cr, nir_ishl(b, cg, nir_imm_int(b, 5))),
+nir_ior(b, nir_ishl(b, cb, nir_imm_int(b, 10)), nir_ishl(b, ca, 
nir_imm_int(b, 15;
+
+   return pack;
+}
+
 static nir_ssa_def *
 nir_shader_to_native(nir_builder *b,
   nir_ssa_def *c_shader,
@@ -87,7 +167,22 @@ nir_shader_to_native(nir_builder *b,
   return nir_float_to_unorm8(b, c_shader);
else if (homogenous_bits && float_or_pure_int)
   return c_shader; /* type is already correct */
-   else {
+   else if (homogenous_bits && bits == 4 && 
util_format_is_unorm(desc->format)) {
+  /* TODO: Swizzle generally */
+  unsigned swiz[4] = { 2, 1, 0, 3 }; /* BGRA */
+  c_shader = nir_swizzle(b, c_shader, swiz, 4);
+  return nir_float_to_unorm4(b, c_shader);
+   } else if (desc->format == PIPE_FORMAT_R10G10B10A2_UNORM)
+ return nir_float_to_rgb10a2(b, c_shader, true); 
+   else if

[Mesa-dev] [PATCH 23/42] panfrost/midgard: Fix scalarification

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/midgard_emit.c   |  3 ++-
 .../panfrost/midgard/midgard_schedule.c   | 27 ---
 2 files changed, 25 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_emit.c 
b/src/gallium/drivers/panfrost/midgard/midgard_emit.c
index 2a71d1c0da1..f5d2d7212b3 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_emit.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_emit.c
@@ -89,12 +89,13 @@ vector_to_scalar_alu(midgard_vector_alu v, 
midgard_instruction *ins)
 {
 bool is_int = midgard_is_integer_op(v.op);
 bool is_full = v.reg_mode == midgard_reg_mode_32;
+bool is_inline_constant = ins->ssa_args.inline_constant;
 
 /* The output component is from the mask */
 midgard_scalar_alu s = {
 .op = v.op,
 .src1 = vector_to_scalar_source(v.src1, is_int, is_full),
-.src2 = vector_to_scalar_source(v.src2, is_int, is_full),
+.src2 = !is_inline_constant ? vector_to_scalar_source(v.src2, 
is_int, is_full) : 0,
 .unknown = 0,
 .outmod = v.outmod,
 .output_full = is_full,
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c 
b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
index ebbabae10bf..191017671cd 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
@@ -191,7 +191,6 @@ schedule_bundle(compiler_context *ctx, midgard_block 
*block, midgard_instruction
 int op = ains->alu.op;
 int units = alu_opcode_props[op].props;
 
-bool vectorable = units & UNITS_ANY_VECTOR;
 bool scalarable = units & UNITS_SCALAR;
 bool could_scalar = 
is_single_component_mask(ains->mask);
 
@@ -200,15 +199,35 @@ schedule_bundle(compiler_context *ctx, midgard_block 
*block, midgard_instruction
 could_scalar &= ains->alu.reg_mode != 
midgard_reg_mode_64;
 could_scalar &= ains->alu.dest_override == 
midgard_dest_override_none;
 
-bool vector = vectorable && !(could_scalar && 
scalarable);
+if (ains->alu.reg_mode == midgard_reg_mode_16) 
{
+/* If we're running in 16-bit mode, we
+ * can't have any 8-bit sources on the
+ * scalar unit (since the scalar unit
+ * doesn't understand 8-bit) */
+
+midgard_vector_alu_src s1 =
+
vector_alu_from_unsigned(ains->alu.src1);
+
+could_scalar &= !s1.half;
+
+if (!ains->ssa_args.inline_constant) {
+midgard_vector_alu_src s2 =
+
vector_alu_from_unsigned(ains->alu.src2);
+
+could_scalar &= !s2.half;
+}
+
+}
+
+bool scalar = could_scalar && scalarable;
 
 /* TODO: Check ahead-of-time for other scalar
  * hazards that otherwise get aborted out */
 
-if (!vector)
+if (scalar)
 assert(units & UNITS_SCALAR);
 
-if (vector) {
+if (!scalar) {
if (last_unit >= UNIT_VADD) {
 if (units & UNIT_VLUT)
 unit = UNIT_VLUT;
-- 
2.20.1

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[Mesa-dev] [PATCH 17/42] panfrost/midgard: Implement f2u16 and friends

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_compile.c   | 5 +
 src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index fc17ad2b051..21197efa499 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -841,6 +841,11 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 ALU_CASE(i2f32, i2f_rtz);
 ALU_CASE(u2f32, u2f_rtz);
 
+ALU_CASE(f2i16, f2i_rtz);
+ALU_CASE(f2u16, f2u_rtz);
+ALU_CASE(i2f16, i2f_rtz);
+ALU_CASE(u2f16, u2f_rtz);
+
 ALU_CASE(fsin, fsin);
 ALU_CASE(fcos, fcos);
 
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 5233fbc9280..9a08a4c43bf 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -51,7 +51,7 @@ nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, degraded), 255.0);
 
/* Next, we type convert */
-   nir_ssa_def *converted = nir_u2u8(b, nir_f2u32(b,
+   nir_ssa_def *converted = nir_u2u8(b, nir_f2u16(b,
 nir_fround_even(b, scaled)));
 
return converted;
-- 
2.20.1

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[Mesa-dev] [PATCH 32/42] panfrost: Set rt_count_2 for bpp>4 formats

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_mfbd.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/gallium/drivers/panfrost/pan_mfbd.c 
b/src/gallium/drivers/panfrost/pan_mfbd.c
index d14fb4269db..f262f6a592d 100644
--- a/src/gallium/drivers/panfrost/pan_mfbd.c
+++ b/src/gallium/drivers/panfrost/pan_mfbd.c
@@ -307,7 +307,14 @@ panfrost_mfbd_fragment(struct panfrost_context *ctx, bool 
has_draws)
 
 for (int cb = 0; cb < ctx->pipe_framebuffer.nr_cbufs; ++cb) {
 struct pipe_surface *surf = ctx->pipe_framebuffer.cbufs[cb];
+unsigned bpp = util_format_get_blocksize(surf->format);
+
 panfrost_mfbd_set_cbuf([cb], surf);
+
+/* What is this? Looks like some extension of the bpp field.
+ * Maybe it establishes how much internal tilebuffer space is
+ * reserved? */
+fb.rt_count_2 = MAX2(fb.rt_count_2, ALIGN_POT(bpp, 4) / 4);
 }
 
 if (ctx->pipe_framebuffer.zsbuf) {
-- 
2.20.1

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[Mesa-dev] [PATCH 38/42] panfrost/midgard: Handle PIPE_FORMAT_B10G10R10A2_UNORM

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index b0a8cd66259..c66f77aa406 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -172,7 +172,7 @@ nir_shader_to_native(nir_builder *b,
   unsigned swiz[4] = { 2, 1, 0, 3 }; /* BGRA */
   c_shader = nir_swizzle(b, c_shader, swiz, 4);
   return nir_float_to_unorm4(b, c_shader);
-   } else if (desc->format == PIPE_FORMAT_R10G10B10A2_UNORM)
+   } else if (desc->format == PIPE_FORMAT_R10G10B10A2_UNORM || desc->format == 
PIPE_FORMAT_B10G10R10A2_UNORM)
  return nir_float_to_rgb10a2(b, c_shader, true); 
else if (desc->format == PIPE_FORMAT_R10G10B10A2_UINT)
  return nir_float_to_rgb10a2(b, c_shader, false); 
@@ -239,7 +239,7 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format 
format)
if ((homogenous_bits && bits == 4 && util_format_is_unorm(format)) || 
format == PIPE_FORMAT_B5G5R5A1_UNORM) {
   raw_bitsize_out = 16;
   raw_out_components = 1;
-   } else if (format == PIPE_FORMAT_R10G10B10A2_UNORM || format == 
PIPE_FORMAT_R10G10B10A2_UINT || format == PIPE_FORMAT_R11G11B10_FLOAT) {
+   } else if (format == PIPE_FORMAT_R10G10B10A2_UNORM || format == 
PIPE_FORMAT_B10G10R10A2_UNORM || format == PIPE_FORMAT_R10G10B10A2_UINT || 
format == PIPE_FORMAT_R11G11B10_FLOAT) {
   raw_bitsize_out = 32;
   raw_out_components = 1;
}
-- 
2.20.1

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[Mesa-dev] [PATCH 35/42] panfrost/midgard: Use unsigned blend patch offset

2019-07-08 Thread Alyssa Rosenzweig 
We would like the offset field to be unsigned, letting 0 represent "no
offset" and positive represent an offset.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_compile.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 34b0678cf98..676a46e1236 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -2551,7 +2551,7 @@ midgard_compile_shader_nir(nir_shader *nir, 
midgard_program *program, bool is_bl
 .stage = nir->info.stage,
 
 .is_blend = is_blend,
-.blend_constant_offset = -1,
+.blend_constant_offset = 0,
 
 .alpha_ref = program->alpha_ref
 };
-- 
2.20.1

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[Mesa-dev] [PATCH 33/42] panfrost/mfbd: Handle pure int formats

2019-07-08 Thread Alyssa Rosenzweig 
We see that the render target itself turns out to be typeless
(surprise!)

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_mfbd.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_mfbd.c 
b/src/gallium/drivers/panfrost/pan_mfbd.c
index f262f6a592d..d35e6ebf4de 100644
--- a/src/gallium/drivers/panfrost/pan_mfbd.c
+++ b/src/gallium/drivers/panfrost/pan_mfbd.c
@@ -82,19 +82,31 @@ panfrost_mfbd_format(struct pipe_surface *surf)
 /* Set flags for alternative formats */
 
 bool float_16 =
-surf->format == PIPE_FORMAT_R16_FLOAT;
+surf->format == PIPE_FORMAT_R16_FLOAT ||
+surf->format == PIPE_FORMAT_R16_UINT ||
+surf->format == PIPE_FORMAT_R16_SINT;
 
 bool float_32 =
 surf->format == PIPE_FORMAT_R11G11B10_FLOAT ||
+surf->format == PIPE_FORMAT_R16G16_FLOAT ||
+surf->format == PIPE_FORMAT_R16G16_UINT ||
+surf->format == PIPE_FORMAT_R16G16_SINT ||
 surf->format == PIPE_FORMAT_R32_FLOAT ||
-surf->format == PIPE_FORMAT_R16G16_FLOAT;
+surf->format == PIPE_FORMAT_R32_UINT ||
+surf->format == PIPE_FORMAT_R32_SINT;
 
 bool float_64 =
 surf->format == PIPE_FORMAT_R32G32_FLOAT ||
-surf->format == PIPE_FORMAT_R16G16B16A16_FLOAT;
+surf->format == PIPE_FORMAT_R32G32_SINT ||
+surf->format == PIPE_FORMAT_R32G32_UINT ||
+surf->format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
+surf->format == PIPE_FORMAT_R16G16B16A16_SINT ||
+surf->format == PIPE_FORMAT_R16G16B16A16_UINT;
 
 bool float_128 =
-surf->format == PIPE_FORMAT_R32G32B32A32_FLOAT;
+surf->format == PIPE_FORMAT_R32G32B32A32_FLOAT ||
+surf->format == PIPE_FORMAT_R32G32B32A32_SINT ||
+surf->format == PIPE_FORMAT_R32G32B32A32_UINT;
 
 if (surf->format == PIPE_FORMAT_B5G6R5_UNORM) {
 fmt.unk1 = 0x1400;
-- 
2.20.1

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[Mesa-dev] [PATCH 25/42] panfrost/midgard: Use fp16 exclusively while blending

2019-07-08 Thread Alyssa Rosenzweig 
We now have some preliminary fp16 support available. We're not able to
expose this for GLSL quite yet, but for internal blend shaders, we're
able to do control bitness ourselves just fine. So let's fp16 that
stuff!

Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/nir_lower_blend.c | 14 +++---
 .../panfrost/midgard/nir_lower_framebuffer.c   |  4 ++--
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c
index 7a7f0ebabd7..af0a7ac31cf 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c
@@ -82,7 +82,7 @@ nir_alpha_saturate(
 {
nir_ssa_def *Asrc = nir_channel(b, src, 3);
nir_ssa_def *Adst = nir_channel(b, dst, 3);
-   nir_ssa_def *one = nir_imm_float(b, 1.0);
+   nir_ssa_def *one = nir_imm_float16(b, 1.0);
nir_ssa_def *Adsti = nir_fsub(b, one, Adst);
 
return (chan < 3) ? nir_fmin(b, Asrc, Adsti) : one;
@@ -99,7 +99,7 @@ nir_blend_factor_value(
 {
switch (factor) {
case BLEND_FACTOR_ZERO:
-  return nir_imm_float(b, 0.0);
+  return nir_imm_float16(b, 0.0);
case BLEND_FACTOR_SRC_COLOR:
   return nir_channel(b, src, chan);
case BLEND_FACTOR_DST_COLOR:
@@ -132,7 +132,7 @@ nir_blend_factor(
   nir_blend_factor_value(b, src, dst, bconst, chan, factor);
 
if (inverted)
-  f = nir_fsub(b, nir_imm_float(b, 1.0), f);
+  f = nir_fsub(b, nir_imm_float16(b, 1.0), f);
 
return nir_fmul(b, raw_scalar, f);
 }
@@ -167,7 +167,7 @@ nir_blend(
   nir_ssa_def *src, nir_ssa_def *dst)
 {
/* Grab the blend constant ahead of time */
-   nir_ssa_def *bconst = nir_load_blend_const_color_rgba(b);
+   nir_ssa_def *bconst = nir_f2f16(b, nir_load_blend_const_color_rgba(b));
 
/* We blend per channel and recombine later */
nir_ssa_def *channels[4];
@@ -226,13 +226,13 @@ nir_lower_blend(nir_shader *shader, 
nir_lower_blend_options options)
 b.cursor = nir_before_instr(instr);
 
 /* Grab the input color */
-nir_ssa_def *src = nir_ssa_for_src(, intr->src[1], 4);
+nir_ssa_def *src = nir_f2f16(, nir_ssa_for_src(, intr->src[1], 
4));
 
 /* Grab the tilebuffer color - io lowered to load_output */
-nir_ssa_def *dst = nir_load_var(, var);
+nir_ssa_def *dst = nir_f2f16(, nir_load_var(, var));
 
 /* Blend the two colors per the passed options */
-nir_ssa_def *blended = nir_blend(, options, src, dst);
+nir_ssa_def *blended = nir_f2f32(, nir_blend(, options, src, 
dst));
 
 /* Write out the final color instead of the input */
 nir_instr_rewrite_src(instr, >src[1],
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 9a08a4c43bf..2986c3c3393 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -60,8 +60,8 @@ nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
 static nir_ssa_def *
 nir_native_to_float(nir_builder *b, nir_ssa_def *c_native)
 {
-   /* First, we convert up from u8 to f32 */
-   nir_ssa_def *converted = nir_u2f32(b, nir_u2u32(b, c_native));
+   /* First, we convert up from u8 to f16 */
+   nir_ssa_def *converted = nir_u2f16(b, nir_u2u16(b, c_native));
 
/* Next, we scale down from [0, 255.0] to [0, 1] */
nir_ssa_def *scaled = nir_fsat(b, nir_fmul_imm(b, converted, 1.0/255.0));
-- 
2.20.1

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[Mesa-dev] [PATCH 26/42] panfrost/midgard: Use Gallium framebuffer formats

2019-07-08 Thread Alyssa Rosenzweig 
Ideally, we would keep Galliumisms far away from the compiler;
unfortunately, Mesa hasn't standardized on system of format codes to be
shared across APIs and across drivers, so using Gallium formats is our
best bet in the short run.

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/nir_lower_framebuffer.c  | 41 +--
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 2986c3c3393..f5182ca7394 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -40,9 +40,10 @@
 #include "compiler/nir/nir.h"
 #include "compiler/nir/nir_builder.h"
 #include "nir_lower_blend.h"
+#include "util/u_format.h"
 
 static nir_ssa_def *
-nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
+nir_float_to_unorm8(nir_builder *b, nir_ssa_def *c_float)
 {
/* First, we degrade quality to fp16; we don't need the extra bits */
nir_ssa_def *degraded = nir_f2f16(b, c_float);
@@ -58,7 +59,7 @@ nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
 }
 
 static nir_ssa_def *
-nir_native_to_float(nir_builder *b, nir_ssa_def *c_native)
+nir_unorm8_to_float(nir_builder *b, nir_ssa_def *c_native)
 {
/* First, we convert up from u8 to f16 */
nir_ssa_def *converted = nir_u2f16(b, nir_u2u16(b, c_native));
@@ -69,12 +70,44 @@ nir_native_to_float(nir_builder *b, nir_ssa_def *c_native)
return scaled;
 }
 
+
+
+static nir_ssa_def *
+nir_float_to_native(nir_builder *b,
+  nir_ssa_def *c_float,
+  const struct util_format_description *desc)
+{
+   if (util_format_is_unorm8(desc))
+  return nir_float_to_unorm8(b, c_float);
+   else {
+  printf("%s\n", desc->name);
+  unreachable("Unknown format name");
+   }
+}
+
+static nir_ssa_def *
+nir_native_to_float(nir_builder *b,
+   nir_ssa_def *c_native,
+   const struct util_format_description *desc)
+{
+   if (util_format_is_unorm8(desc))
+  return nir_unorm8_to_float(b, c_native);
+   else {
+  printf("%s\n", desc->name);
+  unreachable("Unknown format name");
+   }
+}
+
 void
 nir_lower_framebuffer(nir_shader *shader)
 {
/* Blend shaders are represented as special fragment shaders */
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
 
+   enum pipe_format format = PIPE_FORMAT_R8G8B8A8_UNORM;
+   const struct util_format_description *format_desc =
+  util_format_description(format);
+
nir_foreach_function(func, shader) {
   nir_foreach_block(block, func->impl) {
  nir_foreach_instr_safe(instr, block) {
@@ -106,7 +139,7 @@ nir_lower_framebuffer(nir_shader *shader)
nir_ssa_def *c_nir = nir_ssa_for_src(, intr->src[1], 4);
 
/* Format convert */
-   nir_ssa_def *converted = nir_float_to_native(, c_nir);
+   nir_ssa_def *converted = nir_float_to_native(, c_nir, 
format_desc);
 
/* Rewrite to use a native store by creating a new intrinsic */
nir_intrinsic_instr *new =
@@ -137,7 +170,7 @@ nir_lower_framebuffer(nir_shader *shader)
 
/* Convert the raw value */
nir_ssa_def *raw = >dest.ssa;
-   nir_ssa_def *converted = nir_native_to_float(, raw);
+   nir_ssa_def *converted = nir_native_to_float(, raw, 
format_desc);
 
/* Rewrite to use the converted value */
nir_src rewritten = nir_src_for_ssa(converted);
-- 
2.20.1

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[Mesa-dev] [PATCH 20/42] panfrost/midgard: Fix fp16 embedded constants

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_schedule.c   | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c 
b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
index caa29b7a2e4..ebbabae10bf 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
@@ -272,6 +272,25 @@ schedule_bundle(compiler_context *ctx, midgard_block 
*block, midgard_instruction
 
 bundle.has_blend_constant = 1;
 bundle.has_embedded_constants = 1;
+} else if (ains->has_constants && ains->alu.reg_mode 
== midgard_reg_mode_16) {
+/* TODO: DRY with the analysis pass */
+
+if (bundle.has_blend_constant)
+break;
+
+if (constant_count)
+break;
+
+/* TODO: Fix packing XXX */
+uint16_t *bundles = (uint16_t *) 
bundle.constants;
+uint32_t *constants = (uint32_t *) 
ains->constants;
+
+/* Copy them wholesale */
+for (unsigned i = 0; i < 4; ++i)
+bundles[i] = constants[i];
+
+bundle.has_embedded_constants = true;
+constant_count = 4;
 } else if (ains->has_constants) {
 /* By definition, blend constants conflict with
  * everything, so if there are already
-- 
2.20.1

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[Mesa-dev] [PATCH 24/42] panfrost/midgard: Remove opt_copy_prop_tex

2019-07-08 Thread Alyssa Rosenzweig 
Eventually this should be replaced by proper tex RA / not emitting so
many silly moves to begin with / better general copy prop. For now
remove it since it breaks things.

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 50 ---
 1 file changed, 50 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index b7498d43501..34b0678cf98 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -2225,55 +2225,6 @@ midgard_opt_pos_propagate(compiler_context *ctx, 
midgard_block *block)
 return progress;
 }
 
-static bool
-midgard_opt_copy_prop_tex(compiler_context *ctx, midgard_block *block)
-{
-bool progress = false;
-
-mir_foreach_instr_in_block_safe(block, ins) {
-if (ins->type != TAG_ALU_4) continue;
-if (!OP_IS_MOVE(ins->alu.op)) continue;
-
-unsigned from = ins->ssa_args.src1;
-unsigned to = ins->ssa_args.dest;
-
-/* Make sure it's simple enough for us to handle */
-
-if (from >= SSA_FIXED_MINIMUM) continue;
-if (from >= ctx->func->impl->ssa_alloc) continue;
-if (to < SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE)) continue;
-if (to > SSA_FIXED_REGISTER(REGISTER_TEXTURE_BASE + 1)) 
continue;
-
-bool eliminated = false;
-
-mir_foreach_instr_in_block_from_rev(block, v, 
mir_prev_op(ins)) {
-/* The texture registers are not SSA so be careful.
- * Conservatively, just stop if we hit a texture op
- * (even if it may not write) to where we are */
-
-if (v->type != TAG_ALU_4)
-break;
-
-if (v->ssa_args.dest == from) {
-/* We don't want to track partial writes ... */
-if (v->mask == 0xF) {
-v->ssa_args.dest = to;
-eliminated = true;
-}
-
-break;
-}
-}
-
-if (eliminated)
-mir_remove_instruction(ins);
-
-progress |= eliminated;
-}
-
-return progress;
-}
-
 /* The following passes reorder MIR instructions to enable better scheduling */
 
 static void
@@ -2699,7 +2650,6 @@ midgard_compile_shader_nir(nir_shader *nir, 
midgard_program *program, bool is_bl
 mir_foreach_block(ctx, block) {
 progress |= midgard_opt_pos_propagate(ctx, block);
 progress |= midgard_opt_copy_prop(ctx, block);
-progress |= midgard_opt_copy_prop_tex(ctx, block);
 progress |= midgard_opt_dead_code_eliminate(ctx, 
block);
 }
 } while (progress);
-- 
2.20.1

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[Mesa-dev] [PATCH 41/42] panfrost/mfbd: Cleanup format code selection

2019-07-08 Thread Alyssa Rosenzweig 
Rather than have random variables flying around and a long if-else
chain, use a switch. They're literally *designed* for this.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_blending.c |   5 +
 src/gallium/drivers/panfrost/pan_mfbd.c | 162 +++-
 2 files changed, 95 insertions(+), 72 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_blending.c 
b/src/gallium/drivers/panfrost/pan_blending.c
index 3acda3101c3..9e38b1c56f6 100644
--- a/src/gallium/drivers/panfrost/pan_blending.c
+++ b/src/gallium/drivers/panfrost/pan_blending.c
@@ -122,6 +122,11 @@ panfrost_can_fixed_blend(enum pipe_format format)
 case PIPE_FORMAT_B10G10R10A2_UNORM:
 case PIPE_FORMAT_R10G10B10X2_UNORM:
 case PIPE_FORMAT_B10G10R10X2_UNORM:
+case PIPE_FORMAT_B4G4R4A4_UNORM:
+case PIPE_FORMAT_B4G4R4X4_UNORM:
+case PIPE_FORMAT_A4R4_UNORM:
+case PIPE_FORMAT_R4A4_UNORM:
+case PIPE_FORMAT_A4B4G4R4_UNORM:
 return true;
 default:
 return false;
diff --git a/src/gallium/drivers/panfrost/pan_mfbd.c 
b/src/gallium/drivers/panfrost/pan_mfbd.c
index 9515b616314..99fa3331ccd 100644
--- a/src/gallium/drivers/panfrost/pan_mfbd.c
+++ b/src/gallium/drivers/panfrost/pan_mfbd.c
@@ -79,79 +79,97 @@ panfrost_mfbd_format(struct pipe_surface *surf)
 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
 fmt.flags |= MALI_MFBD_FORMAT_SRGB;
 
-/* Set flags for alternative formats */
+/* sRGB handled as a dedicated flag */
+enum pipe_format linearized = util_format_linear(surf->format);
+
+/* If RGB, we're good to go */
+if (util_format_is_unorm8(desc))
+return fmt;
 
-bool float_16 =
-surf->format == PIPE_FORMAT_R16_FLOAT ||
-surf->format == PIPE_FORMAT_R16_UINT ||
-surf->format == PIPE_FORMAT_R16_SINT ||
-surf->format == PIPE_FORMAT_B5G5R5A1_UNORM;
-
-bool float_32 =
-surf->format == PIPE_FORMAT_R11G11B10_FLOAT ||
-surf->format == PIPE_FORMAT_R16G16_FLOAT ||
-surf->format == PIPE_FORMAT_R16G16_UINT ||
-surf->format == PIPE_FORMAT_R16G16_SINT ||
-surf->format == PIPE_FORMAT_R32_FLOAT ||
-surf->format == PIPE_FORMAT_R32_UINT ||
-surf->format == PIPE_FORMAT_R32_SINT ||
-surf->format == PIPE_FORMAT_R10G10B10A2_UINT;
-
-bool rgb10_unorm =
-surf->format == PIPE_FORMAT_R10G10B10A2_UNORM ||
-surf->format == PIPE_FORMAT_B10G10R10A2_UNORM ||
-surf->format == PIPE_FORMAT_R10G10B10X2_UNORM ||
-surf->format == PIPE_FORMAT_B10G10R10X2_UNORM;
-
-bool float_64 =
-surf->format == PIPE_FORMAT_R32G32_FLOAT ||
-surf->format == PIPE_FORMAT_R32G32_SINT ||
-surf->format == PIPE_FORMAT_R32G32_UINT ||
-surf->format == PIPE_FORMAT_R16G16B16A16_FLOAT ||
-surf->format == PIPE_FORMAT_R16G16B16A16_SINT ||
-surf->format == PIPE_FORMAT_R16G16B16A16_UINT;
-
-bool float_128 =
-surf->format == PIPE_FORMAT_R32G32B32A32_FLOAT ||
-surf->format == PIPE_FORMAT_R32G32B32A32_SINT ||
-surf->format == PIPE_FORMAT_R32G32B32A32_UINT;
-
-if (surf->format == PIPE_FORMAT_B5G6R5_UNORM) {
-fmt.unk1 = 0x1400;
-fmt.nr_channels = MALI_POSITIVE(2);
-fmt.unk3 |= 0x1;
-} else if (surf->format == PIPE_FORMAT_B4G4R4A4_UNORM) {
-/* XXX: why does the specialized code not work but the generic
- * 16-bit code work? */
-#if 0
-fmt.unk1 = 0x1000;
-fmt.unk3 = 0x5;
-fmt.nr_channels = MALI_POSITIVE(1);
-#endif
-
-fmt.unk1 = 0x8400;
-fmt.unk3 = 0x0;
-fmt.nr_channels = MALI_POSITIVE(2);
-} else if (rgb10_unorm) {
-fmt.unk1 = 0x0800;
-fmt.unk3 = 0x6;
-fmt.nr_channels = MALI_POSITIVE(1);
-} else if (float_32) {
-fmt.unk1 = 0x8800;
-fmt.unk3 = 0x0;
-fmt.nr_channels = MALI_POSITIVE(4);
-} else if (float_16) {
-fmt.unk1 = 0x8400;
-fmt.unk3 = 0x0;
-fmt.nr_channels = MALI_POSITIVE(2);
-} else if (float_64) {
-fmt.unk1 = 0x8c00;
-fmt.unk3 = 0x1;
-fmt.nr_channels = MALI_POSITIVE(2);
-} else if (float_128) {
-fmt.unk1 = 0x9000;
-fmt.unk3 = 0x1;
-fmt.nr_channels = MALI_POSITIVE(4);
+/* Set

[Mesa-dev] [PATCH 27/42] panfrost: Pipe framebuffer format around

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/nir_lower_blend.h| 3 ++-
 .../drivers/panfrost/midgard/nir_lower_framebuffer.c  | 3 +--
 src/gallium/drivers/panfrost/pan_blend_shaders.c  | 8 ++--
 src/gallium/drivers/panfrost/pan_blend_shaders.h  | 6 +-
 src/gallium/drivers/panfrost/pan_context.c| 8 +++-
 5 files changed, 21 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h 
b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h
index 2805ca25d97..7a2df6e5e29 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h
@@ -26,6 +26,7 @@
 #define NIR_BLEND_H
 
 #include "compiler/nir/nir.h"
+#include "pipe/p_format.h"
 
 /* These structs encapsulates the blend state such that it can be lowered
  * cleanly
@@ -54,6 +55,6 @@ typedef struct {
 void nir_lower_blend(nir_shader *shader, nir_lower_blend_options options);
 
 void
-nir_lower_framebuffer(nir_shader *shader);
+nir_lower_framebuffer(nir_shader *shader, enum pipe_format format);
 
 #endif
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index f5182ca7394..85bb6488e69 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -99,12 +99,11 @@ nir_native_to_float(nir_builder *b,
 }
 
 void
-nir_lower_framebuffer(nir_shader *shader)
+nir_lower_framebuffer(nir_shader *shader, enum pipe_format format)
 {
/* Blend shaders are represented as special fragment shaders */
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
 
-   enum pipe_format format = PIPE_FORMAT_R8G8B8A8_UNORM;
const struct util_format_description *format_desc =
   util_format_description(format);
 
diff --git a/src/gallium/drivers/panfrost/pan_blend_shaders.c 
b/src/gallium/drivers/panfrost/pan_blend_shaders.c
index 640ddc86847..91c8fb89688 100644
--- a/src/gallium/drivers/panfrost/pan_blend_shaders.c
+++ b/src/gallium/drivers/panfrost/pan_blend_shaders.c
@@ -115,7 +115,11 @@ nir_make_options(const struct pipe_blend_state *blend, 
unsigned nr_cbufs)
 }
 
 void
-panfrost_make_blend_shader(struct panfrost_context *ctx, struct 
panfrost_blend_state *cso, const struct pipe_blend_color *blend_color)
+panfrost_make_blend_shader(
+struct panfrost_context *ctx,
+struct panfrost_blend_state *cso,
+const struct pipe_blend_color *blend_color,
+enum pipe_format format)
 {
 /* Build the shader */
 
@@ -149,7 +153,7 @@ panfrost_make_blend_shader(struct panfrost_context *ctx, 
struct panfrost_blend_s
 nir_make_options(>base, 1);
 NIR_PASS_V(shader, nir_lower_blend, options);
 
-NIR_PASS_V(shader, nir_lower_framebuffer);
+NIR_PASS_V(shader, nir_lower_framebuffer, format);
 
 /* Compile the built shader */
 
diff --git a/src/gallium/drivers/panfrost/pan_blend_shaders.h 
b/src/gallium/drivers/panfrost/pan_blend_shaders.h
index 1a914772673..23acd39581a 100644
--- a/src/gallium/drivers/panfrost/pan_blend_shaders.h
+++ b/src/gallium/drivers/panfrost/pan_blend_shaders.h
@@ -31,6 +31,10 @@
 #include "pan_context.h"
 
 void
-panfrost_make_blend_shader(struct panfrost_context *ctx, struct 
panfrost_blend_state *cso, const struct pipe_blend_color *blend_color);
+panfrost_make_blend_shader(
+struct panfrost_context *ctx,
+struct panfrost_blend_state *cso,
+const struct pipe_blend_color *blend_color,
+enum pipe_format format);
 
 #endif
diff --git a/src/gallium/drivers/panfrost/pan_context.c 
b/src/gallium/drivers/panfrost/pan_context.c
index 82cd2ea6a48..be5d0a14cf5 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -2381,9 +2381,15 @@ panfrost_create_blend_state(struct pipe_context *pipe,
 if (panfrost_make_fixed_blend_mode(>rt[0], so, 
blend->rt[0].colormask, >blend_color))
 return so;
 
+/* TODO: Key against framebuffer. TODO: MRT explicitly */
+if (!ctx->pipe_framebuffer.nr_cbufs)
+return so;
+
+enum pipe_format format = ctx->pipe_framebuffer.cbufs[0]->format;
+
 /* If we can't, compile a blend shader instead */
 
-panfrost_make_blend_shader(ctx, so, >blend_color);
+panfrost_make_blend_shader(ctx, so, >blend_color, format);
 
 return so;
 }
-- 
2.20.1

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[Mesa-dev] [PATCH 40/42] panfrost/midgard: Cleanup blend switch

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/nir_lower_framebuffer.c  | 49 ---
 1 file changed, 31 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index c66f77aa406..fe6ae121a4c 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -167,24 +167,37 @@ nir_shader_to_native(nir_builder *b,
   return nir_float_to_unorm8(b, c_shader);
else if (homogenous_bits && float_or_pure_int)
   return c_shader; /* type is already correct */
-   else if (homogenous_bits && bits == 4 && 
util_format_is_unorm(desc->format)) {
-  /* TODO: Swizzle generally */
-  unsigned swiz[4] = { 2, 1, 0, 3 }; /* BGRA */
-  c_shader = nir_swizzle(b, c_shader, swiz, 4);
-  return nir_float_to_unorm4(b, c_shader);
-   } else if (desc->format == PIPE_FORMAT_R10G10B10A2_UNORM || desc->format == 
PIPE_FORMAT_B10G10R10A2_UNORM)
- return nir_float_to_rgb10a2(b, c_shader, true); 
-   else if (desc->format == PIPE_FORMAT_R10G10B10A2_UINT)
- return nir_float_to_rgb10a2(b, c_shader, false); 
-   else if (desc->format == PIPE_FORMAT_B5G5R5A1_UNORM) {
-  unsigned swiz[4] = { 2, 1, 0, 3 }; /* BGRA */
-  c_shader = nir_swizzle(b, c_shader, swiz, 4);
-  return nir_float_to_rgb5a1(b, c_shader);
-   } else if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT) {
-  return nir_format_pack_11f11f10f(b, c_shader);
-   } else {
-  printf("%s\n", desc->name);
-  unreachable("Unknown format name");
+
+   //unsigned bgra[4] = { 2, 1, 0, 3 }; /* BGRA */
+   //c_shader = nir_swizzle(b, c_shader, swiz, 4);
+
+   /* Special formats */
+   switch (desc->format) {
+  case PIPE_FORMAT_B4G4R4A4_UNORM:
+  case PIPE_FORMAT_B4G4R4X4_UNORM:
+  case PIPE_FORMAT_A4R4_UNORM:
+  case PIPE_FORMAT_R4A4_UNORM:
+  case PIPE_FORMAT_A4B4G4R4_UNORM:
+ return nir_float_to_unorm4(b, c_shader);
+
+  case PIPE_FORMAT_R10G10B10A2_UNORM:
+  case PIPE_FORMAT_B10G10R10A2_UNORM:
+  case PIPE_FORMAT_R10G10B10X2_UNORM:
+  case PIPE_FORMAT_B10G10R10X2_UNORM:
+return nir_float_to_rgb10a2(b, c_shader, true); 
+
+  case PIPE_FORMAT_R10G10B10A2_UINT:
+return nir_float_to_rgb10a2(b, c_shader, false); 
+
+  case PIPE_FORMAT_B5G5R5A1_UNORM:
+ return nir_float_to_rgb5a1(b, c_shader);
+
+  case PIPE_FORMAT_R11G11B10_FLOAT:
+ return nir_format_pack_11f11f10f(b, c_shader);
+
+  default:
+ printf("%s\n", desc->name);
+ unreachable("Unknown format name");
}
 }
 
-- 
2.20.1

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[Mesa-dev] [PATCH 42/42] panfrost: Update supported formats

2019-07-08 Thread Alyssa Rosenzweig 
Much of the format selection code was inherited from softpipe (!) of all
places, and a lot of it is accordingly cruft. Later if-elses were added
in random places to workaround missing formats at various points in
history. Clean up some of this.

Theoretically, any format we can texture from we can also render to. In
practice, there are a few corner cases that we need to disable
explicitly.

For one, we do have to restrict SCANOUT formats to workaround
buggy apps (in particular, dEQP which with --deqp-surface-type=window
under Weston will end up with RGB10_A2 and complain about low alpha
precision). Just be clearer about how/why.

Also, RGB5_A1 support is still broken; let's not worry about that quite
yet.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_screen.c | 50 +--
 1 file changed, 10 insertions(+), 40 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_screen.c 
b/src/gallium/drivers/panfrost/pan_screen.c
index d53a906838e..b044ae99399 100644
--- a/src/gallium/drivers/panfrost/pan_screen.c
+++ b/src/gallium/drivers/panfrost/pan_screen.c
@@ -460,48 +460,18 @@ panfrost_is_format_supported( struct pipe_screen *screen,
 if (format == PIPE_FORMAT_A1B5G5R5_UNORM || format == 
PIPE_FORMAT_X1B5G5R5_UNORM)
 return FALSE;
 
-/* Allow through special formats */
-
-switch (format) {
-case PIPE_FORMAT_R11G11B10_FLOAT:
-case PIPE_FORMAT_B5G6R5_UNORM:
-return TRUE;
-default:
-break;
-}
-
-if (bind & PIPE_BIND_RENDER_TARGET) {
-if (format_desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS)
-return FALSE;
-
-/* Check for vaguely 8UNORM formats. Looser than
- * util_format_is_rgba8_variant, since it permits R8 (for
- * instance) */
-
-for (unsigned chan = 0; chan < 4; ++chan) {
-enum util_format_type t = 
format_desc->channel[chan].type;
-if (t == UTIL_FORMAT_TYPE_VOID) continue;
-if (t != UTIL_FORMAT_TYPE_UNSIGNED) return FALSE;
-if (!format_desc->channel[chan].normalized) return 
FALSE;
-if (format_desc->channel[chan].size != 8) return FALSE;
-}
-
-/*
- * Although possible, it is unnatural to render into 
compressed or YUV
- * surfaces. So disable these here to avoid going into weird 
paths
- * inside the state trackers.
- */
-if (format_desc->block.width != 1 ||
-format_desc->block.height != 1)
-return FALSE;
-}
+/* TODO */
+if (format == PIPE_FORMAT_B5G5R5A1_UNORM)
+return FALSE;
 
-if (bind & PIPE_BIND_DEPTH_STENCIL) {
-if (format_desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
-return FALSE;
-}
+/* Don't confuse poorly written apps (workaround dEQP bug) that expect
+ * more alpha than they ask for */
+bool scanout = bind & (PIPE_BIND_SCANOUT | PIPE_BIND_SHARED | 
PIPE_BIND_DISPLAY_TARGET);
+if (scanout && !util_format_is_rgba8_variant(format_desc))
+return FALSE;
 
-if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
+if (format_desc->layout != UTIL_FORMAT_LAYOUT_PLAIN &&
+format_desc->layout != UTIL_FORMAT_LAYOUT_OTHER) {
 /* Compressed formats not yet hooked up. */
 return FALSE;
 }
-- 
2.20.1

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[Mesa-dev] [PATCH 36/42] panfrost: Refactor blend infrastructure

2019-07-08 Thread Alyssa Rosenzweig 
We would like to permit keying blend shaders against the framebuffer
format, which requires some new blending abstractions.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/meson.build  |   1 +
 src/gallium/drivers/panfrost/pan_blend.h  | 109 +++
 src/gallium/drivers/panfrost/pan_blend_cso.c  | 268 ++
 .../drivers/panfrost/pan_blend_shaders.c  |  34 ++-
 .../drivers/panfrost/pan_blend_shaders.h  |   8 +-
 src/gallium/drivers/panfrost/pan_blending.c   |  75 ++---
 src/gallium/drivers/panfrost/pan_blending.h   |  13 +-
 src/gallium/drivers/panfrost/pan_context.c| 133 ++---
 src/gallium/drivers/panfrost/pan_context.h|  16 +-
 9 files changed, 455 insertions(+), 202 deletions(-)
 create mode 100644 src/gallium/drivers/panfrost/pan_blend.h
 create mode 100644 src/gallium/drivers/panfrost/pan_blend_cso.c

diff --git a/src/gallium/drivers/panfrost/meson.build 
b/src/gallium/drivers/panfrost/meson.build
index cc49903aaac..6b907f155ae 100644
--- a/src/gallium/drivers/panfrost/meson.build
+++ b/src/gallium/drivers/panfrost/meson.build
@@ -56,6 +56,7 @@ files_panfrost = files(
   'pan_format.c',
   'pan_blending.c',
   'pan_blend_shaders.c',
+  'pan_blend_cso.c',
   'pan_pretty_print.c',
   'pan_fragment.c',
   'pan_invocation.c',
diff --git a/src/gallium/drivers/panfrost/pan_blend.h 
b/src/gallium/drivers/panfrost/pan_blend.h
new file mode 100644
index 000..486ed4dc034
--- /dev/null
+++ b/src/gallium/drivers/panfrost/pan_blend.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2019 Collabora
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 
THE
+ * SOFTWARE.
+ *
+ * Authors (Collabora):
+ *   Alyssa Rosenzweig 
+ *
+ */
+
+#ifndef __PAN_BLEND_H
+#define __PAN_BLEND_H
+
+#include "util/hash_table.h"
+
+/* An internal blend shader descriptor, from the compiler */
+
+struct panfrost_blend_shader {
+/* The compiled shader in GPU memory */
+struct panfrost_transfer shader;
+
+/* Byte count of the shader */
+unsigned size;
+
+/* Number of 128-bit work registers required by the shader */
+unsigned work_count;
+
+/* Offset into the shader to patch constants. Zero to disable patching
+ * (it is illogical to have constants at offset 0). */
+unsigned patch_index;
+
+/* First instruction tag (for tagging the pointer) */
+unsigned first_tag;
+};
+
+/* A blend shader descriptor ready for actual use */
+
+struct panfrost_blend_shader_final {
+/* The upload, possibly to transient memory */
+mali_ptr gpu;
+
+/* Same meaning as panfrost_blend_shader */
+unsigned work_count;
+};
+
+struct panfrost_blend_equation_final {
+struct mali_blend_equation *equation;
+float constant;
+};
+
+struct panfrost_blend_rt {
+/* If has_fixed_function is set, equation is the
+ * fixed-function configuration for this blend state */
+
+bool has_fixed_function;
+struct mali_blend_equation equation;
+
+/* Mask of blend color components read */
+unsigned constant_mask;
+
+/* Regardless of fixed-function blending, this is a map of pipe_format
+ * to panfrost_blend_shader */
+
+struct hash_table_u64 *shaders;
+};
+
+struct panfrost_blend_state {
+struct pipe_blend_state base;
+
+struct panfrost_blend_rt rt[PIPE_MAX_COLOR_BUFS];
+};
+
+/* Container for a final blend state, specialized to constants and a
+ * framebuffer formats. */
+
+struct panfrost_blend_final {
+/* Set for a shader, clear for an equation */
+bool is_shader;
+
+union {
+struct panfrost_blend_shader_final shader;
+struct panfrost_blend_equation_final equation;
+};
+};
+
+void
+panfrost_blend_context_init(struct pipe_context *pipe);
+
+struct panfrost_blend_final

[Mesa-dev] [PATCH 39/42] panfrost/mfbd: Handle PIPE_FORMAT_B10G10R10A2_UNORM

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_blending.c |  4 
 src/gallium/drivers/panfrost/pan_mfbd.c | 11 ++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/pan_blending.c 
b/src/gallium/drivers/panfrost/pan_blending.c
index 9412408bf81..3acda3101c3 100644
--- a/src/gallium/drivers/panfrost/pan_blending.c
+++ b/src/gallium/drivers/panfrost/pan_blending.c
@@ -118,6 +118,10 @@ panfrost_can_fixed_blend(enum pipe_format format)
 /* Certain special formats are, too */
 switch (format) {
 case PIPE_FORMAT_B5G6R5_UNORM:
+case PIPE_FORMAT_R10G10B10A2_UNORM:
+case PIPE_FORMAT_B10G10R10A2_UNORM:
+case PIPE_FORMAT_R10G10B10X2_UNORM:
+case PIPE_FORMAT_B10G10R10X2_UNORM:
 return true;
 default:
 return false;
diff --git a/src/gallium/drivers/panfrost/pan_mfbd.c 
b/src/gallium/drivers/panfrost/pan_mfbd.c
index 731bf0dc45d..9515b616314 100644
--- a/src/gallium/drivers/panfrost/pan_mfbd.c
+++ b/src/gallium/drivers/panfrost/pan_mfbd.c
@@ -95,9 +95,14 @@ panfrost_mfbd_format(struct pipe_surface *surf)
 surf->format == PIPE_FORMAT_R32_FLOAT ||
 surf->format == PIPE_FORMAT_R32_UINT ||
 surf->format == PIPE_FORMAT_R32_SINT ||
-surf->format == PIPE_FORMAT_R10G10B10A2_UNORM ||
 surf->format == PIPE_FORMAT_R10G10B10A2_UINT;
 
+bool rgb10_unorm =
+surf->format == PIPE_FORMAT_R10G10B10A2_UNORM ||
+surf->format == PIPE_FORMAT_B10G10R10A2_UNORM ||
+surf->format == PIPE_FORMAT_R10G10B10X2_UNORM ||
+surf->format == PIPE_FORMAT_B10G10R10X2_UNORM;
+
 bool float_64 =
 surf->format == PIPE_FORMAT_R32G32_FLOAT ||
 surf->format == PIPE_FORMAT_R32G32_SINT ||
@@ -127,6 +132,10 @@ panfrost_mfbd_format(struct pipe_surface *surf)
 fmt.unk1 = 0x8400;
 fmt.unk3 = 0x0;
 fmt.nr_channels = MALI_POSITIVE(2);
+} else if (rgb10_unorm) {
+fmt.unk1 = 0x0800;
+fmt.unk3 = 0x6;
+fmt.nr_channels = MALI_POSITIVE(1);
 } else if (float_32) {
 fmt.unk1 = 0x8800;
 fmt.unk3 = 0x0;
-- 
2.20.1

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[Mesa-dev] [PATCH 34/42] panfrost/midgard: Handle pure int formats

2019-07-08 Thread Alyssa Rosenzweig 
I'm not sure I'm totally comfortable with this, but conceptually neither
float nor pure-int formats require any format conversion, except size
conversion. Going from a shaderable format (fp32 or i16, for instance)
into a blendable format (fp16) is a separate question, one we can defer
momentarily while we're not interested in actually blending.

As an aside, I'd be fascinated by an integer-based blending
implementation.

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/nir_lower_framebuffer.c  | 40 ---
 1 file changed, 26 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index d64292bc29e..fddd8e3f12a 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -73,16 +73,20 @@ nir_unorm8_to_float(nir_builder *b, nir_ssa_def *c_native)
 }
 
 static nir_ssa_def *
-nir_float_to_native(nir_builder *b,
-  nir_ssa_def *c_float,
+nir_shader_to_native(nir_builder *b,
+  nir_ssa_def *c_shader,
   const struct util_format_description *desc,
   unsigned bits,
   bool homogenous_bits)
 {
+   bool float_or_pure_int =
+  util_format_is_float(desc->format) ||
+  util_format_is_pure_integer(desc->format);
+
if (util_format_is_unorm8(desc))
-  return nir_float_to_unorm8(b, c_float);
-   else if (util_format_is_float(desc->format) && homogenous_bits)
-  return c_float;
+  return nir_float_to_unorm8(b, c_shader);
+   else if (homogenous_bits && float_or_pure_int)
+  return c_shader; /* type is already correct */
else {
   printf("%s\n", desc->name);
   unreachable("Unknown format name");
@@ -90,16 +94,20 @@ nir_float_to_native(nir_builder *b,
 }
 
 static nir_ssa_def *
-nir_native_to_float(nir_builder *b,
+nir_native_to_shader(nir_builder *b,
nir_ssa_def *c_native,
const struct util_format_description *desc,
unsigned bits,
bool homogenous_bits)
 {
+   bool float_or_pure_int =
+  util_format_is_float(desc->format) ||
+  util_format_is_pure_integer(desc->format);
+
if (util_format_is_unorm8(desc))
   return nir_unorm8_to_float(b, c_native);
-   else if (util_format_is_float(desc->format) && homogenous_bits)
-  return c_native;
+   else if (homogenous_bits && float_or_pure_int)
+  return c_native; /* type is already correct */
else {
   printf("%s\n", desc->name);
   unreachable("Unknown format name");
@@ -159,12 +167,16 @@ nir_lower_framebuffer(nir_shader *shader, enum 
pipe_format format)
nir_ssa_def *c_nir = nir_ssa_for_src(, intr->src[1], 4);
 
/* Format convert */
-   nir_ssa_def *converted = nir_float_to_native(, c_nir, 
format_desc, bits, homogenous_bits);
+   nir_ssa_def *converted = nir_shader_to_native(, c_nir, 
format_desc, bits, homogenous_bits);
 
-   if (raw_bitsize_out == 16)
-  converted = nir_f2f16(, converted);
-   else if (raw_bitsize_out == 32)
-  converted = nir_f2f32(, converted);
+   if (util_format_is_float(format)) {
+  if (raw_bitsize_out == 16)
+ converted = nir_f2f16(, converted);
+  else if (raw_bitsize_out == 32)
+ converted = nir_f2f32(, converted);
+   } else {
+  converted = nir_i2i(, converted, raw_bitsize_out);
+   }
 
/* Rewrite to use a native store by creating a new intrinsic */
nir_intrinsic_instr *new =
@@ -195,7 +207,7 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format 
format)
 
/* Convert the raw value */
nir_ssa_def *raw = >dest.ssa;
-   nir_ssa_def *converted = nir_native_to_float(, raw, 
format_desc, bits, homogenous_bits);
+   nir_ssa_def *converted = nir_native_to_shader(, raw, 
format_desc, bits, homogenous_bits);
 
/* Rewrite to use the converted value */
nir_src rewritten = nir_src_for_ssa(converted);
-- 
2.20.1

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[Mesa-dev] [PATCH 29/42] panfrost: Handle "blend disabled" blend shaders

2019-07-08 Thread Alyssa Rosenzweig 
Normally, disabled blend can definitely be fixed-function'd away, but
if a blend shader is used merely for format conversion rather than
blending, this code path can be nevertheless hit.

Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/pan_blend_shaders.c  | 34 ---
 1 file changed, 22 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_blend_shaders.c 
b/src/gallium/drivers/panfrost/pan_blend_shaders.c
index 91c8fb89688..2b6206545b3 100644
--- a/src/gallium/drivers/panfrost/pan_blend_shaders.c
+++ b/src/gallium/drivers/panfrost/pan_blend_shaders.c
@@ -89,21 +89,31 @@ nir_make_options(const struct pipe_blend_state *blend, 
unsigned nr_cbufs)
 nir_lower_blend_options options;
 
 for (unsigned i = 0; i < nr_cbufs; ++i) {
+/* If blend is disabled, we just use replace mode */
+
 nir_lower_blend_channel rgb = {
-.func = 
util_blend_func_to_shader(blend->rt[i].rgb_func),
-.src_factor = 
util_blend_factor_to_shader(blend->rt[i].rgb_src_factor),
-.dst_factor = 
util_blend_factor_to_shader(blend->rt[i].rgb_dst_factor),
-.invert_src_factor = 
util_blend_factor_is_inverted(blend->rt[i].rgb_src_factor),
-.invert_dst_factor = 
util_blend_factor_is_inverted(blend->rt[i].rgb_dst_factor)
+.func = BLEND_FUNC_ADD,
+.src_factor = BLEND_FACTOR_ZERO,
+.invert_src_factor = true,
+.dst_factor = BLEND_FACTOR_ZERO,
+.invert_dst_factor = false
 };
 
-nir_lower_blend_channel alpha = {
-.func = 
util_blend_func_to_shader(blend->rt[i].alpha_func),
-.src_factor = 
util_blend_factor_to_shader(blend->rt[i].alpha_src_factor),
-.dst_factor = 
util_blend_factor_to_shader(blend->rt[i].alpha_dst_factor),
-.invert_src_factor = 
util_blend_factor_is_inverted(blend->rt[i].alpha_src_factor),
-.invert_dst_factor = 
util_blend_factor_is_inverted(blend->rt[i].alpha_dst_factor)
-};
+nir_lower_blend_channel alpha = rgb;
+
+if (blend->rt[i].blend_enable) {
+rgb.func = 
util_blend_func_to_shader(blend->rt[i].rgb_func);
+rgb.src_factor = 
util_blend_factor_to_shader(blend->rt[i].rgb_src_factor);
+rgb.dst_factor = 
util_blend_factor_to_shader(blend->rt[i].rgb_dst_factor);
+rgb.invert_src_factor = 
util_blend_factor_is_inverted(blend->rt[i].rgb_src_factor);
+rgb.invert_dst_factor = 
util_blend_factor_is_inverted(blend->rt[i].rgb_dst_factor);
+
+alpha.func = 
util_blend_func_to_shader(blend->rt[i].alpha_func);
+alpha.src_factor = 
util_blend_factor_to_shader(blend->rt[i].alpha_src_factor);
+alpha.dst_factor = 
util_blend_factor_to_shader(blend->rt[i].alpha_dst_factor);
+alpha.invert_src_factor = 
util_blend_factor_is_inverted(blend->rt[i].alpha_src_factor);
+alpha.invert_dst_factor = 
util_blend_factor_is_inverted(blend->rt[i].alpha_dst_factor);
+}
 
 options.rt[i].rgb = rgb;
 options.rt[i].alpha = alpha;
-- 
2.20.1

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[Mesa-dev] [PATCH 31/42] panfrost/midgard: Implement preliminary float converters

2019-07-08 Thread Alyssa Rosenzweig 
We'll need some careful handling, but for now, get some baseline code
out for handling float formats in a blend shader.

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/nir_lower_framebuffer.c  | 40 +++
 1 file changed, 33 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 85bb6488e69..d64292bc29e 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -42,6 +42,8 @@
 #include "nir_lower_blend.h"
 #include "util/u_format.h"
 
+/* Converters for UNORM8 formats, e.g. R8G8B8A8_UNORM */
+
 static nir_ssa_def *
 nir_float_to_unorm8(nir_builder *b, nir_ssa_def *c_float)
 {
@@ -70,15 +72,17 @@ nir_unorm8_to_float(nir_builder *b, nir_ssa_def *c_native)
return scaled;
 }
 
-
-
 static nir_ssa_def *
 nir_float_to_native(nir_builder *b,
   nir_ssa_def *c_float,
-  const struct util_format_description *desc)
+  const struct util_format_description *desc,
+  unsigned bits,
+  bool homogenous_bits)
 {
if (util_format_is_unorm8(desc))
   return nir_float_to_unorm8(b, c_float);
+   else if (util_format_is_float(desc->format) && homogenous_bits)
+  return c_float;
else {
   printf("%s\n", desc->name);
   unreachable("Unknown format name");
@@ -88,10 +92,14 @@ nir_float_to_native(nir_builder *b,
 static nir_ssa_def *
 nir_native_to_float(nir_builder *b,
nir_ssa_def *c_native,
-   const struct util_format_description *desc)
+   const struct util_format_description *desc,
+   unsigned bits,
+   bool homogenous_bits)
 {
if (util_format_is_unorm8(desc))
   return nir_unorm8_to_float(b, c_native);
+   else if (util_format_is_float(desc->format) && homogenous_bits)
+  return c_native;
else {
   printf("%s\n", desc->name);
   unreachable("Unknown format name");
@@ -107,6 +115,19 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format 
format)
const struct util_format_description *format_desc =
   util_format_description(format);
 
+   unsigned nr_channels = format_desc->nr_channels;
+   unsigned bits = format_desc->channel[0].size;
+
+   /* Do all channels have the same bit count? */
+   bool homogenous_bits = true;
+
+   for (unsigned c = 1; c < nr_channels; ++c)
+  homogenous_bits &= (format_desc->channel[c].size == bits);
+
+   /* Figure out the formats for the raw */
+   unsigned raw_bitsize_in = bits;
+   unsigned raw_bitsize_out = bits;
+
nir_foreach_function(func, shader) {
   nir_foreach_block(block, func->impl) {
  nir_foreach_instr_safe(instr, block) {
@@ -138,7 +159,12 @@ nir_lower_framebuffer(nir_shader *shader, enum pipe_format 
format)
nir_ssa_def *c_nir = nir_ssa_for_src(, intr->src[1], 4);
 
/* Format convert */
-   nir_ssa_def *converted = nir_float_to_native(, c_nir, 
format_desc);
+   nir_ssa_def *converted = nir_float_to_native(, c_nir, 
format_desc, bits, homogenous_bits);
+
+   if (raw_bitsize_out == 16)
+  converted = nir_f2f16(, converted);
+   else if (raw_bitsize_out == 32)
+  converted = nir_f2f32(, converted);
 
/* Rewrite to use a native store by creating a new intrinsic */
nir_intrinsic_instr *new =
@@ -163,13 +189,13 @@ nir_lower_framebuffer(nir_shader *shader, enum 
pipe_format format)
 
new->num_components = 4;
 
-   unsigned bitsize = 8;
+   unsigned bitsize = raw_bitsize_in;
nir_ssa_dest_init(>instr, >dest, 4, bitsize, NULL);
nir_builder_instr_insert(, >instr);
 
/* Convert the raw value */
nir_ssa_def *raw = >dest.ssa;
-   nir_ssa_def *converted = nir_native_to_float(, raw, 
format_desc);
+   nir_ssa_def *converted = nir_native_to_float(, raw, 
format_desc, bits, homogenous_bits);
 
/* Rewrite to use the converted value */
nir_src rewritten = nir_src_for_ssa(converted);
-- 
2.20.1

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[Mesa-dev] [PATCH 30/42] panfrost/midgard: Skip blend for REPLACE (shader)

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/nir_lower_blend.c| 23 +++
 1 file changed, 23 insertions(+)

diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c
index af0a7ac31cf..0fadeba6674 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.c
@@ -200,12 +200,35 @@ nir_blend(
return nir_color_mask(b, options.rt[0].colormask, blended, dst);
 }
 
+static bool
+nir_is_blend_channel_replace(nir_lower_blend_channel chan)
+{
+   return
+  (chan.src_factor == BLEND_FACTOR_ZERO) &&
+  (chan.dst_factor == BLEND_FACTOR_ZERO) &&
+  (chan.invert_src_factor && !chan.invert_dst_factor) &&
+  (chan.func == BLEND_FUNC_ADD || chan.func == BLEND_FUNC_SUBTRACT || 
chan.func == BLEND_FUNC_MAX);
+}
+
+static bool
+nir_is_blend_replace(nir_lower_blend_options options)
+{
+   return
+  nir_is_blend_channel_replace(options.rt[0].rgb) &&
+  nir_is_blend_channel_replace(options.rt[0].alpha);
+}
+
 void
 nir_lower_blend(nir_shader *shader, nir_lower_blend_options options)
 {
/* Blend shaders are represented as special fragment shaders */
assert(shader->info.stage == MESA_SHADER_FRAGMENT);
 
+   /* Special case replace, since there's nothing to do and we don't want to
+* degrade intermediate precision (e.g. for non-blendable R32F targets) */
+   if (nir_is_blend_replace(options))
+  return;
+
nir_foreach_function(func, shader) {
   nir_foreach_block(block, func->impl) {
  nir_foreach_instr_safe(instr, block) {
-- 
2.20.1

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[Mesa-dev] [PATCH 28/42] panfrost: Route format through fixed-function blending

2019-07-08 Thread Alyssa Rosenzweig 
Not all framebuffer formats are supported by the fixed-function blender.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_blending.c | 41 -
 src/gallium/drivers/panfrost/pan_blending.h |  7 +++-
 src/gallium/drivers/panfrost/pan_context.c  | 11 +++---
 3 files changed, 51 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_blending.c 
b/src/gallium/drivers/panfrost/pan_blending.c
index 14f99f64edd..6bdc8395d18 100644
--- a/src/gallium/drivers/panfrost/pan_blending.c
+++ b/src/gallium/drivers/panfrost/pan_blending.c
@@ -26,6 +26,7 @@
 #include "pan_blending.h"
 #include "pan_context.h"
 #include "gallium/auxiliary/util/u_blend.h"
+#include "util/u_format.h"
 
 /*
  * Implements fixed-function blending on Midgard.
@@ -98,6 +99,34 @@
  * The following routines implement this fixed function blending encoding
  */
 
+/* Not all formats can be blended by fixed-function hardware */
+
+static bool
+panfrost_can_blend(enum pipe_format format)
+{
+/* Fixed-function can handle sRGB */
+format = util_format_linear(format);
+
+/* Decompose the format */
+const struct util_format_description *desc =
+util_format_description(format);
+
+/* Any 8-bit unorm is supported */
+if (util_format_is_unorm8(desc))
+return true;
+
+/* Certain special formats are, too */
+switch (format) {
+case PIPE_FORMAT_B5G6R5_UNORM:
+case PIPE_FORMAT_B4G4R4A4_UNORM:
+case PIPE_FORMAT_B5G5R5A1_UNORM:
+case PIPE_FORMAT_R10G10B10A2_UNORM:
+return true;
+default:
+return false;
+}
+}
+
 /* Helper to find the uncomplemented Gallium blend factor corresponding to a
  * complemented Gallium blend factor */
 
@@ -345,10 +374,20 @@ panfrost_make_constant(unsigned *factors, unsigned 
num_factors, const struct pip
  */
 
 bool
-panfrost_make_fixed_blend_mode(const struct pipe_rt_blend_state *blend, struct 
panfrost_blend_state *so, unsigned colormask, const struct pipe_blend_color 
*blend_color)
+panfrost_make_fixed_blend_mode(
+const struct pipe_rt_blend_state *blend,
+struct panfrost_blend_state *so,
+unsigned colormask,
+const struct pipe_blend_color *blend_color,
+enum pipe_format format)
 {
 struct mali_blend_equation *out = >equation;
 
+/* Check if the format supports fixed-function blending at all */
+
+if (!panfrost_can_blend(format))
+return false;
+
 /* Gallium and Mali represent colour masks identically. XXX: Static 
assert for future proof */
 out->color_mask = colormask;
 
diff --git a/src/gallium/drivers/panfrost/pan_blending.h 
b/src/gallium/drivers/panfrost/pan_blending.h
index 8ddd81147eb..4be0c4d4385 100644
--- a/src/gallium/drivers/panfrost/pan_blending.h
+++ b/src/gallium/drivers/panfrost/pan_blending.h
@@ -31,6 +31,11 @@
 
 struct panfrost_blend_state;
 
-bool panfrost_make_fixed_blend_mode(const struct pipe_rt_blend_state *blend, 
struct panfrost_blend_state *so, unsigned colormask, const struct 
pipe_blend_color *blend_color);
+bool panfrost_make_fixed_blend_mode(
+const struct pipe_rt_blend_state *blend,
+struct panfrost_blend_state *so,
+unsigned colormask,
+const struct pipe_blend_color *blend_color,
+enum pipe_format format);
 
 #endif
diff --git a/src/gallium/drivers/panfrost/pan_context.c 
b/src/gallium/drivers/panfrost/pan_context.c
index be5d0a14cf5..c26a6dbaabb 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -2378,15 +2378,14 @@ panfrost_create_blend_state(struct pipe_context *pipe,
 
 /* Compile the blend state, first as fixed-function if we can */
 
-if (panfrost_make_fixed_blend_mode(>rt[0], so, 
blend->rt[0].colormask, >blend_color))
-return so;
+/* TODO: Key by format */
+enum pipe_format format = ctx->pipe_framebuffer.nr_cbufs ?
+ctx->pipe_framebuffer.cbufs[0]->format :
+PIPE_FORMAT_R8G8B8A8_UNORM;
 
-/* TODO: Key against framebuffer. TODO: MRT explicitly */
-if (!ctx->pipe_framebuffer.nr_cbufs)
+if (panfrost_make_fixed_blend_mode(>rt[0], so, 
blend->rt[0].colormask, >blend_color, format))
 return so;
 
-enum pipe_format format = ctx->pipe_framebuffer.cbufs[0]->format;
-
 /* If we can't, compile a blend shader instead */
 
 panfrost_make_blend_shader(ctx, so, >blend_color, format);
-- 
2.20.1

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[Mesa-dev] [PATCH 18/42] panfrost/midgard: Allow fp16 in scalar ALU

2019-07-08 Thread Alyssa Rosenzweig 
The packing is a little different, so implement that.

Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/midgard_emit.c   | 47 ++-
 .../panfrost/midgard/midgard_schedule.c   | 21 +++--
 2 files changed, 52 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_emit.c 
b/src/gallium/drivers/panfrost/midgard/midgard_emit.c
index 3c331551dd8..701ef1074ff 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_emit.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_emit.c
@@ -29,11 +29,15 @@
  * this, we just demote vector ALU payloads to scalar. */
 
 static int
-component_from_mask(unsigned mask)
+component_from_mask(unsigned mask, bool full)
 {
-for (int c = 0; c < 4; ++c) {
-if (mask & (3 << (2 * c)))
+for (int c = 0; c < 8; ++c) {
+if (mask & (1 << c))
 return c;
+
+/* Full uses every other bit */
+if (full)
+c++;
 }
 
 assert(0);
@@ -41,17 +45,35 @@ component_from_mask(unsigned mask)
 }
 
 static unsigned
-vector_to_scalar_source(unsigned u, bool is_int)
+vector_to_scalar_source(unsigned u, bool is_int, bool is_full)
 {
 midgard_vector_alu_src v;
 memcpy(, , sizeof(v));
 
 /* TODO: Integers */
 
-midgard_scalar_alu_src s = {
-.full = !v.half,
-.component = (v.swizzle & 3) << 1
-};
+unsigned component = v.swizzle & 3;
+bool upper = false; /* TODO */
+
+midgard_scalar_alu_src s = { 0 };
+
+if (is_full) {
+/* For a 32-bit op, just check the source half flag */
+s.full = !v.half;
+} else if (!v.half) {
+/* For a 16-bit op that's not subdivided, never full */
+s.full = false;
+} else {
+/* We can't do 8-bit scalar, abort! */
+assert(0);
+}
+
+/* Component indexing takes size into account */
+
+if (s.full)
+s.component = component << 1;
+else
+s.component = component + (upper << 2);
 
 if (is_int) {
 /* TODO */
@@ -70,16 +92,17 @@ static midgard_scalar_alu
 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins)
 {
 bool is_int = midgard_is_integer_op(v.op);
+bool is_full = v.reg_mode == midgard_reg_mode_32;
 
 /* The output component is from the mask */
 midgard_scalar_alu s = {
 .op = v.op,
-.src1 = vector_to_scalar_source(v.src1, is_int),
-.src2 = vector_to_scalar_source(v.src2, is_int),
+.src1 = vector_to_scalar_source(v.src1, is_int, is_full),
+.src2 = vector_to_scalar_source(v.src2, is_int, is_full),
 .unknown = 0,
 .outmod = v.outmod,
-.output_full = 1, /* TODO: Half */
-.output_component = component_from_mask(v.mask) << 1,
+.output_full = is_full,
+.output_component = component_from_mask(v.mask, is_full),
 };
 
 /* Inline constant is passed along rather than trying to extract it
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c 
b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
index c0dd5764595..77738731b8a 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
@@ -44,14 +44,19 @@ swizzle_to_access_mask(unsigned swizzle)
 /* Does the mask cover more than a scalar? */
 
 static bool
-is_single_component_mask(unsigned mask)
+is_single_component_mask(unsigned mask, bool full)
 {
 int components = 0;
 
-for (int c = 0; c < 4; ++c)
-if (mask & (3 << (2 * c)))
+for (int c = 0; c < 8; ++c) {
+if (mask & (1 << c))
 components++;
 
+/* Full uses 2-bit components */
+if (full)
+c++;
+}
+
 return components == 1;
 }
 
@@ -193,9 +198,17 @@ schedule_bundle(compiler_context *ctx, midgard_block 
*block, midgard_instruction
 
 bool vectorable = units & UNITS_ANY_VECTOR;
 bool scalarable = units & UNITS_SCALAR;
-bool could_scalar = 
is_single_component_mask(ains->alu.mask);
+bool full = ains->alu.reg_mode == 
midgard_reg_mode_32;
+bool could_scalar = 
is_single_component_mask(ains->alu.mask, full);
 bool vector = vectorable && !(could_scalar && 
scalarable);
 
+/* Only 16/32-bit can run on a scalar unit */
+could_scalar &= ains->alu.reg_mode != 
midgard_reg_mode_8;

[Mesa-dev] [PATCH 13/42] panfrost/midgard: Move blend shader loads to NIR

2019-07-08 Thread Alyssa Rosenzweig 
The scale and type-convert can now be expressed in NIR, rather than MIR,
which is significantly more maintainable and demonstrates correctness of
the type conversion patches.

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 52 ---
 .../panfrost/midgard/nir_lower_framebuffer.c  | 10 +++-
 2 files changed, 8 insertions(+), 54 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index b7379426b38..70e9666ce71 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1255,58 +1255,6 @@ emit_fb_read_blend_scalar(compiler_context *ctx, 
unsigned reg)
 ins.load_store.unknown = c;
 emit_mir_instruction(ctx, ins);
 }
-
-/* vadd.u2f hr2, zext(hr2), #0 */
-
-midgard_vector_alu_src alu_src = blank_alu_src;
-alu_src.mod = midgard_int_zero_extend;
-alu_src.half = true;
-
-midgard_instruction u2f = {
-.type = TAG_ALU_4,
-.ssa_args = {
-.src0 = reg,
-.src1 = SSA_UNUSED_0,
-.dest = reg,
-.inline_constant = true
-},
-.alu = {
-.op = midgard_alu_op_u2f_rtz,
-.reg_mode = midgard_reg_mode_16,
-.dest_override = midgard_dest_override_none,
-.mask = 0xF,
-.src1 = vector_alu_srco_unsigned(alu_src),
-.src2 = vector_alu_srco_unsigned(blank_alu_src),
-}
-};
-
-emit_mir_instruction(ctx, u2f);
-
-/* vmul.fmul.sat r1, hr2, #0.00392151 */
-
-alu_src.mod = 0;
-
-midgard_instruction fmul = {
-.type = TAG_ALU_4,
-.inline_constant = _mesa_float_to_half(1.0 / 255.0),
-.ssa_args = {
-.src0 = reg,
-.dest = reg,
-.src1 = SSA_UNUSED_0,
-.inline_constant = true
-},
-.alu = {
-.op = midgard_alu_op_fmul,
-.reg_mode = midgard_reg_mode_32,
-.dest_override = midgard_dest_override_none,
-.outmod = midgard_outmod_sat,
-.mask = 0xFF,
-.src1 = vector_alu_srco_unsigned(alu_src),
-.src2 = vector_alu_srco_unsigned(blank_alu_src),
-}
-};
-
-emit_mir_instruction(ctx, fmul);
 }
 
 static void
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 08ef290a20b..5f3115b6ae8 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -57,7 +57,13 @@ nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
 static nir_ssa_def *
 nir_native_to_float(nir_builder *b, nir_ssa_def *c_native)
 {
-   return c_native;
+   /* First, we convert up from u8 to f32 */
+   nir_ssa_def *converted = nir_u2f32(b, nir_u2u32(b, c_native));
+
+   /* Next, we scale down from [0, 255.0] to [0, 1] */
+   nir_ssa_def *scaled = nir_fsat(b, nir_fmul_imm(b, converted, 1.0/255.0));
+
+   return scaled;
 }
 
 void
@@ -122,7 +128,7 @@ nir_lower_framebuffer(nir_shader *shader)
 
new->num_components = 4;
 
-   unsigned bitsize = 32;
+   unsigned bitsize = 8;
nir_ssa_dest_init(>instr, >dest, 4, bitsize, NULL);
nir_builder_instr_insert(, >instr);
 
-- 
2.20.1

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[Mesa-dev] [PATCH 16/42] panfrost/midgard: Implement f2f16/f2f32

2019-07-08 Thread Alyssa Rosenzweig 
These conversions handle half-floats within the shader.

Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/midgard_compile.c | 18 ++
 .../panfrost/midgard/midgard_nir_algebraic.py  |  5 -
 .../panfrost/midgard/nir_lower_framebuffer.c   |  7 +--
 3 files changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 353875d173f..fc17ad2b051 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -907,6 +907,24 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 break;
 }
 
+case nir_op_f2f16: {
+assert(src_bitsize == 32);
+
+op = midgard_alu_op_fmov;
+dest_override = midgard_dest_override_lower;
+break;
+}
+
+case nir_op_f2f32: {
+assert(src_bitsize == 16);
+
+op = midgard_alu_op_fmov;
+half_2 = true;
+reg_mode++;
+break;
+}
+
+
 /* For greater-or-equal, we lower to less-or-equal and flip the
  * arguments */
 
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py 
b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
index b05c193e507..871195b48ca 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
+++ b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
@@ -53,7 +53,10 @@ converts = [
 (('u2u8', 'a@32'), ('u2u8', ('u2u16', a))),
 
 (('i2i32', 'a@8'), ('i2i32', ('i2i16', a))),
-(('u2u32', 'a@8'), ('u2u32', ('u2u16', a)))
+(('u2u32', 'a@8'), ('u2u32', ('u2u16', a))),
+
+(('f2i32', 'a@16'), ('f2i32', ('f2f32', a))),
+(('f2u32', 'a@16'), ('f2u32', ('f2f32', a))),
 ]
 
 # Midgard scales fsin/fcos arguments by pi.
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 5f3115b6ae8..5233fbc9280 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -44,8 +44,11 @@
 static nir_ssa_def *
 nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
 {
-   /* First, we scale from [0, 1] to [0, 255.0] */
-   nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, c_float), 255.0);
+   /* First, we degrade quality to fp16; we don't need the extra bits */
+   nir_ssa_def *degraded = nir_f2f16(b, c_float);
+
+   /* Scale from [0, 1] to [0, 255.0] */
+   nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, degraded), 255.0);
 
/* Next, we type convert */
nir_ssa_def *converted = nir_u2u8(b, nir_f2u32(b,
-- 
2.20.1

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[Mesa-dev] [PATCH 14/42] panfrost/midgard: Simplify blend read

2019-07-08 Thread Alyssa Rosenzweig 
It's not clear where the extra indirection was from (older hardware or
just older blobs?)

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 28 ---
 1 file changed, 5 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 70e9666ce71..8edde597cb6 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1236,27 +1236,6 @@ emit_sysval_read(compiler_context *ctx, nir_instr *instr)
 emit_ubo_read(ctx, dest, uniform, NULL, 0);
 }
 
-/* Reads RGBA value from the tilebuffer and converts to a RGBA32F register,
- * using scalar ops functional on earlier Midgard generations. Newer Midgard
- * generations have faster vectorized reads. This operation is for blend
- * shaders in particular; reading the tilebuffer from the fragment shader
- * remains an open problem. */
-
-static void
-emit_fb_read_blend_scalar(compiler_context *ctx, unsigned reg)
-{
-midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
-ins.load_store.swizzle = 0; /*  */
-
-/* Read each component sequentially */
-
-for (unsigned c = 0; c < 4; ++c) {
-ins.load_store.mask = (1 << c);
-ins.load_store.unknown = c;
-emit_mir_instruction(ctx, ins);
-}
-}
-
 static void
 emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
 {
@@ -1367,11 +1346,14 @@ emit_intrinsic(compiler_context *ctx, 
nir_intrinsic_instr *instr)
 break;
}
 
-/* Reads off the tilebuffer during blending, tasty */
+/* Reads 128-bit value raw off the tilebuffer during blending, tasty */
+
 case nir_intrinsic_load_raw_output_pan:
 reg = nir_dest_index(ctx, >dest);
 assert(ctx->is_blend);
-emit_fb_read_blend_scalar(ctx, reg);
+
+midgard_instruction ins = m_ld_color_buffer_8(reg, 0);
+emit_mir_instruction(ctx, ins);
 break;
 
 case nir_intrinsic_load_blend_const_color_rgba: {
-- 
2.20.1

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[Mesa-dev] [PATCH 21/42] panfrost/midgard: Eliminate redundant type convert

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py 
b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
index 871195b48ca..951b4b23241 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
+++ b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
@@ -57,6 +57,9 @@ converts = [
 
 (('f2i32', 'a@16'), ('f2i32', ('f2f32', a))),
 (('f2u32', 'a@16'), ('f2u32', ('f2f32', a))),
+
+# Totally redundant
+(('~f2f16', ('f2f32', 'a@16')), a),
 ]
 
 # Midgard scales fsin/fcos arguments by pi.
-- 
2.20.1

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[Mesa-dev] [PATCH 19/42] panfrost/midgard: Hoist mask field

2019-07-08 Thread Alyssa Rosenzweig 
Share a single mask field in midgard_instruction with a unified format,
rather than using separate masks for each instruction tag with
hardware-specific formats. Eliminates quite a bit of duplicated code and
will enable vec8/vec16 masks as well (which don't map as cleanly to the
hardware as we might like).

Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/compiler.h   |  7 ++-
 .../drivers/panfrost/midgard/helpers.h| 21 ++---
 .../panfrost/midgard/midgard_compile.c| 43 +--
 .../drivers/panfrost/midgard/midgard_emit.c   | 27 +---
 .../drivers/panfrost/midgard/midgard_ops.h|  9 ++--
 .../drivers/panfrost/midgard/midgard_ra.c | 25 ---
 .../panfrost/midgard/midgard_schedule.c   | 18 +++-
 7 files changed, 70 insertions(+), 80 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/compiler.h 
b/src/gallium/drivers/panfrost/midgard/compiler.h
index 4c2202711b1..5fe1d80692c 100644
--- a/src/gallium/drivers/panfrost/midgard/compiler.h
+++ b/src/gallium/drivers/panfrost/midgard/compiler.h
@@ -120,6 +120,11 @@ typedef struct midgard_instruction {
 bool writeout;
 bool prepacked_branch;
 
+/* Masks in a saneish format. One bit per channel, not packed fancy.
+ * Use this instead of the op specific ones, and switch over at emit
+ * time */
+uint16_t mask;
+
 union {
 midgard_load_store_word load_store;
 midgard_vector_alu alu;
@@ -398,6 +403,7 @@ v_mov(unsigned src, midgard_vector_alu_src mod, unsigned 
dest)
 {
 midgard_instruction ins = {
 .type = TAG_ALU_4,
+.mask = 0xF,
 .ssa_args = {
 .src0 = SSA_UNUSED_1,
 .src1 = src,
@@ -408,7 +414,6 @@ v_mov(unsigned src, midgard_vector_alu_src mod, unsigned 
dest)
 .reg_mode = midgard_reg_mode_32,
 .dest_override = midgard_dest_override_none,
 .outmod = midgard_outmod_int_wrap,
-.mask = 0xFF,
 .src1 = vector_alu_srco_unsigned(zero_alu_src),
 .src2 = vector_alu_srco_unsigned(mod)
 },
diff --git a/src/gallium/drivers/panfrost/midgard/helpers.h 
b/src/gallium/drivers/panfrost/midgard/helpers.h
index 25def4c85b3..4a395a4c8cd 100644
--- a/src/gallium/drivers/panfrost/midgard/helpers.h
+++ b/src/gallium/drivers/panfrost/midgard/helpers.h
@@ -217,13 +217,11 @@ struct mir_op_props {
 /* This file is common, so don't define the tables themselves. #include
  * midgard_op.h if you need that, or edit midgard_ops.c directly */
 
-/* Duplicate bits to convert standard 4-bit writemask to duplicated 8-bit
- * format (or do the inverse). The 8-bit format only really matters for
- * int8, as far as I know, where performance can be improved by using a
- * vec8 output */
+/* Duplicate bits to convert a 4-bit writemask to duplicated 8-bit format,
+ * which is used for 32-bit vector units */
 
 static inline unsigned
-expand_writemask(unsigned mask)
+expand_writemask_32(unsigned mask)
 {
 unsigned o = 0;
 
@@ -234,19 +232,6 @@ expand_writemask(unsigned mask)
 return o;
 }
 
-static inline unsigned
-squeeze_writemask(unsigned mask)
-{
-unsigned o = 0;
-
-for (int i = 0; i < 4; ++i)
-if (mask & (3 << (2 * i)))
-o |= (1 << i);
-
-return o;
-
-}
-
 /* Coerce structs to integer */
 
 static inline unsigned
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 21197efa499..de40eeafdd5 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -88,6 +88,7 @@ midgard_block_add_successor(midgard_block *block, 
midgard_block *successor)
static midgard_instruction m_##name(unsigned ssa, unsigned address) { \
midgard_instruction i = { \
.type = TAG_LOAD_STORE_4, \
+.mask = 0xF, \
.ssa_args = { \
.rname = ssa, \
.uname = -1, \
@@ -95,7 +96,6 @@ midgard_block_add_successor(midgard_block *block, 
midgard_block *successor)
}, \
.load_store = { \
.op = midgard_op_##name, \
-   .mask = 0xF, \
.swizzle = SWIZZLE_XYZW, \
.address = address \
} \
@@ -596,6 +596,7 @@ emit_condition(compiler_context *ctx, nir_src *src, bool 
for_branch, unsigned co
 /* We need to set the conditional as close as possible */
 .precede_break = true,
 .unit = for_branch ?

[Mesa-dev] [PATCH 22/42] panfrost/midgard: Handle fp16 in embedded_to_inline_constants

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_compile.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index de40eeafdd5..b7498d43501 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1880,6 +1880,13 @@ embedded_to_inline_constant(compiler_context *ctx)
 /* Blend constants must not be inlined by definition */
 if (ins->has_blend_constant) continue;
 
+/* We can inline 32-bit (sometimes) or 16-bit (usually) */
+bool is_16 = ins->alu.reg_mode == midgard_reg_mode_16;
+bool is_32 = ins->alu.reg_mode == midgard_reg_mode_32;
+
+if (!(is_16 || is_32))
+continue;
+
 /* src1 cannot be an inline constant due to encoding
  * restrictions. So, if possible we try to flip the arguments
  * in that case */
@@ -1930,7 +1937,7 @@ embedded_to_inline_constant(compiler_context *ctx)
 /* Scale constant appropriately, if we can legally */
 uint16_t scaled_constant = 0;
 
-if (midgard_is_integer_op(op)) {
+if (midgard_is_integer_op(op) || is_16) {
 unsigned int *iconstants = (unsigned int *) 
ins->constants;
 scaled_constant = (uint16_t) 
iconstants[component];
 
-- 
2.20.1

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[Mesa-dev] [PATCH 10/42] panfrost/midgard: Route blend load intrinsic

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 17 +++---
 .../panfrost/midgard/nir_lower_framebuffer.c  | 33 +--
 2 files changed, 36 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 0f51104a19d..292c6dc363d 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1380,18 +1380,11 @@ emit_intrinsic(compiler_context *ctx, 
nir_intrinsic_instr *instr)
 break;
}
 
-case nir_intrinsic_load_output:
-assert(nir_src_is_const(instr->src[0]));
+/* Reads off the tilebuffer during blending, tasty */
+case nir_intrinsic_load_raw_output_pan:
 reg = nir_dest_index(ctx, >dest);
-
-if (ctx->is_blend) {
-/* TODO: MRT */
-emit_fb_read_blend_scalar(ctx, reg);
-} else {
-DBG("Unknown output load\n");
-assert(0);
-}
-
+assert(ctx->is_blend);
+emit_fb_read_blend_scalar(ctx, reg);
 break;
 
 case nir_intrinsic_load_blend_const_color_rgba: {
@@ -1460,7 +1453,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr 
*instr)
 break;
 
 /* Special case of store_output for lowered blend shaders */
-case nir_intrinsic_store_blended_output:
+case nir_intrinsic_store_raw_output_pan:
 assert (ctx->stage == MESA_SHADER_FRAGMENT);
 reg = nir_src_index(ctx, >src[0]);
 
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 580df9d7442..08ef290a20b 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -54,6 +54,12 @@ nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
return converted;
 }
 
+static nir_ssa_def *
+nir_native_to_float(nir_builder *b, nir_ssa_def *c_native)
+{
+   return c_native;
+}
+
 void
 nir_lower_framebuffer(nir_shader *shader)
 {
@@ -95,7 +101,7 @@ nir_lower_framebuffer(nir_shader *shader)
 
/* Rewrite to use a native store by creating a new intrinsic */
nir_intrinsic_instr *new =
-  nir_intrinsic_instr_create(shader, 
nir_intrinsic_store_blended_output);
+  nir_intrinsic_instr_create(shader, 
nir_intrinsic_store_raw_output_pan);
new->src[0] = nir_src_for_ssa(converted);
 
/* TODO: What about non-RGBA? Is that different? */
@@ -106,7 +112,30 @@ nir_lower_framebuffer(nir_shader *shader)
/* (And finally removing the old) */
nir_instr_remove(instr);
 } else {
-   /* TODO loads */
+   /* For loads, add conversion after */
+   b.cursor = nir_after_instr(instr);
+
+   /* Rewrite to use a native load by creating a new intrinsic */
+
+   nir_intrinsic_instr *new =
+  nir_intrinsic_instr_create(shader, 
nir_intrinsic_load_raw_output_pan);
+
+   new->num_components = 4;
+
+   unsigned bitsize = 32;
+   nir_ssa_dest_init(>instr, >dest, 4, bitsize, NULL);
+   nir_builder_instr_insert(, >instr);
+
+   /* Convert the raw value */
+   nir_ssa_def *raw = >dest.ssa;
+   nir_ssa_def *converted = nir_native_to_float(, raw);
+
+   /* Rewrite to use the converted value */
+   nir_src rewritten = nir_src_for_ssa(converted);
+   nir_ssa_def_rewrite_uses_after(>dest.ssa, rewritten, 
instr);
+
+   /* Finally, remove the old load */
+   nir_instr_remove(instr);
 }
  }
   }
-- 
2.20.1

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[Mesa-dev] [PATCH 15/42] panfrost/midgard: Verify src_bitsize == dst_bitsize

2019-07-08 Thread Alyssa Rosenzweig 
We can handle differing, but we'd prefer not to because there are
restrictions on sizing which aren't accounted for yet.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_compile.c | 9 +
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 8edde597cb6..353875d173f 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -690,12 +690,14 @@ emit_indirect_offset(compiler_context *ctx, nir_src *src)
 #define ALU_CASE(nir, _op) \
case nir_op_##nir: \
op = midgard_alu_op_##_op; \
+assert(src_bitsize == dst_bitsize); \
break;
 
 #define ALU_CASE_BCAST(nir, _op, count) \
 case nir_op_##nir: \
 op = midgard_alu_op_##_op; \
 broadcast_swizzle = count; \
+assert(src_bitsize == dst_bitsize); \
 break;
 static bool
 nir_is_fzero_constant(nir_src src)
@@ -773,6 +775,9 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 bool half_1 = false, sext_1 = false;
 bool half_2 = false, sext_2 = false;
 
+unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
+unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
+
 switch (instr->op) {
 ALU_CASE(fadd, fadd);
 ALU_CASE(fmul, fmul);
@@ -888,10 +893,6 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 case nir_op_u2u32: {
 op = midgard_alu_op_imov;
 
-unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
-unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
-
-
 if (dst_bitsize == (src_bitsize * 2)) {
 /* Converting up */
 half_2 = true;
-- 
2.20.1

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[Mesa-dev] [PATCH 12/42] panfrost/midgard: Fix blend constant scheduling bug

2019-07-08 Thread Alyssa Rosenzweig 
Blend constant conflicts run in two directions.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_schedule.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c 
b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
index 7059f7bbe2a..c0dd5764595 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_schedule.c
@@ -257,6 +257,10 @@ schedule_bundle(compiler_context *ctx, midgard_block 
*block, midgard_instruction
  * the swizzle */
 
 if (ains->has_blend_constant) {
+/* Everything conflicts with the blend 
constant */
+if (bundle.has_embedded_constants)
+break;
+
 bundle.has_blend_constant = 1;
 bundle.has_embedded_constants = 1;
 } else if (ains->has_constants) {
-- 
2.20.1

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[Mesa-dev] [PATCH 08/42] panfrost/midgard: Use nir_dest_num_components

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/midgard/midgard_compile.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 32cc55c52ee..dba6cb2f6f9 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -732,7 +732,7 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 bool is_ssa = instr->dest.dest.is_ssa;
 
 unsigned dest = nir_dest_index(ctx, >dest.dest);
-unsigned nr_components = is_ssa ? instr->dest.dest.ssa.num_components 
: instr->dest.dest.reg.reg->num_components;
+unsigned nr_components = nir_dest_num_components(instr->dest.dest);
 unsigned nr_inputs = nir_op_infos[instr->op].num_inputs;
 
 /* Most Midgard ALU ops have a 1:1 correspondance to NIR ops; these are
-- 
2.20.1

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[Mesa-dev] [PATCH 07/42] panfrost/midgard: Implement integer downsize ops

2019-07-08 Thread Alyssa Rosenzweig 
Oh, dear. No turning back now.

We begin implementing non-32-bit types, using downsizing integer type
conversions as the initial instructions. We implement them naively as
type-converting moves; substantially more efficient operation is
possible by copypropping the type conversion modifier, but this
optimization is not implemented here.

Size converting modifiers on Midgard allow an instruction to write to a
destination 1/2 the size, or to read from a source 1/2 the size. If we
need an extreme conversion (32-bit to 8-bit, for instance), multiple
type converting ops are chained together, which here is handled via an
algebraic pass.

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 51 ++-
 .../panfrost/midgard/midgard_nir_algebraic.py | 14 -
 2 files changed, 62 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 39b8d9c1005..32cc55c52ee 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -703,6 +703,29 @@ nir_is_fzero_constant(nir_src src)
 return true;
 }
 
+/* Analyze the sizes of inputs/outputs to determine which reg mode to run an
+ * ALU instruction in. Right now, we just consider the size of the first
+ * argument. This will fail for upconverting, for instance (TODO) */
+
+static midgard_reg_mode
+reg_mode_for_nir(nir_alu_instr *instr)
+{
+unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
+
+switch (src_bitsize) {
+case 8:
+return midgard_reg_mode_8;
+case 16:
+return midgard_reg_mode_16;
+case 32:
+return midgard_reg_mode_32;
+case 64:
+return midgard_reg_mode_64;
+default:
+unreachable("Invalid bit size");
+}
+}
+
 static void
 emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 {
@@ -728,6 +751,12 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 
 unsigned broadcast_swizzle = 0;
 
+/* Do we need a destination override? Used for inline
+ * type conversion */
+
+midgard_dest_override dest_override =
+midgard_dest_override_none;
+
 switch (instr->op) {
 ALU_CASE(fadd, fadd);
 ALU_CASE(fmul, fmul);
@@ -824,6 +853,20 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 ALU_CASE(fneg, fmov);
 ALU_CASE(fsat, fmov);
 
+/* For size conversion, we use a move. Ideally though we would squash
+ * these ops together; maybe that has to happen after in NIR as part of
+ * propagation...? An earlier algebraic pass ensured we step down by
+ * only / exactly one size */
+
+case nir_op_u2u8:
+case nir_op_u2u16:
+case nir_op_i2i8:
+case nir_op_i2i16: {
+op = midgard_alu_op_imov;
+dest_override = midgard_dest_override_lower;
+break;
+}
+
 /* For greater-or-equal, we lower to less-or-equal and flip the
  * arguments */
 
@@ -958,8 +1001,8 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 
 midgard_vector_alu alu = {
 .op = op,
-.reg_mode = midgard_reg_mode_32,
-.dest_override = midgard_dest_override_none,
+.reg_mode = reg_mode_for_nir(instr),
+.dest_override = dest_override,
 .outmod = outmod,
 
 /* Writemask only valid for non-SSA NIR */
@@ -2077,6 +2120,10 @@ mir_nontrivial_outmod(midgard_instruction *ins)
 bool is_int = midgard_is_integer_op(ins->alu.op);
 unsigned mod = ins->alu.outmod;
 
+/* Type conversion is a sort of outmod */
+if (ins->alu.dest_override != midgard_dest_override_none)
+return true;
+
 if (is_int)
 return mod != midgard_outmod_int_wrap;
 else
diff --git a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py 
b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
index df0caa26640..b05c193e507 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
+++ b/src/gallium/drivers/panfrost/midgard/midgard_nir_algebraic.py
@@ -44,6 +44,18 @@ algebraic_late = [
 (('b32csel', a, 0, 'b@32'), ('iand', ('inot', a), b)),
 ]
 
+
+# Midgard is able to type convert down by only one "step" per instruction; if
+# NIR wants more than one step, we need to break up into multiple instructions
+
+converts = [
+(('i2i8', 'a@32'), ('i2i8', ('i2i16', a))),
+(('u2u8', 'a@32'), ('u2u8', ('u2u16', a))),
+
+(('i2i32', 'a@8'), ('i2i32', ('i2i16', a))),
+(('u2u32', 'a@8'), ('u2u32', ('u2u16', a)))
+]
+
 # Midgard scales

[Mesa-dev] [PATCH 05/42] panfrost/midgard: Move scale from MIR to NIR

2019-07-08 Thread Alyssa Rosenzweig 
This begins the process of removing blend shader specific MIR into a
more general NIR lowering pass for formats.

Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/midgard_compile.c  | 13 +
 .../panfrost/midgard/nir_lower_framebuffer.c|  4 ++--
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 5559aa44454..2c304d9066e 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -2324,20 +2324,18 @@ emit_fragment_epilogue(compiler_context *ctx)
 static void
 emit_blend_epilogue(compiler_context *ctx)
 {
-/* vmul.fmul.none.fulllow hr48, r0, #255 */
+/* fmov hr48, [...], r0*/
 
 midgard_instruction scale = {
 .type = TAG_ALU_4,
 .unit = UNIT_VMUL,
-.inline_constant = _mesa_float_to_half(255.0),
 .ssa_args = {
-.src0 = SSA_FIXED_REGISTER(0),
-.src1 = SSA_UNUSED_0,
+.src0 = SSA_FIXED_REGISTER(24),
+.src1 = SSA_FIXED_REGISTER(0),
 .dest = SSA_FIXED_REGISTER(24),
-.inline_constant = true
 },
 .alu = {
-.op = midgard_alu_op_fmul,
+.op = midgard_alu_op_fmov,
 .reg_mode = midgard_reg_mode_32,
 .dest_override = midgard_dest_override_lower,
 .mask = 0xFF,
@@ -2348,7 +2346,7 @@ emit_blend_epilogue(compiler_context *ctx)
 
 emit_mir_instruction(ctx, scale);
 
-/* vadd.f2u_rte.pos.low hr0, hr48, #0 */
+/* vadd.f2u_rte qr0, hr48, #0 */
 
 midgard_vector_alu_src alu_src = blank_alu_src;
 alu_src.half = true;
@@ -2365,7 +2363,6 @@ emit_blend_epilogue(compiler_context *ctx)
 .op = midgard_alu_op_f2u_rte,
 .reg_mode = midgard_reg_mode_16,
 .dest_override = midgard_dest_override_lower,
-.outmod = midgard_outmod_pos,
 .mask = 0xF,
 .src1 = vector_alu_srco_unsigned(alu_src),
 .src2 = vector_alu_srco_unsigned(blank_alu_src),
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 67fdf012c04..115fe5f09dd 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -44,8 +44,8 @@
 static nir_ssa_def *
 nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
 {
-   /* TODO */
-   return c_float;
+   nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, c_float), 255.0);
+   return scaled;
 }
 
 void
-- 
2.20.1

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[Mesa-dev] [PATCH 11/42] panfrost/midgard: Implement upscaling type converts

2019-07-08 Thread Alyssa Rosenzweig 
Rather than using a dest_override, we upscale integers by using a half
field with a sign-extend bit. A variant of this trick should also work
for floats, but one step at a time!

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 73 +++
 1 file changed, 59 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 292c6dc363d..b7379426b38 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -111,7 +111,8 @@ midgard_block_add_successor(midgard_block *block, 
midgard_block *successor)
  * the corresponding Midgard source */
 
 static midgard_vector_alu_src
-vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count)
+vector_alu_modifiers(nir_alu_src *src, bool is_int, unsigned broadcast_count,
+bool half, bool sext)
 {
 if (!src) return blank_alu_src;
 
@@ -131,14 +132,21 @@ vector_alu_modifiers(nir_alu_src *src, bool is_int, 
unsigned broadcast_count)
 midgard_vector_alu_src alu_src = {
 .rep_low = 0,
 .rep_high = 0,
-.half = 0, /* TODO */
+.half = half,
 .swizzle = SWIZZLE_FROM_ARRAY(src->swizzle)
 };
 
 if (is_int) {
-/* TODO: sign-extend/zero-extend */
 alu_src.mod = midgard_int_normal;
 
+/* Sign/zero-extend if needed */
+
+if (half) {
+alu_src.mod = sext ?
+  midgard_int_sign_extend
+: midgard_int_zero_extend;
+}
+
 /* These should have been lowered away */
 assert(!(src->abs || src->negate));
 } else {
@@ -703,9 +711,8 @@ nir_is_fzero_constant(nir_src src)
 return true;
 }
 
-/* Analyze the sizes of inputs/outputs to determine which reg mode to run an
- * ALU instruction in. Right now, we just consider the size of the first
- * argument. This will fail for upconverting, for instance (TODO) */
+/* Analyze the sizes of the inputs to determine which reg mode. Ops needed
+ * special treatment override this anyway. */
 
 static midgard_reg_mode
 reg_mode_for_nir(nir_alu_instr *instr)
@@ -751,12 +758,21 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 
 unsigned broadcast_swizzle = 0;
 
+/* What register mode should we operate in? */
+midgard_reg_mode reg_mode =
+reg_mode_for_nir(instr);
+
 /* Do we need a destination override? Used for inline
  * type conversion */
 
 midgard_dest_override dest_override =
 midgard_dest_override_none;
 
+/* Should we use a smaller respective source and sign-extend?  */
+
+bool half_1 = false, sext_1 = false;
+bool half_2 = false, sext_2 = false;
+
 switch (instr->op) {
 ALU_CASE(fadd, fadd);
 ALU_CASE(fmul, fmul);
@@ -856,14 +872,37 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 /* For size conversion, we use a move. Ideally though we would squash
  * these ops together; maybe that has to happen after in NIR as part of
  * propagation...? An earlier algebraic pass ensured we step down by
- * only / exactly one size */
+ * only / exactly one size. If stepping down, we use a dest override to
+ * reduce the size; if stepping up, we use a larger-sized move with a
+ * half source and a sign/zero-extension modifier */
+
+case nir_op_i2i8:
+case nir_op_i2i16:
+case nir_op_i2i32:
+/* If we end up upscale, we'll need a sign-extend on the
+ * operand (the second argument) */
 
+sext_2 = true;
 case nir_op_u2u8:
 case nir_op_u2u16:
-case nir_op_i2i8:
-case nir_op_i2i16: {
+case nir_op_u2u32: {
 op = midgard_alu_op_imov;
-dest_override = midgard_dest_override_lower;
+
+unsigned src_bitsize = nir_src_bit_size(instr->src[0].src);
+unsigned dst_bitsize = nir_dest_bit_size(instr->dest.dest);
+
+
+if (dst_bitsize == (src_bitsize * 2)) {
+/* Converting up */
+half_2 = true;
+
+/* Use a greater register mode */
+reg_mode++;
+} else if (src_bitsize == (dst_bitsize * 2)) {
+/* Converting down */
+dest_override = midgard_dest_override_lower;
+}
+
 break;
 }
 
@@ -1001,15 +1040,15 @@ emit_alu(compiler_context *ctx, nir_alu_instr *instr)
 
 midgard_vector_alu alu = {
 .op = op,
-

[Mesa-dev] [PATCH 06/42] panfrost/midgard: Rewrite to use new blend intrinsic

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 .../drivers/panfrost/midgard/midgard_compile.c| 11 +++
 .../panfrost/midgard/nir_lower_framebuffer.c  | 15 ---
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index 2c304d9066e..39b8d9c1005 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -1416,6 +1416,17 @@ emit_intrinsic(compiler_context *ctx, 
nir_intrinsic_instr *instr)
 
 break;
 
+/* Special case of store_output for lowered blend shaders */
+case nir_intrinsic_store_blended_output:
+assert (ctx->stage == MESA_SHADER_FRAGMENT);
+reg = nir_src_index(ctx, >src[0]);
+
+midgard_instruction move = v_mov(reg, blank_alu_src, 
SSA_FIXED_REGISTER(0));
+emit_mir_instruction(ctx, move);
+ctx->fragment_output = reg;
+
+break;
+
 case nir_intrinsic_load_alpha_ref_float:
 assert(instr->dest.is_ssa);
 
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 115fe5f09dd..202b3658a28 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -87,9 +87,18 @@ nir_lower_framebuffer(nir_shader *shader)
/* Format convert */
nir_ssa_def *converted = nir_float_to_native(, c_nir);
 
-   /* Write out the converted color instead of the input */
-   nir_instr_rewrite_src(instr, >src[1],
-   nir_src_for_ssa(converted));
+   /* Rewrite to use a native store by creating a new intrinsic */
+   nir_intrinsic_instr *new =
+  nir_intrinsic_instr_create(shader, 
nir_intrinsic_store_blended_output);
+   new->src[0] = nir_src_for_ssa(converted);
+
+   /* TODO: What about non-RGBA? Is that different? */
+   new->num_components = 4;
+
+   nir_builder_instr_insert(, >instr);
+
+   /* (And finally removing the old) */
+   nir_instr_remove(instr);
 } else {
/* TODO loads */
 }
-- 
2.20.1

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[Mesa-dev] [PATCH 00/42] panfrost: Render target stuff

2019-07-08 Thread Alyssa Rosenzweig 
This series is focused on rendering to more render target formats,
particularly ones that require the use of a blend shader. As an aside in
the middle, this leads us to implement preliminary fp16/i16 support in
the Midgard compiler.

Depends on the accompanying NIR and Gallium patches.

Alyssa Rosenzweig (42):
  panfrost: Prepare some code for MRT
  panfrost/mfbd: Include codes for float framebuffers
  panfrost: Extend clear colour packing
  panfrost/midgard: Passthrough nir_lower_framebuffer
  panfrost/midgard: Move scale from MIR to NIR
  panfrost/midgard: Rewrite to use new blend intrinsic
  panfrost/midgard: Implement integer downsize ops
  panfrost/midgard: Use nir_dest_num_components
  panfrost/midgard: Move blend type conversion into NIR
  panfrost/midgard: Route blend load intrinsic
  panfrost/midgard: Implement upscaling type converts
  panfrost/midgard: Fix blend constant scheduling bug
  panfrost/midgard: Move blend shader loads to NIR
  panfrost/midgard: Simplify blend read
  panfrost/midgard: Verify src_bitsize == dst_bitsize
  panfrost/midgard: Implement f2f16/f2f32
  panfrost/midgard: Implement f2u16 and friends
  panfrost/midgard: Allow fp16 in scalar ALU
  panfrost/midgard: Hoist mask field
  panfrost/midgard: Fix fp16 embedded constants
  panfrost/midgard: Eliminate redundant type convert
  panfrost/midgard: Handle fp16 in embedded_to_inline_constants
  panfrost/midgard: Fix scalarification
  panfrost/midgard: Remove opt_copy_prop_tex
  panfrost/midgard: Use fp16 exclusively while blending
  panfrost/midgard: Use Gallium framebuffer formats
  panfrost: Pipe framebuffer format around
  panfrost: Route format through fixed-function blending
  panfrost: Handle "blend disabled" blend shaders
  panfrost/midgard: Skip blend for REPLACE (shader)
  panfrost/midgard: Implement preliminary float converters
  panfrost: Set rt_count_2 for bpp>4 formats
  panfrost/mfbd: Handle pure int formats
  panfrost/midgard: Handle pure int formats
  panfrost/midgard: Use unsigned blend patch offset
  panfrost: Refactor blend infrastructure
  panfrost: Implement ES3-format writeout
  panfrost/midgard: Handle PIPE_FORMAT_B10G10R10A2_UNORM
  panfrost/mfbd: Handle PIPE_FORMAT_B10G10R10A2_UNORM
  panfrost/midgard: Cleanup blend switch
  panfrost/mfbd: Cleanup format code selection
  panfrost: Update supported formats

 src/gallium/drivers/panfrost/meson.build  |   2 +
 .../drivers/panfrost/midgard/compiler.h   |   7 +-
 .../drivers/panfrost/midgard/helpers.h|  21 +-
 .../panfrost/midgard/midgard_compile.c| 402 --
 .../drivers/panfrost/midgard/midgard_emit.c   |  61 ++-
 .../panfrost/midgard/midgard_nir_algebraic.py |  22 +-
 .../drivers/panfrost/midgard/midgard_ops.h|   9 +-
 .../drivers/panfrost/midgard/midgard_ra.c |  25 +-
 .../panfrost/midgard/midgard_schedule.c   |  71 +++-
 .../panfrost/midgard/nir_lower_blend.c|  37 +-
 .../panfrost/midgard/nir_lower_blend.h|   4 +
 .../panfrost/midgard/nir_lower_framebuffer.c  | 345 +++
 src/gallium/drivers/panfrost/pan_blend.h  | 109 +
 src/gallium/drivers/panfrost/pan_blend_cso.c  | 268 
 .../drivers/panfrost/pan_blend_shaders.c  |  70 +--
 .../drivers/panfrost/pan_blend_shaders.h  |   8 +-
 src/gallium/drivers/panfrost/pan_blending.c   | 100 +++--
 src/gallium/drivers/panfrost/pan_blending.h   |  10 +-
 src/gallium/drivers/panfrost/pan_context.c| 167 ++--
 src/gallium/drivers/panfrost/pan_context.h|  16 +-
 src/gallium/drivers/panfrost/pan_job.c|  86 +++-
 src/gallium/drivers/panfrost/pan_job.h|   8 +-
 src/gallium/drivers/panfrost/pan_mfbd.c   | 124 +-
 src/gallium/drivers/panfrost/pan_screen.c |  50 +--
 src/gallium/drivers/panfrost/pan_sfbd.c   |   8 +-
 25 files changed, 1438 insertions(+), 592 deletions(-)
 create mode 100644 src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
 create mode 100644 src/gallium/drivers/panfrost/pan_blend.h
 create mode 100644 src/gallium/drivers/panfrost/pan_blend_cso.c

-- 
2.20.1

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[Mesa-dev] [PATCH 04/42] panfrost/midgard: Passthrough nir_lower_framebuffer

2019-07-08 Thread Alyssa Rosenzweig 
Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/meson.build  |   1 +
 .../panfrost/midgard/nir_lower_blend.h|   3 +
 .../panfrost/midgard/nir_lower_framebuffer.c  | 102 ++
 .../drivers/panfrost/pan_blend_shaders.c  |   2 +
 4 files changed, 108 insertions(+)
 create mode 100644 src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c

diff --git a/src/gallium/drivers/panfrost/meson.build 
b/src/gallium/drivers/panfrost/meson.build
index b69b41bfd90..cc49903aaac 100644
--- a/src/gallium/drivers/panfrost/meson.build
+++ b/src/gallium/drivers/panfrost/meson.build
@@ -37,6 +37,7 @@ files_panfrost = files(
   'midgard/midgard_ops.c',
 
   'midgard/nir_lower_blend.c',
+  'midgard/nir_lower_framebuffer.c',
   'midgard/cppwrap.cpp',
   'midgard/disassemble.c',
 
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h 
b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h
index f8075768e7a..2805ca25d97 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_blend.h
@@ -53,4 +53,7 @@ typedef struct {
 
 void nir_lower_blend(nir_shader *shader, nir_lower_blend_options options);
 
+void
+nir_lower_framebuffer(nir_shader *shader);
+
 #endif
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
new file mode 100644
index 000..67fdf012c04
--- /dev/null
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2019 Collabora, Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors (Collabora):
+ *  Alyssa Rosenzweig 
+ */
+
+/**
+ * @file
+ *
+ * Implements framebuffer format conversions in software, specifically for
+ * blend shaders on Midgard/Bifrost. load_output/store_output (derefs more
+ * correctly -- pre I/O lowering) normally for the fragment stage within the
+ * blend shader will operate with purely vec4 float ("nir") encodings. This
+ * lowering stage, to be run before I/O is lowered, converts the native
+ * framebuffer format to a NIR encoding after loads and vice versa before
+ * stores. This pass is designed for a single render target; Midgard duplicates
+ * blend shaders for MRT to simplify everything.
+ */
+
+#include "compiler/nir/nir.h"
+#include "compiler/nir/nir_builder.h"
+#include "nir_lower_blend.h"
+
+static nir_ssa_def *
+nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
+{
+   /* TODO */
+   return c_float;
+}
+
+void
+nir_lower_framebuffer(nir_shader *shader)
+{
+   /* Blend shaders are represented as special fragment shaders */
+   assert(shader->info.stage == MESA_SHADER_FRAGMENT);
+
+   nir_foreach_function(func, shader) {
+  nir_foreach_block(block, func->impl) {
+ nir_foreach_instr_safe(instr, block) {
+if (instr->type != nir_instr_type_intrinsic)
+   continue;
+
+nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
+
+bool is_load = intr->intrinsic == nir_intrinsic_load_deref;
+bool is_store = intr->intrinsic == nir_intrinsic_store_deref;
+
+if (!(is_load || is_store))
+   continue;
+
+/* Don't worry about MRT */
+nir_variable *var = nir_intrinsic_get_var(intr, 0);
+
+if (var->data.location != FRAG_RESULT_COLOR)
+   continue;
+
+nir_builder b;
+nir_builder_init(, func->impl);
+
+if (is_store) {
+   /* For stores, add conversion before */
+   b.cursor = nir_before_instr(instr);
+
+   /* Grab the input color */
+   nir_ssa_def *c_nir = nir_ssa_for_src(, intr->src[1], 4);
+
+   /* Format convert */
+   nir_ssa_def *converted = nir_float_to_native(, c_nir);
+
+   /* Write

[Mesa-dev] [PATCH 09/42] panfrost/midgard: Move blend type conversion into NIR

2019-07-08 Thread Alyssa Rosenzweig 
Now that we have u2u8 implemented, we can move everything up into NIR
and eliminate the silly "blend epilogue" (no such thing; it's just a
fragment epilogue).

Signed-off-by: Alyssa Rosenzweig 
---
 .../panfrost/midgard/midgard_compile.c| 63 +--
 .../panfrost/midgard/nir_lower_framebuffer.c  |  8 ++-
 2 files changed, 8 insertions(+), 63 deletions(-)

diff --git a/src/gallium/drivers/panfrost/midgard/midgard_compile.c 
b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
index dba6cb2f6f9..0f51104a19d 100644
--- a/src/gallium/drivers/panfrost/midgard/midgard_compile.c
+++ b/src/gallium/drivers/panfrost/midgard/midgard_compile.c
@@ -2375,64 +2375,6 @@ emit_fragment_epilogue(compiler_context *ctx)
 EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 
-1, midgard_condition_always);
 }
 
-/* For the blend epilogue, we need to convert the blended fragment vec4 (stored
- * in r0) to a RGBA value by scaling and type converting. We then output it
- * with the int8 analogue to the fragment epilogue */
-
-static void
-emit_blend_epilogue(compiler_context *ctx)
-{
-/* fmov hr48, [...], r0*/
-
-midgard_instruction scale = {
-.type = TAG_ALU_4,
-.unit = UNIT_VMUL,
-.ssa_args = {
-.src0 = SSA_FIXED_REGISTER(24),
-.src1 = SSA_FIXED_REGISTER(0),
-.dest = SSA_FIXED_REGISTER(24),
-},
-.alu = {
-.op = midgard_alu_op_fmov,
-.reg_mode = midgard_reg_mode_32,
-.dest_override = midgard_dest_override_lower,
-.mask = 0xFF,
-.src1 = vector_alu_srco_unsigned(blank_alu_src),
-.src2 = vector_alu_srco_unsigned(blank_alu_src),
-}
-};
-
-emit_mir_instruction(ctx, scale);
-
-/* vadd.f2u_rte qr0, hr48, #0 */
-
-midgard_vector_alu_src alu_src = blank_alu_src;
-alu_src.half = true;
-
-midgard_instruction f2u_rte = {
-.type = TAG_ALU_4,
-.ssa_args = {
-.src0 = SSA_FIXED_REGISTER(24),
-.src1 = SSA_UNUSED_0,
-.dest = SSA_FIXED_REGISTER(0),
-.inline_constant = true
-},
-.alu = {
-.op = midgard_alu_op_f2u_rte,
-.reg_mode = midgard_reg_mode_16,
-.dest_override = midgard_dest_override_lower,
-.mask = 0xF,
-.src1 = vector_alu_srco_unsigned(alu_src),
-.src2 = vector_alu_srco_unsigned(blank_alu_src),
-}
-};
-
-emit_mir_instruction(ctx, f2u_rte);
-
-EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 
0, midgard_condition_always);
-EMIT(alu_br_compact_cond, midgard_jmp_writeout_op_writeout, TAG_ALU_4, 
-1, midgard_condition_always);
-}
-
 static midgard_block *
 emit_block(compiler_context *ctx, nir_block *block)
 {
@@ -2469,10 +2411,7 @@ emit_block(compiler_context *ctx, nir_block *block)
 /* Append fragment shader epilogue (value writeout) */
 if (ctx->stage == MESA_SHADER_FRAGMENT) {
 if (block == nir_impl_last_block(ctx->func->impl)) {
-if (ctx->is_blend)
-emit_blend_epilogue(ctx);
-else
-emit_fragment_epilogue(ctx);
+emit_fragment_epilogue(ctx);
 }
 }
 
diff --git a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c 
b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
index 202b3658a28..580df9d7442 100644
--- a/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
+++ b/src/gallium/drivers/panfrost/midgard/nir_lower_framebuffer.c
@@ -44,8 +44,14 @@
 static nir_ssa_def *
 nir_float_to_native(nir_builder *b, nir_ssa_def *c_float)
 {
+   /* First, we scale from [0, 1] to [0, 255.0] */
nir_ssa_def *scaled = nir_fmul_imm(b, nir_fsat(b, c_float), 255.0);
-   return scaled;
+
+   /* Next, we type convert */
+   nir_ssa_def *converted = nir_u2u8(b, nir_f2u32(b,
+nir_fround_even(b, scaled)));
+
+   return converted;
 }
 
 void
-- 
2.20.1

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[Mesa-dev] [PATCH 02/42] panfrost/mfbd: Include codes for float framebuffers

2019-07-08 Thread Alyssa Rosenzweig 
We see the hardware doesn't actually support float framebuffers in the
native sense -- rather, it just allows higher bpp framebuffers and lets
a blend shader / additional clear_color fields sort out the formats.
This will be.. interesting.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_mfbd.c | 29 -
 1 file changed, 28 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/panfrost/pan_mfbd.c 
b/src/gallium/drivers/panfrost/pan_mfbd.c
index b435d20b758..72f938713b1 100644
--- a/src/gallium/drivers/panfrost/pan_mfbd.c
+++ b/src/gallium/drivers/panfrost/pan_mfbd.c
@@ -81,14 +81,41 @@ panfrost_mfbd_format(struct pipe_surface *surf)
 
 /* Set flags for alternative formats */
 
+bool float_16 =
+surf->format == PIPE_FORMAT_R16_FLOAT;
+
+bool float_32 =
+surf->format == PIPE_FORMAT_R11G11B10_FLOAT ||
+surf->format == PIPE_FORMAT_R32_FLOAT ||
+surf->format == PIPE_FORMAT_R16G16_FLOAT;
+
+bool float_64 =
+surf->format == PIPE_FORMAT_R32G32_FLOAT ||
+surf->format == PIPE_FORMAT_R16G16B16A16_FLOAT;
+
+bool float_128 =
+surf->format == PIPE_FORMAT_R32G32B32A32_FLOAT;
+
 if (surf->format == PIPE_FORMAT_B5G6R5_UNORM) {
 fmt.unk1 = 0x1400;
 fmt.nr_channels = MALI_POSITIVE(2);
 fmt.unk3 |= 0x1;
-} else if (surf->format == PIPE_FORMAT_R11G11B10_FLOAT) {
+} else if (float_32) {
 fmt.unk1 = 0x8800;
 fmt.unk3 = 0x0;
 fmt.nr_channels = MALI_POSITIVE(4);
+} else if (float_16) {
+fmt.unk1 = 0x8400;
+fmt.unk3 = 0x0;
+fmt.nr_channels = MALI_POSITIVE(2);
+} else if (float_64) {
+fmt.unk1 = 0x8c00;
+fmt.unk3 = 0x1;
+fmt.nr_channels = MALI_POSITIVE(2);
+} else if (float_128) {
+fmt.unk1 = 0x9000;
+fmt.unk3 = 0x1;
+fmt.nr_channels = MALI_POSITIVE(4);
 }
 
 return fmt;
-- 
2.20.1

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[Mesa-dev] [PATCH 03/42] panfrost: Extend clear colour packing

2019-07-08 Thread Alyssa Rosenzweig 
Eventually, this will allow packing clear colours for all formats,
including floating-point framebuffers, pure integer buffers, and special
formats. Currently, a few of these formats are supported, and many more
are handled through a generic Gallium colour packing path (which is not
a perfect fit for the hardware, but works for many formats and is a sane
default for the moment.)

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_job.c  | 86 +
 src/gallium/drivers/panfrost/pan_job.h  |  8 ++-
 src/gallium/drivers/panfrost/pan_mfbd.c | 18 --
 src/gallium/drivers/panfrost/pan_sfbd.c |  8 +--
 4 files changed, 94 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_job.c 
b/src/gallium/drivers/panfrost/pan_job.c
index 2f7fe9e3cc3..6838050e575 100644
--- a/src/gallium/drivers/panfrost/pan_job.c
+++ b/src/gallium/drivers/panfrost/pan_job.c
@@ -184,8 +184,26 @@ panfrost_job_set_requirements(struct panfrost_context *ctx,
 job->requirements |= PAN_REQ_DEPTH_WRITE;
 }
 
-static uint32_t
-pan_pack_color(const union pipe_color_union *color, enum pipe_format format)
+/* Helper to smear a 32-bit color across 128-bit components */
+
+static void
+pan_pack_color_32(uint32_t *packed, uint32_t v)
+{
+for (unsigned i = 0; i < 4; ++i)
+packed[i] = v;
+}
+
+static void
+pan_pack_color_64(uint32_t *packed, uint32_t lo, uint32_t hi)
+{
+for (unsigned i = 0; i < 4; i += 2) {
+packed[i + 0] = lo;
+packed[i + 1] = hi;
+}
+}
+
+static void
+pan_pack_color(uint32_t *packed, const union pipe_color_union *color, enum 
pipe_format format)
 {
 /* Alpha magicked to 1.0 if there is no alpha */
 
@@ -198,10 +216,11 @@ pan_pack_color(const union pipe_color_union *color, enum 
pipe_format format)
 util_format_description(format);
 
 if (util_format_is_rgba8_variant(desc)) {
-return (float_to_ubyte(clear_alpha) << 24) |
-   (float_to_ubyte(color->f[2]) << 16) |
-   (float_to_ubyte(color->f[1]) <<  8) |
-   (float_to_ubyte(color->f[0]) <<  0);
+pan_pack_color_32(packed,
+(float_to_ubyte(clear_alpha) << 24) |
+(float_to_ubyte(color->f[2]) << 16) |
+(float_to_ubyte(color->f[1]) <<  8) |
+(float_to_ubyte(color->f[0]) <<  0));
 } else if (format == PIPE_FORMAT_B5G6R5_UNORM) {
 /* First, we convert the components to R5, G6, B5 separately */
 unsigned r5 = CLAMP(color->f[0], 0.0, 1.0) * 31.0;
@@ -209,17 +228,53 @@ pan_pack_color(const union pipe_color_union *color, enum 
pipe_format format)
 unsigned b5 = CLAMP(color->f[2], 0.0, 1.0) * 31.0;
 
 /* Then we pack into a sparse u32. TODO: Why these shifts? */
-return (b5 << 25) | (g6 << 14) | (r5 << 5);
+pan_pack_color_32(packed, (b5 << 25) | (g6 << 14) | (r5 << 5));
+} else if (format == PIPE_FORMAT_B4G4R4A4_UNORM) {
+/* We scale the components against 0xF0 (=240.0), rather than 
0xFF */
+unsigned r4 = CLAMP(color->f[0], 0.0, 1.0) * 240.0;
+unsigned g4 = CLAMP(color->f[1], 0.0, 1.0) * 240.0;
+unsigned b4 = CLAMP(color->f[2], 0.0, 1.0) * 240.0;
+unsigned a4 = CLAMP(clear_alpha, 0.0, 1.0) * 240.0;
+
+/* Pack on *byte* intervals */
+pan_pack_color_32(packed, (a4 << 24) | (b4 << 16) | (g4 << 8) 
| r4);
+} else if (format == PIPE_FORMAT_B5G5R5A1_UNORM) {
+/* Scale as expected but shift oddly */
+unsigned r5 = round(CLAMP(color->f[0], 0.0, 1.0)) * 31.0;
+unsigned g5 = round(CLAMP(color->f[1], 0.0, 1.0)) * 31.0;
+unsigned b5 = round(CLAMP(color->f[2], 0.0, 1.0)) * 31.0;
+unsigned a1 = round(CLAMP(clear_alpha, 0.0, 1.0)) * 1.0;
+
+pan_pack_color_32(packed, (a1 << 31) | (b5 << 25) | (g5 << 15) 
| (r5 << 5));
 } else {
 /* Try Gallium's generic default path. Doesn't work for all
  * formats but it's a good guess. */
 
 union util_color out;
-util_pack_color(color->f, format, );
-return out.ui[0];
-}
 
-return 0;
+if (util_format_is_pure_integer(format)) {
+memcpy(out.ui, color->ui, 16);
+} else {
+util_pack_color(color->f, format, );
+}
+
+unsigned size = util_format_get_blocksize(format);
+
+if (size == 1) {
+unsigned b = out.ui[0];
+unsigned s = b | (b << 8);
+pan_pack_color_32(packed, s | (s << 16));
+

[Mesa-dev] [PATCH 01/42] panfrost: Prepare some code for MRT

2019-07-08 Thread Alyssa Rosenzweig 
Full MRT support is a while away, but in the mean time, we can remove
code that explicitly assumes nr_cbufs <= 0, to minimize the obstacles
we'll face later when we add the whole thing.

Signed-off-by: Alyssa Rosenzweig 
---
 src/gallium/drivers/panfrost/pan_context.c | 39 --
 1 file changed, 13 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/panfrost/pan_context.c 
b/src/gallium/drivers/panfrost/pan_context.c
index 90ea38645dc..82cd2ea6a48 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -190,7 +190,7 @@ bool
 panfrost_is_scanout(struct panfrost_context *ctx)
 {
 /* If there is no color buffer, it's an FBO */
-if (!ctx->pipe_framebuffer.nr_cbufs)
+if (ctx->pipe_framebuffer.nr_cbufs != 1)
 return false;
 
 /* If we're too early that no framebuffer was sent, it's scanout */
@@ -1459,7 +1459,7 @@ panfrost_draw_wallpaper(struct pipe_context *pipe)
 {
struct panfrost_context *ctx = pan_context(pipe);
 
-   /* Nothing to reload? */
+   /* Nothing to reload? TODO: MRT wallpapers */
if (ctx->pipe_framebuffer.cbufs[0] == NULL)
return;
 
@@ -2333,23 +2333,27 @@ panfrost_set_framebuffer_state(struct pipe_context 
*pctx,
 ctx->pipe_framebuffer.width = fb->width;
 ctx->pipe_framebuffer.height = fb->height;
 
+struct pipe_surface *zb = fb->zsbuf;
+bool needs_reattach = false;
+
 for (int i = 0; i < PIPE_MAX_COLOR_BUFS; i++) {
 struct pipe_surface *cb = i < fb->nr_cbufs ? fb->cbufs[i] : 
NULL;
 
 /* check if changing cbuf */
 if (ctx->pipe_framebuffer.cbufs[i] == cb) continue;
 
-if (cb && (i != 0)) {
-DBG("XXX: Multiple render targets not supported before 
t7xx!\n");
-assert(0);
-}
-
 /* assign new */
 pipe_surface_reference(>pipe_framebuffer.cbufs[i], cb);
 
-if (!cb)
-continue;
+needs_reattach |= (cb != NULL);
+}
+
+if (ctx->pipe_framebuffer.zsbuf != zb) {
+pipe_surface_reference(>pipe_framebuffer.zsbuf, zb);
+needs_reattach |= (zb != NULL);
+}
 
+if (needs_reattach) {
 if (ctx->require_sfbd)
 ctx->vt_framebuffer_sfbd = panfrost_emit_sfbd(ctx, ~0);
 else
@@ -2357,23 +2361,6 @@ panfrost_set_framebuffer_state(struct pipe_context *pctx,
 
 panfrost_attach_vt_framebuffer(ctx);
 }
-
-{
-struct pipe_surface *zb = fb->zsbuf;
-
-if (ctx->pipe_framebuffer.zsbuf != zb) {
-pipe_surface_reference(>pipe_framebuffer.zsbuf, 
zb);
-
-if (zb) {
-if (ctx->require_sfbd)
-ctx->vt_framebuffer_sfbd = 
panfrost_emit_sfbd(ctx, ~0);
-else
-ctx->vt_framebuffer_mfbd = 
panfrost_emit_mfbd(ctx, ~0);
-
-panfrost_attach_vt_framebuffer(ctx);
-}
-}
-}
 }
 
 static void *
-- 
2.20.1

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Re: [Mesa-dev] [MR] Update README to recommend MRs instead of `git send-email`

2019-07-08 Thread Ernst Sjöstrand 
git send-email with a gmail account is quite messy IMHO, I'd much
rather do a pull request.

Regards
//Ernst

Den mån 8 juli 2019 kl 15:32 skrev Eric Engestrom :
>
> On Saturday, 2019-07-06 13:39:16 -0400, Ilia Mirkin wrote:
> > I see this as driving away contributions, esp from new people. MR's
> > are annoying to create, since they require dealing with the hosting
> > provider, getting it to host clones, etc. Everyone has email.
>
> MRs have a one-time cost of having to create an account and forking the
> repo, I agree, although I really don't understand why a couple of you
> guys consider that cost so high...
>
> Anyway, we're not talking about preventing people from sending patches
> via email, or even just telling people not to do that, we are simply
> updating the recommendation for people who don't know where to start.
>
> As for "driving away contributions", we have noticed the exact opposite,
> which is exactly what we expected since that's what everyone else had
> been reporting as well: web interfaces instead of email make it much
> *easier* for new people to submit patches, which translated into many
> new people sending patches since we enabled MRs.
>
> On the technical side, MRs also allow things like the pre-merge CI to
> make sure we don't accidentally break the build for other people, and
> that alone is enough for many of us to want to eventually not let anyone
> push anything that hasn't gone through that CI, so while this is *not*
> what we're talking about here, let's be clear that it's the end-goal for
> many of us.
>
> >
> > Cheers,
> >
> >   -ilia
> >
> > On Sat, Jul 6, 2019 at 7:41 AM Eric Engestrom  wrote:
> > >
> > > Hi,
> > >
> > > I sent an MR to update the README, but as pointed out there I should
> > > make sure people who don't look at MRs are also aware of it, so here is:
> > >
> > > https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1223
> > >
> > > ---8<---
> > > diff --git a/README.rst b/README.rst
> > > index 4ccd72eca38a0845571c..eba097e652edde48a735 100644
> > > --- a/README.rst
> > > +++ b/README.rst
> > > @@ -56,5 +56,6 @@ Contributions are welcome, and step-by-step 
> > > instructions can be found in our
> > >  documentation (`docs/submittingpatches.html
> > >  `_).
> > >
> > > -Note that Mesa uses email mailing-lists for patches submission, review 
> > > and
> > > -discussions.
> > > +We recommend using GitLab Merge Requests (MRs) for patch submission and
> > > +review, and email mailing-lists for discussions, but the old `git 
> > > send-email`
> > > +method is still accepted.
> > > --->8---
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [MR] Update README to recommend MRs instead of `git send-email`

2019-07-08 Thread Eric Engestrom 
On Saturday, 2019-07-06 13:39:16 -0400, Ilia Mirkin wrote:
> I see this as driving away contributions, esp from new people. MR's
> are annoying to create, since they require dealing with the hosting
> provider, getting it to host clones, etc. Everyone has email.

MRs have a one-time cost of having to create an account and forking the
repo, I agree, although I really don't understand why a couple of you
guys consider that cost so high...

Anyway, we're not talking about preventing people from sending patches
via email, or even just telling people not to do that, we are simply
updating the recommendation for people who don't know where to start.

As for "driving away contributions", we have noticed the exact opposite,
which is exactly what we expected since that's what everyone else had
been reporting as well: web interfaces instead of email make it much
*easier* for new people to submit patches, which translated into many
new people sending patches since we enabled MRs.

On the technical side, MRs also allow things like the pre-merge CI to
make sure we don't accidentally break the build for other people, and
that alone is enough for many of us to want to eventually not let anyone
push anything that hasn't gone through that CI, so while this is *not*
what we're talking about here, let's be clear that it's the end-goal for
many of us.

> 
> Cheers,
> 
>   -ilia
> 
> On Sat, Jul 6, 2019 at 7:41 AM Eric Engestrom  wrote:
> >
> > Hi,
> >
> > I sent an MR to update the README, but as pointed out there I should
> > make sure people who don't look at MRs are also aware of it, so here is:
> >
> > https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1223
> >
> > ---8<---
> > diff --git a/README.rst b/README.rst
> > index 4ccd72eca38a0845571c..eba097e652edde48a735 100644
> > --- a/README.rst
> > +++ b/README.rst
> > @@ -56,5 +56,6 @@ Contributions are welcome, and step-by-step instructions 
> > can be found in our
> >  documentation (`docs/submittingpatches.html
> >  `_).
> >
> > -Note that Mesa uses email mailing-lists for patches submission, review and
> > -discussions.
> > +We recommend using GitLab Merge Requests (MRs) for patch submission and
> > +review, and email mailing-lists for discussions, but the old `git 
> > send-email`
> > +method is still accepted.
> > --->8---
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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Re: [Mesa-dev] [PATCH] radv: do not emit VGT_FLUSH on GFX10

2019-07-08 Thread Bas Nieuwenhuizen 
r-b

On Mon, Jul 8, 2019 at 1:45 PM Samuel Pitoiset
 wrote:
>
> We don't need it.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_device.c | 7 +--
>  1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 5a92e5276d9..09614067a4a 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -2747,8 +2747,11 @@ radv_get_preamble_cs(struct radv_queue *queue,
> if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo)  {
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) 
> | EVENT_INDEX(4));
> -   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> -   radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | 
> EVENT_INDEX(0));
> +
> +   if 
> (queue->device->physical_device->rad_info.chip_class < GFX10) {
> +   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> +   radeon_emit(cs, 
> EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
> +   }
> }
>
> radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, 
> esgs_ring_size,
> --
> 2.22.0
>
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[Mesa-dev] [PATCH] radv: do not emit VGT_FLUSH on GFX10

2019-07-08 Thread Samuel Pitoiset 
We don't need it.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5a92e5276d9..09614067a4a 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2747,8 +2747,11 @@ radv_get_preamble_cs(struct radv_queue *queue,
if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo)  {
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | 
EVENT_INDEX(4));
-   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
-   radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | 
EVENT_INDEX(0));
+
+   if (queue->device->physical_device->rad_info.chip_class 
< GFX10) {
+   radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+   radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) 
| EVENT_INDEX(0));
+   }
}
 
radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
-- 
2.22.0

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