[Mesa-dev] [PATCH 1/2] mesa:amd get device name from kernel
Signed-off-by: Sonny Jiang
---
src/amd/common/ac_gpu_info.c | 72
1 file changed, 64 insertions(+), 8 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 5fb1e26376a..c8bc398319e 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -106,6 +106,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
int r, i, j;
amdgpu_device_handle dev = dev_p;
drmDevicePtr devinfo;
+ drmVersionPtr version;
/* Get PCI info. */
r = drmGetDevice2(fd, 0, );
@@ -304,18 +305,73 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
info->vce_harvest_config = amdinfo->vce_harvest_config;
- switch (info->pci_id) {
+ static struct ac_chip_mapping {
+ const char *kernel_name;
+ enum radeon_family family;
+ const char *mesa_name;
+ } table[] = {
+ {"TAHITI", CHIP_TAHITI, "TAHITI"},
+ {"PITCAIRN", CHIP_PITCAIRN, "PITCAIRN"},
+ {"VERDE", CHIP_VERDE, "VERDE"},
+ {"OLAND", CHIP_OLAND, "OLAND"},
+ {"HAINAN", CHIP_HAINAN, "HAINAN"},
+ {"BONAIRE", CHIP_BONAIRE, "BONAIRE"},
+ {"KAVERI", CHIP_KAVERI, "KAVERI"},
+ {"KABINI", CHIP_KABINI, "KABINI"},
+ {"HAWAII", CHIP_HAWAII, "HAWAII"},
+ {"MULLINS", CHIP_KABINI, "KABINI"},
+ {"TOPAZ", CHIP_ICELAND, "ICELAND"},
+ {"TONGA", CHIP_TONGA, "TONGA"},
+ {"FIJI", CHIP_FIJI, "FIJI"},
+ {"CARRIZO", CHIP_CARRIZO, "CARRIZO"},
+ {"STONEY", CHIP_STONEY, "STONEY"},
+ {"POLARIS10", CHIP_POLARIS10, "POLARIS10"},
+ {"POLARIS11", CHIP_POLARIS11, "POLARIS11"},
+ {"POLARIS12", CHIP_POLARIS12, "POLARIS12"},
+ {"VEGAM", CHIP_VEGAM, "VEGAM"},
+ {"VEGA10", CHIP_VEGA10, "VEGA10"},
+ {"VEGA12", CHIP_VEGA12, "VEGA12"},
+ {"VEGA20", CHIP_VEGA20, "VEGA20"},
+ {"RAVEN", CHIP_RAVEN, "RAVEN"},
+ {"ARCTURUS", CHIP_ARCTURUS, "ARCTURUS"},
+ {"RENOIR", CHIP_RENOIR, "RENOIR"},
+ {"NAVI10", CHIP_NAVI10, "NAVI10"},
+ {"NAVI14", CHIP_NAVI14, "NAVI14"},
+ {"NAVI12", CHIP_NAVI12, "NAVI12"}
+ };
+
+ version = drmGetVersion(fd);
+ if (!version) {
+ fprintf(stderr, "amdgpu: drmGetVersion failed.\n");
+ return false;
+ }
+
+ if (version->desc_len && version->desc) {
+ for (unsigned i = 0; i < ARRAY_SIZE(table); i++) {
+ if (strcmp(version->desc, table[i].kernel_name) == 0) {
+ info->family = table[i].family;
+ info->name = table[i].mesa_name;
+ break;
+ }
+ }
+ }
+
+ drmFreeVersion(version);
+
+ if (!info->name) {
+ switch (info->pci_id) {
#define CHIPSET(pci_id, cfamily) \
- case pci_id: \
- info->family = CHIP_##cfamily; \
- info->name = #cfamily; \
- break;
+ case pci_id: \
+ info->family = CHIP_##cfamily; \
+ info->name = #cfamily; \
+ break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
- default:
- fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
- return false;
+ default:
+ fprintf(stderr, "amdgpu: Invalid PCI ID.\n");
+ return false;
+ }
}
/* Raven2 uses the same PCI IDs as Raven1, but different revision IDs.
*/
--
2.17.1
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[Mesa-dev] [PATCH 2/2] loader: driver name radeonsi chosen from kernel name amdgpu
Signed-off-by: Sonny Jiang
---
src/loader/loader.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/loader/loader.c b/src/loader/loader.c
index d8d71c30200..45834aa2082 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -457,6 +457,14 @@ loader_get_driver_for_fd(int fd)
return driver;
#endif
+ driver = loader_get_kernel_driver_name(fd);
+ if (driver && strcmp(driver, "amdgpu") == 0) {
+ free(driver);
+ driver = strdup("radeonsi");
+ return driver;
+ } else
+ free(driver);
+
if (!loader_get_pci_id_for_fd(fd, _id, _id)) {
driver = loader_get_kernel_driver_name(fd);
if (driver)
--
2.17.1
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[Mesa-dev] [PATCH] mesa gallium: use compute shaders for vaapi blit
Signed-off-by: Sonny Jiang
---
src/gallium/auxiliary/Makefile.sources | 2 +
src/gallium/auxiliary/util/u_compute.c | 165 +
src/gallium/auxiliary/util/u_compute.h | 44 ++
src/gallium/state_trackers/va/context.c| 2 +
src/gallium/state_trackers/va/postproc.c | 6 +-
src/gallium/state_trackers/va/va_private.h | 1 +
6 files changed, 219 insertions(+), 1 deletion(-)
create mode 100644 src/gallium/auxiliary/util/u_compute.c
create mode 100644 src/gallium/auxiliary/util/u_compute.h
diff --git a/src/gallium/auxiliary/Makefile.sources
b/src/gallium/auxiliary/Makefile.sources
index 02cc5df70a7..6f5266fe273 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -218,6 +218,8 @@ C_SOURCES := \
util/u_box.h \
util/u_cache.c \
util/u_cache.h \
+ util/u_compute.c \
+ util/u_compute.h \
util/u_debug_gallium.h \
util/u_debug_gallium.c \
util/u_debug_describe.c \
diff --git a/src/gallium/auxiliary/util/u_compute.c
b/src/gallium/auxiliary/util/u_compute.c
new file mode 100644
index 000..e2e39227206
--- /dev/null
+++ b/src/gallium/auxiliary/util/u_compute.c
@@ -0,0 +1,165 @@
+/**
+ *
+ * Copyright 2019 Sonny Jiang
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **/
+
+#include "pipe/p_context.h"
+#include "pipe/p_state.h"
+
+#include "u_bitcast.h"
+#include "u_format.h"
+#include "u_sampler.h"
+#include "tgsi/tgsi_text.h"
+#include "tgsi/tgsi_ureg.h"
+#include "u_inlines.h"
+
+void *blit_compute_shader(struct pipe_context *ctx)
+{
+ static const char text[] =
+ "COMP\n"
+ "PROPERTY CS_FIXED_BLOCK_WIDTH 64\n"
+ "PROPERTY CS_FIXED_BLOCK_HEIGHT 1\n"
+ "PROPERTY CS_FIXED_BLOCK_DEPTH 1\n"
+ "DCL SV[0], THREAD_ID\n"
+ "DCL SV[1], BLOCK_ID\n"
+ "DCL IMAGE[0], 2D_ARRAY, PIPE_FORMAT_R32G32B32A32_FLOAT, WR\n"
+ "DCL SAMP[0]\n"
+ "DCL SVIEW[0], 2D_ARRAY, FLOAT\n"
+ "DCL CONST[0][0..2]\n" // 0:xyzw 1:xyzw
+ "DCL TEMP[0..4], LOCAL\n"
+ "IMM[0] UINT32 {64, 1, 0, 0}\n"
+
+ "UMAD TEMP[0].xyz, SV[1].xyzz, IMM[0].xyyy, SV[0].xyzz\n"
+ "U2F TEMP[1].xyz, TEMP[0]\n"
+ "MAD TEMP[2].xyz, TEMP[1], CONST[0][1], CONST[0][0]\n"
+ "TEX_LZ TEMP[3], TEMP[2], SAMP[0], 2D_ARRAY\n"
+ "UADD TEMP[4].xyz, TEMP[0], CONST[0][2]\n"
+ "STORE IMAGE[0], TEMP[4], TEMP[3], 2D_ARRAY,
PIPE_FORMAT_R32G32B32A32_FLOAT\n"
+ "END\n";
+
+ struct tgsi_token tokens[1024];
+ struct pipe_compute_state state = {0};
+
+ if (!tgsi_text_translate(text, tokens, ARRAY_SIZE(tokens))) {
+ assert(false);
+ return NULL;
+ }
+
+ state.ir_type = PIPE_SHADER_IR_TGSI;
+ state.prog = tokens;
+
+ return ctx->create_compute_state(ctx, );
+}
+
+void util_compute_blit(struct pipe_context *ctx, struct pipe_blit_info
*blit_info,
+ void **compute_state)
+{
+ if (blit_info->src.box.width == 0 || blit_info->src.box.height == 0 ||
+ blit_info->dst.box.width == 0 || blit_info->dst.box.height == 0)
+ return;
+
+ struct pipe_resource *src = blit_info->src.resource;
+ struct pipe_resource *dst = blit_info->dst.resource;
+ struct pipe_sampler_view src_templ = {0}, *src_view;
+ void *sampler_state_p;
+ unsigned width = blit_info->dst.box.width;
+ unsigned height = blit_info->dst.box.height;
+ float x_scale =
[Mesa-dev] [PATCH] gallium: add pipe_grid_info::partial_block
and add radeonsi support. This will be used by radeonsi internally.
Signed-off-by: Sonny Jiang
---
src/gallium/drivers/radeonsi/si_compute.c | 33 +++
src/gallium/include/pipe/p_state.h| 7 +
2 files changed, 35 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_compute.c
b/src/gallium/drivers/radeonsi/si_compute.c
index cbcd8e79c7b..69ffad45cd9 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -797,11 +797,6 @@ static void si_emit_dispatch_packets(struct si_context
*sctx,
radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
compute_resource_limits);
- radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
- radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
- radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
- radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
-
unsigned dispatch_initiator =
S_00B800_COMPUTE_SHADER_EN(1) |
S_00B800_FORCE_START_AT_000(1) |
@@ -809,6 +804,34 @@ static void si_emit_dispatch_packets(struct si_context
*sctx,
* allow launching waves out-of-order. (same as Vulkan) */
S_00B800_ORDER_MODE(sctx->chip_class >= CIK);
+ bool partial_block_en = info->partial_block[0] ||
+ info->partial_block[1] ||
+ info->partial_block[2];
+
+ radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
+
+ if (partial_block_en) {
+ unsigned partial[3];
+
+ /* If no partial_block, these should be an entire block size,
not 0. */
+ partial[0] = info->partial_block[0] ? info->partial_block[0] :
info->block[0];
+ partial[1] = info->partial_block[1] ? info->partial_block[1] :
info->block[1];
+ partial[2] = info->partial_block[2] ? info->partial_block[2] :
info->block[2];
+
+ radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]) |
+ S_00B81C_NUM_THREAD_PARTIAL(partial[0]));
+ radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]) |
+ S_00B820_NUM_THREAD_PARTIAL(partial[1]));
+ radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]) |
+ S_00B824_NUM_THREAD_PARTIAL(partial[2]));
+
+ dispatch_initiator |= S_00B800_PARTIAL_TG_EN(1);
+ } else {
+ radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(info->block[0]));
+ radeon_emit(cs, S_00B820_NUM_THREAD_FULL(info->block[1]));
+ radeon_emit(cs, S_00B824_NUM_THREAD_FULL(info->block[2]));
+ }
+
if (info->indirect) {
uint64_t base_va = r600_resource(info->indirect)->gpu_address;
diff --git a/src/gallium/include/pipe/p_state.h
b/src/gallium/include/pipe/p_state.h
index 38052e5fd3d..56f5bdd4c85 100644
--- a/src/gallium/include/pipe/p_state.h
+++ b/src/gallium/include/pipe/p_state.h
@@ -838,6 +838,13 @@ struct pipe_grid_info
*/
uint block[3];
+ /**
+* Number of threads to add to the grid in X, Y, and Z directions for
+* compute dispatches that are not aligned to the block size.
+* The added threads will be launched as partial thread blocks.
+*/
+ uint partial_block[3];
+
/**
* Determine the layout of the grid (in block units) to be used.
*/
--
2.17.1
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[Mesa-dev] [PATCH v4] radeonsi: Disable clear_state with radeon kernel driver
Signed-off-by: Sonny Jiang Tested-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_pipe.c | 6 -- src/gallium/drivers/radeonsi/si_state.c | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 46cf37567f..e285b056db 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -993,8 +993,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs -* on SI. */ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK; +* on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. +* SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ + sscreen->has_clear_state = sscreen->info.chip_class >= CIK && + sscreen->info.drm_major == 3; sscreen->has_distributed_tess = sscreen->info.chip_class >= VI && diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 176ec74914..2977474130 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx) bool has_clear_state = sscreen->has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - /* Only SI can disable CLEAR_STATE for now. */ - assert(has_clear_state || sscreen->info.chip_class == SI); + /* SI, radeon kernel disabled CLEAR_STATE. */ + assert(has_clear_state || sscreen->info.chip_class == SI || + sscreen->info.drm_major != 3); if (!pm4) return; -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v3] radeonsi: Disable clear_state with radeon kernel driver
Signed-off-by: Sonny Jiang Tested-by: Michel Dänzer --- src/gallium/drivers/radeonsi/si_pipe.c | 6 -- src/gallium/drivers/radeonsi/si_state.c | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 9d25748df4..a82171c2dc 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -991,8 +991,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs -* on SI. */ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK; +* on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. +* SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ + sscreen->has_clear_state = sscreen->info.chip_class >= CIK && + sscreen->info.drm_major == 3; sscreen->has_distributed_tess = sscreen->info.chip_class >= VI && diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8b2e6e57f4..cd43276b50 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx) bool has_clear_state = sscreen->has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - /* Only SI can disable CLEAR_STATE for now. */ - assert(has_clear_state || sscreen->info.chip_class == SI); + /* SI, radeon kernel disabled CLEAR_STATE. */ + assert(has_clear_state || sscreen->info.chip_class == SI || + sscreen->info.drm_major != 3); if (!pm4) return; -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v2] radeonsi: fix a radeon kernel clear state error
Signed-off-by: Sonny Jiang --- src/gallium/drivers/radeonsi/si_pipe.c | 6 -- src/gallium/drivers/radeonsi/si_state.c | 5 +++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 9d25748df4..a82171c2dc 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -991,8 +991,10 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs -* on SI. */ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK; +* on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. +* SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ + sscreen->has_clear_state = sscreen->info.chip_class >= CIK && + sscreen->info.drm_major == 3; sscreen->has_distributed_tess = sscreen->info.chip_class >= VI && diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8b2e6e57f4..cd43276b50 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx) bool has_clear_state = sscreen->has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - /* Only SI can disable CLEAR_STATE for now. */ - assert(has_clear_state || sscreen->info.chip_class == SI); + /* SI, radeon kernel disabled CLEAR_STATE. */ + assert(has_clear_state || sscreen->info.chip_class == SI || + sscreen->info.drm_major != 3); if (!pm4) return; -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radeonsi: fix a radeon kernel clear state error
Signed-off-by: Sonny Jiang --- src/gallium/drivers/radeonsi/si_pipe.c | 7 +-- src/gallium/drivers/radeonsi/si_state.c | 5 +++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 9d25748df4..3da44483d6 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -991,8 +991,11 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws, } /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs -* on SI. */ - sscreen->has_clear_state = sscreen->info.chip_class >= CIK; +* on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc. +* SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/ + sscreen->has_clear_state = sscreen->info.chip_class > CIK || + (sscreen->info.chip_class == CIK && + sscreen->info.drm_major == 3); sscreen->has_distributed_tess = sscreen->info.chip_class >= VI && diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 8b2e6e57f4..ba84a5a42a 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -4899,8 +4899,9 @@ static void si_init_config(struct si_context *sctx) bool has_clear_state = sscreen->has_clear_state; struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state); - /* Only SI can disable CLEAR_STATE for now. */ - assert(has_clear_state || sscreen->info.chip_class == SI); + /* SI, radeon kernel CIK disabled CLEAR_STATE. */ + assert(has_clear_state || sscreen->info.chip_class == SI || + (sscreen->info.chip_class == CIK && sscreen->info.drm_major != 3)); if (!pm4) return; -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/6] radeonsi: emit_db_render_state packets optimization
By applied patch 1, gfx IB size changes obviously.
openarena GFX-IB-size changes from 7.64k to 7.44k.
glxgears GFX-IB-size changes from 8.48k to 8.416k.
The adding CPU workloads are quite small in this case and it's hard to measure
it. So the assumption is that writing a SET_CONTEXT_REG packet is more
expensive. And we emit too many redundant packets. Some registers rarely get
different values.
Thanks,
Sonny
From: Dave Airlie
Sent: Thursday, June 7, 2018 5:20:12 PM
To: Jiang, Sonny
Cc: mesa-dev
Subject: Re: [Mesa-dev] [PATCH 1/6] radeonsi: emit_db_render_state packets
optimization
On 8 June 2018 at 02:13, Sonny Jiang wrote:
> Remembering latest states of registers to eliminate redunant SET_CONTEXT_REG
> packets
>
Does this help anywhere btw? Numbers for an app or game.
In the past I've always found this sort of optimisation pointless, the
CP on the GPU side
does a pretty good job at nuking pointless register sets or at least
hiding them.
This will increase CPU and memory usage in some ways in favour of
reducing CP and
possibly memory bandwidth, but without numbers I'm not sure it's a good plan.
Dave.
> Signed-off-by: Sonny Jiang
> ---
> src/gallium/drivers/radeonsi/si_build_pm4.h | 43 +
> src/gallium/drivers/radeonsi/si_gfx_cs.c| 3 ++
> src/gallium/drivers/radeonsi/si_pipe.h | 2 +
> src/gallium/drivers/radeonsi/si_state.c | 60
> +++--
> src/gallium/drivers/radeonsi/si_state.h | 16
> 5 files changed, 95 insertions(+), 29 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h
> b/src/gallium/drivers/radeonsi/si_build_pm4.h
> index 22f5558..45d943f 100644
> --- a/src/gallium/drivers/radeonsi/si_build_pm4.h
> +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h
> @@ -110,4 +110,47 @@ static inline void radeon_set_uconfig_reg_idx(struct
> radeon_winsys_cs *cs,
> radeon_emit(cs, value);
> }
>
> +/* Emit PKT3_SET_CONTEXT_REG if the register value is different. */
> +static inline void radeon_opt_set_context_reg(struct si_context *sctx,
> unsigned offset,
> + enum si_tracked_reg reg,
> unsigned value)
> +{
> + struct radeon_winsys_cs *cs = sctx->gfx_cs;
> +
> + if (!(sctx->tracked_regs.reg_saved & (1 << reg)) ||
> + sctx->tracked_regs.reg_value[reg] != value ) {
> +
> + radeon_set_context_reg(cs, offset, value);
> +
> + sctx->tracked_regs.reg_saved |= 1 << reg;
> + sctx->tracked_regs.reg_value[reg] = value;
> + }
> +}
> +
> +/**
> + * Set 2 consecutive registers if any registers value is different.
> + * @param offsetstarting register offset
> + * @param value1is written to first register
> + * @param value2is written to second register
> + */
> +static inline void radeon_opt_set_context_reg2(struct si_context *sctx,
> unsigned offset,
> + enum si_tracked_reg reg,
> unsigned value1,
> + unsigned value2)
> +{
> + struct radeon_winsys_cs *cs = sctx->gfx_cs;
> +
> + if (!(sctx->tracked_regs.reg_saved & (1 << reg)) ||
> + !(sctx->tracked_regs.reg_saved & (1 << (reg + 1))) ||
> + sctx->tracked_regs.reg_value[reg] != value1 ||
> + sctx->tracked_regs.reg_value[reg+1] != value2 ) {
> +
> + radeon_set_context_reg_seq(cs, offset, 2);
> + radeon_emit(cs, value1);
> + radeon_emit(cs, value2);
> +
> + sctx->tracked_regs.reg_value[reg] = value1;
> + sctx->tracked_regs.reg_value[reg+1] = value2;
> + sctx->tracked_regs.reg_saved |= 3 << reg;
> + }
> +}
> +
> #endif
> diff --git a/src/gallium/drivers/radeonsi/si_gfx_cs.c
> b/src/gallium/drivers/radeonsi/si_gfx_cs.c
> index ec74c1b..0b9a020 100644
> --- a/src/gallium/drivers/radeonsi/si_gfx_cs.c
> +++ b/src/gallium/drivers/radeonsi/si_gfx_cs.c
> @@ -321,4 +321,7 @@ void si_begin_new_gfx_cs(struct si_context *ctx)
> ctx->last_num_tcs_input_cp = -1;
>
> ctx->cs_shader_state.initialized = false;
> +
> + /* Set all saved registers state to unknown */
> + ctx->tracked_regs.reg_saved = 0;
> }
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
> b/src/gallium/drivers/radeonsi/si_pipe.h
> index 5d1671f..82a8263 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -1033,6 +1033,8 @@ struct si_context {
>
> void (*dma_c
Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon uvd add uvd fw version for amdgpu
Hi Emil, Are you Okay with these? Thanks, Sonny From: Jiang, Sonny Sent: Monday, July 4, 2016 5:33:29 PM To: Christian König; Emil Velikov Cc: 12.0; mesa-dev@lists.freedesktop.org Subject: Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon uvd add uvd fw version for amdgpu Hi Emil, I have added comments for each patch, and applied for branch 12.0. Please find attached patches. Thanks, Sonny From: mesa-dev <mesa-dev-boun...@lists.freedesktop.org> on behalf of Christian König <deathsim...@vodafone.de> Sent: Friday, July 1, 2016 8:07:51 AM To: Emil Velikov Cc: Jiang, Sonny; 12.0; mesa-dev@lists.freedesktop.org Subject: Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon uvd add uvd fw version for amdgpu Am 01.07.2016 um 13:14 schrieb Emil Velikov: > Hi all, > > On 29 June 2016 at 20:20, Christian König <deathsim...@vodafone.de> wrote: >> Am 29.06.2016 um 18:35 schrieb Alex Deucher: >>> On Wed, Jun 29, 2016 at 11:38 AM, Leo Liu <leo@amd.com> wrote: >>>> From: sonjiang <sonny.ji...@amd.com> >>>> >>>> Signed-off-by: sonjiang <sonny.ji...@amd.com> >>>> Cc: "12.0" <mesa-sta...@lists.freedesktop.org> >>> For the series: >>> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com> >> >> Reviewed-by: Christian König <christian.koe...@amd.com> as well. >> > Here we have three patches, suggesting a bug with absolutely no > information what the issue is and/or why this approach is correct. > > I'm sorry to say this, but as is, this series is not landing in > stable. Sonjiang, being the author of these please reply with a brief > justification why we want those. Before doing so I would strongly > recommend reading this [1] blog post. Well to put a carrot on the front of your stick: I asked what the firmware version patch is all about internally as well when I've seen those patches. So it would have even made our internal review much easier if Sonny added a commit message in the first place. My fault to not requesting that his answer is put as a commit message on the patches. On the other hand this is for Polaris, we had time pressure to get it out of the door and today is a public holiday in Canada. So you probably won't get updated message before Monday. Is that soon enough? Otherwise UVD will be broken on Polaris in the stable branch. Regards, Christian. > > Thanks > Emil > > [1] http://who-t.blogspot.co.uk/2009/12/on-commit-messages.html ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon uvd add uvd fw version for amdgpu
Hi Emil,
I have added comments for each patch, and applied for branch 12.0.
Please find attached patches.
Thanks,
Sonny
From: mesa-dev <mesa-dev-boun...@lists.freedesktop.org> on behalf of Christian
König <deathsim...@vodafone.de>
Sent: Friday, July 1, 2016 8:07:51 AM
To: Emil Velikov
Cc: Jiang, Sonny; 12.0; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [Mesa-stable] [PATCH] radeon uvd add uvd fw version for
amdgpu
Am 01.07.2016 um 13:14 schrieb Emil Velikov:
> Hi all,
>
> On 29 June 2016 at 20:20, Christian König <deathsim...@vodafone.de> wrote:
>> Am 29.06.2016 um 18:35 schrieb Alex Deucher:
>>> On Wed, Jun 29, 2016 at 11:38 AM, Leo Liu <leo@amd.com> wrote:
>>>> From: sonjiang <sonny.ji...@amd.com>
>>>>
>>>> Signed-off-by: sonjiang <sonny.ji...@amd.com>
>>>> Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
>>> For the series:
>>> Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
>>
>> Reviewed-by: Christian König <christian.koe...@amd.com> as well.
>>
> Here we have three patches, suggesting a bug with absolutely no
> information what the issue is and/or why this approach is correct.
>
> I'm sorry to say this, but as is, this series is not landing in
> stable. Sonjiang, being the author of these please reply with a brief
> justification why we want those. Before doing so I would strongly
> recommend reading this [1] blog post.
Well to put a carrot on the front of your stick: I asked what the
firmware version patch is all about internally as well when I've seen
those patches. So it would have even made our internal review much
easier if Sonny added a commit message in the first place.
My fault to not requesting that his answer is put as a commit message on
the patches.
On the other hand this is for Polaris, we had time pressure to get it
out of the door and today is a public holiday in Canada. So you probably
won't get updated message before Monday.
Is that soon enough? Otherwise UVD will be broken on Polaris in the
stable branch.
Regards,
Christian.
>
> Thanks
> Emil
>
> [1] http://who-t.blogspot.co.uk/2009/12/on-commit-messages.html
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
From 53248a0392b1baf4c1cf67600088557f16d6ec8a Mon Sep 17 00:00:00 2001
From: sonjiang <sonny.ji...@amd.com>
Date: Mon, 4 Jul 2016 16:48:37 -0400
Subject: [PATCH] radeon uvd add uvd fw version for amdgpu
Because Polaris uvd fw interface changes, the driver need to check fw version
to apply right interface. This change is to add uvd fw version.
Signed-off-by: sonjiang <sonny.ji...@amd.com>
Cc: "12.0" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
---
src/gallium/drivers/radeon/radeon_winsys.h| 1 +
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 11 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 699a9eb..8b16325 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -250,6 +250,7 @@ struct radeon_info {
boolgfx_ib_pad_with_type2;
boolean has_sdma;
boolean has_uvd;
+uint32_tuvd_fw_version;
uint32_tvce_fw_version;
uint32_tvce_harvest_config;
uint32_tclock_crystal_freq;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 7016221..38b0376 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -98,7 +98,7 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws, int fd)
struct amdgpu_buffer_size_alignments alignment_info = {};
struct amdgpu_heap_info vram, gtt;
struct drm_amdgpu_info_hw_ip dma = {}, uvd = {}, vce = {};
- uint32_t vce_version = 0, vce_feature = 0;
+ uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
int r, i, j;
drmDevicePtr devinfo;
@@ -151,6 +151,13 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws, int fd)
goto fail;
}
+ r = amdgpu_query_firmware_version(ws->dev, AMDGPU_INFO_FW_UVD, 0, 0,
+_version, _feature);
+ if (r) {
+ fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
+ goto fail;
+ }
+
r = amdgpu_query_hw_ip_info(ws->dev, AMDGPU_HW_IP_VCE
