Re: [Mesa-dev] [PATCH] i965/CFL: Add PCI Ids for Coffee Lake.
>-Original Message-
>From: Anuj Phogat [mailto:anuj.pho...@gmail.com]
>Sent: Thursday, June 22, 2017 10:54 AM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: mesa-dev@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.v...@intel.com>;
>Phogat, Anuj <anuj.pho...@intel.com>; Widawsky, Benjamin
><benjamin.widaw...@intel.com>
>Subject: Re: [Mesa-dev] [PATCH] i965/CFL: Add PCI Ids for Coffee Lake.
>
>On Thu, Jun 22, 2017 at 10:42 AM, Anusha Srivatsa <anusha.sriva...@intel.com>
>wrote:
>> Coffee Lake has a gen9 graphics following KBL.
>> From 3D perspective, CFL is a clone of KBL/SKL features.
>>
>> v2: Change commit message, correct alignment
>> v3: Update IDs.
>> v4: Initialize l3_banks, correct nomenclature
>>
>> Cc: Benjamin Widawsky <benjamin.widaw...@intel.com>
>> Cc: Anuj Phogat <anuj.pho...@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> ---
>> include/pci_ids/i965_pci_ids.h | 11 +++
>> src/intel/common/gen_device_info.c | 26 ++
>> src/intel/common/gen_device_info.h | 1 +
>> 3 files changed, 38 insertions(+)
>>
>> diff --git a/include/pci_ids/i965_pci_ids.h
>> b/include/pci_ids/i965_pci_ids.h index b296359..57e70b7 100644
>> --- a/include/pci_ids/i965_pci_ids.h
>> +++ b/include/pci_ids/i965_pci_ids.h
>> @@ -165,6 +165,17 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus
>> Graphics 650 (Kaby Lake GT3)") CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake
>GT4")
>> CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
>> CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
>> +CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
>> +CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 2x6 GT1)")
>> +CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
>> +CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
>> +CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
>> +CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
>> +CHIPSET(0x3E94, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 3x8 GT2)")
>> +CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>> +CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>> +CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>> +CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 3x8 GT3)")
>> CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8
>> GT0.5)") CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake
>> 2x8 GT0.5)") CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics
>> (Cannonlake 3x8 GT1)") diff --git a/src/intel/common/gen_device_info.c
>> b/src/intel/common/gen_device_info.c
>> index 423748e..a1541ed 100644
>> --- a/src/intel/common/gen_device_info.c
>> +++ b/src/intel/common/gen_device_info.c
>> @@ -607,6 +607,32 @@ static const struct gen_device_info
>gen_device_info_glk_2x6 = {
>> .is_geminilake = true,
>> };
>>
>> +static const struct gen_device_info gen_device_info_cfl_gt1 = {
>> + GEN9_FEATURES,
>> + .is_coffeelake = true,
>> + .gt = 1,
>> + .l3_banks = 2,
>> +
>> + .num_slices = 1,
>I'll omit the blank line and move l3_banks after num_slices just for
>consistency.
>You need not send out another version for this.
Thanks Anuj.
Anusha
>> +};
>> +static const struct gen_device_info gen_device_info_cfl_gt2 = {
>> + GEN9_FEATURES,
>> + .is_coffeelake = true,
>> + .gt = 2,
>> + .l3_banks = 4,
>> +
>> + .num_slices = 1,
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_cfl_gt3 = {
>> + GEN9_FEATURES,
>> + .is_coffeelake = true,
>> + .gt = 3,
>> + .l3_banks = 8,
>> +
>> + .num_slices = 2,
>> +};
>> +
>> #define GEN10_HW_INFO \
>> .gen = 10, \
>> .num_thread_per_eu = 7, \
>> diff --git a/src/intel/common/gen_device_info.h
>> b/src/intel/common/gen_device_info.h
>> index cc83857..a83251c 100644
>> --- a/src/intel/common/gen_device_info.h
>> +++ b/src/intel/common/gen_device_info.h
>> @@ -46,6 +46,7 @@ struct gen_device_info
>> bool is_broxton;
>> bool is_kabylake;
>> bool is_geminilake;
>> + bool is_coffeelake;
>> bool is_cannonlake;
>>
>> bool has_hiz_and_separate_stencil;
>> --
>> 2.7.4
>>
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
>Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
>
>I'll push the patch upstream for you. Thanks.
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Re: [Mesa-dev] [PATCH] i965/CFL: Add PCI Ids for Coffee Lake.
>-Original Message-
>From: Anuj Phogat [mailto:anuj.pho...@gmail.com]
>Sent: Wednesday, June 21, 2017 12:32 PM
>To: Srivatsa, Anusha <anusha.sriva...@intel.com>
>Cc: mesa-dev@lists.freedesktop.org; Vivi, Rodrigo <rodrigo.v...@intel.com>;
>Phogat, Anuj <anuj.pho...@intel.com>; Widawsky, Benjamin
><benjamin.widaw...@intel.com>
>Subject: Re: [Mesa-dev] [PATCH] i965/CFL: Add PCI Ids for Coffee Lake.
>
>On Wed, Jun 21, 2017 at 11:19 AM, Anusha Srivatsa <anusha.sriva...@intel.com>
>wrote:
>> Coffee Lake has a gen9 graphics following KBL.
>> From 3D perspective, CFL is a clone of KBL/SKL features.
>>
>> v2: Change commit message, correct alignment
>> v3: Update IDs.
>>
>> Cc: Benjamin Widawsky <benjamin.widaw...@intel.com>
>> Cc: Anuj Phogat <anuj.pho...@intel.com>
>> Cc: Rodrigo Vivi <rodrigo.v...@intel.com>
>> Signed-off-by: Anusha Srivatsa <anusha.sriva...@intel.com>
>> ---
>> include/pci_ids/i965_pci_ids.h | 11 +++
>> src/intel/common/gen_device_info.c | 23 +++
>> src/intel/common/gen_device_info.h | 1 +
>> 3 files changed, 35 insertions(+)
>>
>> diff --git a/include/pci_ids/i965_pci_ids.h
>> b/include/pci_ids/i965_pci_ids.h index b296359..5e9566c 100644
>> --- a/include/pci_ids/i965_pci_ids.h
>> +++ b/include/pci_ids/i965_pci_ids.h
>> @@ -165,6 +165,17 @@ CHIPSET(0x5927, kbl_gt3, "Intel(R) Iris Plus
>> Graphics 650 (Kaby Lake GT3)") CHIPSET(0x593B, kbl_gt4, "Intel(R) Kabylake
>GT4")
>> CHIPSET(0x3184, glk, "Intel(R) HD Graphics (Geminilake)")
>> CHIPSET(0x3185, glk_2x6, "Intel(R) HD Graphics (Geminilake 2x6)")
>> +CHIPSET(0x3E90, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 6x1)")
>> +CHIPSET(0x3E93, cfl_gt1, "Intel(R) HD Graphics (Coffeelake 4x1)")
>(Coffeelake 2x6 GT1). All CFL GT1 have 2 subslices and 6 EU/subslice.
Oops Thanks for pointing out.
Will send revised patch soon.
>> +CHIPSET(0x3E91, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 4x2)")
>> +CHIPSET(0x3E92, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 6x2)")
>> +CHIPSET(0x3E96, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 6x2)")
>> +CHIPSET(0x3E9B, cfl_gt2, "Intel(R) HD Graphics (Coffeelake 6x2)")
>(Coffeelake 3x8 GT2). All CFL GT2 have 3 subslices and 8 EU/subslice.
>> +CHIPSET(0x3E94, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 4x3)")
>This is GT2 with 24 EUs.
>> +CHIPSET(0x3EA6, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 4x3)")
>> +CHIPSET(0x3EA7, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 4x3)")
>> +CHIPSET(0x3EA8, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 4x3)")
>> +CHIPSET(0x3EA5, cfl_gt3, "Intel(R) HD Graphics (Coffeelake 4x3)")
>(Coffeelake 3x8 GT3). All CFL GT2 have 3 subslices and 8 EU/subslice.
>> CHIPSET(0x5A49, cnl_2x8, "Intel(R) HD Graphics (Cannonlake 2x8
>> GT0.5)") CHIPSET(0x5A4A, cnl_2x8, "Intel(R) HD Graphics (Cannonlake
>> 2x8 GT0.5)") CHIPSET(0x5A41, cnl_3x8, "Intel(R) HD Graphics
>> (Cannonlake 3x8 GT1)") diff --git a/src/intel/common/gen_device_info.c
>> b/src/intel/common/gen_device_info.c
>> index 423748e..d49beaa 100644
>> --- a/src/intel/common/gen_device_info.c
>> +++ b/src/intel/common/gen_device_info.c
>> @@ -607,6 +607,29 @@ static const struct gen_device_info
>gen_device_info_glk_2x6 = {
>> .is_geminilake = true,
>> };
>>
>> +static const struct gen_device_info gen_device_info_cfl_gt1 = {
>> + GEN9_FEATURES,
>> + .is_coffeelake = true,
>> + .gt = 1,
>> +
>> + .num_slices = 1,
>Also initialize l3_banks variable.
Sure. Thanks again,
Anusha
>> +};
>> +static const struct gen_device_info gen_device_info_cfl_gt2 = {
>> + GEN9_FEATURES,
>> + .is_coffeelake = true,
>> + .gt = 2,
>> +
>> + .num_slices = 1,
>Here too.
>> +};
>> +
>> +static const struct gen_device_info gen_device_info_cfl_gt3 = {
>> + GEN9_FEATURES,
>> + .is_coffeelake = true,
>> + .gt = 3,
>> +
>> + .num_slices = 2,
>and here.
>> +};
>> +
>> #define GEN10_HW_INFO \
>> .gen = 10, \
>> .num_thread_per_eu = 7, \
>> diff --git a/src/intel/common/gen_device_info.h
>> b/src/intel/common/gen_device_info.h
>> index cc83857..a83251c 100644
>> --- a/src/intel/common/gen_device_info.h
>> +++ b/src/intel/common/gen_device_info.h
>> @@ -46,6 +46,7 @@ struct gen_device_info
>> bool is_broxton;
>> bool is_kabylake;
>> bool is_geminilake;
>> + bool is_coffeelake;
>> bool is_cannonlake;
>>
>> bool has_hiz_and_separate_stencil;
>> --
>> 2.7.4
>>
>> ___
>> mesa-dev mailing list
>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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