[Mesa-dev] [PATCH] anv/cmd_buffer: Reuse gen8 Cmd{Set, Reset}Event on gen7

[Ville Syrjala]

From: Ville Syrjälä 

Modern DXVK requires event support [1], but looks like it only
uses vkCmdSetEvent() + vkGetEventStatus(). So we can just
borrow the relevant code from gen8, leaving CmdWaitEvents still
unimplemented.

[1] 
https://github.com/doitsujin/dxvk/commit/8c3900c533d83d12c970b905183d17a1d3e8df1f

v2: Also move CmdWaitEvents into genX_cmd_buffer.c (Jason)

Signed-off-by: Ville Syrjälä 
---
 src/intel/vulkan/gen7_cmd_buffer.c |  38 --
 src/intel/vulkan/gen8_cmd_buffer.c | 102 ---
 src/intel/vulkan/genX_cmd_buffer.c | 107 +
 3 files changed, 107 insertions(+), 140 deletions(-)

diff --git a/src/intel/vulkan/gen7_cmd_buffer.c 
b/src/intel/vulkan/gen7_cmd_buffer.c
index 380283bdd563..115d12b35362 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -286,41 +286,3 @@ genX(cmd_buffer_enable_pma_fix)(struct anv_cmd_buffer 
*cmd_buffer,
 {
/* The NP PMA fix doesn't exist on gen7 */
 }
-
-void genX(CmdSetEvent)(
-VkCommandBuffer commandBuffer,
-VkEvent event,
-VkPipelineStageFlagsstageMask)
-{
-   anv_finishme("Implement events on gen7");
-}
-
-void genX(CmdResetEvent)(
-VkCommandBuffer commandBuffer,
-VkEvent event,
-VkPipelineStageFlagsstageMask)
-{
-   anv_finishme("Implement events on gen7");
-}
-
-void genX(CmdWaitEvents)(
-VkCommandBuffer commandBuffer,
-uint32_teventCount,
-const VkEvent*  pEvents,
-VkPipelineStageFlagssrcStageMask,
-VkPipelineStageFlagsdestStageMask,
-uint32_tmemoryBarrierCount,
-const VkMemoryBarrier*  pMemoryBarriers,
-uint32_tbufferMemoryBarrierCount,
-const VkBufferMemoryBarrier*pBufferMemoryBarriers,
-uint32_timageMemoryBarrierCount,
-const VkImageMemoryBarrier* pImageMemoryBarriers)
-{
-   anv_finishme("Implement events on gen7");
-
-   genX(CmdPipelineBarrier)(commandBuffer, srcStageMask, destStageMask,
-false, /* byRegion */
-memoryBarrierCount, pMemoryBarriers,
-bufferMemoryBarrierCount, pBufferMemoryBarriers,
-imageMemoryBarrierCount, pImageMemoryBarriers);
-}
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c 
b/src/intel/vulkan/gen8_cmd_buffer.c
index 6568d2c75113..2e6d9de9f4a8 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -565,105 +565,3 @@ void genX(CmdBindIndexBuffer)(
 
cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER;
 }
-
-/* Set of stage bits for which are pipelined, i.e. they get queued by the
- * command streamer for later execution.
- */
-#define ANV_PIPELINE_STAGE_PIPELINED_BITS \
-   (VK_PIPELINE_STAGE_VERTEX_INPUT_BIT | \
-VK_PIPELINE_STAGE_VERTEX_SHADER_BIT | \
-VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT | \
-VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT | \
-VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT | \
-VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT | \
-VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT | \
-VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT | \
-VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT | \
-VK_PIPELINE_STAGE_COMPUTE_SHADER_BIT | \
-VK_PIPELINE_STAGE_TRANSFER_BIT | \
-VK_PIPELINE_STAGE_BOTTOM_OF_PIPE_BIT | \
-VK_PIPELINE_STAGE_ALL_GRAPHICS_BIT | \
-VK_PIPELINE_STAGE_ALL_COMMANDS_BIT)
-
-void genX(CmdSetEvent)(
-VkCommandBuffer commandBuffer,
-VkEvent _event,
-VkPipelineStageFlagsstageMask)
-{
-   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
-   ANV_FROM_HANDLE(anv_event, event, _event);
-
-   anv_batch_emit(_buffer->batch, GENX(PIPE_CONTROL), pc) {
-  if (stageMask & ANV_PIPELINE_STAGE_PIPELINED_BITS) {
- pc.StallAtPixelScoreboard = true;
- pc.CommandStreamerStallEnable = true;
-  }
-
-  pc.DestinationAddressType  = DAT_PPGTT,
-  pc.PostSyncOperation   = WriteImmediateData,
-  pc.Address = (struct anv_address) {
- cmd_buffer->device->dynamic_state_pool.block_pool.bo,
- event->state.offset
-  };
-  pc.ImmediateData   = VK_EVENT_SET;
-   }
-}
-
-void genX(CmdResetEvent)(
-VkCommandBuffer commandBuffer,
-VkEvent _event,
-VkPipelineStageFlagsstageMask)
-{
-   ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, 

[Mesa-dev] [PATCH] meson: Fix build for egl platform_x11 with dri3

[Ville Syrjala]

From: Ville Syrjälä 

platform_x11 with dri3 needs inc_loader.

In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No 
such file or directory
In file included from ../src/egl/drivers/dri2/platform_x11.c:46:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No 
such file or directory
In file included from ../src/egl/drivers/dri2/egl_dri2.c:61:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No 
such file or directory

Cc: Dylan Baker 
Signed-off-by: Ville Syrjälä 
---
 src/egl/meson.build | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/egl/meson.build b/src/egl/meson.build
index 6537e4bdee61..9050d763a6cd 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -102,6 +102,7 @@ if with_platform_x11
   if with_dri3
 files_egl += files('drivers/dri2/platform_x11_dri3.c')
 link_for_egl += libloader_dri3_helper
+incs_for_egl += inc_loader
   endif
   deps_for_egl += [dep_x11_xcb, dep_xcb_dri2, dep_xcb_xfixes]
 endif
-- 
2.16.1

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[Mesa-dev] [PATCH 2/2] meson: Build i915

[Ville Syrjala]

From: Ville Syrjälä 

Build i915 with meson. More or less copied from i965, with all
the unneeded cruft removed, and the libdrm_intel dependency added.

Cc: Dylan Baker 
Cc: Eric Anholt 
Signed-off-by: Ville Syrjälä 
---
 meson.build   |  7 +++
 meson_options.txt |  2 +-
 src/mesa/drivers/dri/i915/meson.build | 97 +++
 src/mesa/drivers/dri/meson.build  |  3 ++
 4 files changed, 108 insertions(+), 1 deletion(-)
 create mode 100644 src/mesa/drivers/dri/i915/meson.build

diff --git a/meson.build b/meson.build
index 4ba00283cec7..02264aeed4ef 100644
--- a/meson.build
+++ b/meson.build
@@ -72,16 +72,23 @@ if (with_gles1 or with_gles2) and not with_opengl
 endif
 
 with_dri = false
+with_dri_i915 = false
 with_dri_i965 = false
 with_dri_swrast = false
 _drivers = get_option('dri-drivers')
 if _drivers != ''
   _split = _drivers.split(',')
+  with_dri_i915 = _split.contains('i915')
   with_dri_i965 = _split.contains('i965')
   with_dri_swrast = _split.contains('swrast')
   with_dri = true
 endif
 
+dep_libdrm_intel = []
+if with_dri_i915
+  dep_libdrm_intel = dependency('libdrm_intel', version : '>= 2.4.75')
+endif
+
 if not with_dri
   with_gles1 = false
   with_gles2 = false
diff --git a/meson_options.txt b/meson_options.txt
index 029626d69a47..abd5135742ac 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -22,7 +22,7 @@ option('platforms', type : 'string', value : 'x11,wayland',
description : 'comma separated list of window systems to support. 
wayland, x11, surfaceless, drm, etc.')
 option('dri3', type : 'combo', value : 'auto', choices : ['auto', 'yes', 'no'],
description : 'enable support for dri3')
-option('dri-drivers', type : 'string', value : 'swrast,i965',
+option('dri-drivers', type : 'string', value : 'swrast,i915,i965',
description : 'comma separated list of dri drivers to build.')
 option('dri-drivers-path', type : 'string', value : '',
description : 'Location of dri drivers. Default: $libdir/dri.')
diff --git a/src/mesa/drivers/dri/i915/meson.build 
b/src/mesa/drivers/dri/i915/meson.build
new file mode 100644
index ..1971419a6b71
--- /dev/null
+++ b/src/mesa/drivers/dri/i915/meson.build
@@ -0,0 +1,97 @@
+# Copyright © 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+files_i915 = files(
+  'i830_context.c',
+  'i830_context.h',
+  'i830_reg.h',
+  'i830_state.c',
+  'i830_texblend.c',
+  'i830_texstate.c',
+  'i830_vtbl.c',
+  'i915_context.c',
+  'i915_context.h',
+  'i915_debug_fp.c',
+  'i915_debug.h',
+  'i915_fragprog.c',
+  'i915_program.c',
+  'i915_program.h',
+  'i915_reg.h',
+  'i915_state.c',
+  'i915_tex_layout.c',
+  'i915_texstate.c',
+  'i915_vtbl.c',
+  'intel_batchbuffer.c',
+  'intel_batchbuffer.h',
+  'intel_blit.c',
+  'intel_blit.h',
+  'intel_buffer_objects.c',
+  'intel_buffer_objects.h',
+  'intel_buffers.c',
+  'intel_buffers.h',
+  'intel_chipset.h',
+  'intel_clear.c',
+  'intel_clear.h',
+  'intel_context.c',
+  'intel_context.h',
+  'intel_extensions.c',
+  'intel_extensions.h',
+  'intel_fbo.c',
+  'intel_fbo.h',
+  'intel_mipmap_tree.c',
+  'intel_mipmap_tree.h',
+  'intel_pixel_bitmap.c',
+  'intel_pixel.c',
+  'intel_pixel_copy.c',
+  'intel_pixel_draw.c',
+  'intel_pixel.h',
+  'intel_pixel_read.c',
+  'intel_reg.h',
+  'intel_regions.c',
+  'intel_regions.h',
+  'intel_render.c',
+  'intel_screen.c',
+  'intel_screen.h',
+  'intel_state.c',
+  'intel_syncobj.c',
+  'intel_tex.c',
+  'intel_tex_copy.c',
+  'intel_tex.h',
+  'intel_tex_image.c',
+  'intel_tex_layout.c',
+  'intel_tex_layout.h',
+  'intel_tex_obj.h',
+  'intel_tex_subimage.c',
+  'intel_tex_validate.c',
+  'intel_tris.c',
+  'intel_tris.h',
+)
+
+libi915 = static_library(
+  'i915',
+  [files_i915, xmlpool_options_h],
+  include_directories : 

[Mesa-dev] [PATCH 1/2] meson: Fix xf86vm dep

[Ville Syrjala]

From: Ville Syrjälä 

The pkg-config file is called xxf86vm.pc not xf86vm.pc.

Cc: Dylan Baker 
Cc: Eric Anholt 
Signed-off-by: Ville Syrjälä 
---
 meson.build | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/meson.build b/meson.build
index bff40f697d37..4ba00283cec7 100644
--- a/meson.build
+++ b/meson.build
@@ -582,7 +582,7 @@ if with_platform_x11
 dependency('xcb-glx', version : '>= 1.8.1'),
   ]
 
-  dep_xf86vm = dependency('xf86vm', required : false)
+  dep_xf86vm = dependency('xxf86vm', required : false)
 endif
 # TODO: XF86VIDMODE
   endif
-- 
2.13.6

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[Mesa-dev] [PATCH] meta: Fix BlitFramebuffer temp texture setup

[ville . syrjala]

From: Ville Syrjälä 

Pass the correct src coordinates to CopyTexSubImage()
when creating the temporary texture, and also take care to adjust
flipX/Y if the original src coordinates were flipped compared to
the new temporary texture src coordinates.

This fixes all the flip_src_x/y tests in
piglit.spec.arb_framebuffer_object.fbo-blit-stretch on i915, but
we're still left with the some failures in the stretch tests.

It looks to me like commit b702233f53d6 ("meta: Refactor the
BlitFramebuffer color CopyTexImage fallback.") most likely
broke this codepath.

Cc: mesa-sta...@lists.freedesktop.org
Cc: Eric Anholt 
Cc: Kenneth Graunke 
Cc: Ian Romanick 
Cc: Anuj Phogat 
Fixes: b702233f53d6 ("meta: Refactor the BlitFramebuffer color CopyTexImage 
fallback.")
References: https://bugs.freedesktop.org/show_bug.cgi?id=101414
Signed-off-by: Ville Syrjälä 
---
 src/mesa/drivers/common/meta_blit.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index 7adad469aceb..7262ecdfaf13 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -680,12 +680,16 @@ blitframebuffer_texture(struct gl_context *ctx,
   }
 
   _mesa_meta_setup_copypix_texture(ctx, meta_temp_texture,
-   srcX0, srcY0,
+   MIN2(srcX0, srcX1),
+   MIN2(srcY0, srcY1),
srcW, srcH,
tex_base_format,
filter);
 
-
+  if (srcX0 > srcX1)
+ flipX = -flipX;
+  if (srcY0 > srcY1)
+ flipY = -flipY;
   srcX0 = 0;
   srcY0 = 0;
   srcX1 = srcW;
-- 
2.13.0

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[Mesa-dev] [PATCH] i915: Fix gl_Fragcoord interpolation

[ville . syrjala]

From: Ville Syrjälä 

gl_FragCoord contains the window coordinates so it seems to me that
we should not use perspective correct interpolation for it. At least
now I get similar output as i965/swrast/llvmpipe produce.

This fixes dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_w.
dEQP-GLES2.functional.shaders.builtin_variable.fragcoord_xyz was already
passing, though I'm not quite sure how it managed to do that.

Signed-off-by: Ville Syrjälä 
---
 src/mesa/drivers/dri/i915/i915_context.h  | 13 +++--
 src/mesa/drivers/dri/i915/i915_fragprog.c |  4 
 src/mesa/drivers/dri/i915/i915_state.c|  7 ---
 src/mesa/drivers/dri/i915/i915_vtbl.c |  7 +--
 src/mesa/drivers/dri/i915/intel_reg.h |  3 ++-
 5 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.h 
b/src/mesa/drivers/dri/i915/i915_context.h
index f95b531a413e..4e68d1193ca6 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -79,12 +79,13 @@
 #define I915_CTXREG_STATE4 0
 #define I915_CTXREG_LI 1
 #define I915_CTXREG_LIS2   2
-#define I915_CTXREG_LIS4   3
-#define I915_CTXREG_LIS5   4
-#define I915_CTXREG_LIS6   5
-#define I915_CTXREG_BF_STENCIL_OPS 6
-#define I915_CTXREG_BF_STENCIL_MASKS   7
-#define I915_CTX_SETUP_SIZE8
+#define I915_CTXREG_LIS3   3
+#define I915_CTXREG_LIS4   4
+#define I915_CTXREG_LIS5   5
+#define I915_CTXREG_LIS6   6
+#define I915_CTXREG_BF_STENCIL_OPS 7
+#define I915_CTXREG_BF_STENCIL_MASKS   8
+#define I915_CTX_SETUP_SIZE9
 
 #define I915_BLENDREG_IAB  0
 #define I915_BLENDREG_BLENDCOLOR0  1
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c 
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 3657b2d82565..2e0431951217 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1238,6 +1238,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
const GLbitfield64 inputsRead = p->FragProg.info.inputs_read;
GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
GLuint s2 = S2_TEXCOORD_NONE;
+   GLuint s3 = 0;
int i, offset = 0;
 
/* Important:
@@ -1301,6 +1302,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
   */
  s2 &= ~S2_TEXCOORD_FMT(i, S2_TEXCOORD_FMT0_MASK);
  s2 |= S2_TEXCOORD_FMT(i, SZ_TO_HW(wpos_size));
+ s3 |= S3_TEXCOORD_PERSPECTIVE_DISABLE(i);
 
  intel->wpos_offset = offset;
  EMIT_PAD(wpos_size);
@@ -1308,6 +1310,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
}
 
if (s2 != i915->state.Ctx[I915_CTXREG_LIS2] ||
+   s3 != i915->state.Ctx[I915_CTXREG_LIS3] ||
s4 != i915->state.Ctx[I915_CTXREG_LIS4]) {
   I915_STATECHANGE(i915, I915_UPLOAD_CTX);
 
@@ -1326,6 +1329,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
   intel->vertex_size >>= 2;
 
   i915->state.Ctx[I915_CTXREG_LIS2] = s2;
+  i915->state.Ctx[I915_CTXREG_LIS3] = s3;
   i915->state.Ctx[I915_CTXREG_LIS4] = s4;
 
   assert(intel->vtbl.check_vertex_size(intel, intel->vertex_size));
diff --git a/src/mesa/drivers/dri/i915/i915_state.c 
b/src/mesa/drivers/dri/i915/i915_state.c
index 715db1fffa3d..4c4d95c420a1 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -925,11 +925,12 @@ i915_init_packets(struct i915_context *i915)
* piece changes.
*/
   i915->state.Ctx[I915_CTXREG_LI] = (_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
- I1_LOAD_S(2) |
- I1_LOAD_S(4) |
- I1_LOAD_S(5) | I1_LOAD_S(6) | (3));
+ I1_LOAD_S(2) | I1_LOAD_S(3) |
+ I1_LOAD_S(4) | I1_LOAD_S(5) |
+ I1_LOAD_S(6) | (4));
   i915->state.Ctx[I915_CTXREG_LIS2] = 0;
   i915->state.Ctx[I915_CTXREG_LIS4] = 0;
+  i915->state.Ctx[I915_CTXREG_LIS3] = 0;
   i915->state.Ctx[I915_CTXREG_LIS5] = 0;
 
   if (i915->intel.ctx.Visual.rgbBits == 16)
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c 
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index c41cd37bcc23..6a0a121856d7 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -176,7 +176,7 @@ i915_emit_invarient_state(struct intel_context *intel)
 {
BATCH_LOCALS;
 
-   BEGIN_BATCH(17);
+   BEGIN_BATCH(15);
 
OUT_BATCH(_3DSTATE_AA_CMD |
  AA_LINE_ECAAR_WIDTH_ENABLE |
@@ -200,11 +200,6 @@ i915_emit_invarient_state(struct intel_context *intel)
  CSB_TCB(3, 3) |
  CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | 

[Mesa-dev] [PATCH] i915: Always emit W on gen3

[ville . syrjala]

From: Ville Syrjälä 

Unlike the older gen2 hardware, gen3 performs perspective
correct interpolation even for the primary/secondary colors.
To do that it naturally needs us to emit W for the vertices.

Currently we emit W only when at least one texture coordinate
set gets emitted. This means the interpolation of color will
change depending on whether texcoords/varyings are used or not.
That's probably not what anyone would expect, so let's just
always emit W to get consistent behaviour. Trying to avoid
emitting W seems like more hassle than it's worth, especially
as bspec seems to suggest that the hardware will perform the
perspective division anyway.

This used to be broken until it was accidentally fixed it in
commit c349031c27b7 ("i915: Fix texcoord vs. varying collision
in fragment programs") by introducing a bug that made the driver
always emit W. After fixing that bug in commit c1eedb43f32f
("i915: Fix wpos_tex vs. -1 comparison") we went back to the
old behaviour and caused an apparent regression.

Fixes: c1eedb43f32f ("i915: Fix wpos_tex vs. -1 comparison")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101451
Signed-off-by: Ville Syrjälä 
---
 src/mesa/drivers/dri/i915/i915_fragprog.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c 
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index e19ca60bd334..3657b2d82565 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1252,12 +1252,10 @@ i915ValidateFragmentProgram(struct i915_context *i915)
intel->coloroffset = 0;
intel->specoffset = 0;
 
-   if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != 
I915_WPOS_TEX_INVALID) {
-  EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16);
-   }
-   else {
-  EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, S4_VFMT_XYZ, 12);
-   }
+   /* Always emit W to get consistent perspective
+* correct interpolation of primary/secondary colors.
+*/
+   EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16);
 
/* Handle gl_PointSize builtin var here */
if (ctx->Point._Attenuated || ctx->VertexProgram.PointSizeEnabled)
-- 
2.13.0

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[Mesa-dev] [PATCH] i915: Fix wpos_tex vs. -1 comparison

[ville . syrjala]

From: Ville Syrjälä 

wpos_tex used to be a GLuint so assinging -1 to it and
later comparing with -1 worked correctly, but commit
c349031c27b7 ("i915: Fix texcoord vs. varying collision in
fragment programs") changed wpos_tex to uint8_t and hence
broke the comparison. To fix this define a more explicit
invalid value for wpos_tex.

gcc warns us:
i915_fragprog.c:1255:57: warning: comparison is always true due to limited 
range of data type [-Wtype-limits]
if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != -1) {
 ^

And clang says:
i915_fragprog.c:1255:57: warning: comparison of constant -1 with expression of 
type 'uint8_t' (aka 'unsigned char') is always true 
[-Wtautological-constant-out-of-range-compare]
   if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != -1) {
~~~ ^  ~~

Cc: Chih-Wei Huang 
Cc: Eric Anholt 
Cc: Ian Romanick 
Cc: mesa-sta...@lists.freedesktop.org
Fixes: c349031c27b7 ("i915: Fix texcoord vs. varying collision in fragment 
programs")
Signed-off-by: Ville Syrjälä 
---
 src/mesa/drivers/dri/i915/i915_context.h  | 1 +
 src/mesa/drivers/dri/i915/i915_fragprog.c | 4 ++--
 src/mesa/drivers/dri/i915/i915_program.c  | 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.h 
b/src/mesa/drivers/dri/i915/i915_context.h
index 2046d78471d7..f95b531a413e 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -116,6 +116,7 @@ enum {
 };
 
 #define I915_TEX_UNITS 8
+#define I915_WPOS_TEX_INVALID 0xff
 
 #define I915_MAX_CONSTANT  32
 #define I915_CONSTANT_SIZE (2+(4*I915_MAX_CONSTANT))
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c 
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 0fad2c34c346..e19ca60bd334 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1063,7 +1063,7 @@ check_wpos(struct i915_fragment_program *p)
GLint i;
unsigned unit = 0;
 
-   p->wpos_tex = -1;
+   p->wpos_tex = I915_WPOS_TEX_INVALID;
 
if ((inputs & VARYING_BIT_POS) == 0)
   return;
@@ -1252,7 +1252,7 @@ i915ValidateFragmentProgram(struct i915_context *i915)
intel->coloroffset = 0;
intel->specoffset = 0;
 
-   if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != -1) {
+   if (inputsRead & VARYING_BITS_TEX_ANY || p->wpos_tex != 
I915_WPOS_TEX_INVALID) {
   EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, S4_VFMT_XYZW, 16);
}
else {
diff --git a/src/mesa/drivers/dri/i915/i915_program.c 
b/src/mesa/drivers/dri/i915/i915_program.c
index a8f693f71af8..20a47804249e 100644
--- a/src/mesa/drivers/dri/i915/i915_program.c
+++ b/src/mesa/drivers/dri/i915/i915_program.c
@@ -482,7 +482,7 @@ i915_init_program(struct i915_context *i915, struct 
i915_fragment_program *p)
p->decl_t = 0;
p->temp_flag = 0x000;
p->utemp_flag = ~0x7;
-   p->wpos_tex = -1;
+   p->wpos_tex = I915_WPOS_TEX_INVALID;
p->depth_written = 0;
p->nr_params = 0;
 
-- 
2.13.0

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[Mesa-dev] [PATCH] configure.ac: Refuse to build Vulkan without DRI3

[ville . syrjala]

From: Ville Syrjälä 

Trying to build the Vulkan WSI code results in a failure without DRI3.
Make configure check that DRI3 is available before trying to build
the Vulkan drivers.

Signed-off-by: Ville Syrjälä 
---
 configure.ac | 4 
 1 file changed, 4 insertions(+)

diff --git a/configure.ac b/configure.ac
index 957d15df8caa..248736c63aaa 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1844,6 +1844,10 @@ if test -n "$with_vulkan_drivers"; then
 AC_MSG_ERROR([Vulkan drivers require the dl_iterate_phdr function])
 fi
 
+if test "x$enable_dri3" = xno; then
+AC_MSG_ERROR([Vulkan requires DRI3])
+fi
+
 VULKAN_DRIVERS=`IFS=', '; echo $with_vulkan_drivers`
 for driver in $VULKAN_DRIVERS; do
 case "x$driver" in
-- 
2.10.2

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[Mesa-dev] [PATCH] anv: Prefer in-tree headers to out-of-tree headers

[ville . syrjala]

From: Ville Syrjälä 

Set the include paths to consider in-tree headers before out-of-tree
headers.

Avoids the build failing due to stale headers being present in
$prefix. Previosuly 'make -ki install' or something similar was required
to update the out-of-tree headers to allow the build to succeed.

Also avoids having to rebuild the entire thing after every 'make
install'.

Cc: Rob Clark 
Cc: Jason Ekstrand 
Signed-off-by: Ville Syrjälä 
---
 src/intel/vulkan/Makefile.am | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am
index ce31abb2fce7..b80f8767296c 100644
--- a/src/intel/vulkan/Makefile.am
+++ b/src/intel/vulkan/Makefile.am
@@ -43,9 +43,6 @@ noinst_LTLIBRARIES = $(PER_GEN_LIBS)
 # The gallium includes are for the util/u_math.h include from main/macros.h
 
 AM_CPPFLAGS = \
-   $(INTEL_CFLAGS) \
-   $(VALGRIND_CFLAGS) \
-   $(DEFINES) \
-I$(top_srcdir)/include \
-I$(top_builddir)/src \
-I$(top_srcdir)/src \
@@ -61,6 +58,17 @@ AM_CPPFLAGS = \
-I$(top_builddir)/src/intel \
-I$(top_srcdir)/src/intel
 
+if HAVE_PLATFORM_WAYLAND
+AM_CPPFLAGS += \
+   -I$(top_builddir)/src/egl/wayland/wayland-drm \
+   -I$(top_srcdir)/src/egl/wayland/wayland-drm
+endif
+
+AM_CPPFLAGS += \
+   $(INTEL_CFLAGS) \
+   $(VALGRIND_CFLAGS) \
+   $(DEFINES)
+
 AM_CFLAGS = \
$(VISIBILITY_CFLAGS) \
-Wno-override-init -msse2
@@ -99,8 +107,6 @@ endif
 
 if HAVE_PLATFORM_WAYLAND
 AM_CPPFLAGS += \
-   -I$(top_builddir)/src/egl/wayland/wayland-drm \
-   -I$(top_srcdir)/src/egl/wayland/wayland-drm \
$(WAYLAND_CFLAGS) \
-DVK_USE_PLATFORM_WAYLAND_KHR
 
-- 
2.7.4

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[Mesa-dev] [PATCH] anv/formats: Fix build on gcc-4 and earlier

[ville . syrjala]

From: Ville Syrjälä 

gcc-4 and earlier don't allow compound literals where a constant
is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
when populating the anv_formats[] array. There are a few ways around
it: First one would be -std=c89/gnu89, but the rest of the code
depends on c99 so it's not really an option. The second option
would be to upgrade to gcc-5+ where the compiler behaviour was relaxed
a bit [1]. And the third option is just to avoid using compound
literals. I chose the last option since it keeps gcc-4 and earlier
working.

[1] https://gcc.gnu.org/gcc-5/porting_to.html

Cc: Jason Ekstrand 
Cc: Topi Pohjolainen 
Fixes: 7ddb21708c80 ("intel/isl: Add an isl_swizzle structure and use it for 
isl_view swizzles")
Signed-off-by: Ville Syrjälä 
---
 src/intel/vulkan/anv_formats.c | 23 +++
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 7341d725cd0a..f6915540fb3d 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -24,9 +24,24 @@
 #include "anv_private.h"
 #include "vk_format_info.h"
 
-#define RGBA ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
-#define BGRA ISL_SWIZZLE(BLUE, GREEN, RED, ALPHA)
-#define RGB1 ISL_SWIZZLE(RED, GREEN, BLUE, ONE)
+/*
+ * gcc-4 and earlier don't allow compound literals where a constant
+ * is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE()
+ * here. -std=c89/gnu89 would allow it, but we depend on c99 features
+ * so using -std=c89/gnu89 is not an option. Starting from gcc-5
+ * compound literals can also be considered constant in -std=c99/gnu99
+ * mode.
+ */
+#define _ISL_SWIZZLE(r, g, b, a) { \
+  ISL_CHANNEL_SELECT_##r, \
+  ISL_CHANNEL_SELECT_##g, \
+  ISL_CHANNEL_SELECT_##b, \
+  ISL_CHANNEL_SELECT_##a, \
+}
+
+#define RGBA _ISL_SWIZZLE(RED, GREEN, BLUE, ALPHA)
+#define BGRA _ISL_SWIZZLE(BLUE, GREEN, RED, ALPHA)
+#define RGB1 _ISL_SWIZZLE(RED, GREEN, BLUE, ONE)
 
 #define swiz_fmt(__vk_fmt, __hw_fmt, __swizzle) \
[__vk_fmt] = { \
@@ -276,7 +291,7 @@ anv_get_format(const struct gen_device_info *devinfo, 
VkFormat vk_format,
  format.isl_format = rgbx;
   } else {
  format.isl_format = isl_format_rgb_to_rgba(format.isl_format);
- format.swizzle = RGB1;
+ format.swizzle = ISL_SWIZZLE(RED, GREEN, BLUE, ONE);
   }
}
 
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] i965: Actually enable L3 caching for everything on CHV

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Looks like CHV MOCS behaves a bit differently than BDW MOCS. On BDW the
target cache bits can be used to enable L3 caching regardless if how the
other bits are set up to select the UC/WT/WB caching mode for LLC/eLLC.
On CHV however it appears that the other bits control the caching mode
for the specified target cache, which is obviously just L3. So, to
actually enable L3 caching we need to specify L3+WB instead of L3+UC
in the MOCS.

Also note that there is no CPU cache snoop control in MOCS on CHV
like there was on VLV.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_defines.h | 6 ++
 src/mesa/drivers/dri/i965/brw_device_info.c | 2 ++
 2 files changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3cf778b..2ec7f39 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2493,6 +2493,12 @@ enum brw_wm_barycentric_interp_mode {
 #define BDW_MOCS_WT  0x58
 #define BDW_MOCS_PTE 0x18
 
+/* Cherryview: always use L3 caching. Apparently we have to
+ * say L3+WB instead of L3+UC to actually get L3 caching.
+ * CPU cache snooping is specifid in the PTE only.
+ */
+#define CHV_MOCS_L30x78
+
 /* Skylake: MOCS is now an index into an array of 64 different configurable
  * cache settings.  We still use only either write-back or write-through; and
  * rely on the documented default values.
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index edcfbd4..4e10c2c 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -292,6 +292,8 @@ static const struct brw_device_info brw_device_info_chv = {
.max_gs_threads = 80,
.max_wm_threads = 128,
.max_cs_threads = 28,
+   .mocs_pte = CHV_MOCS_L3,
+   .mocs_wb = CHV_MOCS_L3,
.urb = {
   .size = 192,
   .min_vs_entries = 34,
-- 
2.3.6

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[Mesa-dev] [PATCH 1/2] i965: House MOCS settings in brw_context/brw_device_info

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The layout of the MOCS bits has kept changing for each new
platform. Instead of adding platform checks all over the
place just store the MOCS settings in the device info
and context.

Currently MOCS is only ever set up in two ways: either
let the PTE choose the LLC/eLLC caching mode, or override
it to WB. L3 caching is enabled in both cases. That means
at most two different MOCS settings are required per
platform: PTE and WB.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_context.c   |  3 +++
 src/mesa/drivers/dri/i965/brw_context.h   |  2 ++
 src/mesa/drivers/dri/i965/brw_defines.h   |  2 ++
 src/mesa/drivers/dri/i965/brw_device_info.c   | 12 ++--
 src/mesa/drivers/dri/i965/brw_device_info.h   |  3 +++
 src/mesa/drivers/dri/i965/brw_draw_upload.c   |  2 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c|  6 ++
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  |  8 +++-
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  |  6 +++---
 src/mesa/drivers/dri/i965/gen7_misc_state.c   |  7 +++
 src/mesa/drivers/dri/i965/gen7_vs_state.c |  2 +-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |  7 +++
 src/mesa/drivers/dri/i965/gen8_depth_state.c  |  8 +++-
 src/mesa/drivers/dri/i965/gen8_draw_upload.c  |  8 +++-
 src/mesa/drivers/dri/i965/gen8_misc_state.c   | 13 ++---
 src/mesa/drivers/dri/i965/gen8_sol_state.c|  3 +--
 src/mesa/drivers/dri/i965/gen8_surface_state.c| 10 +++---
 17 files changed, 52 insertions(+), 50 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index f39b350..144142e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -756,6 +756,9 @@ brwCreateContext(gl_api api,
brw-needs_unlit_centroid_workaround =
   devinfo-needs_unlit_centroid_workaround;
 
+   brw-mocs_pte = devinfo-mocs_pte;
+   brw-mocs_wb = devinfo-mocs_wb;
+
brw-must_use_separate_stencil = screen-hw_must_use_separate_stencil;
brw-has_swizzling = screen-hw_has_swizzling;
 
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 58119ee..b3d9bf9 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1148,6 +1148,8 @@ struct brw_context
 */
bool needs_unlit_centroid_workaround;
 
+   uint8_t mocs_pte, mocs_wb;
+
GLuint NewGLState;
struct {
   struct brw_state_flags pipelines[BRW_NUM_PIPELINES];
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index bfcc442..3cf778b 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -29,6 +29,8 @@
   *   Keith Whitwell kei...@vmware.com
   */
 
+#include util/macros.h
+
 #define INTEL_MASK(high, low) (((1((high)-(low)+1))-1)(low))
 /* Using the GNU statement expression extension */
 #define SET_FIELD(value, field) \
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 97243a4..edcfbd4 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -23,6 +23,7 @@
 
 #include stdio.h
 #include stdlib.h
+#include brw_defines.h
 #include brw_device_info.h
 
 static const struct brw_device_info brw_device_info_i965 = {
@@ -107,7 +108,9 @@ static const struct brw_device_info brw_device_info_snb_gt2 
= {
.must_use_separate_stencil = true,   \
.has_llc = true, \
.has_pln = true, \
-   .has_surface_tile_offset = true
+   .has_surface_tile_offset = true, \
+   .mocs_pte = GEN7_MOCS_L3,\
+   .mocs_wb = GEN7_MOCS_L3
 
 static const struct brw_device_info brw_device_info_ivb_gt1 = {
GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
@@ -237,7 +240,9 @@ static const struct brw_device_info brw_device_info_hsw_gt3 
= {
.max_hs_threads = 504,   \
.max_ds_threads = 504,   \
.max_gs_threads = 504,   \
-   .max_wm_threads = 384
+   .max_wm_threads = 384,   \
+   .mocs_pte = BDW_MOCS_PTE,\
+   .mocs_wb = BDW_MOCS_WB
 
 static const struct brw_device_info brw_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
@@ -298,6 +303,7 @@ static const struct brw_device_info brw_device_info_chv = {
 };
 
 /* Thread counts and URB limits are placeholders, and may not be accurate. */
+/* FINISHME: Use PTE MOCS on Skylake. */
 #define GEN9_FEATURES   \
.gen = 9,\
.has_hiz_and_separate_stencil = true,\
@@ 

[Mesa-dev] [PATCH] i965: Add marketing names for CHV

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

All CHV devices will be branded as Intel(r) HD Graphics.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 include/pci_ids/i965_pci_ids.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
index 3e3e8fe..8d757aa 100644
--- a/include/pci_ids/i965_pci_ids.h
+++ b/include/pci_ids/i965_pci_ids.h
@@ -124,7 +124,7 @@ CHIPSET(0x1921, skl_gt2, Intel(R) Skylake ULT GT2F)
 CHIPSET(0x1926, skl_gt3, Intel(R) Skylake ULT GT3)
 CHIPSET(0x192A, skl_gt3, Intel(R) Skylake SRV GT3)
 CHIPSET(0x192B, skl_gt3, Intel(R) Skylake Halo GT3)
-CHIPSET(0x22B0, chv, Intel(R) Cherryview)
-CHIPSET(0x22B1, chv, Intel(R) Cherryview)
-CHIPSET(0x22B2, chv, Intel(R) Cherryview)
-CHIPSET(0x22B3, chv, Intel(R) Cherryview)
+CHIPSET(0x22B0, chv, Intel(R) HD Graphics (Cherryview))
+CHIPSET(0x22B1, chv, Intel(R) HD Graphics (Cherryview))
+CHIPSET(0x22B2, chv, Intel(R) HD Graphics (Cherryview))
+CHIPSET(0x22B3, chv, Intel(R) HD Graphics (Cherryview))
-- 
2.0.5

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[Mesa-dev] [PATCH] i965/disasm: Print the type after the swizzle also for 3src src operands

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The disassembly currently has the swizzle after the type for 3src source
operands, and the other way around for 2src. Flip the type and swizzle
around for 3src so that the output matches 2src.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_disasm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
b/src/mesa/drivers/dri/i965/brw_disasm.c
index c41dde2..2630218 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -955,9 +955,9 @@ src0_3src(FILE *file, struct brw_context *brw, brw_inst 
*inst)
   string(file, 0,1,0);
else
   string(file, 4,4,1);
+   err |= src_swizzle(file, brw_inst_3src_src0_swizzle(brw, inst));
err |= control(file, src da16 reg type, three_source_reg_encoding,
   brw_inst_3src_src_type(brw, inst), NULL);
-   err |= src_swizzle(file, brw_inst_3src_src0_swizzle(brw, inst));
return err;
 }
 
@@ -981,9 +981,9 @@ src1_3src(FILE *file, struct brw_context *brw, brw_inst 
*inst)
   string(file, 0,1,0);
else
   string(file, 4,4,1);
+   err |= src_swizzle(file, brw_inst_3src_src1_swizzle(brw, inst));
err |= control(file, src da16 reg type, three_source_reg_encoding,
   brw_inst_3src_src_type(brw, inst), NULL);
-   err |= src_swizzle(file, brw_inst_3src_src1_swizzle(brw, inst));
return err;
 }
 
@@ -1008,9 +1008,9 @@ src2_3src(FILE *file, struct brw_context *brw, brw_inst 
*inst)
   string(file, 0,1,0);
else
   string(file, 4,4,1);
+   err |= src_swizzle(file, brw_inst_3src_src2_swizzle(brw, inst));
err |= control(file, src da16 reg type, three_source_reg_encoding,
   brw_inst_3src_src_type(brw, inst), NULL);
-   err |= src_swizzle(file, brw_inst_3src_src2_swizzle(brw, inst));
return err;
 }
 
-- 
2.0.5

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[Mesa-dev] [PATCH 19/20] i915: Fix culling with user fbos on gen2

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Flip the cull bits when rendering to a user fbo on gen2. This
was already done on gen3 (since before git history starts)
but was missing from the gen2 code.

Fixes rendering of the driver+kart model in supertuxkart kart
selection screen.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_state.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i915/i830_state.c 
b/src/mesa/drivers/dri/i915/i830_state.c
index 3e379f3..3e7021c 100644
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -601,6 +601,8 @@ i830CullFaceFrontFace(struct gl_context * ctx, GLenum 
unused)
else if (ctx-Polygon.CullFaceMode != GL_FRONT_AND_BACK) {
   mode = CULLMODE_CW;
 
+  if (ctx-DrawBuffer  _mesa_is_user_fbo(ctx-DrawBuffer))
+ mode ^= (CULLMODE_CW ^ CULLMODE_CCW);
   if (ctx-Polygon.CullFaceMode == GL_FRONT)
  mode ^= (CULLMODE_CW ^ CULLMODE_CCW);
   if (ctx-Polygon.FrontFace != GL_CCW)
-- 
2.0.5

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[Mesa-dev] [PATCH 20/20] i915: Fix texcoord vs. varying collision in fragment programs

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

i915 fragment programs utilize the texture coordinate registers
for both texture coordinates and varyings. Unfortunately the
code doesn't check if the same index might be in use for both.
It just naively uses the index to pick a texture unit, which
could lead to collisions.

Add an extra mapping step to allocate non conflicting texture
units for both uses.

The issue can be reproduced with a pair of simple shaders like
these:
 attribute vec4 in_mod;
 varying vec4 mod;
 void main() {
   mod = in_mod;
   gl_TexCoord[0] = gl_MultiTexCoord0;
   gl_Position = gl_ModelViewProjectionMatrix * gl_Vertex;
 }

 varying vec4 mod;
 uniform sampler2D tex;
 void main() {
   gl_FragColor = texture2D(tex, vec2(gl_TexCoord[0])) * mod;
 }

This was tested on a PNV.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i915_context.h  | 14 ++---
 src/mesa/drivers/dri/i915/i915_fragprog.c | 86 +--
 2 files changed, 74 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.h 
b/src/mesa/drivers/dri/i915/i915_context.h
index fa58ecb..d8f592b 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -115,6 +115,8 @@ enum {
I915_RASTER_RULES_SETUP_SIZE,
 };
 
+#define I915_TEX_UNITS 8
+
 #define I915_MAX_CONSTANT  32
 #define I915_CONSTANT_SIZE (2+(4*I915_MAX_CONSTANT))
 
@@ -194,7 +196,8 @@ struct i915_fragment_program
 
/* Helpers for i915_fragprog.c:
 */
-   GLuint wpos_tex;
+   uint8_t texcoord_mapping[I915_TEX_UNITS];
+   uint8_t wpos_tex;
bool depth_written;
 
struct
@@ -205,15 +208,6 @@ struct i915_fragment_program
GLuint nr_params;
 };
 
-
-
-
-
-
-
-#define I915_TEX_UNITS 8
-
-
 struct i915_hw_state
 {
GLuint Ctx[I915_CTX_SETUP_SIZE];
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c 
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 9b00223..0be9c06 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -72,6 +72,24 @@ static const GLfloat cos_constants[4] = { 1.0,
-1.0 / (6 * 5 * 4 * 3 * 2 * 1)
 };
 
+/* texcoord_mapping[unit] = index | TEXCOORD_{TEX,VAR} */
+#define TEXCOORD_TEX (07)
+#define TEXCOORD_VAR (17)
+
+static GLint get_texcoord_mapping(struct i915_fragment_program *p,
+  uint8_t texcoord)
+{
+   GLint i;
+
+   for (i = 0; i  p-ctx-Const.MaxTextureCoordUnits; i++) {
+  if (p-texcoord_mapping[i] == texcoord)
+ return i;
+   }
+
+   /* blah */
+   return p-ctx-Const.MaxTextureCoordUnits - 1;
+}
+
 /**
  * Retrieve a ureg for the given source register.  Will emit
  * constants, apply swizzling and negation as needed.
@@ -82,6 +100,7 @@ src_vector(struct i915_fragment_program *p,
const struct gl_fragment_program *program)
 {
GLuint src;
+   GLint unit;
 
switch (source-File) {
 
@@ -119,8 +138,10 @@ src_vector(struct i915_fragment_program *p,
   case VARYING_SLOT_TEX5:
   case VARYING_SLOT_TEX6:
   case VARYING_SLOT_TEX7:
+ unit = get_texcoord_mapping(p, (source-Index -
+ VARYING_SLOT_TEX0) | TEXCOORD_TEX);
  src = i915_emit_decl(p, REG_TYPE_T,
-  T_TEX0 + (source-Index - VARYING_SLOT_TEX0),
+  T_TEX0 + unit,
   D0_CHANNEL_ALL);
 break;
 
@@ -132,8 +153,10 @@ src_vector(struct i915_fragment_program *p,
   case VARYING_SLOT_VAR0 + 5:
   case VARYING_SLOT_VAR0 + 6:
   case VARYING_SLOT_VAR0 + 7:
+ unit = get_texcoord_mapping(p, (source-Index -
+ VARYING_SLOT_VAR0) | TEXCOORD_VAR);
  src = i915_emit_decl(p, REG_TYPE_T,
-  T_TEX0 + (source-Index - VARYING_SLOT_VAR0),
+  T_TEX0 + unit,
   D0_CHANNEL_ALL);
  break;
 
@@ -1176,27 +1199,55 @@ fixup_depth_write(struct i915_fragment_program *p)
}
 }
 
+static void
+check_texcoord_mapping(struct i915_fragment_program *p)
+{
+   GLbitfield64 inputs = p-FragProg.Base.InputsRead;
+   GLint i;
+   GLint unit = 0;
+
+   for (i = 0; i  p-ctx-Const.MaxTextureCoordUnits; i++) {
+  if (inputs  VARYING_BIT_TEX(i)) {
+ if (unit = p-ctx-Const.MaxTextureCoordUnits) {
+unit++;
+break;
+ }
+ p-texcoord_mapping[unit++] = i | TEXCOORD_TEX;
+  }
+  if (inputs  VARYING_BIT_VAR(i)) {
+ if (unit = p-ctx-Const.MaxTextureCoordUnits) {
+unit++;
+break;
+ }
+ p-texcoord_mapping[unit++] = i | TEXCOORD_VAR;
+  }
+   }
+
+   if (unit  p-ctx-Const.MaxTextureCoordUnits)
+  i915_program_error(p, Too many texcoord units);
+}
 
 static void
 check_wpos(struct i915_fragment_program *p)
 {
GLbitfield64 inputs = 

[Mesa-dev] [PATCH 15/20] i915: Enable intel_render path for points

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The sub-pixel adjustment for points was killed off in
 commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
 Author: Xiang, Haihao haihao.xi...@intel.com
 Date:   Wed Jan 2 11:38:51 2008 +0800

i915: Needn't adjust pixel centers. fix #12944

so if we don't need it in intel_tris.c we don't need it in
intel_render.c either, which means we can allow
intel_render.c to render points.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_render.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_render.c 
b/src/mesa/drivers/dri/i915/intel_render.c
index 65ecd05..ef1c718 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -54,9 +54,7 @@
  * dma buffers.  Use strip/fan hardware primitives where possible.
  * Try to simulate missing primitives with indexed vertices.
  */
-#define HAVE_POINTS  0  /* Has it, but can't use because subpixel has 
to
- * be adjusted for points on the INTEL/I845G
- */
+#define HAVE_POINTS  1
 #define HAVE_LINES   1
 #define HAVE_LINE_STRIPS 1
 #define HAVE_TRIANGLES   1
@@ -70,7 +68,7 @@
 #define HAVE_ELTS0
 
 static const uint32_t hw_prim[GL_POLYGON + 1] = {
-   [GL_POINTS] = 0,
+   [GL_POINTS] = PRIM3D_POINTLIST,
[GL_LINES ] = PRIM3D_LINELIST,
[GL_LINE_LOOP] = PRIM3D_LINESTRIP,
[GL_LINE_STRIP] = PRIM3D_LINESTRIP,
@@ -96,7 +94,7 @@ static const GLenum reduced_prim[GL_POLYGON + 1] = {
 };
 
 static const int scale_prim[GL_POLYGON + 1] = {
-   [GL_POINTS] = 0, /* fallback case */
+   [GL_POINTS] = 1,
[GL_LINES] = 1,
[GL_LINE_LOOP] = 2,
[GL_LINE_STRIP] = 2,
-- 
2.0.5

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[Mesa-dev] [PATCH 14/20] i915: Use COPY_DWORDS for points

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The sub-pixel adjustment for points was killed off in
 commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c
 Author: Xiang, Haihao haihao.xi...@intel.com
 Date:   Wed Jan 2 11:38:51 2008 +0800

i915: Needn't adjust pixel centers. fix #12944

so we can just as well use COPY_DWORDS().

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_tris.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_tris.c 
b/src/mesa/drivers/dri/i915/intel_tris.c
index 2d91ca8..e46b142 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -457,11 +457,7 @@ intel_draw_point(struct intel_context *intel, 
intelVertexPtr v0)
GLuint *vb = intel_get_prim_space(intel, 1);
int j;
 
-   /* Adjust for sub pixel position -- still required for conform. */
-   *(float *) vb[0] = v0-v.x;
-   *(float *) vb[1] = v0-v.y;
-   for (j = 2; j  vertsize; j++)
-  vb[j] = v0-ui[j];
+   COPY_DWORDS(j, vb, vertsize, v0);
 }
 
 
-- 
2.0.5

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[Mesa-dev] [PATCH 07/20] t_dd_dmatmp: Make the render_tab[]s const

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

These tables hold function pointers and they never change so
make them const.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index 2132c07..7f9b433 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -553,7 +553,7 @@ static void TAG(render_noop)( struct gl_context *ctx,
 
 
 
-static tnl_render_func TAG(render_tab_verts)[GL_POLYGON+2] =
+static const tnl_render_func TAG(render_tab_verts)[GL_POLYGON+2] =
 {
TAG(render_points_verts),
TAG(render_lines_verts),
@@ -1046,7 +1046,7 @@ static void TAG(render_quads_elts)( struct gl_context 
*ctx,
 
 
 
-static tnl_render_func TAG(render_tab_elts)[GL_POLYGON+2] =
+static const tnl_render_func TAG(render_tab_elts)[GL_POLYGON+2] =
 {
TAG(render_points_elts),
TAG(render_lines_elts),
-- 
2.0.5

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[Mesa-dev] [PATCH 16/20] i915: Adjust line size limits

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The hardware can draw lines 0.5 to 7.5 pixels wide. Adjust the limits
to 1.0-7.0. The old limits seems to be from the era when i915 and i965
were sharing this code.

Not really sure if 1.0-7.0 is correct. Maybe it could be 0.5.7.5 as
those are the hw limits, or maybe some combination of the two?

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_context.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_context.c 
b/src/mesa/drivers/dri/i915/intel_context.c
index 12a1d2b..5f45125 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -475,8 +475,8 @@ intelInitContext(struct intel_context *intel,
 
ctx-Const.MinLineWidth = 1.0;
ctx-Const.MinLineWidthAA = 1.0;
-   ctx-Const.MaxLineWidth = 5.0;
-   ctx-Const.MaxLineWidthAA = 5.0;
+   ctx-Const.MaxLineWidth = 7.0;
+   ctx-Const.MaxLineWidthAA = 7.0;
ctx-Const.LineWidthGranularity = 0.5;
 
ctx-Const.MinPointSize = 1.0;
-- 
2.0.5

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[Mesa-dev] [PATCH 18/20] i915: Drop broken front_buffer_reading/drawing optimization

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Bring the following commit over to i915:
 commit ec542d74578bbef6b55125dd6aba1dc7f5079e65
 Author: Eric Anholt e...@anholt.net
 Date:   Mon Mar 3 10:43:10 2014 -0800

i965: Drop broken front_buffer_reading/drawing optimization.

Not sure if it might fix anything, but since the i965 and i915 used to
share a bunch of that code, it would seem reasonable the same problems
could be present in the i915 code still, and the i965 approach is well
tested by now so bringing it over seems fairly safe.

No piglit regressions on 855.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_buffers.c | 47 ++-
 src/mesa/drivers/dri/i915/intel_buffers.h |  3 ++
 src/mesa/drivers/dri/i915/intel_context.c | 12 
 src/mesa/drivers/dri/i915/intel_context.h | 16 ---
 4 files changed, 37 insertions(+), 41 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_buffers.c 
b/src/mesa/drivers/dri/i915/intel_buffers.c
index 51eaea4..d413998 100644
--- a/src/mesa/drivers/dri/i915/intel_buffers.c
+++ b/src/mesa/drivers/dri/i915/intel_buffers.c
@@ -52,23 +52,36 @@ intel_check_front_buffer_rendering(struct intel_context 
*intel)
}
 }
 
+bool
+intel_is_front_buffer_reading(struct gl_framebuffer *fb)
+{
+   if (!fb || _mesa_is_user_fbo(fb))
+  return false;
+
+   return fb-_ColorReadBufferIndex == BUFFER_FRONT_LEFT;
+}
+
+bool
+intel_is_front_buffer_drawing(struct gl_framebuffer *fb)
+{
+   if (!fb || _mesa_is_user_fbo(fb))
+  return false;
+
+   return (fb-_NumColorDrawBuffers = 1 
+   fb-_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT);
+}
+
 static void
 intelDrawBuffer(struct gl_context * ctx, GLenum mode)
 {
-   if (ctx-DrawBuffer  _mesa_is_winsys_fbo(ctx-DrawBuffer)) {
+   if (intel_is_front_buffer_drawing(ctx-DrawBuffer)) {
   struct intel_context *const intel = intel_context(ctx);
-  const bool was_front_buffer_rendering =
-   intel-is_front_buffer_rendering;
 
-  intel-is_front_buffer_rendering = (mode == GL_FRONT_LEFT)
-   || (mode == GL_FRONT) || (mode == GL_FRONT_AND_BACK);
-
-  /* If we weren't front-buffer rendering before but we are now,
-   * invalidate our DRI drawable so we'll ask for new buffers
+  /* If we might be front-buffer rendering on this buffer for the first
+   * time, invalidate our DRI drawable so we'll ask for new buffers
* (including the fake front) before we start rendering again.
*/
-  if (!was_front_buffer_rendering  intel-is_front_buffer_rendering)
-dri2InvalidateDrawable(intel-driContext-driDrawablePriv);
+  dri2InvalidateDrawable(intel-driContext-driDrawablePriv);
}
 
intel_draw_buffer(ctx);
@@ -78,20 +91,14 @@ intelDrawBuffer(struct gl_context * ctx, GLenum mode)
 static void
 intelReadBuffer(struct gl_context * ctx, GLenum mode)
 {
-   if (ctx-ReadBuffer  _mesa_is_winsys_fbo(ctx-ReadBuffer)) {
+   if (intel_is_front_buffer_reading(ctx-ReadBuffer)) {
   struct intel_context *const intel = intel_context(ctx);
-  const bool was_front_buffer_reading =
-   intel-is_front_buffer_reading;
-
-  intel-is_front_buffer_reading = (mode == GL_FRONT_LEFT)
-   || (mode == GL_FRONT);
 
-  /* If we weren't front-buffer reading before but we are now,
-   * invalidate our DRI drawable so we'll ask for new buffers
+  /* If we might be front-buffer reading on this buffer for the first
+   * time, invalidate our DRI drawable so we'll ask for new buffers
* (including the fake front) before we start reading again.
*/
-  if (!was_front_buffer_reading  intel-is_front_buffer_reading)
-dri2InvalidateDrawable(intel-driContext-driReadablePriv);
+  dri2InvalidateDrawable(intel-driContext-driReadablePriv);
}
 }
 
diff --git a/src/mesa/drivers/dri/i915/intel_buffers.h 
b/src/mesa/drivers/dri/i915/intel_buffers.h
index 42d84bc..890444c 100644
--- a/src/mesa/drivers/dri/i915/intel_buffers.h
+++ b/src/mesa/drivers/dri/i915/intel_buffers.h
@@ -49,4 +49,7 @@ intel_draw_buffer(struct gl_context * ctx)
 extern void intelInitBufferFuncs(struct dd_function_table *functions);
 void intelCalcViewport(struct gl_context * ctx);
 
+bool intel_is_front_buffer_reading(struct gl_framebuffer *fb);
+bool intel_is_front_buffer_drawing(struct gl_framebuffer *fb);
+
 #endif /* INTEL_BUFFERS_H */
diff --git a/src/mesa/drivers/dri/i915/intel_context.c 
b/src/mesa/drivers/dri/i915/intel_context.c
index 5f45125..be209dc 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -243,7 +243,7 @@ intel_prepare_render(struct intel_context *intel)
 * that will happen next will probably dirty the front buffer.  So
 * mark it as dirty here.
 */
-   if (intel-is_front_buffer_rendering)
+   if (intel_is_front_buffer_drawing(intel-ctx.DrawBuffer))
   intel-front_buffer_dirty = true;
 
/* Wait 

[Mesa-dev] [PATCH 13/20] i915: Use c99 initializers for primitive arrays

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Using c99 initializers for the primitive arrays makes things more
readable.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_render.c | 60 
 src/mesa/drivers/dri/i915/intel_tris.c   | 40 ++---
 2 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_render.c 
b/src/mesa/drivers/dri/i915/intel_render.c
index d06f75a..65ecd05 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -70,42 +70,42 @@
 #define HAVE_ELTS0
 
 static const uint32_t hw_prim[GL_POLYGON + 1] = {
-   0,
-   PRIM3D_LINELIST,
-   PRIM3D_LINESTRIP,
-   PRIM3D_LINESTRIP,
-   PRIM3D_TRILIST,
-   PRIM3D_TRISTRIP,
-   PRIM3D_TRIFAN,
-   0,
-   0,
-   PRIM3D_POLY
+   [GL_POINTS] = 0,
+   [GL_LINES ] = PRIM3D_LINELIST,
+   [GL_LINE_LOOP] = PRIM3D_LINESTRIP,
+   [GL_LINE_STRIP] = PRIM3D_LINESTRIP,
+   [GL_TRIANGLES] = PRIM3D_TRILIST,
+   [GL_TRIANGLE_STRIP] = PRIM3D_TRISTRIP,
+   [GL_TRIANGLE_FAN] = PRIM3D_TRIFAN,
+   [GL_QUADS] = 0,
+   [GL_QUAD_STRIP] = 0,
+   [GL_POLYGON] = PRIM3D_POLY,
 };
 
 static const GLenum reduced_prim[GL_POLYGON + 1] = {
-   GL_POINTS,
-   GL_LINES,
-   GL_LINES,
-   GL_LINES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES
+   [GL_POINTS] = GL_POINTS,
+   [GL_LINES] = GL_LINES,
+   [GL_LINE_LOOP] = GL_LINES,
+   [GL_LINE_STRIP] = GL_LINES,
+   [GL_TRIANGLES] = GL_TRIANGLES,
+   [GL_TRIANGLE_STRIP] = GL_TRIANGLES,
+   [GL_TRIANGLE_FAN] = GL_TRIANGLES,
+   [GL_QUADS] = GL_TRIANGLES,
+   [GL_QUAD_STRIP] = GL_TRIANGLES,
+   [GL_POLYGON] = GL_TRIANGLES,
 };
 
 static const int scale_prim[GL_POLYGON + 1] = {
-   0,   /* fallback case */
-   1,
-   2,
-   2,
-   1,
-   3,
-   3,
-   0,   /* fallback case */
-   0,   /* fallback case */
-   3
+   [GL_POINTS] = 0, /* fallback case */
+   [GL_LINES] = 1,
+   [GL_LINE_LOOP] = 2,
+   [GL_LINE_STRIP] = 2,
+   [GL_TRIANGLES] = 1,
+   [GL_TRIANGLE_STRIP] = 3,
+   [GL_TRIANGLE_FAN] = 3,
+   [GL_QUADS] = 0,  /* fallback case */
+   [GL_QUAD_STRIP] = 0, /* fallback case */
+   [GL_POLYGON] = 3,
 };
 
 
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c 
b/src/mesa/drivers/dri/i915/intel_tris.c
index 13d60b6..2d91ca8 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -701,16 +701,16 @@ do {  
\
  ***/
 
 static const GLuint hw_prim[GL_POLYGON + 1] = {
-   PRIM3D_POINTLIST,
-   PRIM3D_LINELIST,
-   PRIM3D_LINELIST,
-   PRIM3D_LINELIST,
-   PRIM3D_TRILIST,
-   PRIM3D_TRILIST,
-   PRIM3D_TRILIST,
-   PRIM3D_TRILIST,
-   PRIM3D_TRILIST,
-   PRIM3D_TRILIST
+   [GL_POINTS] = PRIM3D_POINTLIST,
+   [GL_LINES] = PRIM3D_LINELIST,
+   [GL_LINE_LOOP] = PRIM3D_LINELIST,
+   [GL_LINE_STRIP] = PRIM3D_LINELIST,
+   [GL_TRIANGLES] = PRIM3D_TRILIST,
+   [GL_TRIANGLE_STRIP] = PRIM3D_TRILIST,
+   [GL_TRIANGLE_FAN] = PRIM3D_TRILIST,
+   [GL_QUADS] = PRIM3D_TRILIST,
+   [GL_QUAD_STRIP] = PRIM3D_TRILIST,
+   [GL_POLYGON] = PRIM3D_TRILIST,
 };
 
 #define RASTERIZE(x) intelRasterPrimitive( ctx, x, hw_prim[x] )
@@ -1067,16 +1067,16 @@ intelChooseRenderState(struct gl_context * ctx)
 }
 
 static const GLenum reduced_prim[GL_POLYGON + 1] = {
-   GL_POINTS,
-   GL_LINES,
-   GL_LINES,
-   GL_LINES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES,
-   GL_TRIANGLES
+   [GL_POINTS] = GL_POINTS,
+   [GL_LINES] = GL_LINES,
+   [GL_LINE_LOOP] = GL_LINES,
+   [GL_LINE_STRIP] = GL_LINES,
+   [GL_TRIANGLES] = GL_TRIANGLES,
+   [GL_TRIANGLE_STRIP] = GL_TRIANGLES,
+   [GL_TRIANGLE_FAN] = GL_TRIANGLES,
+   [GL_QUADS] = GL_TRIANGLES,
+   [GL_QUAD_STRIP] = GL_TRIANGLES,
+   [GL_POLYGON] = GL_TRIANGLES
 };
 
 
-- 
2.0.5

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[Mesa-dev] [PATCH 11/20] i915: Use _tnl_RenderClippedPolygon and _tnl_RenderClippedLine

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

_tnl_RenderClippedPolygon and _tnl_RenderClippedLine already do most of
what we want so use them.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_tris.c | 19 ++-
 1 file changed, 2 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_tris.c 
b/src/mesa/drivers/dri/i915/intel_tris.c
index 09f0c78..13d60b6 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -922,18 +922,11 @@ intelRenderClippedPoly(struct gl_context * ctx, const 
GLuint * elts, GLuint n)
 {
struct intel_context *intel = intel_context(ctx);
TNLcontext *tnl = TNL_CONTEXT(ctx);
-   struct vertex_buffer *VB = TNL_CONTEXT(ctx)-vb;
GLuint prim = intel-render_primitive;
 
/* Render the new vertices as an unclipped polygon.
 */
-   {
-  GLuint *tmp = VB-Elts;
-  VB-Elts = (GLuint *) elts;
-  tnl-Driver.Render.PrimTabElts[GL_POLYGON] (ctx, 0, n,
-  PRIM_BEGIN | PRIM_END);
-  VB-Elts = tmp;
-   }
+   _tnl_RenderClippedPolygon(ctx, elts, n);
 
/* Restore the render primitive
 */
@@ -942,14 +935,6 @@ intelRenderClippedPoly(struct gl_context * ctx, const 
GLuint * elts, GLuint n)
 }
 
 static void
-intelRenderClippedLine(struct gl_context * ctx, GLuint ii, GLuint jj)
-{
-   TNLcontext *tnl = TNL_CONTEXT(ctx);
-
-   tnl-Driver.Render.Line(ctx, ii, jj);
-}
-
-static void
 intelFastRenderClippedPoly(struct gl_context * ctx, const GLuint * elts, 
GLuint n)
 {
struct intel_context *intel = intel_context(ctx);
@@ -1075,7 +1060,7 @@ intelChooseRenderState(struct gl_context * ctx)
   else {
  tnl-Driver.Render.PrimTabVerts = _tnl_render_tab_verts;
  tnl-Driver.Render.PrimTabElts = _tnl_render_tab_elts;
- tnl-Driver.Render.ClippedLine = intelRenderClippedLine;
+ tnl-Driver.Render.ClippedLine = _tnl_RenderClippedLine;
  tnl-Driver.Render.ClippedPolygon = intelRenderClippedPoly;
   }
}
-- 
2.0.5

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[Mesa-dev] [PATCH 12/20] i915: Make hw_prim[] const

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The table used to map the GL primitive to the hw primitive never
changes so make it const.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_render.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i915/intel_render.c 
b/src/mesa/drivers/dri/i915/intel_render.c
index bf48f38..d06f75a 100644
--- a/src/mesa/drivers/dri/i915/intel_render.c
+++ b/src/mesa/drivers/dri/i915/intel_render.c
@@ -69,7 +69,7 @@
 
 #define HAVE_ELTS0
 
-static uint32_t hw_prim[GL_POLYGON + 1] = {
+static const uint32_t hw_prim[GL_POLYGON + 1] = {
0,
PRIM3D_LINELIST,
PRIM3D_LINESTRIP,
-- 
2.0.5

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[Mesa-dev] [PATCH 17/20] i915: Remember to call intel_prepare_render() before blitting

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Bring over the following fix from i965:
 commit fb3d62fe3d4fc40ba4ad9804d8b6f451316c9ae2
 Author: Kenneth Graunke kenn...@whitecape.org
 Date:   Tue Aug 6 14:36:09 2013 -0700

i965: Remember to call intel_prepare_render() before blitting.

Fixes a crash in the following piglit tests:
 bin/fbo-sys-blit -auto
 bin/fbo-sys-sub-blit -auto

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_fbo.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c 
b/src/mesa/drivers/dri/i915/intel_fbo.c
index 8ce1dbf..45c8fb6 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915/intel_fbo.c
@@ -658,6 +658,11 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
 {
struct intel_context *intel = intel_context(ctx);
 
+   /* Sync up the state of window system buffers.  We need to do this before
+* we go looking for the buffers.
+*/
+   intel_prepare_render(intel);
+
if (mask  GL_COLOR_BUFFER_BIT) {
   GLint i;
   struct gl_renderbuffer *src_rb = readFb-_ColorReadBuffer;
-- 
2.0.5

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[Mesa-dev] [PATCH 04/20] t_dd_dmatmp: Check provoking vertex convention when rendering quads

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

When drawing quads using triangles we need to be careful to make
the provoking vertices match when flat shading.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index f56b0aa..010369f 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -511,7 +511,9 @@ static void TAG(render_quads_verts)( struct gl_context *ctx,
  currentsz = dmasz;
   }
}
-   else if (HAVE_TRIANGLES) {
+   else if (HAVE_TRIANGLES 
+   (ctx-Light.ShadeModel == GL_SMOOTH ||
+ctx-Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION_EXT)) {
   /* Hardware doesn't have a quad primitive type -- try to
* simulate it using triangle primitive.  This is a win for
* gears, but is it useful in the broader world?
@@ -993,7 +995,9 @@ static void TAG(render_quads_elts)( struct gl_context *ctx,
 FLUSH();
 currentsz = dmasz;
   }
-   } else {
+   } else if (HAVE_TRIANGLES 
+ (ctx-Light.ShadeModel == GL_SMOOTH ||
+  ctx-Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION_EXT)) {
   LOCAL_VARS;
   GLuint *elts = TNL_CONTEXT(ctx)-vb.Elts;
   int dmasz = GET_SUBSEQUENT_VB_MAX_ELTS();
@@ -1131,7 +1135,9 @@ static GLboolean TAG(validate_render)( struct gl_context 
*ctx,
 if (HAVE_QUADS) {
ok = GL_TRUE;
 } else {
-   ok = HAVE_TRIANGLES; /* flatshading is ok. */
+   ok = (HAVE_TRIANGLES 
+ (ctx-Light.ShadeModel == GL_SMOOTH ||
+  ctx-Light.ProvokingVertex == 
GL_LAST_VERTEX_CONVENTION_EXT));
 }
 break;
   default:
-- 
2.0.5

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[Mesa-dev] [PATCH 03/20] t_dd_dmatmp: Disallow flat shading when rendering quad strips via tri strips

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

When rendering quad strips via tri strips we can't get the provoking
vertex right, so disallow flat shading.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index 3ed4a98..f56b0aa 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -447,7 +447,7 @@ static void TAG(render_quad_strip_verts)( struct gl_context 
*ctx,
 
   FLUSH();
}
-   else if (HAVE_TRI_STRIPS) {
+   else if (HAVE_TRI_STRIPS  ctx-Light.ShadeModel == GL_SMOOTH) {
   LOCAL_VARS;
   int dmasz = GET_SUBSEQUENT_VB_MAX_VERTS();
   int currentsz;
@@ -1124,7 +1124,7 @@ static GLboolean TAG(validate_render)( struct gl_context 
*ctx,
 } else if (HAVE_QUAD_STRIPS) {
ok = GL_TRUE;
 } else {
-   ok = HAVE_TRI_STRIPS;
+   ok = (HAVE_TRI_STRIPS  ctx-Light.ShadeModel == GL_SMOOTH);
 }
 break;
   case GL_QUADS:
-- 
2.0.5

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[Mesa-dev] [PATCH 06/20] t_dd_dmatmp: Fix render_quad_strip_elts

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Split the tri vs. tristrip paths in render_quad_strip_elts apart
and add the appropriate smooth vs. flat shading and provoking
vertex checks. Add the same checks to validate_render to make
sure we don't end up there under the wrong circumstances.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 37 +++--
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index 82493a3..2132c07 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -906,7 +906,8 @@ static void TAG(render_quad_strip_elts)( struct gl_context 
*ctx,
 {
if (HAVE_QUAD_STRIPS  0) {
}
-   else if (HAVE_TRI_STRIPS) {
+   else if ((HAVE_TRIANGLES || HAVE_TRI_STRIPS) 
+   ctx-Light.ShadeModel == GL_SMOOTH) {
   LOCAL_VARS;
   GLuint *elts = TNL_CONTEXT(ctx)-vb.Elts;
   int dmasz = GET_SUBSEQUENT_VB_MAX_ELTS();
@@ -925,7 +926,16 @@ static void TAG(render_quad_strip_elts)( struct gl_context 
*ctx,
   if (currentsz  12)
 currentsz = dmasz;
 
-  if (ctx-Light.ShadeModel == GL_FLAT) {
+  if (HAVE_TRI_STRIPS) {
+ELT_INIT( GL_TRIANGLE_STRIP );
+
+for (j = start; j + 3  count; j += nr - 2 ) {
+   nr = MIN2( currentsz, count - j );
+   TAG(emit_elts)( ctx, elts+j, nr, ALLOC_ELTS(nr) );
+   FLUSH();
+   currentsz = dmasz;
+}
+  } else {
 ELT_INIT( GL_TRIANGLES );
 
 currentsz = currentsz/6*2;
@@ -934,8 +944,7 @@ static void TAG(render_quad_strip_elts)( struct gl_context 
*ctx,
 for (j = start; j + 3  count; j += nr - 2 ) {
nr = MIN2( currentsz, count - j );
 
-   if (nr = 4)
-   {
+   if (nr = 4) {
   GLint i;
   GLint quads = (nr/2)-1;
   ELTS_VARS( ALLOC_ELTS( quads*6 ) );
@@ -948,22 +957,12 @@ static void TAG(render_quad_strip_elts)( struct 
gl_context *ctx,
   }
 
   FLUSH();
-   }
-
-   currentsz = dmasz;
 }
-  }
-  else {
-ELT_INIT( GL_TRIANGLE_STRIP );
 
-for (j = start; j + 3  count; j += nr - 2 ) {
-   nr = MIN2( currentsz, count - j );
-   TAG(emit_elts)( ctx, elts+j, nr, ALLOC_ELTS(nr) );
-   FLUSH();
-   currentsz = dmasz;
-}
+currentsz = dmasz;
   }
}
+
 }
 
 
@@ -1124,8 +1123,10 @@ static GLboolean TAG(validate_render)( struct gl_context 
*ctx,
 break;
   case GL_QUAD_STRIP:
 if (VB-Elts) {
-   ok = HAVE_TRI_STRIPS;
-} else if (HAVE_QUAD_STRIPS) {
+   ok = ((HAVE_TRI_STRIPS || HAVE_TRIANGLES) 
+ ctx-Light.ShadeModel == GL_SMOOTH);
+}
+else if (HAVE_QUAD_STRIPS) {
ok = GL_TRUE;
 } else {
ok = (HAVE_TRI_STRIPS  ctx-Light.ShadeModel == GL_SMOOTH);
-- 
2.0.5

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[Mesa-dev] [PATCH 08/20] i915: Fix collision between I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0)

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0) are trying to occupy
the same bit. Move the texture bits upwards a bit to make room for
I830_UPLOAD_RASTER_RULES.

Now the driver will actually upload the raster rules which is rather
important to get the provoking vertex right. Fixes the appearance
of glxgears teeth on gen2.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_context.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_context.h 
b/src/mesa/drivers/dri/i915/i830_context.h
index 140f617..92952cf 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -42,10 +42,10 @@
 #define I830_UPLOAD_STIPPLE  0x4
 #define I830_UPLOAD_INVARIENT0x8
 #define I830_UPLOAD_RASTER_RULES 0x10
-#define I830_UPLOAD_TEX(i)   (0x10(i))
-#define I830_UPLOAD_TEXBLEND(i)  (0x100(i))
-#define I830_UPLOAD_TEX_ALL  (0x0f0)
-#define I830_UPLOAD_TEXBLEND_ALL (0xf00)
+#define I830_UPLOAD_TEX(i)   (0x0100(i))
+#define I830_UPLOAD_TEXBLEND(i)  (0x1000(i))
+#define I830_UPLOAD_TEX_ALL  (0x0f00)
+#define I830_UPLOAD_TEXBLEND_ALL (0xf000)
 
 /* State structure offsets - these will probably disappear.
  */
-- 
2.0.5

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[Mesa-dev] [PATCH 09/20] i915: Handle provoking vertex in intelFastRenderClippedPoly()

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

intelFastRenderClippedPoly() renders the polygon using triangles. For
polygons the provoking vertex is always the first one, and currently
this function assumes that the provoking vertex for triangles is the
last one. In case the user changed the provoking vertex convention,
the hardware may be configured to treat the first vertex of triangles
as the provoking vertex. So check the convention and emit the triangles
in the appropriate order to avoid having to change the hardware
provoking vertex convention for rendering polygons.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_tris.c | 16 
 1 file changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_tris.c 
b/src/mesa/drivers/dri/i915/intel_tris.c
index 2c0a785..2b62104 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -928,10 +928,18 @@ intelFastRenderClippedPoly(struct gl_context * ctx, const 
GLuint * elts, GLuint
const GLuint *start = (const GLuint *) V(elts[0]);
int i, j;
 
-   for (i = 2; i  n; i++) {
-  COPY_DWORDS(j, vb, vertsize, V(elts[i - 1]));
-  COPY_DWORDS(j, vb, vertsize, V(elts[i]));
-  COPY_DWORDS(j, vb, vertsize, start);
+   if (ctx-Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION) {
+  for (i = 2; i  n; i++) {
+ COPY_DWORDS(j, vb, vertsize, V(elts[i - 1]));
+ COPY_DWORDS(j, vb, vertsize, V(elts[i]));
+ COPY_DWORDS(j, vb, vertsize, start);
+  }
+   } else {
+  for (i = 2; i  n; i++) {
+ COPY_DWORDS(j, vb, vertsize, start);
+ COPY_DWORDS(j, vb, vertsize, V(elts[i - 1]));
+ COPY_DWORDS(j, vb, vertsize, V(elts[i]));
+  }
}
 }
 
-- 
2.0.5

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[Mesa-dev] [PATCH 10/20] i915: Fix t_vb_rendertmp.h's provoking vertex handywork

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

t_vb_rendertmp.h reorder the vertices passed to the driver based on
the provoking vertex convention. The last vertex passed is always the
provoking vertex. For us however that's a bit bad since the hardware
itself handles the provoking vertex. Reorder the vertices back to the
original order in the driver to make sure the correct provoking vertex
is used.

This seemed easier than trying to adjust t_vd_rendertmp.h to not
reorder (mainly because swrast would still need the reordering),
or having to mess about with the hardware state depending on the
path we take to render the primitives.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_tris.c | 33 -
 1 file changed, 32 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i915/intel_tris.c 
b/src/mesa/drivers/dri/i915/intel_tris.c
index 2b62104..09f0c78 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -372,6 +372,17 @@ intel_draw_quad(struct intel_context *intel,
GLuint *vb = intel_get_prim_space(intel, 6);
int j;
 
+   /* hardware handles provoking vertex so undo t_vb_rendertmp.h's handywork */
+   if (intel-ctx.Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
+  intelVertexPtr _v0;
+
+  _v0 = v0;
+  v0 = v3;
+  v3 = v2;
+  v2 = v1;
+  v1 = _v0;
+   }
+
COPY_DWORDS(j, vb, vertsize, v0);
COPY_DWORDS(j, vb, vertsize, v1);
 
@@ -379,7 +390,8 @@ intel_draw_quad(struct intel_context *intel,
 * rasterization.  Otherwise draw as two triangles with provoking
 * vertex in third position as required for flat shading.
 */
-   if (intel-ctx.Light.ShadeModel == GL_FLAT) {
+   if (intel-ctx.Light.ShadeModel == GL_FLAT 
+   intel-ctx.Light.ProvokingVertex == GL_LAST_VERTEX_CONVENTION) {
   COPY_DWORDS(j, vb, vertsize, v3);
   COPY_DWORDS(j, vb, vertsize, v1);
}
@@ -400,6 +412,16 @@ intel_draw_triangle(struct intel_context *intel,
GLuint *vb = intel_get_prim_space(intel, 3);
int j;
 
+  /* hardware handles provoking vertex so undo t_vb_rendertmp.h's handywork */
+   if (intel-ctx.Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
+  intelVertexPtr _v0;
+
+  _v0 = v0;
+  v0 = v2;
+  v2 = v1;
+  v1 = _v0;
+   }
+
COPY_DWORDS(j, vb, vertsize, v0);
COPY_DWORDS(j, vb, vertsize, v1);
COPY_DWORDS(j, vb, vertsize, v2);
@@ -414,6 +436,15 @@ intel_draw_line(struct intel_context *intel,
GLuint *vb = intel_get_prim_space(intel, 2);
int j;
 
+   /* hardware handles provoking vertex so undo t_vb_rendertmp.h's handywork */
+   if (intel-ctx.Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION) {
+  intelVertexPtr _v0;
+
+  _v0 = v0;
+  v0 = v1;
+  v1 = _v0;
+   }
+
COPY_DWORDS(j, vb, vertsize, v0);
COPY_DWORDS(j, vb, vertsize, v1);
 }
-- 
2.0.5

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[Mesa-dev] [PATCH 02/20] t_dd_dmatmp: Allow flat shaded polygons with tri fans

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

We can allow rendering flat shaded polygons using tri fans if we check
the provoking vertex convention.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index 5ea2d31..3ed4a98 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -406,7 +406,9 @@ static void TAG(render_poly_verts)( struct gl_context *ctx,
 
   FLUSH();
}
-   else if (HAVE_TRI_FANS  ctx-Light.ShadeModel == GL_SMOOTH) {
+   else if (HAVE_TRI_FANS 
+   (ctx-Light.ShadeModel == GL_SMOOTH ||
+ctx-Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION_EXT)) {
   TAG(render_tri_fan_verts)( ctx, start, count, flags );
} else {
   fprintf(stderr, %s - cannot draw primitive\n, __FUNCTION__);
@@ -885,7 +887,9 @@ static void TAG(render_poly_elts)( struct gl_context *ctx,
 FLUSH();
 currentsz = dmasz;
   }
-   } else if (HAVE_TRI_FANS  ctx-Light.ShadeModel == GL_SMOOTH) {
+   } else if (HAVE_TRI_FANS 
+ (ctx-Light.ShadeModel == GL_SMOOTH ||
+  ctx-Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION_EXT)) {
   TAG(render_tri_fan_verts)( ctx, start, count, flags );
} else {
   fprintf(stderr, %s - cannot draw primitive\n, __FUNCTION__);
@@ -1109,7 +1113,9 @@ static GLboolean TAG(validate_render)( struct gl_context 
*ctx,
ok = GL_TRUE;
 }
 else {
-   ok = (HAVE_TRI_FANS  ctx-Light.ShadeModel == GL_SMOOTH);
+   ok = (HAVE_TRI_FANS 
+ (ctx-Light.ShadeModel == GL_SMOOTH ||
+  ctx-Light.ProvokingVertex == 
GL_FIRST_VERTEX_CONVENTION_EXT));
  }
 break;
   case GL_QUAD_STRIP:
-- 
2.0.5

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[Mesa-dev] [PATCH 05/20] t_dd_dmatmp: Call render_tri_fan_elts from render_poly_elts

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Calling render_tri_fan_verts() from render_poly_elts() doesn't seem sane.
I presume the intention was to call render_tri_fan_elts() instead.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index 010369f..82493a3 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -892,7 +892,7 @@ static void TAG(render_poly_elts)( struct gl_context *ctx,
} else if (HAVE_TRI_FANS 
  (ctx-Light.ShadeModel == GL_SMOOTH ||
   ctx-Light.ProvokingVertex == GL_FIRST_VERTEX_CONVENTION_EXT)) {
-  TAG(render_tri_fan_verts)( ctx, start, count, flags );
+  TAG(render_tri_fan_elts)( ctx, start, count, flags );
} else {
   fprintf(stderr, %s - cannot draw primitive\n, __FUNCTION__);
   return;
-- 
2.0.5

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[Mesa-dev] [PATCH 01/20] t_dd_dmatmp: Kill the paths rendering quads/quad strips via indexed vertices

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

No driver supports elts currently, and these make the validate_render
code a bit hard to follow. Just kill them.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 133 ++
 1 file changed, 5 insertions(+), 128 deletions(-)

diff --git a/src/mesa/tnl_dd/t_dd_dmatmp.h b/src/mesa/tnl_dd/t_dd_dmatmp.h
index 52ea2bf..5ea2d31 100644
--- a/src/mesa/tnl_dd/t_dd_dmatmp.h
+++ b/src/mesa/tnl_dd/t_dd_dmatmp.h
@@ -36,7 +36,7 @@
  * Produces code for both inline triangles and indexed triangles.
  * Where various primitive types are unaccelerated by hardware, the
  * code attempts to fallback to other primitive types (quadstrips to
- * tristrips, lineloops to linestrips), or to indexed vertices.
+ * tristrips, lineloops to linestrips).
  */
 
 #if !defined(HAVE_TRIANGLES)
@@ -444,65 +444,6 @@ static void TAG(render_quad_strip_verts)( struct 
gl_context *ctx,
   }
 
   FLUSH();
-
-   } else if (HAVE_TRI_STRIPS  
- ctx-Light.ShadeModel == GL_FLAT 
- TNL_CONTEXT(ctx)-vb.AttribPtr[_TNL_ATTRIB_COLOR0]-stride) {
-  if (HAVE_ELTS) {
-LOCAL_VARS;
-int dmasz = GET_SUBSEQUENT_VB_MAX_ELTS();
-int currentsz;
-GLuint j, nr;
-
- EMIT_INDEXED_VERTS( ctx, start, count );
-
-/* Simulate flat-shaded quadstrips using indexed vertices:
- */
-ELT_INIT( GL_TRIANGLES );
-
-currentsz = GET_CURRENT_VB_MAX_ELTS();
-
-/* Emit whole number of quads in total, and in each buffer.
- */
-dmasz -= dmasz  1;
-count -= (count-start)  1;
-currentsz -= currentsz  1;
-
-if (currentsz  12)
-   currentsz = dmasz;
-
-currentsz = currentsz/6*2;
-dmasz = dmasz/6*2;
-
-for (j = start; j + 3  count; j += nr - 2 ) {
-   nr = MIN2( currentsz, count - j );
-   if (nr = 4) {
-  GLint quads = (nr/2)-1;
-  GLint i;
-  ELTS_VARS( ALLOC_ELTS( quads*6 ) );
-
-  for ( i = j-start ; i  j-start+quads*2 ; i+=2 ) {
- EMIT_TWO_ELTS( 0, (i+0), (i+1) );
- EMIT_TWO_ELTS( 2, (i+2), (i+1) );
- EMIT_TWO_ELTS( 4, (i+3), (i+2) );
- INCR_ELTS( 6 );
-  }
-
-  FLUSH();
-   }
-   currentsz = dmasz;
-}
-
-RELEASE_ELT_VERTS();
-FLUSH();
-  }
-  else {
-/* Vertices won't fit in a single buffer or elts not
- * available - should never happen.
- */
-fprintf(stderr, %s - cannot draw primitive\n, __FUNCTION__);
-return;
-  }
}
else if (HAVE_TRI_STRIPS) {
   LOCAL_VARS;
@@ -568,57 +509,6 @@ static void TAG(render_quads_verts)( struct gl_context 
*ctx,
  currentsz = dmasz;
   }
}
-   else if (HAVE_ELTS) {
-  /* Hardware doesn't have a quad primitive type -- try to
-   * simulate it using indexed vertices and the triangle
-   * primitive:
-   */
-  LOCAL_VARS;
-  int dmasz = GET_SUBSEQUENT_VB_MAX_ELTS();
-  int currentsz;
-  GLuint j, nr;
-
-  EMIT_INDEXED_VERTS( ctx, start, count );
-
-  FLUSH();
-  ELT_INIT( GL_TRIANGLES );
-  currentsz = GET_CURRENT_VB_MAX_ELTS();
-
-  /* Emit whole number of quads in total, and in each buffer.
-   */
-  dmasz -= dmasz  3;
-  count -= (count-start)  3;
-  currentsz -= currentsz  3;
-
-  /* Adjust for rendering as triangles:
-   */
-  currentsz = currentsz/6*4;
-  dmasz = dmasz/6*4;
-
-  if (currentsz  8)
-currentsz = dmasz;
-
-  for (j = start; j  count; j += nr ) {
-nr = MIN2( currentsz, count - j );
-if (nr = 4) {
-   GLint quads = nr/4;
-   GLint i;
-   ELTS_VARS( ALLOC_ELTS( quads*6 ) );
-
-   for ( i = j-start ; i  j-start+quads*4 ; i+=4 ) {
-  EMIT_TWO_ELTS( 0, (i+0), (i+1) );
-  EMIT_TWO_ELTS( 2, (i+3), (i+1) );
-  EMIT_TWO_ELTS( 4, (i+2), (i+3) );
-  INCR_ELTS( 6 );
-   }
-
-   FLUSH();
-}
-currentsz = dmasz;
-  }
-
-  RELEASE_ELT_VERTS();
-   }
else if (HAVE_TRIANGLES) {
   /* Hardware doesn't have a quad primitive type -- try to
* simulate it using triangle primitive.  This is a win for
@@ -1225,29 +1115,16 @@ static GLboolean TAG(validate_render)( struct 
gl_context *ctx,
   case GL_QUAD_STRIP:
 if (VB-Elts) {
ok = HAVE_TRI_STRIPS;
-}
-else if (HAVE_QUAD_STRIPS) {
+} else if (HAVE_QUAD_STRIPS) {
ok = GL_TRUE;
-} else if (HAVE_TRI_STRIPS  
-   ctx-Light.ShadeModel == GL_FLAT 
-   VB-AttribPtr[_TNL_ATTRIB_COLOR0]-stride != 0) {
-   if (HAVE_ELTS) {
-  ok = (GLint) count  GET_SUBSEQUENT_VB_MAX_ELTS();
- 

[Mesa-dev] [PATCH 00/20] i915: Pile of fixes and cleanups

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

I've had some of these i915 patches lying around for half a year or more,
so I figured it's time to post them.

This series fixes rendering problems in glxgears and supertuxkart. It
also fixes a few piglit tests (provoking vertex, and a few crashers).
No piglit regressions on 855.

Summary of the changes:
 * provoking vertex fixes
 * gen2 user fbo culling fix
 * some buffer handling fixes ported over from i965
 * gen3 fragment shader texcoord vs. varying fix (already posted before)
 * random point/line rendering stuff
 * a bit of polish here and there

Ville Syrjälä (20):
  t_dd_dmatmp: Kill the paths rendering quads/quad strips via indexed
vertices
  t_dd_dmatmp: Allow flat shaded polygons with tri fans
  t_dd_dmatmp: Disallow flat shading when rendering quad strips via tri
strips
  t_dd_dmatmp: Check provoking vertex convention when rendering quads
  t_dd_dmatmp: Call render_tri_fan_elts from render_poly_elts
  t_dd_dmatmp: Fix render_quad_strip_elts
  t_dd_dmatmp: Make the render_tab[]s const
  i915: Fix collision between I830_UPLOAD_RASTER_RULES and
I830_UPLOAD_TEX(0)
  i915: Handle provoking vertex in intelFastRenderClippedPoly()
  i915: Fix t_vb_rendertmp.h's provoking vertex handywork
  i915: Use _tnl_RenderClippedPolygon and _tnl_RenderClippedLine
  i915: Make hw_prim[] const
  i915: Use c99 initializers for primitive arrays
  i915: Use COPY_DWORDS for points
  i915: Enable intel_render path for points
  i915: Adjust line size limits
  i915: Remember to call intel_prepare_render() before blitting
  i915: Drop broken front_buffer_reading/drawing optimization
  i915: Fix culling with user fbos on gen2
  i915: Fix texcoord vs. varying collision in fragment programs

 src/mesa/drivers/dri/i915/i830_context.h  |   8 +-
 src/mesa/drivers/dri/i915/i830_state.c|   2 +
 src/mesa/drivers/dri/i915/i915_context.h  |  14 +--
 src/mesa/drivers/dri/i915/i915_fragprog.c |  86 ++---
 src/mesa/drivers/dri/i915/intel_buffers.c |  47 ---
 src/mesa/drivers/dri/i915/intel_buffers.h |   3 +
 src/mesa/drivers/dri/i915/intel_context.c |  16 +--
 src/mesa/drivers/dri/i915/intel_context.h |  16 ---
 src/mesa/drivers/dri/i915/intel_fbo.c |   5 +
 src/mesa/drivers/dri/i915/intel_render.c  |  66 +-
 src/mesa/drivers/dri/i915/intel_tris.c| 114 ++---
 src/mesa/tnl_dd/t_dd_dmatmp.h | 196 +++---
 12 files changed, 266 insertions(+), 307 deletions(-)

-- 
2.0.5

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[Mesa-dev] [PATCH] mesa: Fix build errors on x86+sse

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

tnl/t_vertex_sse.c: In function ‘build_vertex_emit’:
tnl/t_vertex_sse.c:500:6: error: implicit declaration of function ‘printf’ 
[-Werror=implicit-function-declaration]
  printf(Can't emit 1ub %x %x %d\n, a-vertoffset, a[-1].vertoffset, 
a[-1].vertattrsize );
  ^
tnl/t_vertex_sse.c:500:6: warning: incompatible implicit declaration of 
built-in function ‘printf’ [enabled by default]
tnl/t_vertex_sse.c:546:6: warning: incompatible implicit declaration of 
built-in function ‘printf’ [enabled by default]
  printf(Can't emit 3ub\n);
  ^
tnl/t_vertex_sse.c:594:6: warning: incompatible implicit declaration of 
built-in function ‘printf’ [enabled by default]
  printf(unknown CHAN_TYPE %s\n, _mesa_lookup_enum_by_nr(CHAN_TYPE));
  ^
tnl/t_vertex_sse.c:599:3: warning: incompatible implicit declaration of 
built-in function ‘printf’ [enabled by default]
   printf(unknown a[%d].format %d\n, j, a-format);

x86/rtasm/x86sse.c: In function ‘x86_get_func’:
x86/rtasm/x86sse.c:1187:7: error: implicit declaration of function ‘printf’ 
[-Werror=implicit-function-declaration]
   printf(disassemble %p %p\n, p-store, p-csr);
   ^
x86/rtasm/x86sse.c:1187:7: warning: incompatible implicit declaration of 
built-in function ‘printf’ [enabled by default]

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/tnl/t_vertex_sse.c | 2 ++
 src/mesa/x86/rtasm/x86sse.c | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/mesa/tnl/t_vertex_sse.c b/src/mesa/tnl/t_vertex_sse.c
index 4b52f7d..7352b1f 100644
--- a/src/mesa/tnl/t_vertex_sse.c
+++ b/src/mesa/tnl/t_vertex_sse.c
@@ -25,6 +25,8 @@
  *Keith Whitwell kei...@vmware.com
  */
 
+#include stdio.h
+
 #include main/glheader.h
 #include main/context.h
 #include main/colormac.h
diff --git a/src/mesa/x86/rtasm/x86sse.c b/src/mesa/x86/rtasm/x86sse.c
index c93faba..c9f52a4 100644
--- a/src/mesa/x86/rtasm/x86sse.c
+++ b/src/mesa/x86/rtasm/x86sse.c
@@ -1,6 +1,8 @@
 #ifdef USE_X86_ASM
 #if defined(__i386__) || defined(__386__)
 
+#include stdio.h
+
 #include main/imports.h
 #include x86sse.h
 
-- 
2.0.5

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[Mesa-dev] [PATCH] i965: Fix URB size for CHV

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Increase the device info .urb.size for CHV to match the default URB
size (192kB).

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 3c3c564..ba65584 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -241,7 +241,7 @@ static const struct brw_device_info brw_device_info_chv = {
.max_gs_threads = 80,
.max_wm_threads = 128,
.urb = {
-  .size = 128,
+  .size = 192,
   .min_vs_entries = 34,
   .max_vs_entries = 640,
   .max_gs_entries = 256,
-- 
2.0.5

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[Mesa-dev] [PATCH 1/3] i965: Fix max_wm_threads for gen8

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

max_wm_threads depends on the GT SKU on gen8. Update the values to
match the spec.

The max number of threads in 3DSTATE_PS is always programmed to 64
and the hardware internally scales that depending on the GT SKU. So
this doesn't change the max number of threads actually used, but it
does affect the scratch space calculation.

This is most important on CHV where the old value was too small, so
the amount of scratch space allocated wasn't sufficient to satisfy the
actual max number of threads used. On BDW GT1 and GT2 we reduce the
value to avoid overallocating the scratch space needlessly. BDW GT3
is unaffected.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_device_info.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 65942c2..2c3af66 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -198,11 +198,11 @@ static const struct brw_device_info 
brw_device_info_hsw_gt3 = {
.has_llc = true, \
.has_pln = true, \
.max_vs_threads = 504,   \
-   .max_gs_threads = 504,   \
-   .max_wm_threads = 384\
+   .max_gs_threads = 504\
 
 static const struct brw_device_info brw_device_info_bdw_gt1 = {
GEN8_FEATURES, .gt = 1,
+   .max_wm_threads = 128,
.urb = {
   .size = 192,
   .min_vs_entries = 64,
@@ -213,6 +213,7 @@ static const struct brw_device_info brw_device_info_bdw_gt1 
= {
 
 static const struct brw_device_info brw_device_info_bdw_gt2 = {
GEN8_FEATURES, .gt = 2,
+   .max_wm_threads = 192,
.urb = {
   .size = 384,
   .min_vs_entries = 64,
@@ -223,6 +224,7 @@ static const struct brw_device_info brw_device_info_bdw_gt2 
= {
 
 static const struct brw_device_info brw_device_info_bdw_gt3 = {
GEN8_FEATURES, .gt = 3,
+   .max_wm_threads = 384,
.urb = {
   .size = 384,
   .min_vs_entries = 64,
@@ -239,7 +241,7 @@ static const struct brw_device_info brw_device_info_chv = {
.has_llc = false,
.max_vs_threads = 80,
.max_gs_threads = 80,
-   .max_wm_threads = 102,
+   .max_wm_threads = 128,
.urb = {
   .size = 128,
   .min_vs_entries = 64,
-- 
2.0.5

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[Mesa-dev] [PATCH 2/3] i965: Fix min_vs_entries for CHV

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

According to BSpec the correct number for min_vs_entries is 34 for CHV.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index 2c3af66..bdef42b 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -244,7 +244,7 @@ static const struct brw_device_info brw_device_info_chv = {
.max_wm_threads = 128,
.urb = {
   .size = 128,
-  .min_vs_entries = 64,
+  .min_vs_entries = 34,
   .max_vs_entries = 640,
   .max_gs_entries = 256,
}
-- 
2.0.5

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[Mesa-dev] [PATCH 3/3] i965: Fix URB size for gen8

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Increase the device info .urb.size for BDW GT3 and CHV to match the
default URB size for each.

Also add all missing platforms (BYT,BDW,CHV) to the comment describing
the default URB size in gen7_urb.c.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_device_info.c | 4 ++--
 src/mesa/drivers/dri/i965/gen7_urb.c| 5 -
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c 
b/src/mesa/drivers/dri/i965/brw_device_info.c
index bdef42b..d0b9e05 100644
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -226,7 +226,7 @@ static const struct brw_device_info brw_device_info_bdw_gt3 
= {
GEN8_FEATURES, .gt = 3,
.max_wm_threads = 384,
.urb = {
-  .size = 384,
+  .size = 768,
   .min_vs_entries = 64,
   .max_vs_entries = 2560,
   .max_gs_entries = 960,
@@ -243,7 +243,7 @@ static const struct brw_device_info brw_device_info_chv = {
.max_gs_threads = 80,
.max_wm_threads = 128,
.urb = {
-  .size = 128,
+  .size = 192,
   .min_vs_entries = 34,
   .max_vs_entries = 640,
   .max_gs_entries = 256,
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 201f42e..f90d6e3 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -50,9 +50,12 @@
  * Currently we split the constant buffer space evenly among whatever stages
  * are active.  This is probably not ideal, but simple.
  *
- * Ivybridge GT1 and Haswell GT1 have 128kB of URB space.
+ * Ivybridge GT1, Baytrail and Haswell GT1 have 128kB of URB space.
  * Ivybridge GT2 and Haswell GT2 have 256kB of URB space.
  * Haswell GT3 has 512kB of URB space.
+ * Broadwell GT1 and Cherryview have 192kB of URB space.
+ * Broadwell GT2 has 384kB of URB space.
+ * Broadwell GT3 has 768kB of URB space.
  *
  * See Volume 2a: 3D Pipeline, section 1.8, Volume 1b: Configurations,
  * and the documentation for 3DSTATE_PUSH_CONSTANT_ALLOC_xS.
-- 
2.0.5

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[Mesa-dev] [PATCH] i915: Fix texcoord vs. varying collision in fragment programs

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

i915 fragment programs utilize the texture coordinate registers
for both texture coordinates and varyings. Unfortunately the
code doesn't check if the same index might be in use for both.
It just naively uses the index to pick a texture unit, which
could lead to collisions.

Add an extra mapping step to allocate non conflicting texture
units for both uses.

The issue can be reproduced with a pair of simple shaders like
these:
 attribute vec4 in_mod;
 varying vec4 mod;
 void main() {
   mod = in_mod;
   gl_TexCoord[0] = gl_MultiTexCoord0;
   gl_Position = gl_ModelViewProjectionMatrix * gl_Vertex;
 }

 varying vec4 mod;
 uniform sampler2D tex;
 void main() {
   gl_FragColor = texture2D(tex, vec2(gl_TexCoord[0])) * mod;
 }

This was tested on a PNV.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i915_context.h  | 14 ++---
 src/mesa/drivers/dri/i915/i915_fragprog.c | 86 +--
 2 files changed, 74 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.h 
b/src/mesa/drivers/dri/i915/i915_context.h
index 34af202..2615bd6 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -115,6 +115,8 @@ enum {
I915_RASTER_RULES_SETUP_SIZE,
 };
 
+#define I915_TEX_UNITS 8
+
 #define I915_MAX_CONSTANT  32
 #define I915_CONSTANT_SIZE (2+(4*I915_MAX_CONSTANT))
 
@@ -194,7 +196,8 @@ struct i915_fragment_program
 
/* Helpers for i915_fragprog.c:
 */
-   GLuint wpos_tex;
+   uint8_t texcoord_mapping[I915_TEX_UNITS];
+   uint8_t wpos_tex;
bool depth_written;
 
struct
@@ -205,15 +208,6 @@ struct i915_fragment_program
GLuint nr_params;
 };
 
-
-
-
-
-
-
-#define I915_TEX_UNITS 8
-
-
 struct i915_hw_state
 {
GLuint Ctx[I915_CTX_SETUP_SIZE];
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c 
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 96fdd3c..05e1de6 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -72,6 +72,24 @@ static const GLfloat cos_constants[4] = { 1.0,
-1.0 / (6 * 5 * 4 * 3 * 2 * 1)
 };
 
+/* texcoord_mapping[unit] = index | TEXCOORD_{TEX,VAR} */
+#define TEXCOORD_TEX (07)
+#define TEXCOORD_VAR (17)
+
+static GLint get_texcoord_mapping(struct i915_fragment_program *p,
+  uint8_t texcoord)
+{
+   GLint i;
+
+   for (i = 0; i  p-ctx-Const.MaxTextureCoordUnits; i++) {
+  if (p-texcoord_mapping[i] == texcoord)
+ return i;
+   }
+
+   /* blah */
+   return p-ctx-Const.MaxTextureCoordUnits - 1;
+}
+
 /**
  * Retrieve a ureg for the given source register.  Will emit
  * constants, apply swizzling and negation as needed.
@@ -82,6 +100,7 @@ src_vector(struct i915_fragment_program *p,
const struct gl_fragment_program *program)
 {
GLuint src;
+   GLint unit;
 
switch (source-File) {
 
@@ -119,8 +138,10 @@ src_vector(struct i915_fragment_program *p,
   case VARYING_SLOT_TEX5:
   case VARYING_SLOT_TEX6:
   case VARYING_SLOT_TEX7:
+ unit = get_texcoord_mapping(p, (source-Index -
+ VARYING_SLOT_TEX0) | TEXCOORD_TEX);
  src = i915_emit_decl(p, REG_TYPE_T,
-  T_TEX0 + (source-Index - VARYING_SLOT_TEX0),
+  T_TEX0 + unit,
   D0_CHANNEL_ALL);
 break;
 
@@ -132,8 +153,10 @@ src_vector(struct i915_fragment_program *p,
   case VARYING_SLOT_VAR0 + 5:
   case VARYING_SLOT_VAR0 + 6:
   case VARYING_SLOT_VAR0 + 7:
+ unit = get_texcoord_mapping(p, (source-Index -
+ VARYING_SLOT_VAR0) | TEXCOORD_VAR);
  src = i915_emit_decl(p, REG_TYPE_T,
-  T_TEX0 + (source-Index - VARYING_SLOT_VAR0),
+  T_TEX0 + unit,
   D0_CHANNEL_ALL);
  break;
 
@@ -1190,27 +1213,55 @@ fixup_depth_write(struct i915_fragment_program *p)
}
 }
 
+static void
+check_texcoord_mapping(struct i915_fragment_program *p)
+{
+   GLbitfield64 inputs = p-FragProg.Base.InputsRead;
+   GLint i;
+   GLint unit = 0;
+
+   for (i = 0; i  p-ctx-Const.MaxTextureCoordUnits; i++) {
+  if (inputs  VARYING_BIT_TEX(i)) {
+ if (unit = p-ctx-Const.MaxTextureCoordUnits) {
+unit++;
+break;
+ }
+ p-texcoord_mapping[unit++] = i | TEXCOORD_TEX;
+  }
+  if (inputs  VARYING_BIT_VAR(i)) {
+ if (unit = p-ctx-Const.MaxTextureCoordUnits) {
+unit++;
+break;
+ }
+ p-texcoord_mapping[unit++] = i | TEXCOORD_VAR;
+  }
+   }
+
+   if (unit  p-ctx-Const.MaxTextureCoordUnits)
+  i915_program_error(p, Too many texcoord units);
+}
 
 static void
 check_wpos(struct i915_fragment_program *p)
 {
GLbitfield64 inputs = 

[Mesa-dev] [PATCH] kms_flip: Improve the accuracy of out frame time calculation

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Don't use the rounded vrefresh info to predict the frame duration.
Instead calculate if from the clock.
---
 tests/kms_flip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tests/kms_flip.c b/tests/kms_flip.c
index 227a176..f609ac0 100644
--- a/tests/kms_flip.c
+++ b/tests/kms_flip.c
@@ -431,7 +431,7 @@ static void page_flip_handler(int fd, unsigned int frame, 
unsigned int sec,
 
 static double frame_time(struct test_output *o)
 {
-   return 1000.0 * 1000.0 / o-kmode[0].vrefresh;
+   return 1000.0 * o-kmode[0].htotal * o-kmode[0].vtotal / 
o-kmode[0].clock;
 }
 
 static void fixup_premature_vblank_ts(struct test_output *o,
@@ -1017,7 +1017,7 @@ static void check_final_state(struct test_output *o, 
struct event_state *es,
int count = es-count;
 
count *= es-seq_step;
-   expected = elapsed * o-kmode[0].vrefresh / (1000 * 1000);
+   expected = elapsed / frame_time(o);
igt_assert_f(count = expected * 99/100  count = expected * 
101/100,
 dropped frames, expected %d, counted %d, encoder 
type %d\n,
 expected, count, o-kencoder[0]-encoder_type);
-- 
1.8.1.5

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[Mesa-dev] [PATCH 2/2] Use floating point for VTotal when calculating refresh rate

[ville . syrjala]

From: Foo Bar f...@bar.com

Interlaced modes generally have an odd VTotal, so we lose half a line
from VTotal when we divide by two. That causes the final refresh rate
to be slightly off. Make VTotal a double to avoid the problem.

Signed-off-by: Foo Bar f...@bar.com
---
 xrandr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/xrandr.c b/xrandr.c
index 9467c29..f94cfab 100644
--- a/xrandr.c
+++ b/xrandr.c
@@ -541,7 +541,7 @@ static double
 mode_refresh (XRRModeInfo *mode_info)
 {
 double rate;
-unsigned int vTotal = mode_info-vTotal;
+double vTotal = mode_info-vTotal;
 
 if (mode_info-modeFlags  RR_DoubleScan) {
/* doublescan doubles the number of lines */
-- 
1.8.1.5

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[Mesa-dev] [PATCH 1/2] Use more decimal places when printing various rates

[ville . syrjala]

From: Foo Bar f...@bar.com

Using just one decimal place for dotclock and refresh rates loses quite
a bit of information. When dealing with 60Hz and 59.94Hz modes for
example it's useful to see at least two decimal places. Also for the
dotclock in the same cases three decimal places seems quite a bit better
than just one.

Signed-off-by: Foo Bar f...@bar.com
---
 xrandr.c | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/xrandr.c b/xrandr.c
index 94e5c2e..9467c29 100644
--- a/xrandr.c
+++ b/xrandr.c
@@ -1564,7 +1564,7 @@ crtc_apply (crtc_t *crtc)
rr_outputs[o] = crtc-outputs[o]-output.xid;
 mode = crtc-mode_info-id;
 if (verbose) {
-   printf (crtc %d: %12s %6.1f +%d+%d, crtc-crtc.index,
+   printf (crtc %d: %12s %6.2f +%d+%d, crtc-crtc.index,
crtc-mode_info-name, mode_refresh (crtc-mode_info),
crtc-x, crtc-y);
for (o = 0; o  crtc-noutput; o++)
@@ -3589,7 +3589,7 @@ main (int argc, char **argv)
XRRModeInfo *mode = find_mode_by_xid 
(output_info-modes[j]);
int f;

-   printf (  %s (0x%x) %6.1fMHz,
+   printf (  %s (0x%x) %6.3fMHz,
mode-name, (int)mode-id,
(double)mode-dotClock / 100.0);
for (f = 0; mode_flags[f].flag; f++)
@@ -3600,10 +3600,10 @@ main (int argc, char **argv)
if (j  output_info-npreferred)
printf ( +preferred);
printf (\n);
-   printf (h: width  %4d start %4d end %4d total %4d 
skew %4d clock %6.1fKHz\n,
+   printf (h: width  %4d start %4d end %4d total %4d 
skew %4d clock %6.2fKHz\n,
mode-width, mode-hSyncStart, mode-hSyncEnd,
mode-hTotal, mode-hSkew, mode_hsync (mode) / 
1000);
-   printf (v: height %4d start %4d end %4d total %4d  
 clock %6.1fHz\n,
+   printf (v: height %4d start %4d end %4d total %4d  
 clock %6.2fHz\n,
mode-height, mode-vSyncStart, mode-vSyncEnd, 
mode-vTotal,
mode_refresh (mode));
mode-modeFlags |= ModeShown;
@@ -3630,7 +3630,7 @@ main (int argc, char **argv)
if (strcmp (jmode-name, kmode-name) != 0) continue;
mode_shown[k] = True;
kmode-modeFlags |= ModeShown;
-   printf ( %6.1f, mode_refresh (kmode));
+   printf ( %6.2f, mode_refresh (kmode));
if (kmode == output-mode_info)
printf (*);
else
@@ -3651,13 +3651,13 @@ main (int argc, char **argv)
 
if (!(mode-modeFlags  ModeShown))
{
-   printf (  %s (0x%x) %6.1fMHz\n,
+   printf (  %s (0x%x) %6.3fMHz\n,
mode-name, (int)mode-id,
(double)mode-dotClock / 100.0);
-   printf (h: width  %4d start %4d end %4d total %4d skew 
%4d clock %6.1fKHz\n,
+   printf (h: width  %4d start %4d end %4d total %4d skew 
%4d clock %6.2fKHz\n,
mode-width, mode-hSyncStart, mode-hSyncEnd,
mode-hTotal, mode-hSkew, mode_hsync (mode) / 1000);
-   printf (v: height %4d start %4d end %4d total %4d  
 clock %6.1fHz\n,
+   printf (v: height %4d start %4d end %4d total %4d  
 clock %6.2fHz\n,
mode-height, mode-vSyncStart, mode-vSyncEnd, 
mode-vTotal,
mode_refresh (mode));
}
@@ -3747,7 +3747,7 @@ main (int argc, char **argv)
if (rate == rates[i])
break;
if (i == nrate) {
-   fprintf (stderr, Rate %.1f Hz not available for this size\n, 
rate);
+   fprintf (stderr, Rate %.2f Hz not available for this size\n, 
rate);
exit (1);
}
 }
-- 
1.8.1.5

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[Mesa-dev] [PATCH v2 3/9] i915: Use L8A8 instead of I8 to simulate A8 on gen2

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.

v2: Handle the fallback in _mesa_choose_tex_format() and also
do it for all alpha formats that currently accept A8

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72819
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80050
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38873
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_texstate.c | 2 --
 src/mesa/drivers/dri/i915/i915_context.c  | 3 ++-
 src/mesa/main/texformat.c | 3 +++
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c 
b/src/mesa/drivers/dri/i915/i830_texstate.c
index 58d3356..b1414c7 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -47,8 +47,6 @@ translate_texture_format(GLuint mesa_format)
   return MAPSURF_8BIT | MT_8BIT_L8;
case MESA_FORMAT_I_UNORM8:
   return MAPSURF_8BIT | MT_8BIT_I8;
-   case MESA_FORMAT_A_UNORM8:
-  return MAPSURF_8BIT | MT_8BIT_I8; /* Kludge! */
case MESA_FORMAT_L8A8_UNORM:
   return MAPSURF_16BIT | MT_16BIT_AY88;
case MESA_FORMAT_B5G6R5_UNORM:
diff --git a/src/mesa/drivers/dri/i915/i915_context.c 
b/src/mesa/drivers/dri/i915/i915_context.c
index 7f43896..3fd571d 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -109,7 +109,8 @@ intel_init_texture_formats(struct gl_context *ctx)
ctx-TextureFormatSupported[MESA_FORMAT_B5G5R5A1_UNORM] = true;
ctx-TextureFormatSupported[MESA_FORMAT_B5G6R5_UNORM] = true;
ctx-TextureFormatSupported[MESA_FORMAT_L_UNORM8] = true;
-   ctx-TextureFormatSupported[MESA_FORMAT_A_UNORM8] = true;
+   if (intel-gen == 3)
+  ctx-TextureFormatSupported[MESA_FORMAT_A_UNORM8] = true;
ctx-TextureFormatSupported[MESA_FORMAT_I_UNORM8] = true;
ctx-TextureFormatSupported[MESA_FORMAT_L8A8_UNORM] = true;
 
diff --git a/src/mesa/main/texformat.c b/src/mesa/main/texformat.c
index c61a748..f414ea3 100644
--- a/src/mesa/main/texformat.c
+++ b/src/mesa/main/texformat.c
@@ -155,12 +155,14 @@ _mesa_choose_tex_format(struct gl_context *ctx, GLenum 
target,
case GL_ALPHA4:
case GL_ALPHA8:
   RETURN_IF_SUPPORTED(MESA_FORMAT_A_UNORM8);
+  RETURN_IF_SUPPORTED(MESA_FORMAT_L8A8_UNORM);
   break;
 
case GL_ALPHA12:
case GL_ALPHA16:
   RETURN_IF_SUPPORTED(MESA_FORMAT_A_UNORM16);
   RETURN_IF_SUPPORTED(MESA_FORMAT_A_UNORM8);
+  RETURN_IF_SUPPORTED(MESA_FORMAT_L8A8_UNORM);
   break;
 
/* Luminance formats */
@@ -224,6 +226,7 @@ _mesa_choose_tex_format(struct gl_context *ctx, GLenum 
target,
 
case GL_COMPRESSED_ALPHA_ARB:
   RETURN_IF_SUPPORTED(MESA_FORMAT_A_UNORM8);
+  RETURN_IF_SUPPORTED(MESA_FORMAT_L8A8_UNORM);
   break;
case GL_COMPRESSED_LUMINANCE_ARB:
   RETURN_IF_SUPPORTED(MESA_FORMAT_L_UNORM8);
-- 
1.8.5.5

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[Mesa-dev] [PATCH 0/9] i915: Gen2 texturing fixes and a few random patches

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

I had a few rainy days during my summer vacation so I decided to fix a
chromnium-bsu texturing problem that was nagging me for a while now. I
ended up fixing a few other things too that I spotted mostly from reading
the code.

The aniso vs. mip filter thing probably comes down to personal preference,
but at least to me aniso+mip nearest looks better than trilinear. At least
when playing the old classic glaxium :)

I have no idea if the scissor patch makes any difference anywhere. I just
caught the note in the spec and noticed we're doing it in the opposite order.

The rest should be pretty clear.

Ville Syrjälä (9):
  i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2
  i915: Fix GL_DOT3_RGBA a bit
  i915: Use L8A8 instead of I8 to simulate A8 on gen2
  i915: Override mip filter to nearest with aniso
  i915: Accept GL_DEPTH_STENCIL GL_DEPTH_COMPONENT formats for
renderbuffers
  i915: Kill intel_context::hw_stencil
  i915: Protect macro argument for TEXTURE_SET()
  i915: Don't call _mesa_meta_glsl_Clear() on gen2
  i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE

 src/mesa/drivers/dri/i915/i830_context.h|  8 +++---
 src/mesa/drivers/dri/i915/i830_reg.h|  2 +-
 src/mesa/drivers/dri/i915/i830_state.c  |  4 +--
 src/mesa/drivers/dri/i915/i830_texblend.c   |  5 ++--
 src/mesa/drivers/dri/i915/i830_texstate.c   |  4 +--
 src/mesa/drivers/dri/i915/i830_vtbl.c   | 39 +++--
 src/mesa/drivers/dri/i915/i915_context.c|  3 ++-
 src/mesa/drivers/dri/i915/i915_context.h|  8 +++---
 src/mesa/drivers/dri/i915/i915_state.c  |  4 +--
 src/mesa/drivers/dri/i915/i915_vtbl.c   |  8 +++---
 src/mesa/drivers/dri/i915/intel_clear.c |  2 +-
 src/mesa/drivers/dri/i915/intel_context.c   |  1 -
 src/mesa/drivers/dri/i915/intel_context.h   |  1 -
 src/mesa/drivers/dri/i915/intel_fbo.c   |  9 +++
 src/mesa/drivers/dri/i915/intel_tex_image.c | 22 
 15 files changed, 76 insertions(+), 44 deletions(-)

-- 
1.8.5.5

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[Mesa-dev] [PATCH 3/9] i915: Use L8A8 instead of I8 to simulate A8 on gen2

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72819
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80050
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38873
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_texstate.c   |  2 --
 src/mesa/drivers/dri/i915/i915_context.c|  3 ++-
 src/mesa/drivers/dri/i915/intel_tex_image.c | 22 ++
 3 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c 
b/src/mesa/drivers/dri/i915/i830_texstate.c
index 58d3356..b1414c7 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -47,8 +47,6 @@ translate_texture_format(GLuint mesa_format)
   return MAPSURF_8BIT | MT_8BIT_L8;
case MESA_FORMAT_I_UNORM8:
   return MAPSURF_8BIT | MT_8BIT_I8;
-   case MESA_FORMAT_A_UNORM8:
-  return MAPSURF_8BIT | MT_8BIT_I8; /* Kludge! */
case MESA_FORMAT_L8A8_UNORM:
   return MAPSURF_16BIT | MT_16BIT_AY88;
case MESA_FORMAT_B5G6R5_UNORM:
diff --git a/src/mesa/drivers/dri/i915/i915_context.c 
b/src/mesa/drivers/dri/i915/i915_context.c
index 7f43896..3fd571d 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -109,7 +109,8 @@ intel_init_texture_formats(struct gl_context *ctx)
ctx-TextureFormatSupported[MESA_FORMAT_B5G5R5A1_UNORM] = true;
ctx-TextureFormatSupported[MESA_FORMAT_B5G6R5_UNORM] = true;
ctx-TextureFormatSupported[MESA_FORMAT_L_UNORM8] = true;
-   ctx-TextureFormatSupported[MESA_FORMAT_A_UNORM8] = true;
+   if (intel-gen == 3)
+  ctx-TextureFormatSupported[MESA_FORMAT_A_UNORM8] = true;
ctx-TextureFormatSupported[MESA_FORMAT_I_UNORM8] = true;
ctx-TextureFormatSupported[MESA_FORMAT_L8A8_UNORM] = true;
 
diff --git a/src/mesa/drivers/dri/i915/intel_tex_image.c 
b/src/mesa/drivers/dri/i915/intel_tex_image.c
index 57674b9..be9a4ff 100644
--- a/src/mesa/drivers/dri/i915/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i915/intel_tex_image.c
@@ -14,6 +14,7 @@
 #include main/texobj.h
 #include main/teximage.h
 #include main/texstore.h
+#include main/texformat.h
 
 #include intel_context.h
 #include intel_mipmap_tree.h
@@ -362,9 +363,30 @@ intel_image_target_texture_2d(struct gl_context *ctx, 
GLenum target,
   image-tile_x, image-tile_y);
 }
 
+static mesa_format intel_choose_tex_format(struct gl_context *ctx,
+   GLenum target,
+   GLint internalFormat,
+   GLenum format, GLenum type)
+{
+   struct intel_context *intel = intel_context(ctx);
+
+   switch (internalFormat) {
+   case GL_ALPHA:
+   case GL_ALPHA4:
+   case GL_ALPHA8:
+  /* no A8 on gen2 :( */
+  if (intel-gen == 2)
+ return MESA_FORMAT_L8A8_UNORM;
+  /* fall through */
+   default:
+  return _mesa_choose_tex_format(ctx, target, internalFormat, format, 
type);
+   }
+}
+
 void
 intelInitTextureImageFuncs(struct dd_function_table *functions)
 {
functions-TexImage = intelTexImage;
+   functions-ChooseTextureFormat = intel_choose_tex_format;
functions-EGLImageTargetTexture2D = intel_image_target_texture_2d;
 }
-- 
1.8.5.5

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[Mesa-dev] [PATCH 1/9] i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.

I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates for cube maps always. For other targets use
CARTESIAN or HOMOGENOUS depending on the number of texture
coordinates provided.

Fixes rendering of the electric background texture in chromium-bsu
main menu. We appear to be provided with three texture coordinates
there (I'm guessing due to the funky texture matrix rotation it does).
So the code would decide to use TEXCOORDTYPE_VECTOR instead of
TEXCOORDTYPE_CARTESIAN even though we're dealing with a 2D texure.
The results weren't what one might expect.

demos/cubemap still works, which hopefully indicates that this doesn't
break things.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_vtbl.c | 37 ++-
 1 file changed, 19 insertions(+), 18 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c 
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 53d408b..0f22d86 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -134,27 +134,28 @@ i830_render_start(struct intel_context *intel)
 GLuint mcs = (i830-state.Tex[i][I830_TEXREG_MCS] 
   ~TEXCOORDTYPE_MASK);
 
-switch (sz) {
-case 1:
-case 2:
-   emit = EMIT_2F;
-   sz = 2;
-   mcs |= TEXCOORDTYPE_CARTESIAN;
-   break;
-case 3:
+if (intel-ctx.Texture.Unit[i]._Current-Target == 
GL_TEXTURE_CUBE_MAP) {
emit = EMIT_3F;
sz = 3;
mcs |= TEXCOORDTYPE_VECTOR;
-   break;
-case 4:
-   emit = EMIT_3F_XYW;
-   sz = 3;
-   mcs |= TEXCOORDTYPE_HOMOGENEOUS;
-   break;
-default:
-   continue;
-};
-
+} else {
+   switch (sz) {
+   case 1:
+   case 2:
+   case 3:
+  emit = EMIT_2F;
+  sz = 2;
+  mcs |= TEXCOORDTYPE_CARTESIAN;
+  break;
+   case 4:
+  emit = EMIT_3F_XYW;
+  sz = 3;
+  mcs |= TEXCOORDTYPE_HOMOGENEOUS;
+  break;
+   default:
+  continue;
+   }
+}
 
 EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
 v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
-- 
1.8.5.5

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[Mesa-dev] [PATCH 6/9] i915: Kill intel_context::hw_stencil

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

ctx.hw_stencil is not used anywhere so kill it.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_context.c | 1 -
 src/mesa/drivers/dri/i915/intel_context.h | 1 -
 2 files changed, 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_context.c 
b/src/mesa/drivers/dri/i915/intel_context.c
index 3104776..12a1d2b 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -507,7 +507,6 @@ intelInitContext(struct intel_context *intel,
 
_mesa_meta_init(ctx);
 
-   intel-hw_stencil = mesaVis  mesaVis-stencilBits  mesaVis-depthBits 
== 24;
intel-hw_stipple = 1;
 
intel-RenderIndex = ~0;
diff --git a/src/mesa/drivers/dri/i915/intel_context.h 
b/src/mesa/drivers/dri/i915/intel_context.h
index fccf821..c314594 100644
--- a/src/mesa/drivers/dri/i915/intel_context.h
+++ b/src/mesa/drivers/dri/i915/intel_context.h
@@ -226,7 +226,6 @@ struct intel_context
 
GLfloat polygon_offset_scale;/* dependent on depth_scale, bpp */
 
-   bool hw_stencil;
bool hw_stipple;
bool no_rast;
bool always_flush_batch;
-- 
1.8.5.5

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[Mesa-dev] [PATCH 5/9] i915: Accept GL_DEPTH_STENCIL GL_DEPTH_COMPONENT formats for renderbuffers

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Gen2 doesn't support depth/stencil textures, and since

 commit c1d4d4999303f9167b20f4e0674b9436e6295cf7
 Author: Ville Syrjälä ville.syrj...@linux.intel.com
 Date:   Thu Apr 24 14:11:43 2014 +0300

i915: Don't advertise Z formats in TextureFormatSupported on gen2

depth/stencil formats are no longer accepted as texture formats.
However we still want depth/stencil renderbuffers, so add explicit
format checks to intel_alloc_renderbuffer_storage() to allow such
things.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_fbo.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c 
b/src/mesa/drivers/dri/i915/intel_fbo.c
index a77c3d6..b260d16 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915/intel_fbo.c
@@ -180,6 +180,15 @@ intel_renderbuffer_format(struct gl_context * ctx, GLenum 
internalFormat)
   return intel-ctx.Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
internalFormat,
GL_NONE, GL_NONE);
+
+   case GL_DEPTH_COMPONENT16:
+  return MESA_FORMAT_Z_UNORM16;
+   case GL_DEPTH_COMPONENT:
+   case GL_DEPTH_COMPONENT24:
+   case GL_DEPTH_COMPONENT32:
+  return MESA_FORMAT_Z24_UNORM_X8_UINT;
+   case GL_DEPTH_STENCIL_EXT:
+   case GL_DEPTH24_STENCIL8_EXT:
case GL_STENCIL_INDEX:
case GL_STENCIL_INDEX1_EXT:
case GL_STENCIL_INDEX4_EXT:
-- 
1.8.5.5

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[Mesa-dev] [PATCH 9/9] i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.

gen3 BSpec no longer has that piece of text, but let's make the same
change there too for symmetry. The spec does still say that the scissor
rectangle must be defined before enabling it, so the new order does seem
more in line with the spec.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_context.h | 8 
 src/mesa/drivers/dri/i915/i830_state.c   | 4 ++--
 src/mesa/drivers/dri/i915/i830_vtbl.c| 2 +-
 src/mesa/drivers/dri/i915/i915_context.h | 8 
 src/mesa/drivers/dri/i915/i915_state.c   | 4 ++--
 src/mesa/drivers/dri/i915/i915_vtbl.c| 8 
 6 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_context.h 
b/src/mesa/drivers/dri/i915/i830_context.h
index 1a7222d..09076c3 100644
--- a/src/mesa/drivers/dri/i915/i830_context.h
+++ b/src/mesa/drivers/dri/i915/i830_context.h
@@ -55,10 +55,10 @@
 #define I830_DESTREG_DBUFADDR1 3
 #define I830_DESTREG_DV0 4
 #define I830_DESTREG_DV1 5
-#define I830_DESTREG_SENABLE 6
-#define I830_DESTREG_SR0 7
-#define I830_DESTREG_SR1 8
-#define I830_DESTREG_SR2 9
+#define I830_DESTREG_SR0 6
+#define I830_DESTREG_SR1 7
+#define I830_DESTREG_SR2 8
+#define I830_DESTREG_SENABLE 9
 #define I830_DESTREG_DRAWRECT0 10
 #define I830_DESTREG_DRAWRECT1 11
 #define I830_DESTREG_DRAWRECT2 12
diff --git a/src/mesa/drivers/dri/i915/i830_state.c 
b/src/mesa/drivers/dri/i915/i830_state.c
index bae9204..3e379f3 100644
--- a/src/mesa/drivers/dri/i915/i830_state.c
+++ b/src/mesa/drivers/dri/i915/i830_state.c
@@ -1069,11 +1069,11 @@ i830_init_packets(struct i830_context *i830)
i830-state.Stipple[I830_STPREG_ST0] = _3DSTATE_STIPPLE;
 
i830-state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
-   i830-state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
-   DISABLE_SCISSOR_RECT);
i830-state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
i830-state.Buffer[I830_DESTREG_SR1] = 0;
i830-state.Buffer[I830_DESTREG_SR2] = 0;
+   i830-state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
+   DISABLE_SCISSOR_RECT);
 }
 
 void
diff --git a/src/mesa/drivers/dri/i915/i830_vtbl.c 
b/src/mesa/drivers/dri/i915/i830_vtbl.c
index 0f22d86..91da977 100644
--- a/src/mesa/drivers/dri/i915/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i830_vtbl.c
@@ -511,10 +511,10 @@ i830_emit_state(struct intel_context *intel)
 
   OUT_BATCH(state-Buffer[I830_DESTREG_DV0]);
   OUT_BATCH(state-Buffer[I830_DESTREG_DV1]);
-  OUT_BATCH(state-Buffer[I830_DESTREG_SENABLE]);
   OUT_BATCH(state-Buffer[I830_DESTREG_SR0]);
   OUT_BATCH(state-Buffer[I830_DESTREG_SR1]);
   OUT_BATCH(state-Buffer[I830_DESTREG_SR2]);
+  OUT_BATCH(state-Buffer[I830_DESTREG_SENABLE]);
 
   assert(state-Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
   OUT_BATCH(state-Buffer[I830_DESTREG_DRAWRECT0]);
diff --git a/src/mesa/drivers/dri/i915/i915_context.h 
b/src/mesa/drivers/dri/i915/i915_context.h
index 34af202..10f1f8b 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -64,10 +64,10 @@
 #define I915_DESTREG_DBUFADDR1 4
 #define I915_DESTREG_DV0 6
 #define I915_DESTREG_DV1 7
-#define I915_DESTREG_SENABLE 8
-#define I915_DESTREG_SR0 9
-#define I915_DESTREG_SR1 10
-#define I915_DESTREG_SR2 11
+#define I915_DESTREG_SR0 8
+#define I915_DESTREG_SR1 9
+#define I915_DESTREG_SR2 10
+#define I915_DESTREG_SENABLE 11
 #define I915_DESTREG_DRAWRECT0 12
 #define I915_DESTREG_DRAWRECT1 13
 #define I915_DESTREG_DRAWRECT2 14
diff --git a/src/mesa/drivers/dri/i915/i915_state.c 
b/src/mesa/drivers/dri/i915/i915_state.c
index f31b271..203e4a0 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -988,11 +988,11 @@ i915_init_packets(struct i915_context *i915)
   i915-state.Buffer[I915_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
 
   /* scissor */
-  i915-state.Buffer[I915_DESTREG_SENABLE] =
- (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
   i915-state.Buffer[I915_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;
   i915-state.Buffer[I915_DESTREG_SR1] = 0;
   i915-state.Buffer[I915_DESTREG_SR2] = 0;
+  i915-state.Buffer[I915_DESTREG_SENABLE] =
+ (_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
}
 
i915-state.RasterRules[I915_RASTER_RULES] = _3DSTATE_RASTER_RULES_CMD |
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c 
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 74173d4..706e0c3 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ 

[Mesa-dev] [PATCH 8/9] i915: Don't call _mesa_meta_glsl_Clear() on gen2

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Gen2 doesn't have fragmnts shaders so we shouldn't be calling
_mesa_meta_glsl_Clear() on gen2. Restore the appropriate
ARB_fragment_shader check to the clear path which was lost in:

 commit 94f22fbe787214580a1a13a774114d2650c166cb
 Author: Tapani Pälli tapani.pa...@intel.com
 Date:   Wed Aug 8 20:46:45 2012 +0300

intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_clear.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i915/intel_clear.c 
b/src/mesa/drivers/dri/i915/intel_clear.c
index 1762c1d..5374e19 100644
--- a/src/mesa/drivers/dri/i915/intel_clear.c
+++ b/src/mesa/drivers/dri/i915/intel_clear.c
@@ -179,7 +179,7 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
 
if (tri_mask) {
   debug_mask(tri, tri_mask);
-  if (ctx-API == API_OPENGLES)
+  if (ctx-API == API_OPENGLES || !ctx-Extensions.ARB_fragment_shader)
 _mesa_meta_Clear(intel-ctx, tri_mask);
   else
 _mesa_meta_glsl_Clear(intel-ctx, tri_mask);
-- 
1.8.5.5

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[Mesa-dev] [PATCH 7/9] i915: Protect macro argument for TEXTURE_SET()

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

TEXTURE_SET() is the only register macro that forgets to wrap the
argument evaluation in parens. Only simple integers are passed to this
macro so there's no bug but sitll it seems prudent to add the
parens.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i915/i830_reg.h 
b/src/mesa/drivers/dri/i915/i830_reg.h
index e08cbe5..d7ccc16 100644
--- a/src/mesa/drivers/dri/i915/i830_reg.h
+++ b/src/mesa/drivers/dri/i915/i830_reg.h
@@ -256,7 +256,7 @@
 
 #define _3DSTATE_MAP_COORD_TRANSFORM   ((329)|(0x1d24)|(0x8c16))
 #define DISABLE_TEX_TRANSFORM  (128)
-#define TEXTURE_SET(x) (x29)
+#define TEXTURE_SET(x) ((x)29)
 
 #define _3DSTATE_VERTEX_TRANSFORM  ((329)|(0x1d24)|(0x8b16))
 #define DISABLE_VIEWPORT_TRANSFORM (131)
-- 
1.8.5.5

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[Mesa-dev] [PATCH 4/9] i915: Override mip filter to nearest with aniso

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

gen2 doesn't supporte linear mip filter with anisotropic min/mag
filtering. The hardware would automagically downgrade the min/mag
filters to linear in such cases, which IMO looks worse than forcing
the mip filter to nearest.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_texstate.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i915/i830_texstate.c 
b/src/mesa/drivers/dri/i915/i830_texstate.c
index b1414c7..00731e6 100644
--- a/src/mesa/drivers/dri/i915/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915/i830_texstate.c
@@ -225,6 +225,8 @@ i830_update_tex_unit(struct intel_context *intel, GLuint 
unit, GLuint ss3)
   if (sampler-MaxAnisotropy  1.0) {
  minFilt = FILTER_ANISOTROPIC;
  magFilt = FILTER_ANISOTROPIC;
+ /* no trilinear + anisotropic */
+ mipFilt = MIPFILTER_NEAREST;
   }
   else {
  switch (sampler-MagFilter) {
-- 
1.8.5.5

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[Mesa-dev] [PATCH 2/9] i915: Fix GL_DOT3_RGBA a bit

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

The spec says using DOT4 for alpha is undefined unless DOT4 is also used
for color. It seems to do the right thing anyway, but better safe than sorry.

Also override numAlphaArgs to 2 for DOT4 since that's what it wants.
This migth fix something in case the specified alpha mode has only one
argument. Also avoids emitting a needless 3DSTATE_MAP_BLEND_ARG if
the specified alpha mode has three arguments.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_texblend.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i830_texblend.c 
b/src/mesa/drivers/dri/i915/i830_texblend.c
index 236be59..feea383 100644
--- a/src/mesa/drivers/dri/i915/i830_texblend.c
+++ b/src/mesa/drivers/dri/i915/i830_texblend.c
@@ -136,7 +136,7 @@ i830SetTexEnvCombine(struct i830_context * i830,
  GLuint texel_op, GLuint * state, const GLfloat * factor)
 {
const GLuint numColorArgs = combine-_NumArgsRGB;
-   const GLuint numAlphaArgs = combine-_NumArgsA;
+   GLuint numAlphaArgs = combine-_NumArgsA;
 
GLuint blendop;
GLuint ablendop;
@@ -209,7 +209,7 @@ i830SetTexEnvCombine(struct i830_context * i830,
   break;
case GL_DOT3_RGBA_EXT:
case GL_DOT3_RGBA:
-  blendop = TEXBLENDOP_DOT3;
+  blendop = TEXBLENDOP_DOT4;
   break;
default:
   return pass_through(state, blendUnit);
@@ -273,6 +273,7 @@ i830SetTexEnvCombine(struct i830_context * i830,
if (combine-ModeRGB == GL_DOT3_RGBA_EXT ||
combine-ModeRGB == GL_DOT3_RGBA) {
   ablendop = TEXBLENDOP_DOT4;
+  numAlphaArgs = 2;
   args_A[0] = TEXBLENDARG_FACTOR;   /* the global factor */
   args_A[1] = TEXBLENDARG_FACTOR;
   args_A[2] = TEXBLENDARG_FACTOR;
-- 
1.8.5.5

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[Mesa-dev] [PATCH] i915: Fix gen2 texblend setup

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Fix an off by one in the texture unit walk during texblend
setup on gen2. This caused the last enabled texunit to be
skipped resulting in totally messed up texturing.

This is a regression introduced here:
 commit 1ad443ecdd694dd9bf3c4a5050d749fb80db6fa2
 Author: Eric Anholt e...@anholt.net
 Date:   Wed Apr 23 15:35:27 2014 -0700

i915: Redo texture unit walking on i830.

Cc: 10.2 mesa-sta...@lists.freedesktop.org
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i830_texblend.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i915/i830_texblend.c 
b/src/mesa/drivers/dri/i915/i830_texblend.c
index 6e991c4..236be59 100644
--- a/src/mesa/drivers/dri/i915/i830_texblend.c
+++ b/src/mesa/drivers/dri/i915/i830_texblend.c
@@ -445,7 +445,7 @@ i830EmitTextureBlend(struct i830_context *i830)
I830_ACTIVESTATE(i830, I830_UPLOAD_TEXBLEND_ALL, false);
 
if (ctx-Texture._MaxEnabledTexImageUnit != -1) {
-  for (unit = 0; unit  ctx-Texture._MaxEnabledTexImageUnit; unit++)
+  for (unit = 0; unit = ctx-Texture._MaxEnabledTexImageUnit; unit++)
  if (ctx-Texture.Unit[unit]._Current)
 emit_texblend(i830, unit, blendunit++,
   unit == ctx-Texture._MaxEnabledTexImageUnit);
-- 
1.8.5.5

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[Mesa-dev] [PATCH 2/3] i915: Don't advertise Z formats in TextureFormatSupported on gen2

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Gen2 doesn't support texturing from Z formats, so state as much.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/i915_context.c | 28 +++-
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/i915_context.c 
b/src/mesa/drivers/dri/i915/i915_context.c
index ebcab94..44b0d8b 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -114,19 +114,21 @@ intel_init_texture_formats(struct gl_context *ctx)
ctx-TextureFormatSupported[MESA_FORMAT_L8A8_UNORM] = true;
 
/* Depth and stencil */
-   ctx-TextureFormatSupported[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
-   ctx-TextureFormatSupported[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
-
-   /*
-* This was disabled in initial FBO enabling to avoid combinations
-* of depth+stencil that wouldn't work together.  We since decided
-* that it was OK, since it's up to the app to come up with the
-* combo that actually works, so this can probably be re-enabled.
-*/
-   /*
-   ctx-TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true;
-   ctx-TextureFormatSupported[MESA_FORMAT_Z24] = true;
-   */
+   if (intel-gen == 3) {
+  ctx-TextureFormatSupported[MESA_FORMAT_Z24_UNORM_S8_UINT] = true;
+  ctx-TextureFormatSupported[MESA_FORMAT_Z24_UNORM_X8_UINT] = true;
+
+  /*
+   * This was disabled in initial FBO enabling to avoid combinations
+   * of depth+stencil that wouldn't work together.  We since decided
+   * that it was OK, since it's up to the app to come up with the
+   * combo that actually works, so this can probably be re-enabled.
+   */
+  /*
+  ctx-TextureFormatSupported[MESA_FORMAT_Z_UNORM16] = true;
+  ctx-TextureFormatSupported[MESA_FORMAT_Z24] = true;
+  */
+   }
 
/* ctx-Extensions.MESA_ycbcr_texture */
ctx-TextureFormatSupported[MESA_FORMAT_YCBCR] = true;
-- 
1.8.3.2

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[Mesa-dev] [PATCH 0/3] i915/i965: Depth buffer format fixes

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

I was a bit annoyed when chromium-bsu stopped rendering the spinning
title text on my gen2 machine. So I bisected it down and found the
problem with the renderbuffer code overwriting the selected depth
buffer format.

This series fixes that particular problem, and I included the same fix
for i965 since the code is almost identical and it too picks the wrong
format for the depthBits==16 case.

I also threw in another patch for i915 to drop the Z formats from the 
list of supported texture formats on gen2 since the hardware doesn't
support that. But I don't have a test that would hit that issue.

Ville Syrjälä (3):
  i915: Fix format of private renderbuffers
  i915: Don't advertise Z formats in TextureFormatSupported on gen2
  i965: Fix format of private renderbuffers

 src/mesa/drivers/dri/i915/i915_context.c | 28 +
 src/mesa/drivers/dri/i915/intel_fbo.c| 46 ++--
 src/mesa/drivers/dri/i965/intel_fbo.c| 52 
 3 files changed, 78 insertions(+), 48 deletions(-)

-- 
1.8.3.2

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[Mesa-dev] [PATCH 1/3] i915: Fix format of private renderbuffers

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

intel_alloc_renderbuffer_storage() will clobber rb-Format which was
already set up by intel_create_renderbuffer(). This causes the driver
to potentially create the depth buffer in the wrong format.

Long time ago things worked by accident because
_mesa_choose_tex_format() checked for ARB_depth_texture
and thus returned MESA_FORMAT_NONE on gen2 hardware. Somehow
that ended up working when depthBits==16 because the driver
would then pick DEPTH_FRMT_16_FIXED. Not sure how, but things
also seemed to work with depthBits==24.

Things started to go more sideways at:
 commit 6ae473221a53d8bcb584021483c5328797c6b67c
 Author: Eric Anholt e...@anholt.net
 Date:   Mon Apr 22 16:04:25 2013 -0700

intel: Fold the one last function intel_tex_format.c into the caller.

since that caused intel_miptree_create_layout() to divide by zero
when encoutering MESA_FORMAT_NONE (bw==0). So after this
commit things were broken enough that many applications wouldn't even
run.

Things got a bit better at:
 commit c245efe7e8247ba0c845dee7b77e63fdbfc7e1b3
 Author: Eric Anholt e...@anholt.net
 Date:   Thu Mar 21 09:50:45 2013 -0700

mesa: Remove extension checking from ChooseTexFormat.

since now _mesa_choose_tex_format() would return MESA_FORMAT_X8_Z24
for GL_DEPTH_COMPONENT due to i915 erroneosly claiming that
MESA_FORMAT_X8_S24 (and others) are supported texture formats even
on gen2 hardware. So now the the div-by-zero was gone, but now the
driver would pick DEPTH_FRMT_24_FIXED_8_OTHER even when
depthBits==16 which caused rendering problems.

If we prevent rb-Format from getting clobbered for the depth buffer
things work much better. This makes the spinning title text visible
again in chromium-bsu at 16bpp, for example.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i915/intel_fbo.c | 46 +++
 1 file changed, 30 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i915/intel_fbo.c 
b/src/mesa/drivers/dri/i915/intel_fbo.c
index a806a42..2538fac 100644
--- a/src/mesa/drivers/dri/i915/intel_fbo.c
+++ b/src/mesa/drivers/dri/i915/intel_fbo.c
@@ -165,17 +165,10 @@ intel_unmap_renderbuffer(struct gl_context *ctx,
intel_miptree_unmap(intel, irb-mt, irb-mt_level, irb-mt_layer);
 }
 
-/**
- * Called via glRenderbufferStorageEXT() to set the format and allocate
- * storage for a user-created renderbuffer.
- */
-static GLboolean
-intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
- GLenum internalFormat,
- GLuint width, GLuint height)
+static mesa_format
+intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
 {
struct intel_context *intel = intel_context(ctx);
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 
switch (internalFormat) {
default:
@@ -184,19 +177,28 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, 
struct gl_renderbuffer
* except they're less useful because you can't texture with
* them.
*/
-  rb-Format = intel-ctx.Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
-internalFormat,
-GL_NONE, GL_NONE);
-  break;
+  return intel-ctx.Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
+   internalFormat,
+   GL_NONE, GL_NONE);
case GL_STENCIL_INDEX:
case GL_STENCIL_INDEX1_EXT:
case GL_STENCIL_INDEX4_EXT:
case GL_STENCIL_INDEX8_EXT:
case GL_STENCIL_INDEX16_EXT:
   /* These aren't actual texture formats, so force them here. */
-  rb-Format = MESA_FORMAT_Z24_UNORM_S8_UINT;
-  break;
+  return MESA_FORMAT_Z24_UNORM_S8_UINT;
}
+}
+
+static GLboolean
+intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
+ GLenum internalFormat,
+ GLuint width, GLuint height)
+{
+   struct intel_context *intel = intel_context(ctx);
+   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+   assert(rb-Format != MESA_FORMAT_NONE);
 
rb-Width = width;
rb-Height = height;
@@ -219,6 +221,18 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, 
struct gl_renderbuffer
return true;
 }
 
+/**
+ * Called via glRenderbufferStorageEXT() to set the format and allocate
+ * storage for a user-created renderbuffer.
+ */
+static GLboolean
+intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
+ GLenum internalFormat,
+ GLuint width, GLuint height)
+{
+   rb-Format = intel_renderbuffer_format(ctx, internalFormat);
+   return intel_alloc_private_renderbuffer_storage(ctx, 

[Mesa-dev] [PATCH 3/3] i965: Fix format of private renderbuffers

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

intel_alloc_renderbuffer_storage() will clobber rb-Format which was
already set up by intel_create_renderbuffer(). This causes the driver
to potentially create the depth buffer in the wrong format.

In practice this makes the depth buffer Z24 even if the visual has
depthBits==16.

The incorrect depth buffer format doesn't seem to cause any actual
problems in i965, but it seems like we should fix it anyway. I see
Z16 has been more or less deprecated in the driver except the for
the depthBits==16 case. But if we want to use Z24 even in that
case (not sure it's really legal?) it would look better if the
code made that decision explicitly rather than relying on the
format to get magically overwritten by the renderbuffer code.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/intel_fbo.c | 52 ++-
 1 file changed, 33 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c 
b/src/mesa/drivers/dri/i965/intel_fbo.c
index f58d7c8..e6e35fe 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -260,20 +260,10 @@ intel_quantize_num_samples(struct intel_screen *intel, 
unsigned num_samples)
return quantized_samples;
 }
 
-
-/**
- * Called via glRenderbufferStorageEXT() to set the format and allocate
- * storage for a user-created renderbuffer.
- */
-static GLboolean
-intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
- GLenum internalFormat,
- GLuint width, GLuint height)
+static mesa_format
+intel_renderbuffer_format(struct gl_context * ctx, GLenum internalFormat)
 {
struct brw_context *brw = brw_context(ctx);
-   struct intel_screen *screen = brw-intelScreen;
-   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-   rb-NumSamples = intel_quantize_num_samples(screen, rb-NumSamples);
 
switch (internalFormat) {
default:
@@ -282,9 +272,9 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, 
struct gl_renderbuffer
* except they're less useful because you can't texture with
* them.
*/
-  rb-Format = ctx-Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
-   internalFormat,
-   GL_NONE, GL_NONE);
+  return ctx-Driver.ChooseTextureFormat(ctx, GL_TEXTURE_2D,
+ internalFormat,
+ GL_NONE, GL_NONE);
   break;
case GL_STENCIL_INDEX:
case GL_STENCIL_INDEX1_EXT:
@@ -293,14 +283,26 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, 
struct gl_renderbuffer
case GL_STENCIL_INDEX16_EXT:
   /* These aren't actual texture formats, so force them here. */
   if (brw-has_separate_stencil) {
-rb-Format = MESA_FORMAT_S_UINT8;
+return MESA_FORMAT_S_UINT8;
   } else {
 assert(!brw-must_use_separate_stencil);
-rb-Format = MESA_FORMAT_Z24_UNORM_S8_UINT;
+return MESA_FORMAT_Z24_UNORM_S8_UINT;
   }
-  break;
}
+}
+
+static GLboolean
+intel_alloc_private_renderbuffer_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
+ GLenum internalFormat,
+ GLuint width, GLuint height)
+{
+   struct brw_context *brw = brw_context(ctx);
+   struct intel_screen *screen = brw-intelScreen;
+   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
 
+   assert(rb-Format != MESA_FORMAT_NONE);
+
+   rb-NumSamples = intel_quantize_num_samples(screen, rb-NumSamples);
rb-Width = width;
rb-Height = height;
rb-_BaseFormat = _mesa_base_fbo_format(ctx, internalFormat);
@@ -325,6 +327,18 @@ intel_alloc_renderbuffer_storage(struct gl_context * ctx, 
struct gl_renderbuffer
return true;
 }
 
+/**
+ * Called via glRenderbufferStorageEXT() to set the format and allocate
+ * storage for a user-created renderbuffer.
+ */
+static GLboolean
+intel_alloc_renderbuffer_storage(struct gl_context * ctx, struct 
gl_renderbuffer *rb,
+ GLenum internalFormat,
+ GLuint width, GLuint height)
+{
+   rb-Format = intel_renderbuffer_format(ctx, internalFormat);
+   return intel_alloc_private_renderbuffer_storage(ctx, rb, internalFormat, 
width, height);
+}
 
 static void
 intel_image_target_renderbuffer_storage(struct gl_context *ctx,
@@ -469,7 +483,7 @@ intel_create_private_renderbuffer(mesa_format format, 
unsigned num_samples)
struct intel_renderbuffer *irb;
 
irb = intel_create_renderbuffer(format, num_samples);
-   irb-Base.Base.AllocStorage = intel_alloc_renderbuffer_storage;
+   irb-Base.Base.AllocStorage = intel_alloc_private_renderbuffer_storage;
 
return irb;
 }
-- 
1.8.3.2

[Mesa-dev] [PATCH] swrast: Fix vertex color in _swsetup_Translate()

[ville . syrjala]

From: nick n...@fuel7.com

Straightforward fix to properly load dest-color with color data, as
opposed to position data as previously implemented.

[vsyrjala: I noticed the patch languishing in bugzilla.
 It looks correct to me so I refreshed it for master.

 Looks like it's a regression introduced in:
  commit a164d3aee063580503e5e9a77980059d52c486d7
  Author: Brian brian.p...@tungstengraphics.com
  Date:   Fri Jul 6 16:51:19 2007 -0600

In _swsetup_Translate(), update dest-attrib[FRAG_ATTRIB_COL0].]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=27499
Cc: Brian Paul bri...@vmware.com
Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/swrast_setup/ss_context.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/swrast_setup/ss_context.c 
b/src/mesa/swrast_setup/ss_context.c
index 12a4735..237f74c 100644
--- a/src/mesa/swrast_setup/ss_context.c
+++ b/src/mesa/swrast_setup/ss_context.c
@@ -287,7 +287,8 @@ _swsetup_Translate( struct gl_context *ctx, const void 
*vertex, SWvertex *dest )
 
_tnl_get_attr( ctx, vertex, _TNL_ATTRIB_COLOR0,
   dest-attrib[VARYING_SLOT_COL0] );
-   UNCLAMPED_FLOAT_TO_RGBA_CHAN( dest-color, tmp );
+   UNCLAMPED_FLOAT_TO_RGBA_CHAN( dest-color,
+ dest-attrib[VARYING_SLOT_COL0] );
 
_tnl_get_attr( ctx, vertex, _TNL_ATTRIB_COLOR1,
   dest-attrib[VARYING_SLOT_COL1]);
-- 
1.8.3.2

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[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

IVB/BYT also has the same L3 cacheability control in MOCS as HSW,
so let's make use of it.

pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most
other things show less gains/no regressions, except furmark which
loses some 10 points.

I didn't have a BYT at hand for testing.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_draw_upload.c   | 2 +-
 src/mesa/drivers/dri/i965/brw_misc_state.c| 2 +-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp  | 4 ++--
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  | 6 +++---
 src/mesa/drivers/dri/i965/gen7_misc_state.c   | 2 +-
 src/mesa/drivers/dri/i965/gen7_vs_state.c | 2 +-
 src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 4 ++--
 8 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c 
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 897e733..fe840d7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -658,7 +658,7 @@ static void brw_emit_vertices(struct brw_context *brw)
 if (brw-gen = 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 
-if (brw-is_haswell)
+if (brw-gen == 7)
dw0 |= GEN7_MOCS_L3  16;
 
 OUT_BATCH(dw0 | (buffer-stride  BRW_VB0_PITCH_SHIFT));
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 5927b9b..3884f86 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1038,7 +1038,7 @@ static void upload_state_base_address( struct brw_context 
*brw )
 */
 
if (brw-gen = 6) {
-  uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+  uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
 
   if (brw-gen == 6)
 intel_emit_post_sync_nonzero_flush(brw);
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index af0f6fc..3c06a3f 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -74,7 +74,7 @@ void
 gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params)
 {
-   uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
 
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS  16 | (10 - 2));
@@ -165,7 +165,7 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
   if (brw-gen = 7)
  dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 
-  if (brw-is_haswell)
+  if (brw-gen == 7)
  dw0 |= GEN7_MOCS_L3  16;
 
   BEGIN_BATCH(batch_length);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 518d7f5..a9d6198 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -143,7 +143,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
 */
struct intel_region *region = surface-mt-region;
uint32_t tile_x, tile_y;
-   uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
 
uint32_t tiling = surface-map_stencil_as_y_tiled
   ? I915_TILING_Y : region-tiling;
@@ -616,7 +616,7 @@ gen7_blorp_emit_constant_ps(struct brw_context *brw,
 const brw_blorp_params *params,
 uint32_t wm_push_const_offset)
 {
-   uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
 
/* Make sure the push constants fill an exact integer number of
 * registers.
@@ -658,7 +658,7 @@ static void
 gen7_blorp_emit_depth_stencil_config(struct brw_context *brw,
  const brw_blorp_params *params)
 {
-   uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
uint32_t surfwidth, surfheight;
uint32_t surftype;
unsigned int depth = MAX2(params-depth.mt-logical_depth0, 1);
diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 51067b3..10619c1 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -41,7 +41,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
 uint32_t tile_x, uint32_t tile_y)
 {
struct gl_context *ctx = brw-ctx;
-   uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
struct gl_framebuffer *fb = ctx-DrawBuffer;
uint32_t surftype;
unsigned int depth = 1;
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c 
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 0340da4..20f3f58 100644
--- 

[Mesa-dev] [PATCH 1/3] i965/hsw: Populate MOCS for STATE_BASE_ADDRESS

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

Juse spotted these unpopulated MOCS fields when comparing the code
against BSpec. No idea if this makes any difference anywhere, or if
it even makes any sense.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/brw_misc_state.c | 4 +++-
 src/mesa/drivers/dri/i965/gen6_blorp.cpp   | 4 +++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 3bf37b9..5927b9b 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -1038,13 +1038,15 @@ static void upload_state_base_address( struct 
brw_context *brw )
 */
 
if (brw-gen = 6) {
+  uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+
   if (brw-gen == 6)
 intel_emit_post_sync_nonzero_flush(brw);
 
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS  16 | (10 - 2));
/* General state base address: stateless DP read/write requests */
-   OUT_BATCH(1);
+   OUT_BATCH(1 | (mocs  8) | (mocs  4));
/* Surface state base address:
* BINDING_TABLE_STATE
* SURFACE_STATE
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index a4a9081..af0f6fc 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -74,9 +74,11 @@ void
 gen6_blorp_emit_state_base_address(struct brw_context *brw,
const brw_blorp_params *params)
 {
+   uint8_t mocs = brw-is_haswell ? GEN7_MOCS_L3 : 0;
+
BEGIN_BATCH(10);
OUT_BATCH(CMD_STATE_BASE_ADDRESS  16 | (10 - 2));
-   OUT_BATCH(1); /* GeneralStateBaseAddressModifyEnable */
+   OUT_BATCH(1 | (mocs  8) | (mocs  4)); /* 
GeneralStateBaseAddressModifyEnable */
/* SurfaceStateBaseAddress */
OUT_RELOC(brw-batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1);
/* DynamicStateBaseAddress */
-- 
1.8.1.5

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[Mesa-dev] [PATCH 3/3] i965/gen7: Don't use L3$ for render targets

[ville . syrjala]

From: Ville Syrjälä ville.syrj...@linux.intel.com

According to HSW Bspec L3$ evictions may land in LLC regardless of
LLC MOCS/PTE settings. That means we shouldn't set scanout buffers
as L3 cacheable when writing to them.

So far I've been unable to observe this phenomenon on my IVB, but
better safe than sorry. Especially since this doesn't appear to
hurt performance.

Ideally this should be limited to scanout buffers, but that information
is not availabe to Mesa. Limiting it to winsys buffers might be a
reasonable comporomise, but MOCS setup appears to be done at a
lower layer where that information is already lost, and I was too
lazy to start passing that infromation down.

Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com
---
 src/mesa/drivers/dri/i965/gen7_blorp.cpp  | 3 ++-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp 
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index a9d6198..6f34c8d 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -143,7 +143,8 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
 */
struct intel_region *region = surface-mt-region;
uint32_t tile_x, tile_y;
-   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
+   /* FIXME use L3$ for non-scanout render targets */
+   uint8_t mocs = !is_render_target  brw-gen == 7 ? GEN7_MOCS_L3 : 0;
 
uint32_t tiling = surface-map_stencil_as_y_tiled
   ? I915_TILING_Y : region-tiling;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index cd83daf..f7447cb 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -514,7 +514,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
bool is_array = false;
int depth = MAX2(rb-Depth, 1);
int min_array_element;
-   uint8_t mocs = brw-gen == 7 ? GEN7_MOCS_L3 : 0;
+   /* FIXME use L3$ for non-scanout renderbuffers */
+   uint8_t mocs = 0;
GLenum gl_target = rb-TexImage ?
  rb-TexImage-TexObject-Target : GL_TEXTURE_2D;
 
-- 
1.8.1.5

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