Re: [Mesa-dev] [PATCH] intel/fs: Promote execution type to 32-bit when any half-float conversion is needed.

[Jason Ekstrand]

Reviewed-by: Jason Ekstrand 

On Wed, Jan 16, 2019 at 1:32 AM Francisco Jerez 
wrote:

> The docs are fairly incomplete and inconsistent about it, but this
> seems to be the reason why half-float destinations are required to be
> DWORD-aligned on BDW+ projects.  This way the regioning lowering pass
> will make sure that the destination components of W to HF and HF to W
> conversions are aligned like the corresponding conversion operation
> with 32-bit execution data type.
> ---
>  src/intel/compiler/brw_ir_fs.h | 21 +
>  1 file changed, 21 insertions(+)
>
> diff --git a/src/intel/compiler/brw_ir_fs.h
> b/src/intel/compiler/brw_ir_fs.h
> index 3c23fb375e4..08e3d83d910 100644
> --- a/src/intel/compiler/brw_ir_fs.h
> +++ b/src/intel/compiler/brw_ir_fs.h
> @@ -477,6 +477,27 @@ get_exec_type(const fs_inst *inst)
>
> assert(exec_type != BRW_REGISTER_TYPE_B);
>
> +   /* Promotion of the execution type to 32-bit for conversions from or to
> +* half-float seems to be consistent with the following text from the
> +* Cherryview PRM Vol. 7, "Execution Data Type":
> +*
> +* "When single precision and half precision floats are mixed between
> +*  source operands or between source and destination operand [..]
> single
> +*  precision float is the execution datatype."
> +*
> +* and from "Register Region Restrictions":
> +*
> +* "Conversion between Integer and HF (Half Float) must be DWord
> aligned
> +*  and strided by a DWord on the destination."
> +*/
> +   if (type_sz(exec_type) == 2 &&
> +   inst->dst.type != exec_type) {
> +  if (exec_type == BRW_REGISTER_TYPE_HF)
> + exec_type = BRW_REGISTER_TYPE_F;
> +  else if (inst->dst.type == BRW_REGISTER_TYPE_HF)
> + exec_type = BRW_REGISTER_TYPE_D;
> +   }
> +
> return exec_type;
>  }
>
> --
> 2.19.2
>
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Re: [Mesa-dev] [PATCH] intel/fs: Promote execution type to 32-bit when any half-float conversion is needed.

[Iago Toral]

Tested-by: Iago Toral Quiroga 
Reviewed-by: Iago Toral Quiroga 

On Tue, 2019-01-15 at 23:31 -0800, Francisco Jerez wrote:
> The docs are fairly incomplete and inconsistent about it, but this
> seems to be the reason why half-float destinations are required to be
> DWORD-aligned on BDW+ projects.  This way the regioning lowering pass
> will make sure that the destination components of W to HF and HF to W
> conversions are aligned like the corresponding conversion operation
> with 32-bit execution data type.
> ---
>  src/intel/compiler/brw_ir_fs.h | 21 +
>  1 file changed, 21 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_ir_fs.h
> b/src/intel/compiler/brw_ir_fs.h
> index 3c23fb375e4..08e3d83d910 100644
> --- a/src/intel/compiler/brw_ir_fs.h
> +++ b/src/intel/compiler/brw_ir_fs.h
> @@ -477,6 +477,27 @@ get_exec_type(const fs_inst *inst)
>  
> assert(exec_type != BRW_REGISTER_TYPE_B);
>  
> +   /* Promotion of the execution type to 32-bit for conversions from
> or to
> +* half-float seems to be consistent with the following text from
> the
> +* Cherryview PRM Vol. 7, "Execution Data Type":
> +*
> +* "When single precision and half precision floats are mixed
> between
> +*  source operands or between source and destination operand
> [..] single
> +*  precision float is the execution datatype."
> +*
> +* and from "Register Region Restrictions":
> +*
> +* "Conversion between Integer and HF (Half Float) must be DWord
> aligned
> +*  and strided by a DWord on the destination."
> +*/
> +   if (type_sz(exec_type) == 2 &&
> +   inst->dst.type != exec_type) {
> +  if (exec_type == BRW_REGISTER_TYPE_HF)
> + exec_type = BRW_REGISTER_TYPE_F;
> +  else if (inst->dst.type == BRW_REGISTER_TYPE_HF)
> + exec_type = BRW_REGISTER_TYPE_D;
> +   }
> +
> return exec_type;
>  }
>  

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[Mesa-dev] [PATCH] intel/fs: Promote execution type to 32-bit when any half-float conversion is needed.

[Francisco Jerez]

The docs are fairly incomplete and inconsistent about it, but this
seems to be the reason why half-float destinations are required to be
DWORD-aligned on BDW+ projects.  This way the regioning lowering pass
will make sure that the destination components of W to HF and HF to W
conversions are aligned like the corresponding conversion operation
with 32-bit execution data type.
---
 src/intel/compiler/brw_ir_fs.h | 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h
index 3c23fb375e4..08e3d83d910 100644
--- a/src/intel/compiler/brw_ir_fs.h
+++ b/src/intel/compiler/brw_ir_fs.h
@@ -477,6 +477,27 @@ get_exec_type(const fs_inst *inst)
 
assert(exec_type != BRW_REGISTER_TYPE_B);
 
+   /* Promotion of the execution type to 32-bit for conversions from or to
+* half-float seems to be consistent with the following text from the
+* Cherryview PRM Vol. 7, "Execution Data Type":
+*
+* "When single precision and half precision floats are mixed between
+*  source operands or between source and destination operand [..] single
+*  precision float is the execution datatype."
+*
+* and from "Register Region Restrictions":
+*
+* "Conversion between Integer and HF (Half Float) must be DWord aligned
+*  and strided by a DWord on the destination."
+*/
+   if (type_sz(exec_type) == 2 &&
+   inst->dst.type != exec_type) {
+  if (exec_type == BRW_REGISTER_TYPE_HF)
+ exec_type = BRW_REGISTER_TYPE_F;
+  else if (inst->dst.type == BRW_REGISTER_TYPE_HF)
+ exec_type = BRW_REGISTER_TYPE_D;
+   }
+
return exec_type;
 }
 
-- 
2.19.2

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