Re: [Mesa-dev] [PATCH] radeon/uvd: enable rate control for hevc encoding
On Wed, 2019-06-19 at 17:04 -0400, boyuan.zh...@amd.com wrote:
> From: Boyuan Zhang
>
> Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
> off when rate control is disabled (e.g. constant qp).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
> Cc: mesa-sta...@lists.freedesktop.org
>
> V2: fix typo and add bugzilla info
>
> Signed-off-by: Boyuan Zhang
> Acked-by: Leo Liu
What happened with this patch? I see the bug has been closed as resolved, but
neither this patch has been reviewed or landed in master.
> ---
> src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
> b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
> index 8f0e0099e7..9acc33d906 100644
> --- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
> +++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
> @@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder
> *enc)
>enc->enc_pic.hevc_spec_misc.
>constrained_intra_pred_flag, 1);
> radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
> - radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
> + if (enc->enc_pic.rc_session_init.rate_control_method ==
> + RENC_UVD_RATE_CONTROL_METHOD_NONE)
> + radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
> + else {
> + radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
> + radeon_uvd_enc_code_ue(enc, 0x0);
> + }
> radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
> radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
> radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
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[Mesa-dev] [PATCH] radeon/uvd: enable rate control for hevc encoding
From: Boyuan Zhang
Set cu_qp_delta_enable_flag on when rate control is enabled, and set it
off when rate control is disabled (e.g. constant qp).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110673
Cc: mesa-sta...@lists.freedesktop.org
V2: fix typo and add bugzilla info
Signed-off-by: Boyuan Zhang
Acked-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index 8f0e0099e7..9acc33d906 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder
*enc)
enc->enc_pic.hevc_spec_misc.
constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
- radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+ if (enc->enc_pic.rc_session_init.rate_control_method ==
+ RENC_UVD_RATE_CONTROL_METHOD_NONE)
+ radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+ else {
+ radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+ radeon_uvd_enc_code_ue(enc, 0x0);
+ }
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
--
2.17.1
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[Mesa-dev] [PATCH] radeon/uvd: enable rate control for hevc encoding
From: Boyuan Zhang
Set cu_qp_delta_enable_flag on when rate control is enabled, and it
off when no rate control is disabled (constant qp).
Signed-off-by: Boyuan Zhang
---
src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
index 8f0e0099e7..9acc33d906 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc_1_1.c
@@ -573,7 +573,13 @@ radeon_uvd_enc_nalu_pps_hevc(struct radeon_uvd_encoder
*enc)
enc->enc_pic.hevc_spec_misc.
constrained_intra_pred_flag, 1);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
- radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+ if (enc->enc_pic.rc_session_init.rate_control_method ==
+ RENC_UVD_RATE_CONTROL_METHOD_NONE)
+ radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
+ else {
+ radeon_uvd_enc_code_fixed_bits(enc, 0x1, 1);
+ radeon_uvd_enc_code_ue(enc, 0x0);
+ }
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset);
radeon_uvd_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset);
radeon_uvd_enc_code_fixed_bits(enc, 0x0, 1);
--
2.17.1
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