Re: [Mesa-dev] [PATCH] radeonsi: add support for Vega20
On Wed, Jul 11, 2018 at 4:11 PM, Marek Olšák wrote:
> From: Marek Olšák
>
> ---
> include/pci_ids/radeonsi_pci_ids.h | 7 +++
> src/amd/addrlib/amdgpu_asic_addr.h | 2 ++
> src/amd/addrlib/gfx9/gfx9addrlib.cpp| 3 ++-
> src/amd/addrlib/gfx9/gfx9addrlib.h | 1 +
> src/amd/common/ac_llvm_util.c | 4 +++-
> src/amd/common/ac_surface.c | 4
> src/amd/common/amd_family.h | 1 +
> src/amd/common/gfx9d.h | 1 +
> src/gallium/drivers/radeonsi/si_get.c | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
> src/gallium/drivers/radeonsi/si_state.c | 1 +
> src/gallium/drivers/radeonsi/si_state_binning.c | 1 +
> 12 files changed, 26 insertions(+), 3 deletions(-)
Reviewed-by: Alex Deucher
>
> diff --git a/include/pci_ids/radeonsi_pci_ids.h
> b/include/pci_ids/radeonsi_pci_ids.h
> index 6386d21a19f..c8d30597230 100644
> --- a/include/pci_ids/radeonsi_pci_ids.h
> +++ b/include/pci_ids/radeonsi_pci_ids.h
> @@ -228,11 +228,18 @@ CHIPSET(0x6867, VEGA10)
> CHIPSET(0x6868, VEGA10)
> CHIPSET(0x687F, VEGA10)
> CHIPSET(0x686C, VEGA10)
>
> CHIPSET(0x69A0, VEGA12)
> CHIPSET(0x69A1, VEGA12)
> CHIPSET(0x69A2, VEGA12)
> CHIPSET(0x69A3, VEGA12)
> CHIPSET(0x69AF, VEGA12)
>
> +CHIPSET(0x66A0, VEGA20)
> +CHIPSET(0x66A1, VEGA20)
> +CHIPSET(0x66A2, VEGA20)
> +CHIPSET(0x66A3, VEGA20)
> +CHIPSET(0x66A7, VEGA20)
> +CHIPSET(0x66AF, VEGA20)
> +
> CHIPSET(0x15DD, RAVEN)
> diff --git a/src/amd/addrlib/amdgpu_asic_addr.h
> b/src/amd/addrlib/amdgpu_asic_addr.h
> index b4b8aecd42d..e5838d42a3c 100644
> --- a/src/amd/addrlib/amdgpu_asic_addr.h
> +++ b/src/amd/addrlib/amdgpu_asic_addr.h
> @@ -80,20 +80,21 @@
> #define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
> #define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
> #define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
>
> #define AMDGPU_CARRIZO_RANGE0x01, 0x21
> #define AMDGPU_BRISTOL_RANGE0x10, 0x21
> #define AMDGPU_STONEY_RANGE 0x61, 0xFF
>
> #define AMDGPU_VEGA10_RANGE 0x01, 0x14
> #define AMDGPU_VEGA12_RANGE 0x14, 0x28
> +#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
>
> #define AMDGPU_RAVEN_RANGE 0x01, 0x81
>
> #define AMDGPU_EXPAND_FIX(x) x
> #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
> #define AMDGPU_IN_RANGE(val, ...)
> AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val, __VA_ARGS__))
>
>
> // ASICREV_IS(eRevisionId, revisionName)
> #define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r,
> AMDGPU_##rn##_RANGE)
> @@ -121,14 +122,15 @@
> #define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
>
> #define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
> #define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
> #define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
>
> #define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
> #define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
> #define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
> #define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
> +#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
>
> #define ASICREV_IS_RAVEN(r)ASICREV_IS(r, RAVEN)
>
> #endif // _AMDGPU_ASIC_ADDR_H
> diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> index b88d3243228..ef86c3bc7b5 100644
> --- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> +++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
> @@ -1223,20 +1223,21 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
> ADDR_ASSERT((m_blockVarSizeLog2 == 0) ||
> ((m_blockVarSizeLog2 >= 17u) && (m_blockVarSizeLog2 <=
> 20u)));
> m_blockVarSizeLog2 = Min(Max(17u, m_blockVarSizeLog2), 20u);
>
> if ((m_rbPerSeLog2 == 1) &&
> (((m_pipesLog2 == 1) && ((m_seLog2 == 2) || (m_seLog2 == 3))) ||
> ((m_pipesLog2 == 2) && ((m_seLog2 == 1) || (m_seLog2 == 2)
> {
> ADDR_ASSERT(m_settings.isVega10 == FALSE);
> ADDR_ASSERT(m_settings.isRaven == FALSE);
> +ADDR_ASSERT(m_settings.isVega20 == FALSE);
>
> if (m_settings.isVega12)
> {
> m_settings.htileCacheRbConflict = 1;
> }
> }
> }
> else
> {
> valid = FALSE;
> @@ -1266,21 +1267,21 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
> UINT_32 uChipRevision) ///< [in] chip revision defined in
> "asic_family"_id.h
> {
> ChipFamily family = ADDR_CHIP_FAMILY_AI;
>
> switch (uChipFamily)
> {
> case FAMILY_AI:
> m_settings.isArcticIsland = 1;
> m_settings.isVega10= ASICREV_IS_VEGA10_P(uChipRevision);
> m_settings.isVega12= ASICREV_IS_VEGA12_P(uChipRevision);
> -
> +m_settings.isVega20= ASICREV_IS_VEGA20_P(uChipRevision);
> m_settings.isDce12 = 1;
>
>
[Mesa-dev] [PATCH] radeonsi: add support for Vega20
From: Marek Olšák
---
include/pci_ids/radeonsi_pci_ids.h | 7 +++
src/amd/addrlib/amdgpu_asic_addr.h | 2 ++
src/amd/addrlib/gfx9/gfx9addrlib.cpp| 3 ++-
src/amd/addrlib/gfx9/gfx9addrlib.h | 1 +
src/amd/common/ac_llvm_util.c | 4 +++-
src/amd/common/ac_surface.c | 4
src/amd/common/amd_family.h | 1 +
src/amd/common/gfx9d.h | 1 +
src/gallium/drivers/radeonsi/si_get.c | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 3 ++-
src/gallium/drivers/radeonsi/si_state.c | 1 +
src/gallium/drivers/radeonsi/si_state_binning.c | 1 +
12 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/include/pci_ids/radeonsi_pci_ids.h
b/include/pci_ids/radeonsi_pci_ids.h
index 6386d21a19f..c8d30597230 100644
--- a/include/pci_ids/radeonsi_pci_ids.h
+++ b/include/pci_ids/radeonsi_pci_ids.h
@@ -228,11 +228,18 @@ CHIPSET(0x6867, VEGA10)
CHIPSET(0x6868, VEGA10)
CHIPSET(0x687F, VEGA10)
CHIPSET(0x686C, VEGA10)
CHIPSET(0x69A0, VEGA12)
CHIPSET(0x69A1, VEGA12)
CHIPSET(0x69A2, VEGA12)
CHIPSET(0x69A3, VEGA12)
CHIPSET(0x69AF, VEGA12)
+CHIPSET(0x66A0, VEGA20)
+CHIPSET(0x66A1, VEGA20)
+CHIPSET(0x66A2, VEGA20)
+CHIPSET(0x66A3, VEGA20)
+CHIPSET(0x66A7, VEGA20)
+CHIPSET(0x66AF, VEGA20)
+
CHIPSET(0x15DD, RAVEN)
diff --git a/src/amd/addrlib/amdgpu_asic_addr.h
b/src/amd/addrlib/amdgpu_asic_addr.h
index b4b8aecd42d..e5838d42a3c 100644
--- a/src/amd/addrlib/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/amdgpu_asic_addr.h
@@ -80,20 +80,21 @@
#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
#define AMDGPU_CARRIZO_RANGE0x01, 0x21
#define AMDGPU_BRISTOL_RANGE0x10, 0x21
#define AMDGPU_STONEY_RANGE 0x61, 0xFF
#define AMDGPU_VEGA10_RANGE 0x01, 0x14
#define AMDGPU_VEGA12_RANGE 0x14, 0x28
+#define AMDGPU_VEGA20_RANGE 0x28, 0xFF
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
#define AMDGPU_IN_RANGE(val, ...) AMDGPU_EXPAND_FIX(AMDGPU_RANGE_HELPER(val,
__VA_ARGS__))
// ASICREV_IS(eRevisionId, revisionName)
#define ASICREV_IS(r, rn) AMDGPU_IN_RANGE(r, AMDGPU_##rn##_RANGE)
@@ -121,14 +122,15 @@
#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
#define ASICREV_IS_VEGA10_P(r) ASICREV_IS(r, VEGA10)
#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
+#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
#define ASICREV_IS_RAVEN(r)ASICREV_IS(r, RAVEN)
#endif // _AMDGPU_ASIC_ADDR_H
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
index b88d3243228..ef86c3bc7b5 100644
--- a/src/amd/addrlib/gfx9/gfx9addrlib.cpp
+++ b/src/amd/addrlib/gfx9/gfx9addrlib.cpp
@@ -1223,20 +1223,21 @@ BOOL_32 Gfx9Lib::HwlInitGlobalParams(
ADDR_ASSERT((m_blockVarSizeLog2 == 0) ||
((m_blockVarSizeLog2 >= 17u) && (m_blockVarSizeLog2 <=
20u)));
m_blockVarSizeLog2 = Min(Max(17u, m_blockVarSizeLog2), 20u);
if ((m_rbPerSeLog2 == 1) &&
(((m_pipesLog2 == 1) && ((m_seLog2 == 2) || (m_seLog2 == 3))) ||
((m_pipesLog2 == 2) && ((m_seLog2 == 1) || (m_seLog2 == 2)
{
ADDR_ASSERT(m_settings.isVega10 == FALSE);
ADDR_ASSERT(m_settings.isRaven == FALSE);
+ADDR_ASSERT(m_settings.isVega20 == FALSE);
if (m_settings.isVega12)
{
m_settings.htileCacheRbConflict = 1;
}
}
}
else
{
valid = FALSE;
@@ -1266,21 +1267,21 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
UINT_32 uChipRevision) ///< [in] chip revision defined in
"asic_family"_id.h
{
ChipFamily family = ADDR_CHIP_FAMILY_AI;
switch (uChipFamily)
{
case FAMILY_AI:
m_settings.isArcticIsland = 1;
m_settings.isVega10= ASICREV_IS_VEGA10_P(uChipRevision);
m_settings.isVega12= ASICREV_IS_VEGA12_P(uChipRevision);
-
+m_settings.isVega20= ASICREV_IS_VEGA20_P(uChipRevision);
m_settings.isDce12 = 1;
if (m_settings.isVega10 == 0)
{
m_settings.htileAlignFix = 1;
m_settings.applyAliasFix = 1;
}
m_settings.metaBaseAlignFix = 1;
diff --git a/src/amd/addrlib/gfx9/gfx9addrlib.h
b/src/amd/addrlib/gfx9/gfx9addrlib.h
index
