Re: [Mesa-dev] [PATCH] radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
Oops. No, r-b
On Wed, Jun 19, 2019, 9:48 AM Samuel Pitoiset
wrote:
>
> On 6/17/19 12:24 PM, Bas Nieuwenhuizen wrote:
>
>
>
>
> On Thu, Jun 13, 2019, 3:42 PM Samuel Pitoiset
> wrote:
>
>> This allows us to disable the FMASK decompress pass when
>> transitioning from CB writes to shader reads.
>>
>> This will likely be improved and enabled by default in the future.
>>
>> No CTS regressions on GFX8 but a few number of multisample CTS
>> failures on GFX9 (they look related to the small hint).
>>
>> Signed-off-by: Samuel Pitoiset
>> ---
>> src/amd/vulkan/radv_cmd_buffer.c | 9 ++
>> src/amd/vulkan/radv_debug.h | 1 +
>> src/amd/vulkan/radv_device.c | 15 ++
>> src/amd/vulkan/radv_image.c | 42 +++
>> src/amd/vulkan/radv_meta.h| 26 +
>> src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
>> src/amd/vulkan/radv_private.h | 10 +++
>> 7 files changed, 104 insertions(+), 1 deletion(-)
>>
>> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
>> b/src/amd/vulkan/radv_cmd_buffer.c
>> index 2fd5f8b7a07..bf208899887 100644
>> --- a/src/amd/vulkan/radv_cmd_buffer.c
>> +++ b/src/amd/vulkan/radv_cmd_buffer.c
>> @@ -1254,6 +1254,15 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
>> *cmd_buffer,
>> cb_color_info &= C_028C70_DCC_ENABLE;
>> }
>>
>> + if (radv_image_is_tc_compat_cmask(image) &&
>> + (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
>> +radv_is_dcc_decompress_pipeline(cmd_buffer))) {
>> + /* If this bit is set, the FMASK decompression operation
>> +* doesn't occur (DCC_COMPRESS also implies
>> FMASK_DECOMPRESS).
>> +*/
>> + cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
>> + }
>> +
>> if (cmd_buffer->device->physical_device->rad_info.chip_class >=
>> GFX9) {
>> radeon_set_context_reg_seq(cmd_buffer->cs,
>> R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
>> radeon_emit(cmd_buffer->cs, cb->cb_color_base);
>> diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
>> index 652a3b677d2..29793e549ce 100644
>> --- a/src/amd/vulkan/radv_debug.h
>> +++ b/src/amd/vulkan/radv_debug.h
>> @@ -61,6 +61,7 @@ enum {
>> RADV_PERFTEST_OUT_OF_ORDER = 0x8,
>> RADV_PERFTEST_DCC_MSAA = 0x10,
>> RADV_PERFTEST_BO_LIST= 0x20,
>> + RADV_PERFTEST_TC_COMPAT_CMASK = 0x40,
>> };
>>
>> bool
>> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
>> index 3b69e457496..b75ce59dfc3 100644
>> --- a/src/amd/vulkan/radv_device.c
>> +++ b/src/amd/vulkan/radv_device.c
>> @@ -479,6 +479,7 @@ static const struct debug_control
>> radv_perftest_options[] = {
>> {"localbos", RADV_PERFTEST_LOCAL_BOS},
>> {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
>> {"bolist", RADV_PERFTEST_BO_LIST},
>> + {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
>> {NULL, 0}
>> };
>>
>> @@ -4389,6 +4390,20 @@ radv_initialise_color_surface(struct radv_device
>> *device,
>> unsigned fmask_bankh =
>> util_logbase2(iview->image->fmask.bank_height);
>> cb->cb_color_attrib |=
>> S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
>> }
>> +
>> + if (radv_image_is_tc_compat_cmask(iview->image)) {
>> + /* Allow the texture block to read FMASK directly
>> +* without decompressing it. This bit must be
>> cleared
>> +* when performing FMASK_DECOMPRESS or
>> DCC_COMPRESS,
>> +* otherwise the operation doesn't happen.
>> +*/
>> + cb->cb_color_info |=
>> S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
>> +
>> + /* Set CMASK into a tiling format that allows the
>> +* texture block to read it.
>> +*/
>> + cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
>> + }
>> }
>>
>> if (radv_image_has_cmask(iview->image) &&
>> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
>> index d8dc2dfabde..c58c08fca59 100644
>> --- a/src/amd/vulkan/radv_image.c
>> +++ b/src/amd/vulkan/radv_image.c
>> @@ -219,6 +219,29 @@ radv_use_dcc_for_image(struct radv_device *device,
>> return true;
>> }
>>
>> +static bool
>> +radv_use_tc_compat_cmask_for_image(struct radv_device *device,
>> + struct radv_image *image)
>> +{
>
> + if (!(device->instance->perftest_flags &
>> RADV_PERFTEST_TC_COMPAT_CMASK))
>> + return false;
>> +
>> + /* TC-compat CMASK is only available for GFX8+. */
>> + if (device->physical_device->rad_info.chip_class < GFX8)
>> + return false;
>> +
>> + if (image->usage &
Re: [Mesa-dev] [PATCH] radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
On 6/17/19 12:24 PM, Bas Nieuwenhuizen wrote:
On Thu, Jun 13, 2019, 3:42 PM Samuel Pitoiset
mailto:samuel.pitoi...@gmail.com>> wrote:
This allows us to disable the FMASK decompress pass when
transitioning from CB writes to shader reads.
This will likely be improved and enabled by default in the future.
No CTS regressions on GFX8 but a few number of multisample CTS
failures on GFX9 (they look related to the small hint).
Signed-off-by: Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>>
---
src/amd/vulkan/radv_cmd_buffer.c | 9 ++
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 15 ++
src/amd/vulkan/radv_image.c | 42
+++
src/amd/vulkan/radv_meta.h | 26 +
src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
src/amd/vulkan/radv_private.h | 10 +++
7 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c
b/src/amd/vulkan/radv_cmd_buffer.c
index 2fd5f8b7a07..bf208899887 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1254,6 +1254,15 @@ radv_emit_fb_color_state(struct
radv_cmd_buffer *cmd_buffer,
cb_color_info &= C_028C70_DCC_ENABLE;
}
+ if (radv_image_is_tc_compat_cmask(image) &&
+ (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
+ radv_is_dcc_decompress_pipeline(cmd_buffer))) {
+ /* If this bit is set, the FMASK decompression
operation
+ * doesn't occur (DCC_COMPRESS also implies
FMASK_DECOMPRESS).
+ */
+ cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
+ }
+
if
(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE
+ index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 652a3b677d2..29793e549ce 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -61,6 +61,7 @@ enum {
RADV_PERFTEST_OUT_OF_ORDER = 0x8,
RADV_PERFTEST_DCC_MSAA = 0x10,
RADV_PERFTEST_BO_LIST = 0x20,
+ RADV_PERFTEST_TC_COMPAT_CMASK = 0x40,
};
bool
diff --git a/src/amd/vulkan/radv_device.c
b/src/amd/vulkan/radv_device.c
index 3b69e457496..b75ce59dfc3 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -479,6 +479,7 @@ static const struct debug_control
radv_perftest_options[] = {
{"localbos", RADV_PERFTEST_LOCAL_BOS},
{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
{"bolist", RADV_PERFTEST_BO_LIST},
+ {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
{NULL, 0}
};
@@ -4389,6 +4390,20 @@ radv_initialise_color_surface(struct
radv_device *device,
unsigned fmask_bankh =
util_logbase2(iview->image->fmask.bank_height);
cb->cb_color_attrib |=
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
+
+ if (radv_image_is_tc_compat_cmask(iview->image)) {
+ /* Allow the texture block to read FMASK
directly
+ * without decompressing it. This bit must
be cleared
+ * when performing FMASK_DECOMPRESS or
DCC_COMPRESS,
+ * otherwise the operation doesn't happen.
+ */
+ cb->cb_color_info |=
S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
+
+ /* Set CMASK into a tiling format that
allows the
+ * texture block to read it.
+ */
+ cb->cb_color_info |=
S_028C70_CMASK_ADDR_TYPE(2);
+ }
}
if (radv_image_has_cmask(iview->image) &&
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index d8dc2dfabde..c58c08fca59 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -219,6 +219,29 @@ radv_use_dcc_for_image(struct radv_device
*device,
return true;
}
+static bool
+radv_use_tc_compat_cmask_for_image(struct radv_device *device,
+ struct radv_image *image)
+{
+ if (!(device->instance->perftest_flags &
RADV_PERFTEST_TC_COMPAT_CMASK))
+ return false;
+
+ /* TC-compat CMASK is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < GFX8)
Re: [Mesa-dev] [PATCH] radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
On Thu, Jun 13, 2019, 3:42 PM Samuel Pitoiset
wrote:
> This allows us to disable the FMASK decompress pass when
> transitioning from CB writes to shader reads.
>
> This will likely be improved and enabled by default in the future.
>
> No CTS regressions on GFX8 but a few number of multisample CTS
> failures on GFX9 (they look related to the small hint).
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_cmd_buffer.c | 9 ++
> src/amd/vulkan/radv_debug.h | 1 +
> src/amd/vulkan/radv_device.c | 15 ++
> src/amd/vulkan/radv_image.c | 42 +++
> src/amd/vulkan/radv_meta.h| 26 +
> src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
> src/amd/vulkan/radv_private.h | 10 +++
> 7 files changed, 104 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/vulkan/radv_cmd_buffer.c
> b/src/amd/vulkan/radv_cmd_buffer.c
> index 2fd5f8b7a07..bf208899887 100644
> --- a/src/amd/vulkan/radv_cmd_buffer.c
> +++ b/src/amd/vulkan/radv_cmd_buffer.c
> @@ -1254,6 +1254,15 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
> *cmd_buffer,
> cb_color_info &= C_028C70_DCC_ENABLE;
> }
>
> + if (radv_image_is_tc_compat_cmask(image) &&
> + (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
> +radv_is_dcc_decompress_pipeline(cmd_buffer))) {
> + /* If this bit is set, the FMASK decompression operation
> +* doesn't occur (DCC_COMPRESS also implies
> FMASK_DECOMPRESS).
> +*/
> + cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
> + }
> +
> if (cmd_buffer->device->physical_device->rad_info.chip_class >=
> GFX9) {
> radeon_set_context_reg_seq(cmd_buffer->cs,
> R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
> radeon_emit(cmd_buffer->cs, cb->cb_color_base);
> diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
> index 652a3b677d2..29793e549ce 100644
> --- a/src/amd/vulkan/radv_debug.h
> +++ b/src/amd/vulkan/radv_debug.h
> @@ -61,6 +61,7 @@ enum {
> RADV_PERFTEST_OUT_OF_ORDER = 0x8,
> RADV_PERFTEST_DCC_MSAA = 0x10,
> RADV_PERFTEST_BO_LIST= 0x20,
> + RADV_PERFTEST_TC_COMPAT_CMASK = 0x40,
> };
>
> bool
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 3b69e457496..b75ce59dfc3 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -479,6 +479,7 @@ static const struct debug_control
> radv_perftest_options[] = {
> {"localbos", RADV_PERFTEST_LOCAL_BOS},
> {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
> {"bolist", RADV_PERFTEST_BO_LIST},
> + {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
> {NULL, 0}
> };
>
> @@ -4389,6 +4390,20 @@ radv_initialise_color_surface(struct radv_device
> *device,
> unsigned fmask_bankh =
> util_logbase2(iview->image->fmask.bank_height);
> cb->cb_color_attrib |=
> S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
> }
> +
> + if (radv_image_is_tc_compat_cmask(iview->image)) {
> + /* Allow the texture block to read FMASK directly
> +* without decompressing it. This bit must be
> cleared
> +* when performing FMASK_DECOMPRESS or
> DCC_COMPRESS,
> +* otherwise the operation doesn't happen.
> +*/
> + cb->cb_color_info |=
> S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
> +
> + /* Set CMASK into a tiling format that allows the
> +* texture block to read it.
> +*/
> + cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
> + }
> }
>
> if (radv_image_has_cmask(iview->image) &&
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index d8dc2dfabde..c58c08fca59 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -219,6 +219,29 @@ radv_use_dcc_for_image(struct radv_device *device,
> return true;
> }
>
> +static bool
> +radv_use_tc_compat_cmask_for_image(struct radv_device *device,
> + struct radv_image *image)
> +{
+ if (!(device->instance->perftest_flags &
> RADV_PERFTEST_TC_COMPAT_CMASK))
> + return false;
> +
> + /* TC-compat CMASK is only available for GFX8+. */
> + if (device->physical_device->rad_info.chip_class < GFX8)
> + return false;
> +
> + if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
> + return false;
> +
> + if (radv_image_has_dcc(image))
> + return false;
> +
> + if (!radv_image_has_cmask(image))
> + return false;
> +
> + return true;
> +}
> +
> static void
>
[Mesa-dev] [PATCH] radv: implement compressed FMASK texture reads with RADV_PERFTEST=tccompatcmask
This allows us to disable the FMASK decompress pass when
transitioning from CB writes to shader reads.
This will likely be improved and enabled by default in the future.
No CTS regressions on GFX8 but a few number of multisample CTS
failures on GFX9 (they look related to the small hint).
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 9 ++
src/amd/vulkan/radv_debug.h | 1 +
src/amd/vulkan/radv_device.c | 15 ++
src/amd/vulkan/radv_image.c | 42 +++
src/amd/vulkan/radv_meta.h| 26 +
src/amd/vulkan/radv_meta_fast_clear.c | 2 +-
src/amd/vulkan/radv_private.h | 10 +++
7 files changed, 104 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2fd5f8b7a07..bf208899887 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1254,6 +1254,15 @@ radv_emit_fb_color_state(struct radv_cmd_buffer
*cmd_buffer,
cb_color_info &= C_028C70_DCC_ENABLE;
}
+ if (radv_image_is_tc_compat_cmask(image) &&
+ (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
+radv_is_dcc_decompress_pipeline(cmd_buffer))) {
+ /* If this bit is set, the FMASK decompression operation
+* doesn't occur (DCC_COMPRESS also implies FMASK_DECOMPRESS).
+*/
+ cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
+ }
+
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_context_reg_seq(cmd_buffer->cs,
R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
diff --git a/src/amd/vulkan/radv_debug.h b/src/amd/vulkan/radv_debug.h
index 652a3b677d2..29793e549ce 100644
--- a/src/amd/vulkan/radv_debug.h
+++ b/src/amd/vulkan/radv_debug.h
@@ -61,6 +61,7 @@ enum {
RADV_PERFTEST_OUT_OF_ORDER = 0x8,
RADV_PERFTEST_DCC_MSAA = 0x10,
RADV_PERFTEST_BO_LIST= 0x20,
+ RADV_PERFTEST_TC_COMPAT_CMASK = 0x40,
};
bool
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 3b69e457496..b75ce59dfc3 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -479,6 +479,7 @@ static const struct debug_control radv_perftest_options[] =
{
{"localbos", RADV_PERFTEST_LOCAL_BOS},
{"dccmsaa", RADV_PERFTEST_DCC_MSAA},
{"bolist", RADV_PERFTEST_BO_LIST},
+ {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
{NULL, 0}
};
@@ -4389,6 +4390,20 @@ radv_initialise_color_surface(struct radv_device *device,
unsigned fmask_bankh =
util_logbase2(iview->image->fmask.bank_height);
cb->cb_color_attrib |=
S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
}
+
+ if (radv_image_is_tc_compat_cmask(iview->image)) {
+ /* Allow the texture block to read FMASK directly
+* without decompressing it. This bit must be cleared
+* when performing FMASK_DECOMPRESS or DCC_COMPRESS,
+* otherwise the operation doesn't happen.
+*/
+ cb->cb_color_info |=
S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
+
+ /* Set CMASK into a tiling format that allows the
+* texture block to read it.
+*/
+ cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
+ }
}
if (radv_image_has_cmask(iview->image) &&
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index d8dc2dfabde..c58c08fca59 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -219,6 +219,29 @@ radv_use_dcc_for_image(struct radv_device *device,
return true;
}
+static bool
+radv_use_tc_compat_cmask_for_image(struct radv_device *device,
+ struct radv_image *image)
+{
+ if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
+ return false;
+
+ /* TC-compat CMASK is only available for GFX8+. */
+ if (device->physical_device->rad_info.chip_class < GFX8)
+ return false;
+
+ if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
+ return false;
+
+ if (radv_image_has_dcc(image))
+ return false;
+
+ if (!radv_image_has_cmask(image))
+ return false;
+
+ return true;
+}
+
static void
radv_prefill_surface_from_metadata(struct radv_device *device,
struct radeon_surf *surface,
@@ -726,11 +749,26 @@ si_make_texture_descriptor(struct radv_device *device,
