Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Tue, Mar 15, 2016 at 10:13:57AM +0100, Iago Toral wrote:
> On Tue, 2016-03-15 at 11:04 +0200, Pohjolainen, Topi wrote:
> > On Tue, Mar 15, 2016 at 07:44:43AM +0100, Iago Toral wrote:
> > > On Mon, 2016-03-14 at 11:15 -0700, Mark Janes wrote:
> > > > Iago Toral  writes:
> > > > 
> > > > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > > >> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez 
> > > > >> wrote:
> > > > >> > Hello,
> > > > >> > 
> > > > >> > There is only one patch from this series that has been reviewed 
> > > > >> > (patch
> > > > >> > 1).
> > > > >> > 
> > > > >> > Our plans is to start sending patches for adding fp64 support to 
> > > > >> > i965
> > > > >> > driver in the coming weeks but they depend on these patches.
> > > > >> > 
> > > > >> > Can someone take a look at them? ;)
> > > > >> > 
> > > > >> > Sam
> > > > >> > 
> > > > >> > 
> > > > >> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > >> > > Hello,
> > > > >> > > 
> > > > >> > > This patch series is a updated version of the one Iago sent last
> > > > >> > > week [0] that includes patches for gen6 too, as suggested by 
> > > > >> > > Jason.
> > > > >> > > 
> > > > >> > > We checked the gen9 code paths that work with a horizontal width 
> > > > >> > > of 4
> > > > >> > > and we think there won't be any regression on gen9... but we 
> > > > >> > > don't
> > > > >> > > have any gen9 machine to run piglit with these patches. Can 
> > > > >> > > someone
> > > > >> > > check it?
> > > > >> 
> > > > >> I rebased it and ran it through the test system, gen9 seems to be 
> > > > >> fine, I
> > > > >> only got one regression, and that was on old g965:
> > > > >> 
> > > > >> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy
> > > > >>  all_samples srgb depthstencil -auto -fbo
> > > > >> Pixels that should be unlit
> > > > >>   count = 236444
> > > > >>   RMS error = 0.025355
> > > > >> Pixels that should be totally lit
> > > > >>   count = 13308
> > > > >>   Perfect output
> > > > >> The error threshold for unlit and totally lit pixels test is 0.016650
> > > > >> Pixels that should be partially lit
> > > > >>   count = 12392
> > > > >>   RMS error = 0.273876
> > > > >> The error threshold for partially lit pixels is 0.333000
> > > > >> Samples = 0, Result = fail
> > > > >
> > > > > I managed to borrow gen4 hardware to test this. According to glxinfo:
> > > > > Mesa DRI Mobile Intel GM45 Express Chipset
> > > > >
> > > > > but it does not fail for me... never. I left this test running in a 
> > > > > loop
> > > > > for 5 minutes and it never failed. Also, looking at the problem
> > > > > described in the output you pasted above, it seems that the problem 
> > > > > was
> > > > > related to precision calculations and it looks rather odd that our
> > > > > execsize patches could've compromised the precision of anything...
> > > > >
> > > > > Mark, would it be possible for you or someone else to run the piglit
> > > > > test mentioned by Topi above on gen4 hardware against this Mesa 
> > > > > branch?:
> > > > > https://github.com/Igalia/mesa/tree/i965-fix-execsize
> > > > 
> > > > I ran this branch through our CI, and it passed all tests.  My
> > > > recollection is that ext_framebuffer_multisample-accuracy occasionally
> > > > fails on g965.  I would not attribute any failure of that test to this
> > > > branch.
> > > 
> > > Great, thanks Matt!
> > > 
> > > Topi: in that case I guess we can say there are no regressions in any
> > > gen, right? Do you have any other comments to the branch? We have merged
> > > the comments you made so far in case you want to double-check that we
> > > did not miss anything.
> > 
> > Right. We identified two piglit failures, one on hsw and this one on g965.
> > The former is intermittent and reproducible with current mesa master. Now
> > that we have answer for the latter also, I concur, your series should be
> > regression free.
> > 
> > I can take a look if you have a branch somewhere. I only had a few minor
> > comments in the first place and the series looks good to me. But I'll double
> > check.
> 
> Thanks! You can see the updated patches in this branch:
> https://github.com/Igalia/mesa/tree/i965-fix-execsize

Thanks Iago, I gave it a test spin and saw no regression. The series:

Reviewed-by: Topi Pohjolainen 
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Tue, 2016-03-15 at 11:04 +0200, Pohjolainen, Topi wrote:
> On Tue, Mar 15, 2016 at 07:44:43AM +0100, Iago Toral wrote:
> > On Mon, 2016-03-14 at 11:15 -0700, Mark Janes wrote:
> > > Iago Toral  writes:
> > > 
> > > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > >> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez 
> > > >> wrote:
> > > >> > Hello,
> > > >> > 
> > > >> > There is only one patch from this series that has been reviewed 
> > > >> > (patch
> > > >> > 1).
> > > >> > 
> > > >> > Our plans is to start sending patches for adding fp64 support to i965
> > > >> > driver in the coming weeks but they depend on these patches.
> > > >> > 
> > > >> > Can someone take a look at them? ;)
> > > >> > 
> > > >> > Sam
> > > >> > 
> > > >> > 
> > > >> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > >> > > Hello,
> > > >> > > 
> > > >> > > This patch series is a updated version of the one Iago sent last
> > > >> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > >> > > 
> > > >> > > We checked the gen9 code paths that work with a horizontal width 
> > > >> > > of 4
> > > >> > > and we think there won't be any regression on gen9... but we don't
> > > >> > > have any gen9 machine to run piglit with these patches. Can someone
> > > >> > > check it?
> > > >> 
> > > >> I rebased it and ran it through the test system, gen9 seems to be 
> > > >> fine, I
> > > >> only got one regression, and that was on old g965:
> > > >> 
> > > >> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy
> > > >>  all_samples srgb depthstencil -auto -fbo
> > > >> Pixels that should be unlit
> > > >>   count = 236444
> > > >>   RMS error = 0.025355
> > > >> Pixels that should be totally lit
> > > >>   count = 13308
> > > >>   Perfect output
> > > >> The error threshold for unlit and totally lit pixels test is 0.016650
> > > >> Pixels that should be partially lit
> > > >>   count = 12392
> > > >>   RMS error = 0.273876
> > > >> The error threshold for partially lit pixels is 0.333000
> > > >> Samples = 0, Result = fail
> > > >
> > > > I managed to borrow gen4 hardware to test this. According to glxinfo:
> > > > Mesa DRI Mobile Intel GM45 Express Chipset
> > > >
> > > > but it does not fail for me... never. I left this test running in a loop
> > > > for 5 minutes and it never failed. Also, looking at the problem
> > > > described in the output you pasted above, it seems that the problem was
> > > > related to precision calculations and it looks rather odd that our
> > > > execsize patches could've compromised the precision of anything...
> > > >
> > > > Mark, would it be possible for you or someone else to run the piglit
> > > > test mentioned by Topi above on gen4 hardware against this Mesa branch?:
> > > > https://github.com/Igalia/mesa/tree/i965-fix-execsize
> > > 
> > > I ran this branch through our CI, and it passed all tests.  My
> > > recollection is that ext_framebuffer_multisample-accuracy occasionally
> > > fails on g965.  I would not attribute any failure of that test to this
> > > branch.
> > 
> > Great, thanks Matt!
> > 
> > Topi: in that case I guess we can say there are no regressions in any
> > gen, right? Do you have any other comments to the branch? We have merged
> > the comments you made so far in case you want to double-check that we
> > did not miss anything.
> 
> Right. We identified two piglit failures, one on hsw and this one on g965.
> The former is intermittent and reproducible with current mesa master. Now
> that we have answer for the latter also, I concur, your series should be
> regression free.
> 
> I can take a look if you have a branch somewhere. I only had a few minor
> comments in the first place and the series looks good to me. But I'll double
> check.

Thanks! You can see the updated patches in this branch:
https://github.com/Igalia/mesa/tree/i965-fix-execsize

Iago

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Tue, Mar 15, 2016 at 07:44:43AM +0100, Iago Toral wrote:
> On Mon, 2016-03-14 at 11:15 -0700, Mark Janes wrote:
> > Iago Toral  writes:
> > 
> > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > >> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez 
> > >> wrote:
> > >> > Hello,
> > >> > 
> > >> > There is only one patch from this series that has been reviewed (patch
> > >> > 1).
> > >> > 
> > >> > Our plans is to start sending patches for adding fp64 support to i965
> > >> > driver in the coming weeks but they depend on these patches.
> > >> > 
> > >> > Can someone take a look at them? ;)
> > >> > 
> > >> > Sam
> > >> > 
> > >> > 
> > >> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > >> > > Hello,
> > >> > > 
> > >> > > This patch series is a updated version of the one Iago sent last
> > >> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > >> > > 
> > >> > > We checked the gen9 code paths that work with a horizontal width of 4
> > >> > > and we think there won't be any regression on gen9... but we don't
> > >> > > have any gen9 machine to run piglit with these patches. Can someone
> > >> > > check it?
> > >> 
> > >> I rebased it and ran it through the test system, gen9 seems to be fine, I
> > >> only got one regression, and that was on old g965:
> > >> 
> > >> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> > >> all_samples srgb depthstencil -auto -fbo
> > >> Pixels that should be unlit
> > >>   count = 236444
> > >>   RMS error = 0.025355
> > >> Pixels that should be totally lit
> > >>   count = 13308
> > >>   Perfect output
> > >> The error threshold for unlit and totally lit pixels test is 0.016650
> > >> Pixels that should be partially lit
> > >>   count = 12392
> > >>   RMS error = 0.273876
> > >> The error threshold for partially lit pixels is 0.333000
> > >> Samples = 0, Result = fail
> > >
> > > I managed to borrow gen4 hardware to test this. According to glxinfo:
> > > Mesa DRI Mobile Intel GM45 Express Chipset
> > >
> > > but it does not fail for me... never. I left this test running in a loop
> > > for 5 minutes and it never failed. Also, looking at the problem
> > > described in the output you pasted above, it seems that the problem was
> > > related to precision calculations and it looks rather odd that our
> > > execsize patches could've compromised the precision of anything...
> > >
> > > Mark, would it be possible for you or someone else to run the piglit
> > > test mentioned by Topi above on gen4 hardware against this Mesa branch?:
> > > https://github.com/Igalia/mesa/tree/i965-fix-execsize
> > 
> > I ran this branch through our CI, and it passed all tests.  My
> > recollection is that ext_framebuffer_multisample-accuracy occasionally
> > fails on g965.  I would not attribute any failure of that test to this
> > branch.
> 
> Great, thanks Matt!
> 
> Topi: in that case I guess we can say there are no regressions in any
> gen, right? Do you have any other comments to the branch? We have merged
> the comments you made so far in case you want to double-check that we
> did not miss anything.

Right. We identified two piglit failures, one on hsw and this one on g965.
The former is intermittent and reproducible with current mesa master. Now
that we have answer for the latter also, I concur, your series should be
regression free.

I can take a look if you have a branch somewhere. I only had a few minor
comments in the first place and the series looks good to me. But I'll double
check.
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Mon, 2016-03-14 at 11:15 -0700, Mark Janes wrote:
> Iago Toral  writes:
> 
> > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> >> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> >> > Hello,
> >> > 
> >> > There is only one patch from this series that has been reviewed (patch
> >> > 1).
> >> > 
> >> > Our plans is to start sending patches for adding fp64 support to i965
> >> > driver in the coming weeks but they depend on these patches.
> >> > 
> >> > Can someone take a look at them? ;)
> >> > 
> >> > Sam
> >> > 
> >> > 
> >> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> >> > > Hello,
> >> > > 
> >> > > This patch series is a updated version of the one Iago sent last
> >> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> >> > > 
> >> > > We checked the gen9 code paths that work with a horizontal width of 4
> >> > > and we think there won't be any regression on gen9... but we don't
> >> > > have any gen9 machine to run piglit with these patches. Can someone
> >> > > check it?
> >> 
> >> I rebased it and ran it through the test system, gen9 seems to be fine, I
> >> only got one regression, and that was on old g965:
> >> 
> >> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> >> all_samples srgb depthstencil -auto -fbo
> >> Pixels that should be unlit
> >>   count = 236444
> >>   RMS error = 0.025355
> >> Pixels that should be totally lit
> >>   count = 13308
> >>   Perfect output
> >> The error threshold for unlit and totally lit pixels test is 0.016650
> >> Pixels that should be partially lit
> >>   count = 12392
> >>   RMS error = 0.273876
> >> The error threshold for partially lit pixels is 0.333000
> >> Samples = 0, Result = fail
> >
> > I managed to borrow gen4 hardware to test this. According to glxinfo:
> > Mesa DRI Mobile Intel GM45 Express Chipset
> >
> > but it does not fail for me... never. I left this test running in a loop
> > for 5 minutes and it never failed. Also, looking at the problem
> > described in the output you pasted above, it seems that the problem was
> > related to precision calculations and it looks rather odd that our
> > execsize patches could've compromised the precision of anything...
> >
> > Mark, would it be possible for you or someone else to run the piglit
> > test mentioned by Topi above on gen4 hardware against this Mesa branch?:
> > https://github.com/Igalia/mesa/tree/i965-fix-execsize
> 
> I ran this branch through our CI, and it passed all tests.  My
> recollection is that ext_framebuffer_multisample-accuracy occasionally
> fails on g965.  I would not attribute any failure of that test to this
> branch.

Great, thanks Matt!

Topi: in that case I guess we can say there are no regressions in any
gen, right? Do you have any other comments to the branch? We have merged
the comments you made so far in case you want to double-check that we
did not miss anything.

> > BTW, I also tried to run this inside a larger piglit run (all.py with -t
> > framebuffer selects 910 tests, just in case the result could be alatered
> > by parallel runs) and same result, it always passes fine.
> >
> > Iago
> 


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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Mark Janes]

Iago Toral  writes:

> On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
>> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
>> > Hello,
>> > 
>> > There is only one patch from this series that has been reviewed (patch
>> > 1).
>> > 
>> > Our plans is to start sending patches for adding fp64 support to i965
>> > driver in the coming weeks but they depend on these patches.
>> > 
>> > Can someone take a look at them? ;)
>> > 
>> > Sam
>> > 
>> > 
>> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
>> > > Hello,
>> > > 
>> > > This patch series is a updated version of the one Iago sent last
>> > > week [0] that includes patches for gen6 too, as suggested by Jason.
>> > > 
>> > > We checked the gen9 code paths that work with a horizontal width of 4
>> > > and we think there won't be any regression on gen9... but we don't
>> > > have any gen9 machine to run piglit with these patches. Can someone
>> > > check it?
>> 
>> I rebased it and ran it through the test system, gen9 seems to be fine, I
>> only got one regression, and that was on old g965:
>> 
>> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
>> all_samples srgb depthstencil -auto -fbo
>> Pixels that should be unlit
>>   count = 236444
>>   RMS error = 0.025355
>> Pixels that should be totally lit
>>   count = 13308
>>   Perfect output
>> The error threshold for unlit and totally lit pixels test is 0.016650
>> Pixels that should be partially lit
>>   count = 12392
>>   RMS error = 0.273876
>> The error threshold for partially lit pixels is 0.333000
>> Samples = 0, Result = fail
>
> I managed to borrow gen4 hardware to test this. According to glxinfo:
> Mesa DRI Mobile Intel GM45 Express Chipset
>
> but it does not fail for me... never. I left this test running in a loop
> for 5 minutes and it never failed. Also, looking at the problem
> described in the output you pasted above, it seems that the problem was
> related to precision calculations and it looks rather odd that our
> execsize patches could've compromised the precision of anything...
>
> Mark, would it be possible for you or someone else to run the piglit
> test mentioned by Topi above on gen4 hardware against this Mesa branch?:
> https://github.com/Igalia/mesa/tree/i965-fix-execsize

I ran this branch through our CI, and it passed all tests.  My
recollection is that ext_framebuffer_multisample-accuracy occasionally
fails on g965.  I would not attribute any failure of that test to this
branch.

> BTW, I also tried to run this inside a larger piglit run (all.py with -t
> framebuffer selects 910 tests, just in case the result could be alatered
> by parallel runs) and same result, it always passes fine.
>
> Iago
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > Hello,
> > 
> > There is only one patch from this series that has been reviewed (patch
> > 1).
> > 
> > Our plans is to start sending patches for adding fp64 support to i965
> > driver in the coming weeks but they depend on these patches.
> > 
> > Can someone take a look at them? ;)
> > 
> > Sam
> > 
> > 
> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > Hello,
> > > 
> > > This patch series is a updated version of the one Iago sent last
> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > 
> > > We checked the gen9 code paths that work with a horizontal width of 4
> > > and we think there won't be any regression on gen9... but we don't
> > > have any gen9 machine to run piglit with these patches. Can someone
> > > check it?
> 
> I rebased it and ran it through the test system, gen9 seems to be fine, I
> only got one regression, and that was on old g965:
> 
> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> all_samples srgb depthstencil -auto -fbo
> Pixels that should be unlit
>   count = 236444
>   RMS error = 0.025355
> Pixels that should be totally lit
>   count = 13308
>   Perfect output
> The error threshold for unlit and totally lit pixels test is 0.016650
> Pixels that should be partially lit
>   count = 12392
>   RMS error = 0.273876
> The error threshold for partially lit pixels is 0.333000
> Samples = 0, Result = fail

I managed to borrow gen4 hardware to test this. According to glxinfo:
Mesa DRI Mobile Intel GM45 Express Chipset

but it does not fail for me... never. I left this test running in a loop
for 5 minutes and it never failed. Also, looking at the problem
described in the output you pasted above, it seems that the problem was
related to precision calculations and it looks rather odd that our
execsize patches could've compromised the precision of anything...

Mark, would it be possible for you or someone else to run the piglit
test mentioned by Topi above on gen4 hardware against this Mesa branch?:
https://github.com/Igalia/mesa/tree/i965-fix-execsize

BTW, I also tried to run this inside a larger piglit run (all.py with -t
framebuffer selects 910 tests, just in case the result could be alatered
by parallel runs) and same result, it always passes fine.

Iago

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Samuel Iglesias Gonsálvez]

On 10/03/16 10:27, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
>> Hello,
>>
>> There is only one patch from this series that has been reviewed (patch
>> 1).
>>
>> Our plans is to start sending patches for adding fp64 support to i965
>> driver in the coming weeks but they depend on these patches.
>>
>> Can someone take a look at them? ;)
>>
>> Sam
>>
>>
>> On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
>>> Hello,
>>>
>>> This patch series is a updated version of the one Iago sent last
>>> week [0] that includes patches for gen6 too, as suggested by Jason.
>>>
>>> We checked the gen9 code paths that work with a horizontal width of 4
>>> and we think there won't be any regression on gen9... but we don't
>>> have any gen9 machine to run piglit with these patches. Can someone
>>> check it?
>>>
>>> Please read the original cover letter [0] for more information.
>>>
>>> Sam
>>>
>>> [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
>>> 46.html
>>>
>>> Iago Toral Quiroga (5):
>>>   i965/eu: set correct execution size in brw_NOP
>>>   i965/fs: set execution size for SEND messages in
>>> generate_uniform_pull_constant_load_gen7
>>>   i965/eu: set execution size for SEND message in
>>> brw_send_indirect_message
>>>   i965: set correct execsize for MOVS with a width of 4 in
>>> brw_find_live_channel
>>>   i965: Skip execution size adjustment for instructions of width 4
>>>
>>> Samuel Iglesias Gonsálvez (4):
>>>   i965/gs/gen6: fix execsize for instructions with width of 4 in
>>> gen6_sol_program()
> 
> Here we have:
> 
> @@ -406,9 +406,11 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct 
> brw_ff_gs_prog_key *key,
>  : 0x00020001)); /* (1, 0, 2) 
> */
>   brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
>}
> +  brw_push_insn_state(p);
> +  brw_set_default_exec_size(p, BRW_EXECUTE_4);
>brw_ADD(p, c->reg.destination_indices,
>c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));
> 
> I was wondering if we could add an assertion (serves as documention also):
> 
>assert(c->reg.destination_indices.width == BRW_EXECUTE_4);
> 

Yes, we can add it. I will do it locally.

Sam
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> Hello,
> 
> There is only one patch from this series that has been reviewed (patch
> 1).
> 
> Our plans is to start sending patches for adding fp64 support to i965
> driver in the coming weeks but they depend on these patches.
> 
> Can someone take a look at them? ;)
> 
> Sam
> 
> 
> On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > Hello,
> > 
> > This patch series is a updated version of the one Iago sent last
> > week [0] that includes patches for gen6 too, as suggested by Jason.
> > 
> > We checked the gen9 code paths that work with a horizontal width of 4
> > and we think there won't be any regression on gen9... but we don't
> > have any gen9 machine to run piglit with these patches. Can someone
> > check it?
> > 
> > Please read the original cover letter [0] for more information.
> > 
> > Sam
> > 
> > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > 46.html
> > 
> > Iago Toral Quiroga (5):
> >   i965/eu: set correct execution size in brw_NOP
> >   i965/fs: set execution size for SEND messages in
> > generate_uniform_pull_constant_load_gen7
> >   i965/eu: set execution size for SEND message in
> > brw_send_indirect_message
> >   i965: set correct execsize for MOVS with a width of 4 in
> > brw_find_live_channel
> >   i965: Skip execution size adjustment for instructions of width 4
> > 
> > Samuel Iglesias Gonsálvez (4):
> >   i965/gs/gen6: fix execsize for instructions with width of 4 in
> > gen6_sol_program()

Here we have:

@@ -406,9 +406,11 @@ gen6_sol_program(struct brw_ff_gs_compile *c, struct 
brw_ff_gs_prog_key *key,
 : 0x00020001)); /* (1, 0, 2) */
  brw_inst_set_pred_control(p->devinfo, inst, BRW_PREDICATE_NORMAL);
   }
+  brw_push_insn_state(p);
+  brw_set_default_exec_size(p, BRW_EXECUTE_4);
   brw_ADD(p, c->reg.destination_indices,
   c->reg.destination_indices, get_element_ud(c->reg.SVBI, 0));

I was wondering if we could add an assertion (serves as documention also):

   assert(c->reg.destination_indices.width == BRW_EXECUTE_4);
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 18:31 +0200, Pohjolainen, Topi wrote:
> On Wed, Mar 09, 2016 at 11:16:41AM +0100, Iago Toral wrote:
> > On Wed, 2016-03-09 at 11:42 +0200, Pohjolainen, Topi wrote:
> > > On Wed, Mar 09, 2016 at 11:05:17AM +0200, Pohjolainen, Topi wrote:
> > > > On Wed, Mar 09, 2016 at 10:03:08AM +0100, Iago Toral wrote:
> > > > > On Wed, 2016-03-09 at 10:53 +0200, Pohjolainen, Topi wrote:
> > > > > > On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> > > > > > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > > > > > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias 
> > > > > > > > Gons?lvez wrote:
> > > > > > > > > Hello,
> > > > > > > > > 
> > > > > > > > > There is only one patch from this series that has been 
> > > > > > > > > reviewed (patch
> > > > > > > > > 1).
> > > > > > > > > 
> > > > > > > > > Our plans is to start sending patches for adding fp64 support 
> > > > > > > > > to i965
> > > > > > > > > driver in the coming weeks but they depend on these patches.
> > > > > > > > > 
> > > > > > > > > Can someone take a look at them? ;)
> > > > > > > > > 
> > > > > > > > > Sam
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez 
> > > > > > > > > wrote:
> > > > > > > > > > Hello,
> > > > > > > > > > 
> > > > > > > > > > This patch series is a updated version of the one Iago sent 
> > > > > > > > > > last
> > > > > > > > > > week [0] that includes patches for gen6 too, as suggested 
> > > > > > > > > > by Jason.
> > > > > > > > > > 
> > > > > > > > > > We checked the gen9 code paths that work with a horizontal 
> > > > > > > > > > width of 4
> > > > > > > > > > and we think there won't be any regression on gen9... but 
> > > > > > > > > > we don't
> > > > > > > > > > have any gen9 machine to run piglit with these patches. Can 
> > > > > > > > > > someone
> > > > > > > > > > check it?
> > > > > > > > 
> > > > > > > > I rebased it and ran it through the test system, gen9 seems to 
> > > > > > > > be fine, I
> > > > > > > > only got one regression, and that was on old g965:
> > > > > > > 
> > > > > > > Awesome! would it be possible to run that test in g695 with the 
> > > > > > > attached
> > > > > > > change? If this is a regression caused by our code it should 
> > > > > > > break at
> > > > > > > the assert introduced with it.
> > > > > > > 
> > > > > > > > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy
> > > > > > > >  all_samples srgb depthstencil -auto -fbo
> > > > > > > > Pixels that should be unlit
> > > > > > > >   count = 236444
> > > > > > > >   RMS error = 0.025355
> > > > > > > > Pixels that should be totally lit
> > > > > > > >   count = 13308
> > > > > > > >   Perfect output
> > > > > > > > The error threshold for unlit and totally lit pixels test is 
> > > > > > > > 0.016650
> > > > > > > > Pixels that should be partially lit
> > > > > > > >   count = 12392
> > > > > > > >   RMS error = 0.273876
> > > > > > > > The error threshold for partially lit pixels is 0.333000
> > > > > > > > Samples = 0, Result = fail
> > > > > > > > 
> > > > > > > > 
> > > > > > > > But I'm not sure if this is caused by your patches.
> > > > > > > > ___
> > > > > > > > mesa-dev mailing list
> > > > > > > > mesa-dev@lists.freedesktop.org
> > > > > > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > > > > > 
> > > > > > 
> > > > > > > diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> > > > > > > b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > > > index 6f11f59..625447f 100644
> > > > > > > --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > > > +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > > > @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst 
> > > > > > > *inst, struct brw_reg dest)
> > > > > > >  * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > > > > dealing with
> > > > > > >  * small registers, we automatically reduce it to match the 
> > > > > > > register size.
> > > > > > >  */
> > > > > > > +   assert(dest.width != BRW_EXECUTE_4 || 
> > > > > > > brw_inst_exec_size(devinfo, inst) == dest.width);
> > > > > > > if (dest.width < BRW_EXECUTE_8)
> > > > > > >brw_inst_set_exec_size(devinfo, inst, dest.width);
> > > > > > >  }
> > > > > > 
> > > > > > Hmm, on top of your series this looks:
> > > > > > 
> > > > > >/* Generators should set a default exec_size of either 8 
> > > > > > (SIMD4x2 or SIMD8)
> > > > > > * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > > > dealing with
> > > > > > * small registers, we automatically reduce it to match the 
> > > > > > register size.
> > > > > > *
> > > > > > * In platforms that support fp64 we can emit instructions with 
> > > > > > a width of
> > > > > > * 4 that need two SIMD8 registers and an exec_size of 8 or 16. 
> > > > > > In these
> > > > > > 

Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Wed, Mar 09, 2016 at 11:16:41AM +0100, Iago Toral wrote:
> On Wed, 2016-03-09 at 11:42 +0200, Pohjolainen, Topi wrote:
> > On Wed, Mar 09, 2016 at 11:05:17AM +0200, Pohjolainen, Topi wrote:
> > > On Wed, Mar 09, 2016 at 10:03:08AM +0100, Iago Toral wrote:
> > > > On Wed, 2016-03-09 at 10:53 +0200, Pohjolainen, Topi wrote:
> > > > > On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> > > > > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > > > > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias 
> > > > > > > Gons?lvez wrote:
> > > > > > > > Hello,
> > > > > > > > 
> > > > > > > > There is only one patch from this series that has been reviewed 
> > > > > > > > (patch
> > > > > > > > 1).
> > > > > > > > 
> > > > > > > > Our plans is to start sending patches for adding fp64 support 
> > > > > > > > to i965
> > > > > > > > driver in the coming weeks but they depend on these patches.
> > > > > > > > 
> > > > > > > > Can someone take a look at them? ;)
> > > > > > > > 
> > > > > > > > Sam
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez 
> > > > > > > > wrote:
> > > > > > > > > Hello,
> > > > > > > > > 
> > > > > > > > > This patch series is a updated version of the one Iago sent 
> > > > > > > > > last
> > > > > > > > > week [0] that includes patches for gen6 too, as suggested by 
> > > > > > > > > Jason.
> > > > > > > > > 
> > > > > > > > > We checked the gen9 code paths that work with a horizontal 
> > > > > > > > > width of 4
> > > > > > > > > and we think there won't be any regression on gen9... but we 
> > > > > > > > > don't
> > > > > > > > > have any gen9 machine to run piglit with these patches. Can 
> > > > > > > > > someone
> > > > > > > > > check it?
> > > > > > > 
> > > > > > > I rebased it and ran it through the test system, gen9 seems to be 
> > > > > > > fine, I
> > > > > > > only got one regression, and that was on old g965:
> > > > > > 
> > > > > > Awesome! would it be possible to run that test in g695 with the 
> > > > > > attached
> > > > > > change? If this is a regression caused by our code it should break 
> > > > > > at
> > > > > > the assert introduced with it.
> > > > > > 
> > > > > > > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy
> > > > > > >  all_samples srgb depthstencil -auto -fbo
> > > > > > > Pixels that should be unlit
> > > > > > >   count = 236444
> > > > > > >   RMS error = 0.025355
> > > > > > > Pixels that should be totally lit
> > > > > > >   count = 13308
> > > > > > >   Perfect output
> > > > > > > The error threshold for unlit and totally lit pixels test is 
> > > > > > > 0.016650
> > > > > > > Pixels that should be partially lit
> > > > > > >   count = 12392
> > > > > > >   RMS error = 0.273876
> > > > > > > The error threshold for partially lit pixels is 0.333000
> > > > > > > Samples = 0, Result = fail
> > > > > > > 
> > > > > > > 
> > > > > > > But I'm not sure if this is caused by your patches.
> > > > > > > ___
> > > > > > > mesa-dev mailing list
> > > > > > > mesa-dev@lists.freedesktop.org
> > > > > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > > > > 
> > > > > 
> > > > > > diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> > > > > > b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > > index 6f11f59..625447f 100644
> > > > > > --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > > +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > > @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst 
> > > > > > *inst, struct brw_reg dest)
> > > > > >  * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > > > dealing with
> > > > > >  * small registers, we automatically reduce it to match the 
> > > > > > register size.
> > > > > >  */
> > > > > > +   assert(dest.width != BRW_EXECUTE_4 || 
> > > > > > brw_inst_exec_size(devinfo, inst) == dest.width);
> > > > > > if (dest.width < BRW_EXECUTE_8)
> > > > > >brw_inst_set_exec_size(devinfo, inst, dest.width);
> > > > > >  }
> > > > > 
> > > > > Hmm, on top of your series this looks:
> > > > > 
> > > > >/* Generators should set a default exec_size of either 8 (SIMD4x2 
> > > > > or SIMD8)
> > > > > * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > > dealing with
> > > > > * small registers, we automatically reduce it to match the 
> > > > > register size.
> > > > > *
> > > > > * In platforms that support fp64 we can emit instructions with a 
> > > > > width of
> > > > > * 4 that need two SIMD8 registers and an exec_size of 8 or 16. In 
> > > > > these
> > > > > * cases we need to make sure that these instructions have their 
> > > > > exec sizes
> > > > > * set properly when they are emitted and we can't rely on this 
> > > > > code to fix
> > > > > * it.
> > > > > */
> > > > >bool fix_exec_size;
> > > > >if 

Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 11:42 +0200, Pohjolainen, Topi wrote:
> On Wed, Mar 09, 2016 at 11:05:17AM +0200, Pohjolainen, Topi wrote:
> > On Wed, Mar 09, 2016 at 10:03:08AM +0100, Iago Toral wrote:
> > > On Wed, 2016-03-09 at 10:53 +0200, Pohjolainen, Topi wrote:
> > > > On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> > > > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > > > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez 
> > > > > > wrote:
> > > > > > > Hello,
> > > > > > > 
> > > > > > > There is only one patch from this series that has been reviewed 
> > > > > > > (patch
> > > > > > > 1).
> > > > > > > 
> > > > > > > Our plans is to start sending patches for adding fp64 support to 
> > > > > > > i965
> > > > > > > driver in the coming weeks but they depend on these patches.
> > > > > > > 
> > > > > > > Can someone take a look at them? ;)
> > > > > > > 
> > > > > > > Sam
> > > > > > > 
> > > > > > > 
> > > > > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez 
> > > > > > > wrote:
> > > > > > > > Hello,
> > > > > > > > 
> > > > > > > > This patch series is a updated version of the one Iago sent last
> > > > > > > > week [0] that includes patches for gen6 too, as suggested by 
> > > > > > > > Jason.
> > > > > > > > 
> > > > > > > > We checked the gen9 code paths that work with a horizontal 
> > > > > > > > width of 4
> > > > > > > > and we think there won't be any regression on gen9... but we 
> > > > > > > > don't
> > > > > > > > have any gen9 machine to run piglit with these patches. Can 
> > > > > > > > someone
> > > > > > > > check it?
> > > > > > 
> > > > > > I rebased it and ran it through the test system, gen9 seems to be 
> > > > > > fine, I
> > > > > > only got one regression, and that was on old g965:
> > > > > 
> > > > > Awesome! would it be possible to run that test in g695 with the 
> > > > > attached
> > > > > change? If this is a regression caused by our code it should break at
> > > > > the assert introduced with it.
> > > > > 
> > > > > > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy
> > > > > >  all_samples srgb depthstencil -auto -fbo
> > > > > > Pixels that should be unlit
> > > > > >   count = 236444
> > > > > >   RMS error = 0.025355
> > > > > > Pixels that should be totally lit
> > > > > >   count = 13308
> > > > > >   Perfect output
> > > > > > The error threshold for unlit and totally lit pixels test is 
> > > > > > 0.016650
> > > > > > Pixels that should be partially lit
> > > > > >   count = 12392
> > > > > >   RMS error = 0.273876
> > > > > > The error threshold for partially lit pixels is 0.333000
> > > > > > Samples = 0, Result = fail
> > > > > > 
> > > > > > 
> > > > > > But I'm not sure if this is caused by your patches.
> > > > > > ___
> > > > > > mesa-dev mailing list
> > > > > > mesa-dev@lists.freedesktop.org
> > > > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > > > 
> > > > 
> > > > > diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> > > > > b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > index 6f11f59..625447f 100644
> > > > > --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > > @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst 
> > > > > *inst, struct brw_reg dest)
> > > > >  * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > > dealing with
> > > > >  * small registers, we automatically reduce it to match the 
> > > > > register size.
> > > > >  */
> > > > > +   assert(dest.width != BRW_EXECUTE_4 || brw_inst_exec_size(devinfo, 
> > > > > inst) == dest.width);
> > > > > if (dest.width < BRW_EXECUTE_8)
> > > > >brw_inst_set_exec_size(devinfo, inst, dest.width);
> > > > >  }
> > > > 
> > > > Hmm, on top of your series this looks:
> > > > 
> > > >/* Generators should set a default exec_size of either 8 (SIMD4x2 or 
> > > > SIMD8)
> > > > * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > dealing with
> > > > * small registers, we automatically reduce it to match the register 
> > > > size.
> > > > *
> > > > * In platforms that support fp64 we can emit instructions with a 
> > > > width of
> > > > * 4 that need two SIMD8 registers and an exec_size of 8 or 16. In 
> > > > these
> > > > * cases we need to make sure that these instructions have their 
> > > > exec sizes
> > > > * set properly when they are emitted and we can't rely on this code 
> > > > to fix
> > > > * it.
> > > > */
> > > >bool fix_exec_size;
> > > >if (devinfo->gen >= 6)
> > > >   fix_exec_size = dest.width < BRW_EXECUTE_4;
> > > >else
> > > >   fix_exec_size = dest.width < BRW_EXECUTE_8;
> > > > 
> > > >if (fix_exec_size)
> > > >   brw_inst_set_exec_size(devinfo, inst, dest.width);
> > > > 
> > > > Do you want the assertion before or after 

Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Wed, Mar 09, 2016 at 11:05:17AM +0200, Pohjolainen, Topi wrote:
> On Wed, Mar 09, 2016 at 10:03:08AM +0100, Iago Toral wrote:
> > On Wed, 2016-03-09 at 10:53 +0200, Pohjolainen, Topi wrote:
> > > On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> > > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez 
> > > > > wrote:
> > > > > > Hello,
> > > > > > 
> > > > > > There is only one patch from this series that has been reviewed 
> > > > > > (patch
> > > > > > 1).
> > > > > > 
> > > > > > Our plans is to start sending patches for adding fp64 support to 
> > > > > > i965
> > > > > > driver in the coming weeks but they depend on these patches.
> > > > > > 
> > > > > > Can someone take a look at them? ;)
> > > > > > 
> > > > > > Sam
> > > > > > 
> > > > > > 
> > > > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > > > > Hello,
> > > > > > > 
> > > > > > > This patch series is a updated version of the one Iago sent last
> > > > > > > week [0] that includes patches for gen6 too, as suggested by 
> > > > > > > Jason.
> > > > > > > 
> > > > > > > We checked the gen9 code paths that work with a horizontal width 
> > > > > > > of 4
> > > > > > > and we think there won't be any regression on gen9... but we don't
> > > > > > > have any gen9 machine to run piglit with these patches. Can 
> > > > > > > someone
> > > > > > > check it?
> > > > > 
> > > > > I rebased it and ran it through the test system, gen9 seems to be 
> > > > > fine, I
> > > > > only got one regression, and that was on old g965:
> > > > 
> > > > Awesome! would it be possible to run that test in g695 with the attached
> > > > change? If this is a regression caused by our code it should break at
> > > > the assert introduced with it.
> > > > 
> > > > > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy
> > > > >  all_samples srgb depthstencil -auto -fbo
> > > > > Pixels that should be unlit
> > > > >   count = 236444
> > > > >   RMS error = 0.025355
> > > > > Pixels that should be totally lit
> > > > >   count = 13308
> > > > >   Perfect output
> > > > > The error threshold for unlit and totally lit pixels test is 0.016650
> > > > > Pixels that should be partially lit
> > > > >   count = 12392
> > > > >   RMS error = 0.273876
> > > > > The error threshold for partially lit pixels is 0.333000
> > > > > Samples = 0, Result = fail
> > > > > 
> > > > > 
> > > > > But I'm not sure if this is caused by your patches.
> > > > > ___
> > > > > mesa-dev mailing list
> > > > > mesa-dev@lists.freedesktop.org
> > > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > > 
> > > 
> > > > diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> > > > b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > index 6f11f59..625447f 100644
> > > > --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > > @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, 
> > > > struct brw_reg dest)
> > > >  * or 16 (SIMD16), as that's normally correct.  However, when 
> > > > dealing with
> > > >  * small registers, we automatically reduce it to match the 
> > > > register size.
> > > >  */
> > > > +   assert(dest.width != BRW_EXECUTE_4 || brw_inst_exec_size(devinfo, 
> > > > inst) == dest.width);
> > > > if (dest.width < BRW_EXECUTE_8)
> > > >brw_inst_set_exec_size(devinfo, inst, dest.width);
> > > >  }
> > > 
> > > Hmm, on top of your series this looks:
> > > 
> > >/* Generators should set a default exec_size of either 8 (SIMD4x2 or 
> > > SIMD8)
> > > * or 16 (SIMD16), as that's normally correct.  However, when dealing 
> > > with
> > > * small registers, we automatically reduce it to match the register 
> > > size.
> > > *
> > > * In platforms that support fp64 we can emit instructions with a 
> > > width of
> > > * 4 that need two SIMD8 registers and an exec_size of 8 or 16. In 
> > > these
> > > * cases we need to make sure that these instructions have their exec 
> > > sizes
> > > * set properly when they are emitted and we can't rely on this code 
> > > to fix
> > > * it.
> > > */
> > >bool fix_exec_size;
> > >if (devinfo->gen >= 6)
> > >   fix_exec_size = dest.width < BRW_EXECUTE_4;
> > >else
> > >   fix_exec_size = dest.width < BRW_EXECUTE_8;
> > > 
> > >if (fix_exec_size)
> > >   brw_inst_set_exec_size(devinfo, inst, dest.width);
> > > 
> > > Do you want the assertion before or after fixing?
> > > 
> > 
> > Before, you can put it right after that comment. Thanks!
> 
> That is what I thought. Hold on, I'll give it a spin.

Okay, now the system got really mad, I have some 12000 regressions on
g45, ilk and g965.

And for the test discussed above we hit the assert:

Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 09:32 +0200, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > Hello,
> > 
> > There is only one patch from this series that has been reviewed (patch
> > 1).
> > 
> > Our plans is to start sending patches for adding fp64 support to i965
> > driver in the coming weeks but they depend on these patches.
> > 
> > Can someone take a look at them? ;)
> > 
> > Sam
> > 
> > 
> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > Hello,
> > > 
> > > This patch series is a updated version of the one Iago sent last
> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > 
> > > We checked the gen9 code paths that work with a horizontal width of 4
> > > and we think there won't be any regression on gen9... but we don't
> > > have any gen9 machine to run piglit with these patches. Can someone
> > > check it?
> > > 
> > > Please read the original cover letter [0] for more information.
> > > 
> > > Sam
> > > 
> > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > > 46.html
> > > 
> > > Iago Toral Quiroga (5):
> > >   i965/eu: set correct execution size in brw_NOP
> > >   i965/fs: set execution size for SEND messages in
> > > generate_uniform_pull_constant_load_gen7
> 
> Then about the other change. I like it being explicitly set instead of just
> inheriting the size from the previous instruction.

I'll do that, thanks!

> @@ -1248,6 +1248,7 @@ 
> fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
>brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
> +  brw_inst_set_exec_size(devinfo, send, dst.width);
> 
> But I'm seeing other occurrences of BRW_OPCODE_SEND as well. For example, 
> there
> are such instructions generated in generate_urb_read/write() which are not 
> addressed. Don't we end up there with doubles as well needing the same
> treatment?
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 09:24 +0100, Iago Toral wrote:
> On Wed, 2016-03-09 at 09:26 +0200, Pohjolainen, Topi wrote:
> > On Wed, Mar 09, 2016 at 09:07:44AM +0200, Pohjolainen, Topi wrote:
> > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > > > Hello,
> > > > 
> > > > There is only one patch from this series that has been reviewed (patch
> > > > 1).
> > > > 
> > > > Our plans is to start sending patches for adding fp64 support to i965
> > > > driver in the coming weeks but they depend on these patches.
> > > > 
> > > > Can someone take a look at them? ;)
> > > > 
> > > > Sam
> > > > 
> > > > 
> > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > > Hello,
> > > > > 
> > > > > This patch series is a updated version of the one Iago sent last
> > > > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > > > 
> > > > > We checked the gen9 code paths that work with a horizontal width of 4
> > > > > and we think there won't be any regression on gen9... but we don't
> > > > > have any gen9 machine to run piglit with these patches. Can someone
> > > > > check it?
> > > > > 
> > > > > Please read the original cover letter [0] for more information.
> > > > > 
> > > > > Sam
> > > > > 
> > > > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > > > > 46.html
> > > > > 
> > > > > Iago Toral Quiroga (5):
> > > > >   i965/eu: set correct execution size in brw_NOP
> > > > >   i965/fs: set execution size for SEND messages in
> > > > > generate_uniform_pull_constant_load_gen7
> > > 
> > > I don't have the series in my mailbox anymore, so I'll comment here. 
> > > There is:
> > > 
> > >brw_set_dest(p, send, dst);
> > > @@ -1279,6 +1280,7 @@ 
> > > fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
> > >/* dst = send(payload, a0.0 | ) */
> > >brw_inst *insn = brw_send_indirect_message(
> > >   p, BRW_SFID_SAMPLER, dst, src, addr);
> > > +  brw_inst_set_exec_size(devinfo, insn, dst.width);
> > > 
> > > I wonder if we should modify brw_send_indirect_message() instead? It 
> > > already
> > > calls brw_inst_set_exec_size() itself:
> > > 
> > >if (dst.width < BRW_EXECUTE_8)
> > >   brw_inst_set_exec_size(devinfo, send, dst.width);
> > 
> > Actually you set this yourself in the next patch of the series. Is the
> > previous in the caller side really needed after this?
> 
> Good catch! I'll give it a quick test through piglit with the assertion
> I mentioned in my previous reply to see if we can drop this hunk, that's
> the only way to be certain :)

Piglit seems to be happy dropping this hunk on IVB, so I think it is a
safe change.

Iago

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Wed, Mar 09, 2016 at 10:03:08AM +0100, Iago Toral wrote:
> On Wed, 2016-03-09 at 10:53 +0200, Pohjolainen, Topi wrote:
> > On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> > > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez 
> > > > wrote:
> > > > > Hello,
> > > > > 
> > > > > There is only one patch from this series that has been reviewed (patch
> > > > > 1).
> > > > > 
> > > > > Our plans is to start sending patches for adding fp64 support to i965
> > > > > driver in the coming weeks but they depend on these patches.
> > > > > 
> > > > > Can someone take a look at them? ;)
> > > > > 
> > > > > Sam
> > > > > 
> > > > > 
> > > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > > > Hello,
> > > > > > 
> > > > > > This patch series is a updated version of the one Iago sent last
> > > > > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > > > > 
> > > > > > We checked the gen9 code paths that work with a horizontal width of 
> > > > > > 4
> > > > > > and we think there won't be any regression on gen9... but we don't
> > > > > > have any gen9 machine to run piglit with these patches. Can someone
> > > > > > check it?
> > > > 
> > > > I rebased it and ran it through the test system, gen9 seems to be fine, 
> > > > I
> > > > only got one regression, and that was on old g965:
> > > 
> > > Awesome! would it be possible to run that test in g695 with the attached
> > > change? If this is a regression caused by our code it should break at
> > > the assert introduced with it.
> > > 
> > > > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> > > > all_samples srgb depthstencil -auto -fbo
> > > > Pixels that should be unlit
> > > >   count = 236444
> > > >   RMS error = 0.025355
> > > > Pixels that should be totally lit
> > > >   count = 13308
> > > >   Perfect output
> > > > The error threshold for unlit and totally lit pixels test is 0.016650
> > > > Pixels that should be partially lit
> > > >   count = 12392
> > > >   RMS error = 0.273876
> > > > The error threshold for partially lit pixels is 0.333000
> > > > Samples = 0, Result = fail
> > > > 
> > > > 
> > > > But I'm not sure if this is caused by your patches.
> > > > ___
> > > > mesa-dev mailing list
> > > > mesa-dev@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > 
> > 
> > > diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> > > b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > index 6f11f59..625447f 100644
> > > --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > > @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, 
> > > struct brw_reg dest)
> > >  * or 16 (SIMD16), as that's normally correct.  However, when dealing 
> > > with
> > >  * small registers, we automatically reduce it to match the register 
> > > size.
> > >  */
> > > +   assert(dest.width != BRW_EXECUTE_4 || brw_inst_exec_size(devinfo, 
> > > inst) == dest.width);
> > > if (dest.width < BRW_EXECUTE_8)
> > >brw_inst_set_exec_size(devinfo, inst, dest.width);
> > >  }
> > 
> > Hmm, on top of your series this looks:
> > 
> >/* Generators should set a default exec_size of either 8 (SIMD4x2 or 
> > SIMD8)
> > * or 16 (SIMD16), as that's normally correct.  However, when dealing 
> > with
> > * small registers, we automatically reduce it to match the register 
> > size.
> > *
> > * In platforms that support fp64 we can emit instructions with a width 
> > of
> > * 4 that need two SIMD8 registers and an exec_size of 8 or 16. In these
> > * cases we need to make sure that these instructions have their exec 
> > sizes
> > * set properly when they are emitted and we can't rely on this code to 
> > fix
> > * it.
> > */
> >bool fix_exec_size;
> >if (devinfo->gen >= 6)
> >   fix_exec_size = dest.width < BRW_EXECUTE_4;
> >else
> >   fix_exec_size = dest.width < BRW_EXECUTE_8;
> > 
> >if (fix_exec_size)
> >   brw_inst_set_exec_size(devinfo, inst, dest.width);
> > 
> > Do you want the assertion before or after fixing?
> > 
> 
> Before, you can put it right after that comment. Thanks!

That is what I thought. Hold on, I'll give it a spin.
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 10:53 +0200, Pohjolainen, Topi wrote:
> On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> > On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > > > Hello,
> > > > 
> > > > There is only one patch from this series that has been reviewed (patch
> > > > 1).
> > > > 
> > > > Our plans is to start sending patches for adding fp64 support to i965
> > > > driver in the coming weeks but they depend on these patches.
> > > > 
> > > > Can someone take a look at them? ;)
> > > > 
> > > > Sam
> > > > 
> > > > 
> > > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > > Hello,
> > > > > 
> > > > > This patch series is a updated version of the one Iago sent last
> > > > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > > > 
> > > > > We checked the gen9 code paths that work with a horizontal width of 4
> > > > > and we think there won't be any regression on gen9... but we don't
> > > > > have any gen9 machine to run piglit with these patches. Can someone
> > > > > check it?
> > > 
> > > I rebased it and ran it through the test system, gen9 seems to be fine, I
> > > only got one regression, and that was on old g965:
> > 
> > Awesome! would it be possible to run that test in g695 with the attached
> > change? If this is a regression caused by our code it should break at
> > the assert introduced with it.
> > 
> > > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> > > all_samples srgb depthstencil -auto -fbo
> > > Pixels that should be unlit
> > >   count = 236444
> > >   RMS error = 0.025355
> > > Pixels that should be totally lit
> > >   count = 13308
> > >   Perfect output
> > > The error threshold for unlit and totally lit pixels test is 0.016650
> > > Pixels that should be partially lit
> > >   count = 12392
> > >   RMS error = 0.273876
> > > The error threshold for partially lit pixels is 0.333000
> > > Samples = 0, Result = fail
> > > 
> > > 
> > > But I'm not sure if this is caused by your patches.
> > > ___
> > > mesa-dev mailing list
> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 
> 
> > diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> > b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > index 6f11f59..625447f 100644
> > --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> > @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, 
> > struct brw_reg dest)
> >  * or 16 (SIMD16), as that's normally correct.  However, when dealing 
> > with
> >  * small registers, we automatically reduce it to match the register 
> > size.
> >  */
> > +   assert(dest.width != BRW_EXECUTE_4 || brw_inst_exec_size(devinfo, inst) 
> > == dest.width);
> > if (dest.width < BRW_EXECUTE_8)
> >brw_inst_set_exec_size(devinfo, inst, dest.width);
> >  }
> 
> Hmm, on top of your series this looks:
> 
>/* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
> * or 16 (SIMD16), as that's normally correct.  However, when dealing with
> * small registers, we automatically reduce it to match the register size.
> *
> * In platforms that support fp64 we can emit instructions with a width of
> * 4 that need two SIMD8 registers and an exec_size of 8 or 16. In these
> * cases we need to make sure that these instructions have their exec sizes
> * set properly when they are emitted and we can't rely on this code to fix
> * it.
> */
>bool fix_exec_size;
>if (devinfo->gen >= 6)
>   fix_exec_size = dest.width < BRW_EXECUTE_4;
>else
>   fix_exec_size = dest.width < BRW_EXECUTE_8;
> 
>if (fix_exec_size)
>   brw_inst_set_exec_size(devinfo, inst, dest.width);
> 
> Do you want the assertion before or after fixing?
> 

Before, you can put it right after that comment. Thanks!

Iago

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Wed, Mar 09, 2016 at 09:36:42AM +0100, Iago Toral wrote:
> On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > > Hello,
> > > 
> > > There is only one patch from this series that has been reviewed (patch
> > > 1).
> > > 
> > > Our plans is to start sending patches for adding fp64 support to i965
> > > driver in the coming weeks but they depend on these patches.
> > > 
> > > Can someone take a look at them? ;)
> > > 
> > > Sam
> > > 
> > > 
> > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > Hello,
> > > > 
> > > > This patch series is a updated version of the one Iago sent last
> > > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > > 
> > > > We checked the gen9 code paths that work with a horizontal width of 4
> > > > and we think there won't be any regression on gen9... but we don't
> > > > have any gen9 machine to run piglit with these patches. Can someone
> > > > check it?
> > 
> > I rebased it and ran it through the test system, gen9 seems to be fine, I
> > only got one regression, and that was on old g965:
> 
> Awesome! would it be possible to run that test in g695 with the attached
> change? If this is a regression caused by our code it should break at
> the assert introduced with it.
> 
> > /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> > all_samples srgb depthstencil -auto -fbo
> > Pixels that should be unlit
> >   count = 236444
> >   RMS error = 0.025355
> > Pixels that should be totally lit
> >   count = 13308
> >   Perfect output
> > The error threshold for unlit and totally lit pixels test is 0.016650
> > Pixels that should be partially lit
> >   count = 12392
> >   RMS error = 0.273876
> > The error threshold for partially lit pixels is 0.333000
> > Samples = 0, Result = fail
> > 
> > 
> > But I'm not sure if this is caused by your patches.
> > ___
> > mesa-dev mailing list
> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 

> diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
> b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> index 6f11f59..625447f 100644
> --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
> +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
> @@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, 
> struct brw_reg dest)
>  * or 16 (SIMD16), as that's normally correct.  However, when dealing with
>  * small registers, we automatically reduce it to match the register size.
>  */
> +   assert(dest.width != BRW_EXECUTE_4 || brw_inst_exec_size(devinfo, inst) 
> == dest.width);
> if (dest.width < BRW_EXECUTE_8)
>brw_inst_set_exec_size(devinfo, inst, dest.width);
>  }

Hmm, on top of your series this looks:

   /* Generators should set a default exec_size of either 8 (SIMD4x2 or SIMD8)
* or 16 (SIMD16), as that's normally correct.  However, when dealing with
* small registers, we automatically reduce it to match the register size.
*
* In platforms that support fp64 we can emit instructions with a width of
* 4 that need two SIMD8 registers and an exec_size of 8 or 16. In these
* cases we need to make sure that these instructions have their exec sizes
* set properly when they are emitted and we can't rely on this code to fix
* it.
*/
   bool fix_exec_size;
   if (devinfo->gen >= 6)
  fix_exec_size = dest.width < BRW_EXECUTE_4;
   else
  fix_exec_size = dest.width < BRW_EXECUTE_8;

   if (fix_exec_size)
  brw_inst_set_exec_size(devinfo, inst, dest.width);

Do you want the assertion before or after fixing?
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 09:54 +0200, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > Hello,
> > 
> > There is only one patch from this series that has been reviewed (patch
> > 1).
> > 
> > Our plans is to start sending patches for adding fp64 support to i965
> > driver in the coming weeks but they depend on these patches.
> > 
> > Can someone take a look at them? ;)
> > 
> > Sam
> > 
> > 
> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > Hello,
> > > 
> > > This patch series is a updated version of the one Iago sent last
> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > 
> > > We checked the gen9 code paths that work with a horizontal width of 4
> > > and we think there won't be any regression on gen9... but we don't
> > > have any gen9 machine to run piglit with these patches. Can someone
> > > check it?
> 
> I rebased it and ran it through the test system, gen9 seems to be fine, I
> only got one regression, and that was on old g965:

Awesome! would it be possible to run that test in g695 with the attached
change? If this is a regression caused by our code it should break at
the assert introduced with it.

> /tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
> all_samples srgb depthstencil -auto -fbo
> Pixels that should be unlit
>   count = 236444
>   RMS error = 0.025355
> Pixels that should be totally lit
>   count = 13308
>   Perfect output
> The error threshold for unlit and totally lit pixels test is 0.016650
> Pixels that should be partially lit
>   count = 12392
>   RMS error = 0.273876
> The error threshold for partially lit pixels is 0.333000
> Samples = 0, Result = fail
> 
> 
> But I'm not sure if this is caused by your patches.
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diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 6f11f59..625447f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -203,6 +203,7 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest)
 * or 16 (SIMD16), as that's normally correct.  However, when dealing with
 * small registers, we automatically reduce it to match the register size.
 */
+   assert(dest.width != BRW_EXECUTE_4 || brw_inst_exec_size(devinfo, inst) == dest.width);
if (dest.width < BRW_EXECUTE_8)
   brw_inst_set_exec_size(devinfo, inst, dest.width);
 }
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 09:26 +0200, Pohjolainen, Topi wrote:
> On Wed, Mar 09, 2016 at 09:07:44AM +0200, Pohjolainen, Topi wrote:
> > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > > Hello,
> > > 
> > > There is only one patch from this series that has been reviewed (patch
> > > 1).
> > > 
> > > Our plans is to start sending patches for adding fp64 support to i965
> > > driver in the coming weeks but they depend on these patches.
> > > 
> > > Can someone take a look at them? ;)
> > > 
> > > Sam
> > > 
> > > 
> > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > > Hello,
> > > > 
> > > > This patch series is a updated version of the one Iago sent last
> > > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > > 
> > > > We checked the gen9 code paths that work with a horizontal width of 4
> > > > and we think there won't be any regression on gen9... but we don't
> > > > have any gen9 machine to run piglit with these patches. Can someone
> > > > check it?
> > > > 
> > > > Please read the original cover letter [0] for more information.
> > > > 
> > > > Sam
> > > > 
> > > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > > > 46.html
> > > > 
> > > > Iago Toral Quiroga (5):
> > > >   i965/eu: set correct execution size in brw_NOP
> > > >   i965/fs: set execution size for SEND messages in
> > > > generate_uniform_pull_constant_load_gen7
> > 
> > I don't have the series in my mailbox anymore, so I'll comment here. There 
> > is:
> > 
> >brw_set_dest(p, send, dst);
> > @@ -1279,6 +1280,7 @@ 
> > fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
> >/* dst = send(payload, a0.0 | ) */
> >brw_inst *insn = brw_send_indirect_message(
> >   p, BRW_SFID_SAMPLER, dst, src, addr);
> > +  brw_inst_set_exec_size(devinfo, insn, dst.width);
> > 
> > I wonder if we should modify brw_send_indirect_message() instead? It already
> > calls brw_inst_set_exec_size() itself:
> > 
> >if (dst.width < BRW_EXECUTE_8)
> >   brw_inst_set_exec_size(devinfo, send, dst.width);
> 
> Actually you set this yourself in the next patch of the series. Is the
> previous in the caller side really needed after this?

Good catch! I'll give it a quick test through piglit with the assertion
I mentioned in my previous reply to see if we can drop this hunk, that's
the only way to be certain :)

Iago

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Iago Toral]

On Wed, 2016-03-09 at 09:32 +0200, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > Hello,
> > 
> > There is only one patch from this series that has been reviewed (patch
> > 1).
> > 
> > Our plans is to start sending patches for adding fp64 support to i965
> > driver in the coming weeks but they depend on these patches.
> > 
> > Can someone take a look at them? ;)
> > 
> > Sam
> > 
> > 
> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > Hello,
> > > 
> > > This patch series is a updated version of the one Iago sent last
> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > 
> > > We checked the gen9 code paths that work with a horizontal width of 4
> > > and we think there won't be any regression on gen9... but we don't
> > > have any gen9 machine to run piglit with these patches. Can someone
> > > check it?
> > > 
> > > Please read the original cover letter [0] for more information.
> > > 
> > > Sam
> > > 
> > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > > 46.html
> > > 
> > > Iago Toral Quiroga (5):
> > >   i965/eu: set correct execution size in brw_NOP
> > >   i965/fs: set execution size for SEND messages in
> > > generate_uniform_pull_constant_load_gen7
> 
> Then about the other change. I like it being explicitly set instead of just
> inheriting the size from the previous instruction.
> 
> @@ -1248,6 +1248,7 @@ 
> fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
>brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
>brw_set_default_mask_control(p, BRW_MASK_DISABLE);
>brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
> +  brw_inst_set_exec_size(devinfo, send, dst.width);
> 
> But I'm seeing other occurrences of BRW_OPCODE_SEND as well. For example, 
> there
> are such instructions generated in generate_urb_read/write() which are not 
> addressed. Don't we end up there with doubles as well needing the same
> treatment?

Probably those other SENDs always operate with a width of 8/16 (the
default) and don't need to be fixed for other cases because they don't
happen. Notice that we are only trying to fix the cases of width = 4
here, which are the conflicting ones, so if some paths never execute
instructions with a width of 4 we don't need to do anything about them.

What we have done to identify the cases that need fixing was adding this
assertion in brw_set_dest (brw_eu_emit.c):

   assert(dest.width != BRW_EXECUTE_4 ||
  brw_inst_exec_size(devinfo, inst) == dest.width);

That catches any instruction with a width of 4 (the ones that need
fixing) that does not have the correct execsize set. We ran this through
piglit and dEQP functional's tests for all the generations we mentioned
and fixed the cases that broke this assertion one by one.

Iago

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> Hello,
> 
> There is only one patch from this series that has been reviewed (patch
> 1).
> 
> Our plans is to start sending patches for adding fp64 support to i965
> driver in the coming weeks but they depend on these patches.
> 
> Can someone take a look at them? ;)
> 
> Sam
> 
> 
> On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > Hello,
> > 
> > This patch series is a updated version of the one Iago sent last
> > week [0] that includes patches for gen6 too, as suggested by Jason.
> > 
> > We checked the gen9 code paths that work with a horizontal width of 4
> > and we think there won't be any regression on gen9... but we don't
> > have any gen9 machine to run piglit with these patches. Can someone
> > check it?

I rebased it and ran it through the test system, gen9 seems to be fine, I
only got one regression, and that was on old g965:

/tmp/build_root/m64/lib/piglit/bin/ext_framebuffer_multisample-accuracy 
all_samples srgb depthstencil -auto -fbo
Pixels that should be unlit
  count = 236444
  RMS error = 0.025355
Pixels that should be totally lit
  count = 13308
  Perfect output
The error threshold for unlit and totally lit pixels test is 0.016650
Pixels that should be partially lit
  count = 12392
  RMS error = 0.273876
The error threshold for partially lit pixels is 0.333000
Samples = 0, Result = fail


But I'm not sure if this is caused by your patches.
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> Hello,
> 
> There is only one patch from this series that has been reviewed (patch
> 1).
> 
> Our plans is to start sending patches for adding fp64 support to i965
> driver in the coming weeks but they depend on these patches.
> 
> Can someone take a look at them? ;)
> 
> Sam
> 
> 
> On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > Hello,
> > 
> > This patch series is a updated version of the one Iago sent last
> > week [0] that includes patches for gen6 too, as suggested by Jason.
> > 
> > We checked the gen9 code paths that work with a horizontal width of 4
> > and we think there won't be any regression on gen9... but we don't
> > have any gen9 machine to run piglit with these patches. Can someone
> > check it?
> > 
> > Please read the original cover letter [0] for more information.
> > 
> > Sam
> > 
> > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > 46.html
> > 
> > Iago Toral Quiroga (5):
> >   i965/eu: set correct execution size in brw_NOP
> >   i965/fs: set execution size for SEND messages in
> > generate_uniform_pull_constant_load_gen7

Then about the other change. I like it being explicitly set instead of just
inheriting the size from the previous instruction.

@@ -1248,6 +1248,7 @@ 
fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
   brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
   brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_inst_set_exec_size(devinfo, send, dst.width);

But I'm seeing other occurrences of BRW_OPCODE_SEND as well. For example, there
are such instructions generated in generate_urb_read/write() which are not 
addressed. Don't we end up there with doubles as well needing the same
treatment?
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Wed, Mar 09, 2016 at 09:07:44AM +0200, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> > Hello,
> > 
> > There is only one patch from this series that has been reviewed (patch
> > 1).
> > 
> > Our plans is to start sending patches for adding fp64 support to i965
> > driver in the coming weeks but they depend on these patches.
> > 
> > Can someone take a look at them? ;)
> > 
> > Sam
> > 
> > 
> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > Hello,
> > > 
> > > This patch series is a updated version of the one Iago sent last
> > > week [0] that includes patches for gen6 too, as suggested by Jason.
> > > 
> > > We checked the gen9 code paths that work with a horizontal width of 4
> > > and we think there won't be any regression on gen9... but we don't
> > > have any gen9 machine to run piglit with these patches. Can someone
> > > check it?
> > > 
> > > Please read the original cover letter [0] for more information.
> > > 
> > > Sam
> > > 
> > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > > 46.html
> > > 
> > > Iago Toral Quiroga (5):
> > >   i965/eu: set correct execution size in brw_NOP
> > >   i965/fs: set execution size for SEND messages in
> > > generate_uniform_pull_constant_load_gen7
> 
> I don't have the series in my mailbox anymore, so I'll comment here. There is:
> 
>brw_set_dest(p, send, dst);
> @@ -1279,6 +1280,7 @@ 
> fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
>/* dst = send(payload, a0.0 | ) */
>brw_inst *insn = brw_send_indirect_message(
>   p, BRW_SFID_SAMPLER, dst, src, addr);
> +  brw_inst_set_exec_size(devinfo, insn, dst.width);
> 
> I wonder if we should modify brw_send_indirect_message() instead? It already
> calls brw_inst_set_exec_size() itself:
> 
>if (dst.width < BRW_EXECUTE_8)
>   brw_inst_set_exec_size(devinfo, send, dst.width);

Actually you set this yourself in the next patch of the series. Is the
previous in the caller side really needed after this?
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> Hello,
> 
> There is only one patch from this series that has been reviewed (patch
> 1).
> 
> Our plans is to start sending patches for adding fp64 support to i965
> driver in the coming weeks but they depend on these patches.
> 
> Can someone take a look at them? ;)
> 
> Sam
> 
> 
> On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > Hello,
> > 
> > This patch series is a updated version of the one Iago sent last
> > week [0] that includes patches for gen6 too, as suggested by Jason.
> > 
> > We checked the gen9 code paths that work with a horizontal width of 4
> > and we think there won't be any regression on gen9... but we don't
> > have any gen9 machine to run piglit with these patches. Can someone
> > check it?
> > 
> > Please read the original cover letter [0] for more information.
> > 
> > Sam
> > 
> > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > 46.html
> > 
> > Iago Toral Quiroga (5):
> >   i965/eu: set correct execution size in brw_NOP
> >   i965/fs: set execution size for SEND messages in
> > generate_uniform_pull_constant_load_gen7

I don't have the series in my mailbox anymore, so I'll comment here. There is:

   brw_set_dest(p, send, dst);
@@ -1279,6 +1280,7 @@ 
fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
   /* dst = send(payload, a0.0 | ) */
   brw_inst *insn = brw_send_indirect_message(
  p, BRW_SFID_SAMPLER, dst, src, addr);
+  brw_inst_set_exec_size(devinfo, insn, dst.width);

I wonder if we should modify brw_send_indirect_message() instead? It already
calls brw_inst_set_exec_size() itself:

   if (dst.width < BRW_EXECUTE_8)
  brw_inst_set_exec_size(devinfo, send, dst.width);

This would then also serve generate_varying_pull_constant_load_gen7() later on
when we add support for double varyings, right? (It has similar logic
involving brw_send_indirect_message()).


In general, currently we set execution width both in brw_fs_generator.cpp
and in brw_eu_emit.c. I wonder if we should isolate it more. This is me
just thinking aloud for now. I studied this bit some time ago but can't
remember all the details...
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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Samuel Iglesias Gonsálvez]

On Mon, 2016-03-07 at 15:12 +0100, Samuel Iglesias Gonsálvez wrote:
> On Mon, 2016-03-07 at 16:03 +0200, Pohjolainen, Topi wrote:
> > On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez
> > wrote:
> > > Hello,
> > > 
> > > There is only one patch from this series that has been reviewed
> > > (patch
> > > 1).
> > > 
> > > Our plans is to start sending patches for adding fp64 support to
> > > i965
> > > driver in the coming weeks but they depend on these patches.
> > > 
> > > Can someone take a look at them? ;)
> > 
> > I'm interested, although we may need to involve also other people
> > in
> > the end.
> > Do you have a branch somewhere I could clone?
> > 
> 
> Yes, we have this one:
> 
> https://github.com/Igalia/mesa/commits/i965-fix-execsize
> 
> To clone it:
> 
> $ git clone -b i965-fix-execsize g...@github.com:Igalia/mesa.git
> 

Sorry, I have just realized that this command is going to give you
access rights problems, this is the proper one:

$ git clone -b i965-fix-execsize https://github.com/Igalia/mesa.git


> Thanks,
> 
> Sam
> 
> > > 
> > > Sam
> > > 
> > > 
> > > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez
> > > wrote:
> > > > Hello,
> > > > 
> > > > This patch series is a updated version of the one Iago sent
> > > > last
> > > > week [0] that includes patches for gen6 too, as suggested by
> > > > Jason.
> > > > 
> > > > We checked the gen9 code paths that work with a horizontal
> > > > width
> > > > of 4
> > > > and we think there won't be any regression on gen9... but we
> > > > don't
> > > > have any gen9 machine to run piglit with these patches. Can
> > > > someone
> > > > check it?
> > > > 
> > > > Please read the original cover letter [0] for more information.
> > > > 
> > > > Sam
> > > > 
> > > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-Decembe
> > > > r/
> > > > 1027
> > > > 46.html
> > > > 
> > > > Iago Toral Quiroga (5):
> > > >   i965/eu: set correct execution size in brw_NOP
> > > >   i965/fs: set execution size for SEND messages in
> > > > generate_uniform_pull_constant_load_gen7
> > > >   i965/eu: set execution size for SEND message in
> > > > brw_send_indirect_message
> > > >   i965: set correct execsize for MOVS with a width of 4 in
> > > > brw_find_live_channel
> > > >   i965: Skip execution size adjustment for instructions of
> > > > width
> > > > 4
> > > > 
> > > > Samuel Iglesias Gonsálvez (4):
> > > >   i965/gs/gen6: fix execsize for instructions with width of 4
> > > > in
> > > > gen6_sol_program()
> > > >   i965/vec4/gen6: fix exec_size for instructions with width of
> > > > 4
> > > > in
> > > > generate_gs_svb_write()
> > > >   i965/vec4/gen6: fix exec_size for instructions with
> > > > destination
> > > > width
> > > > of 4
> > > >   i965/vec4/gen6: fix exec_size for MOV with a width of 4 in
> > > > generate_gs_ff_sync()
> > > > 
> > > >  src/mesa/drivers/dri/i965/brw_eu_emit.c  | 25
> > > > +---
> > > >  src/mesa/drivers/dri/i965/brw_ff_gs_emit.c   |  9
> > > > -
> > > >  src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |  2 ++
> > > >  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13
> > > > +++-
> > > >  4 files changed, 44 insertions(+), 5 deletions(-)
> > > > 
> > 
> > 
> > 
> > > ___
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> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > 

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Samuel Iglesias Gonsálvez]

On Mon, 2016-03-07 at 16:03 +0200, Pohjolainen, Topi wrote:
> On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez
> wrote:
> > Hello,
> > 
> > There is only one patch from this series that has been reviewed
> > (patch
> > 1).
> > 
> > Our plans is to start sending patches for adding fp64 support to
> > i965
> > driver in the coming weeks but they depend on these patches.
> > 
> > Can someone take a look at them? ;)
> 
> I'm interested, although we may need to involve also other people in
> the end.
> Do you have a branch somewhere I could clone?
> 

Yes, we have this one:

https://github.com/Igalia/mesa/commits/i965-fix-execsize

To clone it:

$ git clone -b i965-fix-execsize g...@github.com:Igalia/mesa.git

Thanks,

Sam

> > 
> > Sam
> > 
> > 
> > On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > > Hello,
> > > 
> > > This patch series is a updated version of the one Iago sent last
> > > week [0] that includes patches for gen6 too, as suggested by
> > > Jason.
> > > 
> > > We checked the gen9 code paths that work with a horizontal width
> > > of 4
> > > and we think there won't be any regression on gen9... but we
> > > don't
> > > have any gen9 machine to run piglit with these patches. Can
> > > someone
> > > check it?
> > > 
> > > Please read the original cover letter [0] for more information.
> > > 
> > > Sam
> > > 
> > > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/
> > > 1027
> > > 46.html
> > > 
> > > Iago Toral Quiroga (5):
> > >   i965/eu: set correct execution size in brw_NOP
> > >   i965/fs: set execution size for SEND messages in
> > > generate_uniform_pull_constant_load_gen7
> > >   i965/eu: set execution size for SEND message in
> > > brw_send_indirect_message
> > >   i965: set correct execsize for MOVS with a width of 4 in
> > > brw_find_live_channel
> > >   i965: Skip execution size adjustment for instructions of width
> > > 4
> > > 
> > > Samuel Iglesias Gonsálvez (4):
> > >   i965/gs/gen6: fix execsize for instructions with width of 4 in
> > > gen6_sol_program()
> > >   i965/vec4/gen6: fix exec_size for instructions with width of 4
> > > in
> > > generate_gs_svb_write()
> > >   i965/vec4/gen6: fix exec_size for instructions with destination
> > > width
> > > of 4
> > >   i965/vec4/gen6: fix exec_size for MOV with a width of 4 in
> > > generate_gs_ff_sync()
> > > 
> > >  src/mesa/drivers/dri/i965/brw_eu_emit.c  | 25
> > > +---
> > >  src/mesa/drivers/dri/i965/brw_ff_gs_emit.c   |  9 -
> > >  src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |  2 ++
> > >  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13
> > > +++-
> > >  4 files changed, 44 insertions(+), 5 deletions(-)
> > > 
> 
> 
> 
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> 
> 

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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Pohjolainen, Topi]

On Mon, Mar 07, 2016 at 10:48:49AM +0100, Samuel Iglesias Gons?lvez wrote:
> Hello,
> 
> There is only one patch from this series that has been reviewed (patch
> 1).
> 
> Our plans is to start sending patches for adding fp64 support to i965
> driver in the coming weeks but they depend on these patches.
> 
> Can someone take a look at them? ;)

I'm interested, although we may need to involve also other people in the end.
Do you have a branch somewhere I could clone?

> 
> Sam
> 
> 
> On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> > Hello,
> > 
> > This patch series is a updated version of the one Iago sent last
> > week [0] that includes patches for gen6 too, as suggested by Jason.
> > 
> > We checked the gen9 code paths that work with a horizontal width of 4
> > and we think there won't be any regression on gen9... but we don't
> > have any gen9 machine to run piglit with these patches. Can someone
> > check it?
> > 
> > Please read the original cover letter [0] for more information.
> > 
> > Sam
> > 
> > [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> > 46.html
> > 
> > Iago Toral Quiroga (5):
> >   i965/eu: set correct execution size in brw_NOP
> >   i965/fs: set execution size for SEND messages in
> > generate_uniform_pull_constant_load_gen7
> >   i965/eu: set execution size for SEND message in
> > brw_send_indirect_message
> >   i965: set correct execsize for MOVS with a width of 4 in
> > brw_find_live_channel
> >   i965: Skip execution size adjustment for instructions of width 4
> > 
> > Samuel Iglesias Gonsálvez (4):
> >   i965/gs/gen6: fix execsize for instructions with width of 4 in
> > gen6_sol_program()
> >   i965/vec4/gen6: fix exec_size for instructions with width of 4 in
> > generate_gs_svb_write()
> >   i965/vec4/gen6: fix exec_size for instructions with destination
> > width
> > of 4
> >   i965/vec4/gen6: fix exec_size for MOV with a width of 4 in
> > generate_gs_ff_sync()
> > 
> >  src/mesa/drivers/dri/i965/brw_eu_emit.c  | 25
> > +---
> >  src/mesa/drivers/dri/i965/brw_ff_gs_emit.c   |  9 -
> >  src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |  2 ++
> >  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13 +++-
> >  4 files changed, 44 insertions(+), 5 deletions(-)
> > 



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Re: [Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Samuel Iglesias Gonsálvez]

Hello,

There is only one patch from this series that has been reviewed (patch
1).

Our plans is to start sending patches for adding fp64 support to i965
driver in the coming weeks but they depend on these patches.

Can someone take a look at them? ;)

Sam


On Thu, 2015-12-17 at 14:44 +0100, Samuel Iglesias Gonsálvez wrote:
> Hello,
> 
> This patch series is a updated version of the one Iago sent last
> week [0] that includes patches for gen6 too, as suggested by Jason.
> 
> We checked the gen9 code paths that work with a horizontal width of 4
> and we think there won't be any regression on gen9... but we don't
> have any gen9 machine to run piglit with these patches. Can someone
> check it?
> 
> Please read the original cover letter [0] for more information.
> 
> Sam
> 
> [0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/1027
> 46.html
> 
> Iago Toral Quiroga (5):
>   i965/eu: set correct execution size in brw_NOP
>   i965/fs: set execution size for SEND messages in
> generate_uniform_pull_constant_load_gen7
>   i965/eu: set execution size for SEND message in
> brw_send_indirect_message
>   i965: set correct execsize for MOVS with a width of 4 in
> brw_find_live_channel
>   i965: Skip execution size adjustment for instructions of width 4
> 
> Samuel Iglesias Gonsálvez (4):
>   i965/gs/gen6: fix execsize for instructions with width of 4 in
> gen6_sol_program()
>   i965/vec4/gen6: fix exec_size for instructions with width of 4 in
> generate_gs_svb_write()
>   i965/vec4/gen6: fix exec_size for instructions with destination
> width
> of 4
>   i965/vec4/gen6: fix exec_size for MOV with a width of 4 in
> generate_gs_ff_sync()
> 
>  src/mesa/drivers/dri/i965/brw_eu_emit.c  | 25
> +---
>  src/mesa/drivers/dri/i965/brw_ff_gs_emit.c   |  9 -
>  src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |  2 ++
>  src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13 +++-
>  4 files changed, 44 insertions(+), 5 deletions(-)
> 

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[Mesa-dev] [PATCH 0/9] Skip automatic execsize for instructions with a width of 4

[Samuel Iglesias Gonsálvez]

Hello,

This patch series is a updated version of the one Iago sent last
week [0] that includes patches for gen6 too, as suggested by Jason.

We checked the gen9 code paths that work with a horizontal width of 4
and we think there won't be any regression on gen9... but we don't
have any gen9 machine to run piglit with these patches. Can someone
check it?

Please read the original cover letter [0] for more information.

Sam

[0] http://lists.freedesktop.org/archives/mesa-dev/2015-December/102746.html

Iago Toral Quiroga (5):
  i965/eu: set correct execution size in brw_NOP
  i965/fs: set execution size for SEND messages in
generate_uniform_pull_constant_load_gen7
  i965/eu: set execution size for SEND message in
brw_send_indirect_message
  i965: set correct execsize for MOVS with a width of 4 in
brw_find_live_channel
  i965: Skip execution size adjustment for instructions of width 4

Samuel Iglesias Gonsálvez (4):
  i965/gs/gen6: fix execsize for instructions with width of 4 in
gen6_sol_program()
  i965/vec4/gen6: fix exec_size for instructions with width of 4 in
generate_gs_svb_write()
  i965/vec4/gen6: fix exec_size for instructions with destination width
of 4
  i965/vec4/gen6: fix exec_size for MOV with a width of 4 in
generate_gs_ff_sync()

 src/mesa/drivers/dri/i965/brw_eu_emit.c  | 25 +---
 src/mesa/drivers/dri/i965/brw_ff_gs_emit.c   |  9 -
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |  2 ++
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 13 +++-
 4 files changed, 44 insertions(+), 5 deletions(-)

-- 
2.5.0

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