subject:"\[Mesa\-dev\] \[PATCH 09\/43\] intel\/isl\: Add gen4_filter

Re: [Mesa-dev] [PATCH 09/43] intel/isl: Add gen4_filter_tiling

2017-05-17 Thread Jason Ekstrand

On Tue, May 16, 2017 at 11:40 PM, Pohjolainen, Topi <
topi.pohjolai...@gmail.com> wrote:

> On Tue, May 16, 2017 at 03:45:03PM -0700, Jason Ekstrand wrote:
> > ---
> >  src/intel/isl/isl.c  |  3 +--
> >  src/intel/isl/isl_gen4.c | 51 ++
> ++
> >  src/intel/isl/isl_gen4.h |  5 +
> >  3 files changed, 57 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> > index c728a85..321850e 100644
> > --- a/src/intel/isl/isl.c
> > +++ b/src/intel/isl/isl.c
> > @@ -296,8 +296,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
> > if (ISL_DEV_GEN(dev) >= 6) {
> >isl_gen6_filter_tiling(dev, info, _flags);
> > } else {
> > -  isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
> > -  isl_gen6_filter_tiling(dev, info, _flags);
> > +  isl_gen4_filter_tiling(dev, info, _flags);
> > }
> >
> > #define CHOOSE(__tiling) \
> > diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
> > index 9fed454..63547f7 100644
> > --- a/src/intel/isl/isl_gen4.c
> > +++ b/src/intel/isl/isl_gen4.c
> > @@ -38,6 +38,57 @@ isl_gen4_choose_msaa_layout(const struct isl_device
> *dev,
> >  }
> >
> >  void
> > +isl_gen4_filter_tiling(const struct isl_device *dev,
> > +   const struct isl_surf_init_info *restrict info,
> > +   isl_tiling_flags_t *flags)
> > +{
> > +   /* Gen4-5 only support linear, X, and Y-tiling. */
> > +   *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT |
> ISL_TILING_Y0_BIT;
>
> Can we put () around .. | .. | .. just as you have further down?
>

Sure.


> > +
> > +   if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
> > +  assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev));
> > +
> > +  /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
> > +   *
> > +   *"The Depth Buffer, if tiled, must use Y-Major tiling"
> > +   */
> > +  *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT;
>
> Same here.
>
> > +   }
> > +
> > +   if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
> > +  ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
> > +  ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
> > +  assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
> > +  isl_finishme("%s:%s: handle rotated display surfaces",
> > +   __FILE__, __func__);
> > +   }
> > +
> > +   if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
> > +  ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
> > +  assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
> > +  isl_finishme("%s:%s: handle flipped display surfaces",
> > +   __FILE__, __func__);
> > +   }
> > +
> > +   if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
> > +  /* Before Skylake, the display engine does not accept Y */
> > +  *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
> > +   }
> > +
> > +   assert(info->samples == 1);
> > +
> > +   /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format
> Support":
> > +*
> > +*"NOTE: 128BPE Format Color buffer ( render target ) MUST be
> either
> > +*TileX or Linear."
> > +*
> > +* This is required all the way up to Sandy Bridge.
> > +*/
> > +   if (isl_format_get_layout(info->format)->bpb >= 128)
> > +  *flags &= ~ISL_TILING_Y0_BIT;
> > +}
> > +
> > +void
> >  isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
> > const struct isl_surf_init_info
> *restrict info,
> > enum isl_tiling tiling,
> > diff --git a/src/intel/isl/isl_gen4.h b/src/intel/isl/isl_gen4.h
> > index dc6102b..c04f7fb 100644
> > --- a/src/intel/isl/isl_gen4.h
> > +++ b/src/intel/isl/isl_gen4.h
> > @@ -37,6 +37,11 @@ isl_gen4_choose_msaa_layout(const struct isl_device
> *dev,
> >  enum isl_msaa_layout *msaa_layout);
> >
> >  void
> > +isl_gen4_filter_tiling(const struct isl_device *dev,
> > +   const struct isl_surf_init_info *restrict info,
> > +   isl_tiling_flags_t *flags);
> > +
> > +void
> >  isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
> > const struct isl_surf_init_info
> *restrict info,
> > enum isl_tiling tiling,
> > --
> > 2.5.0.400.gff86faf
> >
> > ___
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> > mesa-dev@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH 09/43] intel/isl: Add gen4_filter_tiling

2017-05-17 Thread Pohjolainen, Topi

On Tue, May 16, 2017 at 03:45:03PM -0700, Jason Ekstrand wrote:
> ---
>  src/intel/isl/isl.c  |  3 +--
>  src/intel/isl/isl_gen4.c | 51 
> 
>  src/intel/isl/isl_gen4.h |  5 +
>  3 files changed, 57 insertions(+), 2 deletions(-)
> 
> diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> index c728a85..321850e 100644
> --- a/src/intel/isl/isl.c
> +++ b/src/intel/isl/isl.c
> @@ -296,8 +296,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
> if (ISL_DEV_GEN(dev) >= 6) {
>isl_gen6_filter_tiling(dev, info, _flags);
> } else {
> -  isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
> -  isl_gen6_filter_tiling(dev, info, _flags);
> +  isl_gen4_filter_tiling(dev, info, _flags);
> }
>  
> #define CHOOSE(__tiling) \
> diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
> index 9fed454..63547f7 100644
> --- a/src/intel/isl/isl_gen4.c
> +++ b/src/intel/isl/isl_gen4.c
> @@ -38,6 +38,57 @@ isl_gen4_choose_msaa_layout(const struct isl_device *dev,
>  }
>  
>  void
> +isl_gen4_filter_tiling(const struct isl_device *dev,
> +   const struct isl_surf_init_info *restrict info,
> +   isl_tiling_flags_t *flags)
> +{
> +   /* Gen4-5 only support linear, X, and Y-tiling. */
> +   *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT;

Can we put () around .. | .. | .. just as you have further down?

> +
> +   if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
> +  assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev));
> +
> +  /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
> +   *
> +   *"The Depth Buffer, if tiled, must use Y-Major tiling"
> +   */
> +  *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT;

Same here.

> +   }
> +
> +   if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
> +  ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
> +  ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
> +  assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
> +  isl_finishme("%s:%s: handle rotated display surfaces",
> +   __FILE__, __func__);
> +   }
> +
> +   if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
> +  ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
> +  assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
> +  isl_finishme("%s:%s: handle flipped display surfaces",
> +   __FILE__, __func__);
> +   }
> +
> +   if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
> +  /* Before Skylake, the display engine does not accept Y */
> +  *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
> +   }
> +
> +   assert(info->samples == 1);
> +
> +   /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
> +*
> +*"NOTE: 128BPE Format Color buffer ( render target ) MUST be either
> +*TileX or Linear."
> +*
> +* This is required all the way up to Sandy Bridge.
> +*/
> +   if (isl_format_get_layout(info->format)->bpb >= 128)
> +  *flags &= ~ISL_TILING_Y0_BIT;
> +}
> +
> +void
>  isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
> const struct isl_surf_init_info *restrict 
> info,
> enum isl_tiling tiling,
> diff --git a/src/intel/isl/isl_gen4.h b/src/intel/isl/isl_gen4.h
> index dc6102b..c04f7fb 100644
> --- a/src/intel/isl/isl_gen4.h
> +++ b/src/intel/isl/isl_gen4.h
> @@ -37,6 +37,11 @@ isl_gen4_choose_msaa_layout(const struct isl_device *dev,
>  enum isl_msaa_layout *msaa_layout);
>  
>  void
> +isl_gen4_filter_tiling(const struct isl_device *dev,
> +   const struct isl_surf_init_info *restrict info,
> +   isl_tiling_flags_t *flags);
> +
> +void
>  isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
> const struct isl_surf_init_info *restrict 
> info,
> enum isl_tiling tiling,
> -- 
> 2.5.0.400.gff86faf
> 
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> mesa-dev@lists.freedesktop.org
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[Mesa-dev] [PATCH 09/43] intel/isl: Add gen4_filter_tiling

2017-05-16 Thread Jason Ekstrand

---
 src/intel/isl/isl.c  |  3 +--
 src/intel/isl/isl_gen4.c | 51 
 src/intel/isl/isl_gen4.h |  5 +
 3 files changed, 57 insertions(+), 2 deletions(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c728a85..321850e 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -296,8 +296,7 @@ isl_surf_choose_tiling(const struct isl_device *dev,
if (ISL_DEV_GEN(dev) >= 6) {
   isl_gen6_filter_tiling(dev, info, _flags);
} else {
-  isl_finishme("%s: gen%u", __func__, ISL_DEV_GEN(dev));
-  isl_gen6_filter_tiling(dev, info, _flags);
+  isl_gen4_filter_tiling(dev, info, _flags);
}
 
#define CHOOSE(__tiling) \
diff --git a/src/intel/isl/isl_gen4.c b/src/intel/isl/isl_gen4.c
index 9fed454..63547f7 100644
--- a/src/intel/isl/isl_gen4.c
+++ b/src/intel/isl/isl_gen4.c
@@ -38,6 +38,57 @@ isl_gen4_choose_msaa_layout(const struct isl_device *dev,
 }
 
 void
+isl_gen4_filter_tiling(const struct isl_device *dev,
+   const struct isl_surf_init_info *restrict info,
+   isl_tiling_flags_t *flags)
+{
+   /* Gen4-5 only support linear, X, and Y-tiling. */
+   *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT | ISL_TILING_Y0_BIT;
+
+   if (isl_surf_usage_is_depth_or_stencil(info->usage)) {
+  assert(!ISL_DEV_USE_SEPARATE_STENCIL(dev));
+
+  /* From the g35 PRM Vol. 2, 3DSTATE_DEPTH_BUFFER::Tile Walk:
+   *
+   *"The Depth Buffer, if tiled, must use Y-Major tiling"
+   */
+  *flags &= ISL_TILING_LINEAR_BIT | ISL_TILING_Y0_BIT;
+   }
+
+   if (info->usage & (ISL_SURF_USAGE_DISPLAY_ROTATE_90_BIT |
+  ISL_SURF_USAGE_DISPLAY_ROTATE_180_BIT |
+  ISL_SURF_USAGE_DISPLAY_ROTATE_270_BIT)) {
+  assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
+  isl_finishme("%s:%s: handle rotated display surfaces",
+   __FILE__, __func__);
+   }
+
+   if (info->usage & (ISL_SURF_USAGE_DISPLAY_FLIP_X_BIT |
+  ISL_SURF_USAGE_DISPLAY_FLIP_Y_BIT)) {
+  assert(*flags & ISL_SURF_USAGE_DISPLAY_BIT);
+  isl_finishme("%s:%s: handle flipped display surfaces",
+   __FILE__, __func__);
+   }
+
+   if (info->usage & ISL_SURF_USAGE_DISPLAY_BIT) {
+  /* Before Skylake, the display engine does not accept Y */
+  *flags &= (ISL_TILING_LINEAR_BIT | ISL_TILING_X_BIT);
+   }
+
+   assert(info->samples == 1);
+
+   /* From the g35 PRM, Volume 1, 11.5.5, "Per-Stream Tile Format Support":
+*
+*"NOTE: 128BPE Format Color buffer ( render target ) MUST be either
+*TileX or Linear."
+*
+* This is required all the way up to Sandy Bridge.
+*/
+   if (isl_format_get_layout(info->format)->bpb >= 128)
+  *flags &= ~ISL_TILING_Y0_BIT;
+}
+
+void
 isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict 
info,
enum isl_tiling tiling,
diff --git a/src/intel/isl/isl_gen4.h b/src/intel/isl/isl_gen4.h
index dc6102b..c04f7fb 100644
--- a/src/intel/isl/isl_gen4.h
+++ b/src/intel/isl/isl_gen4.h
@@ -37,6 +37,11 @@ isl_gen4_choose_msaa_layout(const struct isl_device *dev,
 enum isl_msaa_layout *msaa_layout);
 
 void
+isl_gen4_filter_tiling(const struct isl_device *dev,
+   const struct isl_surf_init_info *restrict info,
+   isl_tiling_flags_t *flags);
+
+void
 isl_gen4_choose_image_alignment_el(const struct isl_device *dev,
const struct isl_surf_init_info *restrict 
info,
enum isl_tiling tiling,
-- 
2.5.0.400.gff86faf

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Re: [Mesa-dev] [PATCH 09/43] intel/isl: Add gen4_filter_tiling

Re: [Mesa-dev] [PATCH 09/43] intel/isl: Add gen4_filter_tiling

[Mesa-dev] [PATCH 09/43] intel/isl: Add gen4_filter_tiling

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