Re: [Mesa-dev] [PATCH 1/2] r600g: add htile support v9

2012-09-12 Thread Jerome Glisse 
On Tue, Jul 17, 2012 at 1:58 PM,  j.gli...@gmail.com wrote:
 From: Jerome Glisse jgli...@redhat.com

 htile is used for HiZ and HiS support and fast Z/S clears.
 This commit just adds the htile setup and Fast Z clear.
 We don't take full advantage of HiS with that patch.

 v2 really use fast clear, still random issue with some tiles
need to try more flush combination, fix depth/stencil
texture decompression
 v3 fix random issue on r6xx/r7xx
 v4 rebase on top of lastest mesa, disable CB export when clearing
htile surface to avoid wasting bandwidth
 v5 resummarize htile surface when uploading z value. Fix z/stencil
decompression, the custom blitter with custom dsa is no longer
needed.
 v6 Reorganize render control/override update mecanism, fixing more
issues in the process.
 v7 Add nop after depth surface base update to work around some htile
flushing issue. For htile to 8x8 on r6xx/r7xx as other combination
have issue. Do not enable hyperz when flushing/uncompressing
depth buffer.
 v8 Fix htile surface, preload and prefetch setup. Only set preload
and prefetch on htile surface clear like fglrx. Record depth
clear value per level. Support several level for the htile
surface. First depth clear can't be a fast clear.
 v9 Fix comments, properly account new register in emit function,
disable fast zclear if clearing different layer of texture
array to different value

 Signed-off-by: Pierre-Eric Pelloux-Prayer pell...@gmail.com
 Signed-off-by: Alex Deucher alexander.deuc...@amd.com
 Signed-off-by: Jerome Glisse jgli...@redhat.com

Btw v11 version against newer mesa is at:
http://people.freedesktop.org/~glisse/0001-r600g-add-htile-support-v11.patch

Cheers,
Jerome

 ---
  src/gallium/drivers/r600/evergreen_hw_context.c |6 +
  src/gallium/drivers/r600/evergreen_state.c  |  102 -
  src/gallium/drivers/r600/evergreend.h   |4 +
  src/gallium/drivers/r600/r600_blit.c|   38 +++
  src/gallium/drivers/r600/r600_hw_context.c  |   25 +
  src/gallium/drivers/r600/r600_pipe.c|8 ++
  src/gallium/drivers/r600/r600_pipe.h|   13 ++-
  src/gallium/drivers/r600/r600_resource.h|7 ++
  src/gallium/drivers/r600/r600_state.c   |  133 
 ---
  src/gallium/drivers/r600/r600_texture.c |  103 ++
  src/gallium/drivers/r600/r600d.h|6 +
  11 files changed, 399 insertions(+), 46 deletions(-)

 diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c 
 b/src/gallium/drivers/r600/evergreen_hw_context.c
 index 081701f..546c884 100644
 --- a/src/gallium/drivers/r600/evergreen_hw_context.c
 +++ b/src/gallium/drivers/r600/evergreen_hw_context.c
 @@ -62,6 +62,9 @@ static const struct r600_reg evergreen_context_reg_list[] = 
 {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 @@ -319,6 +322,9 @@ static const struct r600_reg cayman_context_reg_list[] = {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 diff --git a/src/gallium/drivers/r600/evergreen_state.c 
 b/src/gallium/drivers/r600/evergreen_state.c
 index a66387b..214d76b 100644
 --- a/src/gallium/drivers/r600/evergreen_state.c
 +++ b/src/gallium/drivers/r600/evergreen_state.c
 @@ -710,13 +710,15 @@ static void *evergreen_create_blend_state(struct 
 pipe_context *ctx,
 }
 blend-cb_target_mask = target_mask;

 -   if (target_mask)
 +   if (target_mask) {
 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
 -   else
 +   } else {
 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 +   }

 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 color_control);
 +
 /* only have dual source on MRT0 */
 blend-dual_src_blend = util_blend_state_is_dual(state, 0);
 for (int i = 0; i  8; i++) {
 @@ -1668,6 +1670,26 @@ static void evergreen_db(struct r600_context *rctx, 
 struct r600_pipe_state *rsta
 }
 }

 +   /* hyperz */
 +   if (rtex-hyperz) {
 +   uint64_t htile_offset = 
 rtex-hyperz-surface.level[level].offset;
 +
 +   rctx-db_misc_state.hyperz = true;
 +

Re: [Mesa-dev] [PATCH 1/2] r600g: add htile support v9

2012-07-30 Thread Jerome Glisse 
On Sun, Jul 29, 2012 at 1:50 PM, Marek Olšák mar...@gmail.com wrote:
 On Tue, Jul 17, 2012 at 7:58 PM,  j.gli...@gmail.com wrote:
 From: Jerome Glisse jgli...@redhat.com

 htile is used for HiZ and HiS support and fast Z/S clears.
 This commit just adds the htile setup and Fast Z clear.
 We don't take full advantage of HiS with that patch.

 v2 really use fast clear, still random issue with some tiles
need to try more flush combination, fix depth/stencil
texture decompression
 v3 fix random issue on r6xx/r7xx
 v4 rebase on top of lastest mesa, disable CB export when clearing
htile surface to avoid wasting bandwidth
 v5 resummarize htile surface when uploading z value. Fix z/stencil
decompression, the custom blitter with custom dsa is no longer
needed.
 v6 Reorganize render control/override update mecanism, fixing more
issues in the process.
 v7 Add nop after depth surface base update to work around some htile
flushing issue. For htile to 8x8 on r6xx/r7xx as other combination
have issue. Do not enable hyperz when flushing/uncompressing
depth buffer.
 v8 Fix htile surface, preload and prefetch setup. Only set preload
and prefetch on htile surface clear like fglrx. Record depth
clear value per level. Support several level for the htile
surface. First depth clear can't be a fast clear.
 v9 Fix comments, properly account new register in emit function,
disable fast zclear if clearing different layer of texture
array to different value

 Signed-off-by: Pierre-Eric Pelloux-Prayer pell...@gmail.com
 Signed-off-by: Alex Deucher alexander.deuc...@amd.com
 Signed-off-by: Jerome Glisse jgli...@redhat.com
 ---
  src/gallium/drivers/r600/evergreen_hw_context.c |6 +
  src/gallium/drivers/r600/evergreen_state.c  |  102 -
  src/gallium/drivers/r600/evergreend.h   |4 +
  src/gallium/drivers/r600/r600_blit.c|   38 +++
  src/gallium/drivers/r600/r600_hw_context.c  |   25 +
  src/gallium/drivers/r600/r600_pipe.c|8 ++
  src/gallium/drivers/r600/r600_pipe.h|   13 ++-
  src/gallium/drivers/r600/r600_resource.h|7 ++
  src/gallium/drivers/r600/r600_state.c   |  133 
 ---
  src/gallium/drivers/r600/r600_texture.c |  103 ++
  src/gallium/drivers/r600/r600d.h|6 +
  11 files changed, 399 insertions(+), 46 deletions(-)

 diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c 
 b/src/gallium/drivers/r600/evergreen_hw_context.c
 index 081701f..546c884 100644
 --- a/src/gallium/drivers/r600/evergreen_hw_context.c
 +++ b/src/gallium/drivers/r600/evergreen_hw_context.c
 @@ -62,6 +62,9 @@ static const struct r600_reg evergreen_context_reg_list[] 
 = {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 @@ -319,6 +322,9 @@ static const struct r600_reg cayman_context_reg_list[] = 
 {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 diff --git a/src/gallium/drivers/r600/evergreen_state.c 
 b/src/gallium/drivers/r600/evergreen_state.c
 index a66387b..214d76b 100644
 --- a/src/gallium/drivers/r600/evergreen_state.c
 +++ b/src/gallium/drivers/r600/evergreen_state.c
 @@ -710,13 +710,15 @@ static void *evergreen_create_blend_state(struct 
 pipe_context *ctx,
 }
 blend-cb_target_mask = target_mask;

 -   if (target_mask)
 +   if (target_mask) {
 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
 -   else
 +   } else {
 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 +   }

 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 color_control);
 +
 /* only have dual source on MRT0 */
 blend-dual_src_blend = util_blend_state_is_dual(state, 0);
 for (int i = 0; i  8; i++) {
 @@ -1668,6 +1670,26 @@ static void evergreen_db(struct r600_context *rctx, 
 struct r600_pipe_state *rsta
 }
 }

 +   /* hyperz */
 +   if (rtex-hyperz) {
 +   uint64_t htile_offset = 
 rtex-hyperz-surface.level[level].offset;
 +
 +   rctx-db_misc_state.hyperz = true;
 +   rctx-db_misc_state.db_htile_surface_mask = 0x;
 +

Re: [Mesa-dev] [PATCH 1/2] r600g: add htile support v9

2012-07-29 Thread Marek Olšák 
On Tue, Jul 17, 2012 at 7:58 PM,  j.gli...@gmail.com wrote:
 From: Jerome Glisse jgli...@redhat.com

 htile is used for HiZ and HiS support and fast Z/S clears.
 This commit just adds the htile setup and Fast Z clear.
 We don't take full advantage of HiS with that patch.

 v2 really use fast clear, still random issue with some tiles
need to try more flush combination, fix depth/stencil
texture decompression
 v3 fix random issue on r6xx/r7xx
 v4 rebase on top of lastest mesa, disable CB export when clearing
htile surface to avoid wasting bandwidth
 v5 resummarize htile surface when uploading z value. Fix z/stencil
decompression, the custom blitter with custom dsa is no longer
needed.
 v6 Reorganize render control/override update mecanism, fixing more
issues in the process.
 v7 Add nop after depth surface base update to work around some htile
flushing issue. For htile to 8x8 on r6xx/r7xx as other combination
have issue. Do not enable hyperz when flushing/uncompressing
depth buffer.
 v8 Fix htile surface, preload and prefetch setup. Only set preload
and prefetch on htile surface clear like fglrx. Record depth
clear value per level. Support several level for the htile
surface. First depth clear can't be a fast clear.
 v9 Fix comments, properly account new register in emit function,
disable fast zclear if clearing different layer of texture
array to different value

 Signed-off-by: Pierre-Eric Pelloux-Prayer pell...@gmail.com
 Signed-off-by: Alex Deucher alexander.deuc...@amd.com
 Signed-off-by: Jerome Glisse jgli...@redhat.com
 ---
  src/gallium/drivers/r600/evergreen_hw_context.c |6 +
  src/gallium/drivers/r600/evergreen_state.c  |  102 -
  src/gallium/drivers/r600/evergreend.h   |4 +
  src/gallium/drivers/r600/r600_blit.c|   38 +++
  src/gallium/drivers/r600/r600_hw_context.c  |   25 +
  src/gallium/drivers/r600/r600_pipe.c|8 ++
  src/gallium/drivers/r600/r600_pipe.h|   13 ++-
  src/gallium/drivers/r600/r600_resource.h|7 ++
  src/gallium/drivers/r600/r600_state.c   |  133 
 ---
  src/gallium/drivers/r600/r600_texture.c |  103 ++
  src/gallium/drivers/r600/r600d.h|6 +
  11 files changed, 399 insertions(+), 46 deletions(-)

 diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c 
 b/src/gallium/drivers/r600/evergreen_hw_context.c
 index 081701f..546c884 100644
 --- a/src/gallium/drivers/r600/evergreen_hw_context.c
 +++ b/src/gallium/drivers/r600/evergreen_hw_context.c
 @@ -62,6 +62,9 @@ static const struct r600_reg evergreen_context_reg_list[] = 
 {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 @@ -319,6 +322,9 @@ static const struct r600_reg cayman_context_reg_list[] = {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 diff --git a/src/gallium/drivers/r600/evergreen_state.c 
 b/src/gallium/drivers/r600/evergreen_state.c
 index a66387b..214d76b 100644
 --- a/src/gallium/drivers/r600/evergreen_state.c
 +++ b/src/gallium/drivers/r600/evergreen_state.c
 @@ -710,13 +710,15 @@ static void *evergreen_create_blend_state(struct 
 pipe_context *ctx,
 }
 blend-cb_target_mask = target_mask;

 -   if (target_mask)
 +   if (target_mask) {
 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
 -   else
 +   } else {
 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 +   }

 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 color_control);
 +
 /* only have dual source on MRT0 */
 blend-dual_src_blend = util_blend_state_is_dual(state, 0);
 for (int i = 0; i  8; i++) {
 @@ -1668,6 +1670,26 @@ static void evergreen_db(struct r600_context *rctx, 
 struct r600_pipe_state *rsta
 }
 }

 +   /* hyperz */
 +   if (rtex-hyperz) {
 +   uint64_t htile_offset = 
 rtex-hyperz-surface.level[level].offset;
 +
 +   rctx-db_misc_state.hyperz = true;
 +   rctx-db_misc_state.db_htile_surface_mask = 0x;
 +   r600_atom_dirty(rctx, rctx-db_misc_state.atom);
 +

Re: [Mesa-dev] [PATCH 1/2] r600g: add htile support v9

2012-07-19 Thread Marek Olšák 
On Tue, Jul 17, 2012 at 7:58 PM,  j.gli...@gmail.com wrote:
 From: Jerome Glisse jgli...@redhat.com

 htile is used for HiZ and HiS support and fast Z/S clears.
 This commit just adds the htile setup and Fast Z clear.
 We don't take full advantage of HiS with that patch.

 v2 really use fast clear, still random issue with some tiles
need to try more flush combination, fix depth/stencil
texture decompression
 v3 fix random issue on r6xx/r7xx
 v4 rebase on top of lastest mesa, disable CB export when clearing
htile surface to avoid wasting bandwidth
 v5 resummarize htile surface when uploading z value. Fix z/stencil
decompression, the custom blitter with custom dsa is no longer
needed.
 v6 Reorganize render control/override update mecanism, fixing more
issues in the process.
 v7 Add nop after depth surface base update to work around some htile
flushing issue. For htile to 8x8 on r6xx/r7xx as other combination
have issue. Do not enable hyperz when flushing/uncompressing
depth buffer.
 v8 Fix htile surface, preload and prefetch setup. Only set preload
and prefetch on htile surface clear like fglrx. Record depth
clear value per level. Support several level for the htile
surface. First depth clear can't be a fast clear.
 v9 Fix comments, properly account new register in emit function,
disable fast zclear if clearing different layer of texture
array to different value

 Signed-off-by: Pierre-Eric Pelloux-Prayer pell...@gmail.com
 Signed-off-by: Alex Deucher alexander.deuc...@amd.com
 Signed-off-by: Jerome Glisse jgli...@redhat.com
 ---
  src/gallium/drivers/r600/evergreen_hw_context.c |6 +
  src/gallium/drivers/r600/evergreen_state.c  |  102 -
  src/gallium/drivers/r600/evergreend.h   |4 +
  src/gallium/drivers/r600/r600_blit.c|   38 +++
  src/gallium/drivers/r600/r600_hw_context.c  |   25 +
  src/gallium/drivers/r600/r600_pipe.c|8 ++
  src/gallium/drivers/r600/r600_pipe.h|   13 ++-
  src/gallium/drivers/r600/r600_resource.h|7 ++
  src/gallium/drivers/r600/r600_state.c   |  133 
 ---
  src/gallium/drivers/r600/r600_texture.c |  103 ++
  src/gallium/drivers/r600/r600d.h|6 +
  11 files changed, 399 insertions(+), 46 deletions(-)

 diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c 
 b/src/gallium/drivers/r600/evergreen_hw_context.c
 index 081701f..546c884 100644
 --- a/src/gallium/drivers/r600/evergreen_hw_context.c
 +++ b/src/gallium/drivers/r600/evergreen_hw_context.c
 @@ -62,6 +62,9 @@ static const struct r600_reg evergreen_context_reg_list[] = 
 {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 @@ -319,6 +322,9 @@ static const struct r600_reg cayman_context_reg_list[] = {
 {GROUP_FORCE_NEW_BLOCK, 0, 0},
 {R_028058_DB_DEPTH_SIZE, 0, 0},
 {R_02805C_DB_DEPTH_SLICE, 0, 0},
 +   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
 +   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
 +   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
 {R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
 {R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
 {R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
 diff --git a/src/gallium/drivers/r600/evergreen_state.c 
 b/src/gallium/drivers/r600/evergreen_state.c
 index a66387b..214d76b 100644
 --- a/src/gallium/drivers/r600/evergreen_state.c
 +++ b/src/gallium/drivers/r600/evergreen_state.c
 @@ -710,13 +710,15 @@ static void *evergreen_create_blend_state(struct 
 pipe_context *ctx,
 }
 blend-cb_target_mask = target_mask;

 -   if (target_mask)
 +   if (target_mask) {
 color_control |= S_028808_MODE(V_028808_CB_NORMAL);
 -   else
 +   } else {
 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
 +   }

 r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 color_control);
 +
 /* only have dual source on MRT0 */
 blend-dual_src_blend = util_blend_state_is_dual(state, 0);
 for (int i = 0; i  8; i++) {
 @@ -1668,6 +1670,26 @@ static void evergreen_db(struct r600_context *rctx, 
 struct r600_pipe_state *rsta
 }
 }

 +   /* hyperz */
 +   if (rtex-hyperz) {
 +   uint64_t htile_offset = 
 rtex-hyperz-surface.level[level].offset;
 +
 +   rctx-db_misc_state.hyperz = true;
 +   rctx-db_misc_state.db_htile_surface_mask = 0x;
 +   r600_atom_dirty(rctx, rctx-db_misc_state.atom);
 +

[Mesa-dev] [PATCH 1/2] r600g: add htile support v9

2012-07-17 Thread j . glisse 
From: Jerome Glisse jgli...@redhat.com

htile is used for HiZ and HiS support and fast Z/S clears.
This commit just adds the htile setup and Fast Z clear.
We don't take full advantage of HiS with that patch.

v2 really use fast clear, still random issue with some tiles
   need to try more flush combination, fix depth/stencil
   texture decompression
v3 fix random issue on r6xx/r7xx
v4 rebase on top of lastest mesa, disable CB export when clearing
   htile surface to avoid wasting bandwidth
v5 resummarize htile surface when uploading z value. Fix z/stencil
   decompression, the custom blitter with custom dsa is no longer
   needed.
v6 Reorganize render control/override update mecanism, fixing more
   issues in the process.
v7 Add nop after depth surface base update to work around some htile
   flushing issue. For htile to 8x8 on r6xx/r7xx as other combination
   have issue. Do not enable hyperz when flushing/uncompressing
   depth buffer.
v8 Fix htile surface, preload and prefetch setup. Only set preload
   and prefetch on htile surface clear like fglrx. Record depth
   clear value per level. Support several level for the htile
   surface. First depth clear can't be a fast clear.
v9 Fix comments, properly account new register in emit function,
   disable fast zclear if clearing different layer of texture
   array to different value

Signed-off-by: Pierre-Eric Pelloux-Prayer pell...@gmail.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
 src/gallium/drivers/r600/evergreen_hw_context.c |6 +
 src/gallium/drivers/r600/evergreen_state.c  |  102 -
 src/gallium/drivers/r600/evergreend.h   |4 +
 src/gallium/drivers/r600/r600_blit.c|   38 +++
 src/gallium/drivers/r600/r600_hw_context.c  |   25 +
 src/gallium/drivers/r600/r600_pipe.c|8 ++
 src/gallium/drivers/r600/r600_pipe.h|   13 ++-
 src/gallium/drivers/r600/r600_resource.h|7 ++
 src/gallium/drivers/r600/r600_state.c   |  133 ---
 src/gallium/drivers/r600/r600_texture.c |  103 ++
 src/gallium/drivers/r600/r600d.h|6 +
 11 files changed, 399 insertions(+), 46 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c 
b/src/gallium/drivers/r600/evergreen_hw_context.c
index 081701f..546c884 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -62,6 +62,9 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0},
+   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
+   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
+   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
@@ -319,6 +322,9 @@ static const struct r600_reg cayman_context_reg_list[] = {
{GROUP_FORCE_NEW_BLOCK, 0, 0},
{R_028058_DB_DEPTH_SIZE, 0, 0},
{R_02805C_DB_DEPTH_SLICE, 0, 0},
+   {R_02802C_DB_DEPTH_CLEAR, 0, 0},
+   {R_028ABC_DB_HTILE_SURFACE, 0, 0},
+   {R_028AC8_DB_PRELOAD_CONTROL, 0, 0},
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c 
b/src/gallium/drivers/r600/evergreen_state.c
index a66387b..214d76b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -710,13 +710,15 @@ static void *evergreen_create_blend_state(struct 
pipe_context *ctx,
}
blend-cb_target_mask = target_mask;
 
-   if (target_mask)
+   if (target_mask) {
color_control |= S_028808_MODE(V_028808_CB_NORMAL);
-   else
+   } else {
color_control |= S_028808_MODE(V_028808_CB_DISABLE);
+   }
 
r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
color_control);
+
/* only have dual source on MRT0 */
blend-dual_src_blend = util_blend_state_is_dual(state, 0);
for (int i = 0; i  8; i++) {
@@ -1668,6 +1670,26 @@ static void evergreen_db(struct r600_context *rctx, 
struct r600_pipe_state *rsta
}
}
 
+   /* hyperz */
+   if (rtex-hyperz) {
+   uint64_t htile_offset = 
rtex-hyperz-surface.level[level].offset;
+
+   rctx-db_misc_state.hyperz = true;
+   rctx-db_misc_state.db_htile_surface_mask = 0x;
+   r600_atom_dirty(rctx, rctx-db_misc_state.atom);
+   z_info |= S_028040_TILE_SURFACE_ENABLE(1);
+   r600_pipe_state_add_reg_bo(rstate, R_028014_DB_HTILE_DATA_BASE,
+