Re: [Mesa-dev] [PATCH 1/6] ac/surface/gfx6: don't overallocate mipmapped HTILE

[Nicolai Hähnle]

For the series:

Reviewed-by: Nicolai Hähnle 

On 23.05.2018 23:29, Marek Olšák wrote:

ping

On Wed, May 16, 2018 at 9:47 PM, Marek Olšák > wrote:


From: Marek Olšák >

---
  src/amd/common/ac_surface.c | 13 +++--
  1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 9e742dc8a45..47de522d15d 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -927,22 +927,31 @@ static int gfx6_compute_surface(ADDR_HANDLE
addrlib,
                  *
                  * "dcc_alignment * 4" was determined by trial and
error.
                  */
                 surf->dcc_size = align64(surf->surf_size >> 8,
                                          surf->dcc_alignment * 4);
         }

         /* Make sure HTILE covers the whole miptree, because the
shader reads
          * TC-compatible HTILE even for levels where it's disabled
by DB.
          */
-       if (surf->htile_size && config->info.levels > 1)
-               surf->htile_size *= 2;
+       if (surf->htile_size && config->info.levels > 1 &&
+           surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
+               /* MSAA can't occur with levels > 1, so ignore the
sample count. */
+               const unsigned total_pixels = surf->surf_size /
surf->bpe;
+               const unsigned htile_block_size = 8 * 8;
+               const unsigned htile_element_size = 4;
+
+               surf->htile_size = (total_pixels / htile_block_size) *
+                                  htile_element_size;
+               surf->htile_size = align(surf->htile_size,
surf->htile_alignment);
+       }

         surf->is_linear = surf->u.legacy.level[0].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED;
         surf->is_displayable = surf->is_linear ||
                                surf->micro_tile_mode ==
RADEON_MICRO_MODE_DISPLAY ||
                                surf->micro_tile_mode ==
RADEON_MICRO_MODE_ROTATED;
         return 0;
  }

  /* This is only called when expecting a tiled layout. */
  static int
-- 
2.17.0





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Re: [Mesa-dev] [PATCH 1/6] ac/surface/gfx6: don't overallocate mipmapped HTILE

[Marek Olšák]

ping

On Wed, May 16, 2018 at 9:47 PM, Marek Olšák  wrote:

> From: Marek Olšák 
>
> ---
>  src/amd/common/ac_surface.c | 13 +++--
>  1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index 9e742dc8a45..47de522d15d 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -927,22 +927,31 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>  *
>  * "dcc_alignment * 4" was determined by trial and error.
>  */
> surf->dcc_size = align64(surf->surf_size >> 8,
>  surf->dcc_alignment * 4);
> }
>
> /* Make sure HTILE covers the whole miptree, because the shader
> reads
>  * TC-compatible HTILE even for levels where it's disabled by DB.
>  */
> -   if (surf->htile_size && config->info.levels > 1)
> -   surf->htile_size *= 2;
> +   if (surf->htile_size && config->info.levels > 1 &&
> +   surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
> +   /* MSAA can't occur with levels > 1, so ignore the sample
> count. */
> +   const unsigned total_pixels = surf->surf_size / surf->bpe;
> +   const unsigned htile_block_size = 8 * 8;
> +   const unsigned htile_element_size = 4;
> +
> +   surf->htile_size = (total_pixels / htile_block_size) *
> +  htile_element_size;
> +   surf->htile_size = align(surf->htile_size,
> surf->htile_alignment);
> +   }
>
> surf->is_linear = surf->u.legacy.level[0].mode ==
> RADEON_SURF_MODE_LINEAR_ALIGNED;
> surf->is_displayable = surf->is_linear ||
>surf->micro_tile_mode ==
> RADEON_MICRO_MODE_DISPLAY ||
>surf->micro_tile_mode ==
> RADEON_MICRO_MODE_ROTATED;
> return 0;
>  }
>
>  /* This is only called when expecting a tiled layout. */
>  static int
> --
> 2.17.0
>
>
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[Mesa-dev] [PATCH 1/6] ac/surface/gfx6: don't overallocate mipmapped HTILE

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_surface.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 9e742dc8a45..47de522d15d 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -927,22 +927,31 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 *
 * "dcc_alignment * 4" was determined by trial and error.
 */
surf->dcc_size = align64(surf->surf_size >> 8,
 surf->dcc_alignment * 4);
}
 
/* Make sure HTILE covers the whole miptree, because the shader reads
 * TC-compatible HTILE even for levels where it's disabled by DB.
 */
-   if (surf->htile_size && config->info.levels > 1)
-   surf->htile_size *= 2;
+   if (surf->htile_size && config->info.levels > 1 &&
+   surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
+   /* MSAA can't occur with levels > 1, so ignore the sample 
count. */
+   const unsigned total_pixels = surf->surf_size / surf->bpe;
+   const unsigned htile_block_size = 8 * 8;
+   const unsigned htile_element_size = 4;
+
+   surf->htile_size = (total_pixels / htile_block_size) *
+  htile_element_size;
+   surf->htile_size = align(surf->htile_size, 
surf->htile_alignment);
+   }
 
surf->is_linear = surf->u.legacy.level[0].mode == 
RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_displayable = surf->is_linear ||
   surf->micro_tile_mode == 
RADEON_MICRO_MODE_DISPLAY ||
   surf->micro_tile_mode == 
RADEON_MICRO_MODE_ROTATED;
return 0;
 }
 
 /* This is only called when expecting a tiled layout. */
 static int
-- 
2.17.0

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