Re: [Mesa-dev] [PATCH 1/8] R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
With the changes Michel suggested, this series is:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Are any of these candidates for the stable branch?
-Tom
On Tue, Feb 19, 2013 at 02:54:23PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Those two files got mixed up.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 500
+++--
lib/Target/R600/SIInstrInfo.td| 495 +++-
2 files changed, 509 insertions(+), 486 deletions(-)
diff --git a/lib/Target/R600/SIInstrFormats.td
b/lib/Target/R600/SIInstrFormats.td
index 40e37aa..fe417d6 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -1,4 +1,4 @@
-//===-- SIInstrFormats.td - SI Instruction Formats
===//
+//===-- SIInstrFormats.td - SI Instruction Encodings
--===//
//
// The LLVM Compiler Infrastructure
//
@@ -9,180 +9,418 @@
//
// SI Instruction format definitions.
//
-// Instructions with _32 take 32-bit operands.
-// Instructions with _64 take 64-bit operands.
-//
-// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
-// encoding is the standard encoding, but instruction that make use of
-// any of the instruction modifiers must use the 64-bit encoding.
-//
-// Instructions with _e32 use the 32-bit encoding.
-// Instructions with _e64 use the 64-bit encoding.
-//
//===--===//
-class VOP3_32 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1,
VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern;
+class InstSI dag outs, dag ins, string asm, listdag pattern :
+AMDGPUInstouts, ins, asm, pattern {
+
+ field bits1 VM_CNT = 0;
+ field bits1 EXP_CNT = 0;
+ field bits1 LGKM_CNT = 0;
+
+ let TSFlags{0} = VM_CNT;
+ let TSFlags{1} = EXP_CNT;
+ let TSFlags{2} = LGKM_CNT;
+}
+
+class Enc32 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
+
+ field bits32 Inst;
+ let Size = 4;
+}
-class VOP3_64 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1,
VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern;
+class Enc64 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
-class SOP1_32 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern;
+ field bits64 Inst;
+ let Size = 8;
+}
-class SOP1_64 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern;
+//===--===//
+// Scalar operations
+//===--===//
-class SOP2_32 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
opName, pattern;
+class SOP1 bits8 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32outs, ins, asm, pattern {
-class SOP2_64 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
opName, pattern;
+ bits7 SDST;
+ bits8 SSRC0;
-class VOP1_Helper bits8 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
- VOP1
-op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
- ;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = op;
+ let Inst{22-16} = SDST;
+ let Inst{31-23} = 0x17d; //encoding;
-multiclass VOP1_32 bits8 op, string opName, listdag pattern {
- def _e32: VOP1_Helper op, VReg_32, VSrc_32, opName, pattern;
- def _e64 : VOP3_32 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1},
op{0}},
- opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-multiclass VOP1_64 bits8 op, string opName, listdag pattern {
+class SOP2 bits7 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32 outs, ins, asm, pattern {
+
+ bits7 SDST;
+ bits8 SSRC0;
+ bits8 SSRC1;
- def _e32 : VOP1_Helper op, VReg_64, VSrc_64, opName, pattern;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = SSRC1;
+ let Inst{22-16} = SDST;
+ let Inst{29-23} = op;
+ let Inst{31-30} = 0x2; // encoding
- def _e64 : VOP3_64
-{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
-opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-class VOP2_Helper bits6 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
Re: [Mesa-dev] [PATCH 1/8] R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
On Thu, Feb 21, 2013 at 09:06:36AM -0500, Tom Stellard wrote:
With the changes Michel suggested, this series is:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
Are any of these candidates for the stable branch?
Please ignore this, I overlooked v2 of this series. I will review the
new version now.
-Tom
On Tue, Feb 19, 2013 at 02:54:23PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Those two files got mixed up.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 500
+++--
lib/Target/R600/SIInstrInfo.td| 495
+++-
2 files changed, 509 insertions(+), 486 deletions(-)
diff --git a/lib/Target/R600/SIInstrFormats.td
b/lib/Target/R600/SIInstrFormats.td
index 40e37aa..fe417d6 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -1,4 +1,4 @@
-//===-- SIInstrFormats.td - SI Instruction Formats
===//
+//===-- SIInstrFormats.td - SI Instruction Encodings
--===//
//
// The LLVM Compiler Infrastructure
//
@@ -9,180 +9,418 @@
//
// SI Instruction format definitions.
//
-// Instructions with _32 take 32-bit operands.
-// Instructions with _64 take 64-bit operands.
-//
-// VOP_* instructions can use either a 32-bit or 64-bit encoding. The
32-bit
-// encoding is the standard encoding, but instruction that make use of
-// any of the instruction modifiers must use the 64-bit encoding.
-//
-// Instructions with _e32 use the 32-bit encoding.
-// Instructions with _e64 use the 64-bit encoding.
-//
//===--===//
-class VOP3_32 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1,
VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern;
+class InstSI dag outs, dag ins, string asm, listdag pattern :
+AMDGPUInstouts, ins, asm, pattern {
+
+ field bits1 VM_CNT = 0;
+ field bits1 EXP_CNT = 0;
+ field bits1 LGKM_CNT = 0;
+
+ let TSFlags{0} = VM_CNT;
+ let TSFlags{1} = EXP_CNT;
+ let TSFlags{2} = LGKM_CNT;
+}
+
+class Enc32 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
+
+ field bits32 Inst;
+ let Size = 4;
+}
-class VOP3_64 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1,
VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern;
+class Enc64 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
-class SOP1_32 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern;
+ field bits64 Inst;
+ let Size = 8;
+}
-class SOP1_64 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern;
+//===--===//
+// Scalar operations
+//===--===//
-class SOP2_32 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
opName, pattern;
+class SOP1 bits8 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32outs, ins, asm, pattern {
-class SOP2_64 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
opName, pattern;
+ bits7 SDST;
+ bits8 SSRC0;
-class VOP1_Helper bits8 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
- VOP1
-op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
- ;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = op;
+ let Inst{22-16} = SDST;
+ let Inst{31-23} = 0x17d; //encoding;
-multiclass VOP1_32 bits8 op, string opName, listdag pattern {
- def _e32: VOP1_Helper op, VReg_32, VSrc_32, opName, pattern;
- def _e64 : VOP3_32 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1},
op{0}},
- opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-multiclass VOP1_64 bits8 op, string opName, listdag pattern {
+class SOP2 bits7 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32 outs, ins, asm, pattern {
+
+ bits7 SDST;
+ bits8 SSRC0;
+ bits8 SSRC1;
- def _e32 : VOP1_Helper op, VReg_64, VSrc_64, opName, pattern;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = SSRC1;
+ let Inst{22-16} = SDST;
+ let Inst{29-23} = op;
+ let Inst{31-30} = 0x2; // encoding
- def
[Mesa-dev] [PATCH 1/8] R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
From: Christian König christian.koe...@amd.com
Those two files got mixed up.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 500 +++--
lib/Target/R600/SIInstrInfo.td| 495 +++-
2 files changed, 509 insertions(+), 486 deletions(-)
diff --git a/lib/Target/R600/SIInstrFormats.td
b/lib/Target/R600/SIInstrFormats.td
index 40e37aa..fe417d6 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -1,4 +1,4 @@
-//===-- SIInstrFormats.td - SI Instruction Formats
===//
+//===-- SIInstrFormats.td - SI Instruction Encodings
--===//
//
// The LLVM Compiler Infrastructure
//
@@ -9,180 +9,418 @@
//
// SI Instruction format definitions.
//
-// Instructions with _32 take 32-bit operands.
-// Instructions with _64 take 64-bit operands.
-//
-// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
-// encoding is the standard encoding, but instruction that make use of
-// any of the instruction modifiers must use the 64-bit encoding.
-//
-// Instructions with _e32 use the 32-bit encoding.
-// Instructions with _e64 use the 64-bit encoding.
-//
//===--===//
-class VOP3_32 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1,
VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName,
pattern;
+class InstSI dag outs, dag ins, string asm, listdag pattern :
+AMDGPUInstouts, ins, asm, pattern {
+
+ field bits1 VM_CNT = 0;
+ field bits1 EXP_CNT = 0;
+ field bits1 LGKM_CNT = 0;
+
+ let TSFlags{0} = VM_CNT;
+ let TSFlags{1} = EXP_CNT;
+ let TSFlags{2} = LGKM_CNT;
+}
+
+class Enc32 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
+
+ field bits32 Inst;
+ let Size = 4;
+}
-class VOP3_64 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1,
VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName,
pattern;
+class Enc64 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
-class SOP1_32 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern;
+ field bits64 Inst;
+ let Size = 8;
+}
-class SOP1_64 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern;
+//===--===//
+// Scalar operations
+//===--===//
-class SOP2_32 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName,
pattern;
+class SOP1 bits8 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32outs, ins, asm, pattern {
-class SOP2_64 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName,
pattern;
+ bits7 SDST;
+ bits8 SSRC0;
-class VOP1_Helper bits8 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
- VOP1
-op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
- ;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = op;
+ let Inst{22-16} = SDST;
+ let Inst{31-23} = 0x17d; //encoding;
-multiclass VOP1_32 bits8 op, string opName, listdag pattern {
- def _e32: VOP1_Helper op, VReg_32, VSrc_32, opName, pattern;
- def _e64 : VOP3_32 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
- opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-multiclass VOP1_64 bits8 op, string opName, listdag pattern {
+class SOP2 bits7 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32 outs, ins, asm, pattern {
+
+ bits7 SDST;
+ bits8 SSRC0;
+ bits8 SSRC1;
- def _e32 : VOP1_Helper op, VReg_64, VSrc_64, opName, pattern;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = SSRC1;
+ let Inst{22-16} = SDST;
+ let Inst{29-23} = op;
+ let Inst{31-30} = 0x2; // encoding
- def _e64 : VOP3_64
-{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
-opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-class VOP2_Helper bits6 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
- VOP2
-op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
- ;
+class SOPC bits7 op, dag outs, dag ins, string asm, listdag pattern :
+ Enc32outs, ins, asm, pattern {
-multiclass VOP2_32 bits6 op, string opName, listdag pattern {
+ bits8 SSRC0;
+ bits8 SSRC1;
- def _e32 : VOP2_Helper op, VReg_32, VSrc_32, opName, pattern;
+ let Inst{7-0}
Re: [Mesa-dev] [PATCH 1/8] R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
Hi Christian,
From now on can you cc llvm-comm...@cs.uiuc.edu when you submit a patch.
Thanks,
Tom
On Tue, Feb 19, 2013 at 02:54:23PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Those two files got mixed up.
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrFormats.td | 500
+++--
lib/Target/R600/SIInstrInfo.td| 495 +++-
2 files changed, 509 insertions(+), 486 deletions(-)
diff --git a/lib/Target/R600/SIInstrFormats.td
b/lib/Target/R600/SIInstrFormats.td
index 40e37aa..fe417d6 100644
--- a/lib/Target/R600/SIInstrFormats.td
+++ b/lib/Target/R600/SIInstrFormats.td
@@ -1,4 +1,4 @@
-//===-- SIInstrFormats.td - SI Instruction Formats
===//
+//===-- SIInstrFormats.td - SI Instruction Encodings
--===//
//
// The LLVM Compiler Infrastructure
//
@@ -9,180 +9,418 @@
//
// SI Instruction format definitions.
//
-// Instructions with _32 take 32-bit operands.
-// Instructions with _64 take 64-bit operands.
-//
-// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
-// encoding is the standard encoding, but instruction that make use of
-// any of the instruction modifiers must use the 64-bit encoding.
-//
-// Instructions with _e32 use the 32-bit encoding.
-// Instructions with _e64 use the 64-bit encoding.
-//
//===--===//
-class VOP3_32 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1,
VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern;
+class InstSI dag outs, dag ins, string asm, listdag pattern :
+AMDGPUInstouts, ins, asm, pattern {
+
+ field bits1 VM_CNT = 0;
+ field bits1 EXP_CNT = 0;
+ field bits1 LGKM_CNT = 0;
+
+ let TSFlags{0} = VM_CNT;
+ let TSFlags{1} = EXP_CNT;
+ let TSFlags{2} = LGKM_CNT;
+}
+
+class Enc32 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
+
+ field bits32 Inst;
+ let Size = 4;
+}
-class VOP3_64 bits9 op, string opName, listdag pattern
- : VOP3 op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1,
VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
opName, pattern;
+class Enc64 dag outs, dag ins, string asm, listdag pattern :
+InstSI outs, ins, asm, pattern {
-class SOP1_32 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern;
+ field bits64 Inst;
+ let Size = 8;
+}
-class SOP1_64 bits8 op, string opName, listdag pattern
- : SOP1 op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern;
+//===--===//
+// Scalar operations
+//===--===//
-class SOP2_32 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
opName, pattern;
+class SOP1 bits8 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32outs, ins, asm, pattern {
-class SOP2_64 bits7 op, string opName, listdag pattern
- : SOP2 op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
opName, pattern;
+ bits7 SDST;
+ bits8 SSRC0;
-class VOP1_Helper bits8 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
- VOP1
-op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
- ;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = op;
+ let Inst{22-16} = SDST;
+ let Inst{31-23} = 0x17d; //encoding;
-multiclass VOP1_32 bits8 op, string opName, listdag pattern {
- def _e32: VOP1_Helper op, VReg_32, VSrc_32, opName, pattern;
- def _e64 : VOP3_32 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1},
op{0}},
- opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-multiclass VOP1_64 bits8 op, string opName, listdag pattern {
+class SOP2 bits7 op, dag outs, dag ins, string asm, listdag pattern :
+Enc32 outs, ins, asm, pattern {
+
+ bits7 SDST;
+ bits8 SSRC0;
+ bits8 SSRC1;
- def _e32 : VOP1_Helper op, VReg_64, VSrc_64, opName, pattern;
+ let Inst{7-0} = SSRC0;
+ let Inst{15-8} = SSRC1;
+ let Inst{22-16} = SDST;
+ let Inst{29-23} = op;
+ let Inst{31-30} = 0x2; // encoding
- def _e64 : VOP3_64
-{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
-opName, []
- ;
+ let mayLoad = 0;
+ let mayStore = 0;
+ let hasSideEffects = 0;
}
-class VOP2_Helper bits6 op, RegisterClass vrc, RegisterClass arc,
- string opName, listdag pattern :
- VOP2
-op, (outs vrc:$dst), (ins arc:$src0,
