Re: [Mesa-dev] [PATCH 13/18] anv/pipeline: Compile to NIR in compile_graphics
On Wed, Jul 25, 2018 at 5:19 PM Timothy Arceri
wrote:
> On 12/07/18 07:18, Jason Ekstrand wrote:
> > This pulls the SPIR-V to NIR step out into common code.
> > ---
> > src/intel/vulkan/anv_pipeline.c | 278 +---
> > 1 file changed, 116 insertions(+), 162 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_pipeline.c
> b/src/intel/vulkan/anv_pipeline.c
> > index bc268b87e55..50d6ab358d2 100644
> > --- a/src/intel/vulkan/anv_pipeline.c
> > +++ b/src/intel/vulkan/anv_pipeline.c
> > @@ -404,6 +404,14 @@ struct anv_pipeline_stage {
> > gl_shader_stage stage;
> > unsigned char sha1[20];
> > } cache_key;
> > +
> > + nir_shader *nir;
> > +
> > + struct anv_pipeline_binding surface_to_descriptor[256];
> > + struct anv_pipeline_binding sampler_to_descriptor[256];
> > + struct anv_pipeline_bind_map bind_map;
> > +
> > + union brw_any_prog_data prog_data;
> > };
> >
> > static void
> > @@ -547,58 +555,40 @@ anv_fill_binding_table(struct brw_stage_prog_data
> *prog_data, unsigned bias)
> > static VkResult
> > anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
> > struct anv_pipeline_cache *cache,
> > -const VkGraphicsPipelineCreateInfo *info,
> > struct anv_pipeline_stage *stage)
> > {
> > const struct brw_compiler *compiler =
> > pipeline->device->instance->physicalDevice.compiler;
> > struct anv_shader_bin *bin = NULL;
> >
> > - ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
> > -
> > if (bin == NULL) {
> > - struct brw_vs_prog_data prog_data = {};
> > - struct anv_pipeline_binding surface_to_descriptor[256];
> > - struct anv_pipeline_binding sampler_to_descriptor[256];
> > -
> > - struct anv_pipeline_bind_map map = {
> > - .surface_to_descriptor = surface_to_descriptor,
> > - .sampler_to_descriptor = sampler_to_descriptor
> > - };
> > -
> > void *mem_ctx = ralloc_context(NULL);
> >
> > - nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout,
> stage,
> > - _data.base.base,
> );
> > - if (nir == NULL) {
> > - ralloc_free(mem_ctx);
> > - return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> > - }
> > -
> > - anv_fill_binding_table(_data.base.base, 0);
> > + anv_fill_binding_table(>prog_data.vs.base.base, 0);
> >
> > brw_compute_vue_map(>device->info,
> > - _data.base.vue_map,
> > - nir->info.outputs_written,
> > - nir->info.separate_shader);
> > + >prog_data.vs.base.vue_map,
> > + stage->nir->info.outputs_written,
> > + stage->nir->info.separate_shader);
> >
> > const unsigned *shader_code =
> >brw_compile_vs(compiler, NULL, mem_ctx, >key.vs,
> > -_data, nir, -1, NULL);
> > +>prog_data.vs, stage->nir, -1, NULL);
> > if (shader_code == NULL) {
> >ralloc_free(mem_ctx);
> >return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> > }
> >
> > - unsigned code_size = prog_data.base.base.program_size;
> > + unsigned code_size = stage->prog_data.vs.base.base.program_size;
> > bin = anv_device_upload_kernel(pipeline->device, cache,
> >>cache_key,
> >sizeof(stage->cache_key),
> >shader_code, code_size,
> > - nir->constant_data,
> > - nir->constant_data_size,
> > - _data.base.base,
> sizeof(prog_data),
> > - );
> > + stage->nir->constant_data,
> > + stage->nir->constant_data_size,
> > + >prog_data.base,
> > + sizeof(stage->prog_data.vs),
> > + >bind_map);
> > if (!bin) {
> >ralloc_free(mem_ctx);
> >return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
> > @@ -654,7 +644,6 @@ merge_tess_info(struct shader_info *tes_info,
> > static VkResult
> > anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
> >struct anv_pipeline_cache *cache,
> > - const VkGraphicsPipelineCreateInfo *info,
> >struct anv_pipeline_stage *tcs_stage,
> >struct anv_pipeline_stage *tes_stage)
> > {
> > @@ -664,85 +653,60 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline
> *pipeline,
> > struct anv_shader_bin *tcs_bin = NULL;
> > struct anv_shader_bin *tes_bin
Re: [Mesa-dev] [PATCH 13/18] anv/pipeline: Compile to NIR in compile_graphics
On 12/07/18 07:18, Jason Ekstrand wrote:
This pulls the SPIR-V to NIR step out into common code.
---
src/intel/vulkan/anv_pipeline.c | 278 +---
1 file changed, 116 insertions(+), 162 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index bc268b87e55..50d6ab358d2 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -404,6 +404,14 @@ struct anv_pipeline_stage {
gl_shader_stage stage;
unsigned char sha1[20];
} cache_key;
+
+ nir_shader *nir;
+
+ struct anv_pipeline_binding surface_to_descriptor[256];
+ struct anv_pipeline_binding sampler_to_descriptor[256];
+ struct anv_pipeline_bind_map bind_map;
+
+ union brw_any_prog_data prog_data;
};
static void
@@ -547,58 +555,40 @@ anv_fill_binding_table(struct brw_stage_prog_data
*prog_data, unsigned bias)
static VkResult
anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
struct anv_pipeline_cache *cache,
-const VkGraphicsPipelineCreateInfo *info,
struct anv_pipeline_stage *stage)
{
const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
struct anv_shader_bin *bin = NULL;
- ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
-
if (bin == NULL) {
- struct brw_vs_prog_data prog_data = {};
- struct anv_pipeline_binding surface_to_descriptor[256];
- struct anv_pipeline_binding sampler_to_descriptor[256];
-
- struct anv_pipeline_bind_map map = {
- .surface_to_descriptor = surface_to_descriptor,
- .sampler_to_descriptor = sampler_to_descriptor
- };
-
void *mem_ctx = ralloc_context(NULL);
- nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout, stage,
- _data.base.base, );
- if (nir == NULL) {
- ralloc_free(mem_ctx);
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- }
-
- anv_fill_binding_table(_data.base.base, 0);
+ anv_fill_binding_table(>prog_data.vs.base.base, 0);
brw_compute_vue_map(>device->info,
- _data.base.vue_map,
- nir->info.outputs_written,
- nir->info.separate_shader);
+ >prog_data.vs.base.vue_map,
+ stage->nir->info.outputs_written,
+ stage->nir->info.separate_shader);
const unsigned *shader_code =
brw_compile_vs(compiler, NULL, mem_ctx, >key.vs,
-_data, nir, -1, NULL);
+>prog_data.vs, stage->nir, -1, NULL);
if (shader_code == NULL) {
ralloc_free(mem_ctx);
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
- unsigned code_size = prog_data.base.base.program_size;
+ unsigned code_size = stage->prog_data.vs.base.base.program_size;
bin = anv_device_upload_kernel(pipeline->device, cache,
>cache_key,
sizeof(stage->cache_key),
shader_code, code_size,
- nir->constant_data,
- nir->constant_data_size,
- _data.base.base, sizeof(prog_data),
- );
+ stage->nir->constant_data,
+ stage->nir->constant_data_size,
+ >prog_data.base,
+ sizeof(stage->prog_data.vs),
+ >bind_map);
if (!bin) {
ralloc_free(mem_ctx);
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
@@ -654,7 +644,6 @@ merge_tess_info(struct shader_info *tes_info,
static VkResult
anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
struct anv_pipeline_cache *cache,
- const VkGraphicsPipelineCreateInfo *info,
struct anv_pipeline_stage *tcs_stage,
struct anv_pipeline_stage *tes_stage)
{
@@ -664,85 +653,60 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline,
struct anv_shader_bin *tcs_bin = NULL;
struct anv_shader_bin *tes_bin = NULL;
- ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
-
if (tcs_bin == NULL || tes_bin == NULL) {
- struct brw_tcs_prog_data tcs_prog_data = {};
- struct brw_tes_prog_data tes_prog_data = {};
- struct anv_pipeline_binding tcs_surface_to_descriptor[256];
- struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
- struct anv_pipeline_binding tes_surface_to_descriptor[256];
- struct
[Mesa-dev] [PATCH 13/18] anv/pipeline: Compile to NIR in compile_graphics
This pulls the SPIR-V to NIR step out into common code.
---
src/intel/vulkan/anv_pipeline.c | 278 +---
1 file changed, 116 insertions(+), 162 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index bc268b87e55..50d6ab358d2 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -404,6 +404,14 @@ struct anv_pipeline_stage {
gl_shader_stage stage;
unsigned char sha1[20];
} cache_key;
+
+ nir_shader *nir;
+
+ struct anv_pipeline_binding surface_to_descriptor[256];
+ struct anv_pipeline_binding sampler_to_descriptor[256];
+ struct anv_pipeline_bind_map bind_map;
+
+ union brw_any_prog_data prog_data;
};
static void
@@ -547,58 +555,40 @@ anv_fill_binding_table(struct brw_stage_prog_data
*prog_data, unsigned bias)
static VkResult
anv_pipeline_compile_vs(struct anv_pipeline *pipeline,
struct anv_pipeline_cache *cache,
-const VkGraphicsPipelineCreateInfo *info,
struct anv_pipeline_stage *stage)
{
const struct brw_compiler *compiler =
pipeline->device->instance->physicalDevice.compiler;
struct anv_shader_bin *bin = NULL;
- ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
-
if (bin == NULL) {
- struct brw_vs_prog_data prog_data = {};
- struct anv_pipeline_binding surface_to_descriptor[256];
- struct anv_pipeline_binding sampler_to_descriptor[256];
-
- struct anv_pipeline_bind_map map = {
- .surface_to_descriptor = surface_to_descriptor,
- .sampler_to_descriptor = sampler_to_descriptor
- };
-
void *mem_ctx = ralloc_context(NULL);
- nir_shader *nir = anv_pipeline_compile(pipeline, mem_ctx, layout, stage,
- _data.base.base, );
- if (nir == NULL) {
- ralloc_free(mem_ctx);
- return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
- }
-
- anv_fill_binding_table(_data.base.base, 0);
+ anv_fill_binding_table(>prog_data.vs.base.base, 0);
brw_compute_vue_map(>device->info,
- _data.base.vue_map,
- nir->info.outputs_written,
- nir->info.separate_shader);
+ >prog_data.vs.base.vue_map,
+ stage->nir->info.outputs_written,
+ stage->nir->info.separate_shader);
const unsigned *shader_code =
brw_compile_vs(compiler, NULL, mem_ctx, >key.vs,
-_data, nir, -1, NULL);
+>prog_data.vs, stage->nir, -1, NULL);
if (shader_code == NULL) {
ralloc_free(mem_ctx);
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
}
- unsigned code_size = prog_data.base.base.program_size;
+ unsigned code_size = stage->prog_data.vs.base.base.program_size;
bin = anv_device_upload_kernel(pipeline->device, cache,
>cache_key,
sizeof(stage->cache_key),
shader_code, code_size,
- nir->constant_data,
- nir->constant_data_size,
- _data.base.base, sizeof(prog_data),
- );
+ stage->nir->constant_data,
+ stage->nir->constant_data_size,
+ >prog_data.base,
+ sizeof(stage->prog_data.vs),
+ >bind_map);
if (!bin) {
ralloc_free(mem_ctx);
return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
@@ -654,7 +644,6 @@ merge_tess_info(struct shader_info *tes_info,
static VkResult
anv_pipeline_compile_tcs_tes(struct anv_pipeline *pipeline,
struct anv_pipeline_cache *cache,
- const VkGraphicsPipelineCreateInfo *info,
struct anv_pipeline_stage *tcs_stage,
struct anv_pipeline_stage *tes_stage)
{
@@ -664,85 +653,60 @@ anv_pipeline_compile_tcs_tes(struct anv_pipeline
*pipeline,
struct anv_shader_bin *tcs_bin = NULL;
struct anv_shader_bin *tes_bin = NULL;
- ANV_FROM_HANDLE(anv_pipeline_layout, layout, info->layout);
-
if (tcs_bin == NULL || tes_bin == NULL) {
- struct brw_tcs_prog_data tcs_prog_data = {};
- struct brw_tes_prog_data tes_prog_data = {};
- struct anv_pipeline_binding tcs_surface_to_descriptor[256];
- struct anv_pipeline_binding tcs_sampler_to_descriptor[256];
- struct anv_pipeline_binding tes_surface_to_descriptor[256];
- struct anv_pipeline_binding tes_sampler_to_descriptor[256];
-
- struct anv_pipeline_bind_map tcs_map = {
-
