Re: [Mesa-dev] [PATCH 13/22] r600g: move CB_TARGET_MASK setup into new cb_misc_state
On Mon, Jul 09, 2012 at 09:15:46PM +0200, Marek Olšák wrote:
to remove some overhead from draw_vbo. This is a derived state.
BTW, I've got no idea how compute interacts with 3D here, but it should
use cb_misc_state, so that 3D and compute don't conflict.
The compute changes look fine to me. I just tested and there are no
regressions. I'll change the compute code to use cb_misc_state when I
get a change.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c |3 +--
.../drivers/r600/evergreen_compute_internal.c |2 +-
src/gallium/drivers/r600/evergreen_hw_context.c|2 --
src/gallium/drivers/r600/evergreen_state.c | 17 +
src/gallium/drivers/r600/r600_hw_context.c |2 +-
src/gallium/drivers/r600/r600_pipe.h |9 -
src/gallium/drivers/r600/r600_state.c | 17 +
src/gallium/drivers/r600/r600_state_common.c | 12 ++--
8 files changed, 51 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 40200ae..322994d 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -280,10 +280,9 @@ void evergreen_direct_dispatch(
struct evergreen_compute_resource* res = get_empty_res(rctx-cs_shader,
COMPUTE_RESOURCE_DISPATCH, 0);
-struct r600_pipe_state * cb_state =
rctx-states[R600_PIPE_STATE_FRAMEBUFFER];
/* Set CB_TARGET_MASK */
- r600_pipe_state_add_reg(cb_state, R_028238_CB_TARGET_MASK,
rctx-cb_target_mask);
+ evergreen_reg_set(res, R_028238_CB_TARGET_MASK,
rctx-compute_cb_target_mask);
evergreen_reg_set(res, R_008958_VGT_PRIMITIVE_TYPE,
V_008958_DI_PT_POINTLIST);
diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.c
b/src/gallium/drivers/r600/evergreen_compute_internal.c
index eb86a34..c5aad93 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.c
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.c
@@ -289,7 +289,7 @@ void evergreen_set_rat(
* XXX: I think this is a potential spot for bugs once we start doing
* GL interop. cb_target_mask may be modified in the 3D sections
* of this driver. */
- pipe-ctx-cb_target_mask |= (0xf (id * 4));
+ pipe-ctx-compute_cb_target_mask |= (0xf (id * 4));
/* Get the CB register writes for the RAT */
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index 2ab29c9..dcbe0a4 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -66,7 +66,6 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
{R_02823C_CB_SHADER_MASK, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
@@ -326,7 +325,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
{R_02823C_CB_SHADER_MASK, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 8b5f664..600e81f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1728,6 +1728,21 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
if (state-zsbuf) {
evergreen_polygon_offset_update(rctx);
}
+
+ if (rctx-cb_misc_state.nr_cbufs != state-nr_cbufs) {
+ rctx-cb_misc_state.nr_cbufs = state-nr_cbufs;
+ r600_atom_dirty(rctx, rctx-cb_misc_state.atom);
+ }
+}
+
+static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct
r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx-cs;
+ struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
+ unsigned fb_colormask = (1ULL ((unsigned)a-nr_cbufs * 4)) - 1;
+
+ r600_write_context_reg(cs, R_028238_CB_TARGET_MASK,
+a-blend_colormask fb_colormask);
}
static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct
r600_atom *atom)
@@ -1862,6 +1877,8 @@ static void evergreen_emit_ps_constant_buffer(struct
r600_context *rctx, struct
void evergreen_init_state_functions(struct r600_context *rctx)
{
+
[Mesa-dev] [PATCH 13/22] r600g: move CB_TARGET_MASK setup into new cb_misc_state
to remove some overhead from draw_vbo. This is a derived state.
BTW, I've got no idea how compute interacts with 3D here, but it should
use cb_misc_state, so that 3D and compute don't conflict.
---
src/gallium/drivers/r600/evergreen_compute.c |3 +--
.../drivers/r600/evergreen_compute_internal.c |2 +-
src/gallium/drivers/r600/evergreen_hw_context.c|2 --
src/gallium/drivers/r600/evergreen_state.c | 17 +
src/gallium/drivers/r600/r600_hw_context.c |2 +-
src/gallium/drivers/r600/r600_pipe.h |9 -
src/gallium/drivers/r600/r600_state.c | 17 +
src/gallium/drivers/r600/r600_state_common.c | 12 ++--
8 files changed, 51 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 40200ae..322994d 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -280,10 +280,9 @@ void evergreen_direct_dispatch(
struct evergreen_compute_resource* res = get_empty_res(rctx-cs_shader,
COMPUTE_RESOURCE_DISPATCH, 0);
-struct r600_pipe_state * cb_state =
rctx-states[R600_PIPE_STATE_FRAMEBUFFER];
/* Set CB_TARGET_MASK */
- r600_pipe_state_add_reg(cb_state, R_028238_CB_TARGET_MASK,
rctx-cb_target_mask);
+ evergreen_reg_set(res, R_028238_CB_TARGET_MASK,
rctx-compute_cb_target_mask);
evergreen_reg_set(res, R_008958_VGT_PRIMITIVE_TYPE,
V_008958_DI_PT_POINTLIST);
diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.c
b/src/gallium/drivers/r600/evergreen_compute_internal.c
index eb86a34..c5aad93 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.c
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.c
@@ -289,7 +289,7 @@ void evergreen_set_rat(
* XXX: I think this is a potential spot for bugs once we start doing
* GL interop. cb_target_mask may be modified in the 3D sections
* of this driver. */
- pipe-ctx-cb_target_mask |= (0xf (id * 4));
+ pipe-ctx-compute_cb_target_mask |= (0xf (id * 4));
/* Get the CB register writes for the RAT */
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index 2ab29c9..dcbe0a4 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -66,7 +66,6 @@ static const struct r600_reg evergreen_context_reg_list[] = {
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
{R_02823C_CB_SHADER_MASK, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
@@ -326,7 +325,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028204_PA_SC_WINDOW_SCISSOR_TL, 0, 0},
{R_028208_PA_SC_WINDOW_SCISSOR_BR, 0, 0},
{R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0, 0},
- {R_028238_CB_TARGET_MASK, 0, 0},
{R_02823C_CB_SHADER_MASK, 0, 0},
{R_028250_PA_SC_VPORT_SCISSOR_0_TL, 0, 0},
{R_028254_PA_SC_VPORT_SCISSOR_0_BR, 0, 0},
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 8b5f664..600e81f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1728,6 +1728,21 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
if (state-zsbuf) {
evergreen_polygon_offset_update(rctx);
}
+
+ if (rctx-cb_misc_state.nr_cbufs != state-nr_cbufs) {
+ rctx-cb_misc_state.nr_cbufs = state-nr_cbufs;
+ r600_atom_dirty(rctx, rctx-cb_misc_state.atom);
+ }
+}
+
+static void evergreen_emit_cb_misc_state(struct r600_context *rctx, struct
r600_atom *atom)
+{
+ struct radeon_winsys_cs *cs = rctx-cs;
+ struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
+ unsigned fb_colormask = (1ULL ((unsigned)a-nr_cbufs * 4)) - 1;
+
+ r600_write_context_reg(cs, R_028238_CB_TARGET_MASK,
+ a-blend_colormask fb_colormask);
}
static void evergreen_emit_db_misc_state(struct r600_context *rctx, struct
r600_atom *atom)
@@ -1862,6 +1877,8 @@ static void evergreen_emit_ps_constant_buffer(struct
r600_context *rctx, struct
void evergreen_init_state_functions(struct r600_context *rctx)
{
+ r600_init_atom(rctx-cb_misc_state.atom, evergreen_emit_cb_misc_state,
0, 0);
+ r600_atom_dirty(rctx, rctx-cb_misc_state.atom);
r600_init_atom(rctx-db_misc_state.atom, evergreen_emit_db_misc_state,
6, 0);
r600_atom_dirty(rctx, rctx-db_misc_state.atom);
