Re: [Mesa-dev] [PATCH 22/35] i965: Port gen6+ 3DSTATE_VS to genxml.

2017-04-21 Thread Rafael Antognolli
On Thu, Apr 20, 2017 at 09:55:56AM -0700, Kristian H. Kristensen wrote:
> Rafael Antognolli  writes:
> 
> > Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
> > structs from genxml.
> >
> > Signed-off-by: Rafael Antognolli 
> > ---
> >  src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
> >  src/mesa/drivers/dri/i965/brw_state.h |   3 +-
> >  src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +---
> >  src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +---
> >  src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +
> >  src/mesa/drivers/dri/i965/genX_state_upload.c | 110 +-
> >  6 files changed, 107 insertions(+), 304 deletions(-)
> >  delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
> >  delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c
> >
> > diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
> > b/src/mesa/drivers/dri/i965/Makefile.sources
> > index 0f893d6..eec63f8 100644
> > --- a/src/mesa/drivers/dri/i965/Makefile.sources
> > +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> > @@ -102,7 +102,6 @@ i965_FILES = \
> > gen7_te_state.c \
> > gen7_urb.c \
> > gen7_viewport_state.c \
> > -   gen7_vs_state.c \
> > gen7_wm_surface_state.c \
> > gen8_blend_state.c \
> > gen8_depth_state.c \
> > @@ -113,7 +112,6 @@ i965_FILES = \
> > gen8_multisample_state.c \
> > gen8_surface_state.c \
> > gen8_viewport_state.c \
> > -   gen8_vs_state.c \
> > hsw_queryobj.c \
> > hsw_sol.c \
> > intel_batchbuffer.c \
> > diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
> > b/src/mesa/drivers/dri/i965/brw_state.h
> > index 71ec9fb..306bfc5 100644
> > --- a/src/mesa/drivers/dri/i965/brw_state.h
> > +++ b/src/mesa/drivers/dri/i965/brw_state.h
> > @@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
> >  extern const struct brw_tracked_state gen6_urb;
> >  extern const struct brw_tracked_state gen6_viewport_state;
> >  extern const struct brw_tracked_state gen6_vs_push_constants;
> > -extern const struct brw_tracked_state gen6_vs_state;
> >  extern const struct brw_tracked_state gen6_wm_push_constants;
> >  extern const struct brw_tracked_state gen7_depthbuffer;
> >  extern const struct brw_tracked_state gen7_ds_state;
> > @@ -136,7 +135,6 @@ extern const struct brw_tracked_state 
> > gen7_sf_clip_viewport;
> >  extern const struct brw_tracked_state gen7_te_state;
> >  extern const struct brw_tracked_state gen7_tes_push_constants;
> >  extern const struct brw_tracked_state gen7_urb;
> > -extern const struct brw_tracked_state gen7_vs_state;
> >  extern const struct brw_tracked_state haswell_cut_index;
> >  extern const struct brw_tracked_state gen8_blend_state;
> >  extern const struct brw_tracked_state gen8_ds_state;
> > @@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
> >  extern const struct brw_tracked_state gen8_sf_clip_viewport;
> >  extern const struct brw_tracked_state gen8_vertices;
> >  extern const struct brw_tracked_state gen8_vf_topology;
> > -extern const struct brw_tracked_state gen8_vs_state;
> >  extern const struct brw_tracked_state brw_cs_work_groups_surface;
> >  
> >  static inline bool
> > diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
> > b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > index 17b8118..b2d2306 100644
> > --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> > @@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = 
> > {
> > },
> > .emit = gen6_upload_vs_push_constants,
> >  };
> > -
> > -static void
> > -upload_vs_state(struct brw_context *brw)
> > -{
> > -   const struct gen_device_info *devinfo = >screen->devinfo;
> > -   const struct brw_stage_state *stage_state = >vs.base;
> > -   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
> > -   const struct brw_vue_prog_data *vue_prog_data =
> > -  brw_vue_prog_data(stage_state->prog_data);
> > -   uint32_t floating_point_mode = 0;
> > -
> > -   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
> > -* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
> > -*
> > -*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
> > -*   command that causes the VS Function Enable to toggle. Pipeline
> > -*   flush can be executed by sending a PIPE_CONTROL command with CS
> > -*   stall bit set and a post sync operation.
> > -*
> > -* We've already done such a flush at the start of state upload, so we
> > -* don't need to do another one here.
> > -*/
> > -
> > -   if (stage_state->push_const_size == 0) {
> > -  /* Disable the push constant buffers. */
> > -  BEGIN_BATCH(5);
> > -  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
> > -  OUT_BATCH(0);
> > -  OUT_BATCH(0);
> > -  OUT_BATCH(0);
> 

Re: [Mesa-dev] [PATCH 22/35] i965: Port gen6+ 3DSTATE_VS to genxml.

2017-04-20 Thread Kristian H. Kristensen
Rafael Antognolli  writes:

> Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
> structs from genxml.
>
> Signed-off-by: Rafael Antognolli 
> ---
>  src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
>  src/mesa/drivers/dri/i965/brw_state.h |   3 +-
>  src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +---
>  src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +---
>  src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +
>  src/mesa/drivers/dri/i965/genX_state_upload.c | 110 +-
>  6 files changed, 107 insertions(+), 304 deletions(-)
>  delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
>  delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c
>
> diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
> b/src/mesa/drivers/dri/i965/Makefile.sources
> index 0f893d6..eec63f8 100644
> --- a/src/mesa/drivers/dri/i965/Makefile.sources
> +++ b/src/mesa/drivers/dri/i965/Makefile.sources
> @@ -102,7 +102,6 @@ i965_FILES = \
>   gen7_te_state.c \
>   gen7_urb.c \
>   gen7_viewport_state.c \
> - gen7_vs_state.c \
>   gen7_wm_surface_state.c \
>   gen8_blend_state.c \
>   gen8_depth_state.c \
> @@ -113,7 +112,6 @@ i965_FILES = \
>   gen8_multisample_state.c \
>   gen8_surface_state.c \
>   gen8_viewport_state.c \
> - gen8_vs_state.c \
>   hsw_queryobj.c \
>   hsw_sol.c \
>   intel_batchbuffer.c \
> diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
> b/src/mesa/drivers/dri/i965/brw_state.h
> index 71ec9fb..306bfc5 100644
> --- a/src/mesa/drivers/dri/i965/brw_state.h
> +++ b/src/mesa/drivers/dri/i965/brw_state.h
> @@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
>  extern const struct brw_tracked_state gen6_urb;
>  extern const struct brw_tracked_state gen6_viewport_state;
>  extern const struct brw_tracked_state gen6_vs_push_constants;
> -extern const struct brw_tracked_state gen6_vs_state;
>  extern const struct brw_tracked_state gen6_wm_push_constants;
>  extern const struct brw_tracked_state gen7_depthbuffer;
>  extern const struct brw_tracked_state gen7_ds_state;
> @@ -136,7 +135,6 @@ extern const struct brw_tracked_state 
> gen7_sf_clip_viewport;
>  extern const struct brw_tracked_state gen7_te_state;
>  extern const struct brw_tracked_state gen7_tes_push_constants;
>  extern const struct brw_tracked_state gen7_urb;
> -extern const struct brw_tracked_state gen7_vs_state;
>  extern const struct brw_tracked_state haswell_cut_index;
>  extern const struct brw_tracked_state gen8_blend_state;
>  extern const struct brw_tracked_state gen8_ds_state;
> @@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
>  extern const struct brw_tracked_state gen8_sf_clip_viewport;
>  extern const struct brw_tracked_state gen8_vertices;
>  extern const struct brw_tracked_state gen8_vf_topology;
> -extern const struct brw_tracked_state gen8_vs_state;
>  extern const struct brw_tracked_state brw_cs_work_groups_surface;
>  
>  static inline bool
> diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
> b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> index 17b8118..b2d2306 100644
> --- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
> +++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
> @@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = {
> },
> .emit = gen6_upload_vs_push_constants,
>  };
> -
> -static void
> -upload_vs_state(struct brw_context *brw)
> -{
> -   const struct gen_device_info *devinfo = >screen->devinfo;
> -   const struct brw_stage_state *stage_state = >vs.base;
> -   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
> -   const struct brw_vue_prog_data *vue_prog_data =
> -  brw_vue_prog_data(stage_state->prog_data);
> -   uint32_t floating_point_mode = 0;
> -
> -   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
> -* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
> -*
> -*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
> -*   command that causes the VS Function Enable to toggle. Pipeline
> -*   flush can be executed by sending a PIPE_CONTROL command with CS
> -*   stall bit set and a post sync operation.
> -*
> -* We've already done such a flush at the start of state upload, so we
> -* don't need to do another one here.
> -*/
> -
> -   if (stage_state->push_const_size == 0) {
> -  /* Disable the push constant buffers. */
> -  BEGIN_BATCH(5);
> -  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
> -  OUT_BATCH(0);
> -  OUT_BATCH(0);
> -  OUT_BATCH(0);
> -  OUT_BATCH(0);
> -  ADVANCE_BATCH();
> -   } else {
> -  BEGIN_BATCH(5);
> -  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
> - GEN6_CONSTANT_BUFFER_0_ENABLE |
> - (5 - 2));
> -  /* Pointer to the VS constant buffer.  

[Mesa-dev] [PATCH 22/35] i965: Port gen6+ 3DSTATE_VS to genxml.

2017-04-19 Thread Rafael Antognolli
Emit 3DSTATE_VS on Gen6+ using brw_batch_emit helper, that uses pack
structs from genxml.

Signed-off-by: Rafael Antognolli 
---
 src/mesa/drivers/dri/i965/Makefile.sources|   2 +-
 src/mesa/drivers/dri/i965/brw_state.h |   3 +-
 src/mesa/drivers/dri/i965/gen6_vs_state.c | 113 +---
 src/mesa/drivers/dri/i965/gen7_vs_state.c |  87 +---
 src/mesa/drivers/dri/i965/gen8_vs_state.c |  96 +
 src/mesa/drivers/dri/i965/genX_state_upload.c | 110 +-
 6 files changed, 107 insertions(+), 304 deletions(-)
 delete mode 100644 src/mesa/drivers/dri/i965/gen7_vs_state.c
 delete mode 100644 src/mesa/drivers/dri/i965/gen8_vs_state.c

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 0f893d6..eec63f8 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -102,7 +102,6 @@ i965_FILES = \
gen7_te_state.c \
gen7_urb.c \
gen7_viewport_state.c \
-   gen7_vs_state.c \
gen7_wm_surface_state.c \
gen8_blend_state.c \
gen8_depth_state.c \
@@ -113,7 +112,6 @@ i965_FILES = \
gen8_multisample_state.c \
gen8_surface_state.c \
gen8_viewport_state.c \
-   gen8_vs_state.c \
hsw_queryobj.c \
hsw_sol.c \
intel_batchbuffer.c \
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 71ec9fb..306bfc5 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -123,7 +123,6 @@ extern const struct brw_tracked_state gen6_sf_vp;
 extern const struct brw_tracked_state gen6_urb;
 extern const struct brw_tracked_state gen6_viewport_state;
 extern const struct brw_tracked_state gen6_vs_push_constants;
-extern const struct brw_tracked_state gen6_vs_state;
 extern const struct brw_tracked_state gen6_wm_push_constants;
 extern const struct brw_tracked_state gen7_depthbuffer;
 extern const struct brw_tracked_state gen7_ds_state;
@@ -136,7 +135,6 @@ extern const struct brw_tracked_state gen7_sf_clip_viewport;
 extern const struct brw_tracked_state gen7_te_state;
 extern const struct brw_tracked_state gen7_tes_push_constants;
 extern const struct brw_tracked_state gen7_urb;
-extern const struct brw_tracked_state gen7_vs_state;
 extern const struct brw_tracked_state haswell_cut_index;
 extern const struct brw_tracked_state gen8_blend_state;
 extern const struct brw_tracked_state gen8_ds_state;
@@ -149,7 +147,6 @@ extern const struct brw_tracked_state gen8_ps_blend;
 extern const struct brw_tracked_state gen8_sf_clip_viewport;
 extern const struct brw_tracked_state gen8_vertices;
 extern const struct brw_tracked_state gen8_vf_topology;
-extern const struct brw_tracked_state gen8_vs_state;
 extern const struct brw_tracked_state brw_cs_work_groups_surface;
 
 static inline bool
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c 
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 17b8118..b2d2306 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -68,116 +68,3 @@ const struct brw_tracked_state gen6_vs_push_constants = {
},
.emit = gen6_upload_vs_push_constants,
 };
-
-static void
-upload_vs_state(struct brw_context *brw)
-{
-   const struct gen_device_info *devinfo = >screen->devinfo;
-   const struct brw_stage_state *stage_state = >vs.base;
-   const struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-   const struct brw_vue_prog_data *vue_prog_data =
-  brw_vue_prog_data(stage_state->prog_data);
-   uint32_t floating_point_mode = 0;
-
-   /* From the BSpec, 3D Pipeline > Geometry > Vertex Shader > State,
-* 3DSTATE_VS, Dword 5.0 "VS Function Enable":
-*
-*   [DevSNB] A pipeline flush must be programmed prior to a 3DSTATE_VS
-*   command that causes the VS Function Enable to toggle. Pipeline
-*   flush can be executed by sending a PIPE_CONTROL command with CS
-*   stall bit set and a post sync operation.
-*
-* We've already done such a flush at the start of state upload, so we
-* don't need to do another one here.
-*/
-
-   if (stage_state->push_const_size == 0) {
-  /* Disable the push constant buffers. */
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (5 - 2));
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  ADVANCE_BATCH();
-   } else {
-  BEGIN_BATCH(5);
-  OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 |
-   GEN6_CONSTANT_BUFFER_0_ENABLE |
-   (5 - 2));
-  /* Pointer to the VS constant buffer.  Covered by the set of
-   * state flags from gen6_upload_vs_constants
-   */
-  OUT_BATCH(stage_state->push_const_offset +
-   stage_state->push_const_size - 1);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-  OUT_BATCH(0);
-