Re: [Mesa-dev] [PATCH 3/4] intel/tools: Break aub file writing into a helper
Reviewed-by: Lionel Landwerlin
On 18/07/18 00:05, Jason Ekstrand wrote:
---
src/intel/tools/aub_write.c | 764 +++
src/intel/tools/aub_write.h | 96
src/intel/tools/intel_dump_gpu.c | 762 +-
src/intel/tools/meson.build | 2 +-
4 files changed, 862 insertions(+), 762 deletions(-)
create mode 100644 src/intel/tools/aub_write.c
create mode 100644 src/intel/tools/aub_write.h
diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c
new file mode 100644
index 000..2ec045830a8
--- /dev/null
+++ b/src/intel/tools/aub_write.c
@@ -0,0 +1,764 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "aub_write.h"
+
+#include
+#include
+#include
+#include
+
+#include "i915_drm.h"
+#include "intel_aub.h"
+
+#ifndef ALIGN
+#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
+#endif
+
+#define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
+#define MI_LRI_FORCE_POSTED (1<<12)
+
+#define MI_BATCH_NON_SECURE_I965 (1 << 8)
+
+#define MI_BATCH_BUFFER_END (0xA << 23)
+
+#define min(a, b) ({\
+ __typeof(a) _a = (a); \
+ __typeof(b) _b = (b); \
+ _a < _b ? _a : _b; \
+ })
+
+#define max(a, b) ({\
+ __typeof(a) _a = (a); \
+ __typeof(b) _b = (b); \
+ _a > _b ? _a : _b; \
+ })
+
+#define HWS_PGA_RCSUNIT 0x02080
+#define HWS_PGA_VCSUNIT0 0x12080
+#define HWS_PGA_BCSUNIT 0x22080
+
+#define GFX_MODE_RCSUNIT 0x0229c
+#define GFX_MODE_VCSUNIT0 0x1229c
+#define GFX_MODE_BCSUNIT 0x2229c
+
+#define EXECLIST_SUBMITPORT_RCSUNIT 0x02230
+#define EXECLIST_SUBMITPORT_VCSUNIT0 0x12230
+#define EXECLIST_SUBMITPORT_BCSUNIT 0x22230
+
+#define EXECLIST_STATUS_RCSUNIT 0x02234
+#define EXECLIST_STATUS_VCSUNIT0 0x12234
+#define EXECLIST_STATUS_BCSUNIT 0x22234
+
+#define EXECLIST_SQ_CONTENTS0_RCSUNIT 0x02510
+#define EXECLIST_SQ_CONTENTS0_VCSUNIT0 0x12510
+#define EXECLIST_SQ_CONTENTS0_BCSUNIT 0x22510
+
+#define EXECLIST_CONTROL_RCSUNIT 0x02550
+#define EXECLIST_CONTROL_VCSUNIT0 0x12550
+#define EXECLIST_CONTROL_BCSUNIT 0x22550
+
+#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
+
+#define PTE_SIZE 4
+#define GEN8_PTE_SIZE 8
+
+#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
+#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
+
+#define RING_SIZE (1 * 4096)
+#define PPHWSP_SIZE (1 * 4096)
+#define GEN11_LR_CONTEXT_RENDER_SIZE(14 * 4096)
+#define GEN10_LR_CONTEXT_RENDER_SIZE(19 * 4096)
+#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
+#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
+#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
+
+
+#define STATIC_GGTT_MAP_START 0
+
+#define RENDER_RING_ADDR STATIC_GGTT_MAP_START
+#define RENDER_CONTEXT_ADDR (RENDER_RING_ADDR + RING_SIZE)
+
+#define BLITTER_RING_ADDR (RENDER_CONTEXT_ADDR + PPHWSP_SIZE +
GEN10_LR_CONTEXT_RENDER_SIZE)
+#define BLITTER_CONTEXT_ADDR (BLITTER_RING_ADDR + RING_SIZE)
+
+#define VIDEO_RING_ADDR (BLITTER_CONTEXT_ADDR + PPHWSP_SIZE +
GEN8_LR_CONTEXT_OTHER_SIZE)
+#define VIDEO_CONTEXT_ADDR (VIDEO_RING_ADDR + RING_SIZE)
+
+#define STATIC_GGTT_MAP_END (VIDEO_CONTEXT_ADDR + PPHWSP_SIZE +
GEN8_LR_CONTEXT_OTHER_SIZE)
+#define STATIC_GGTT_MAP_SIZE (STATIC_GGTT_MAP_END - STATIC_GGTT_MAP_START)
+
+#define PML4_PHYS_ADDR ((uint64_t)(STATIC_GGTT_MAP_END))
+
+#define CONTEXT_FLAGS (0x339) /* Normal Priority | L3-LLC Coherency |
+ * PPGTT Enabled |
+ * Legacy Context with 64 bit VA support |
+ * Valid
+ */
+
+
[Mesa-dev] [PATCH 3/4] intel/tools: Break aub file writing into a helper
---
src/intel/tools/aub_write.c | 764 +++
src/intel/tools/aub_write.h | 96
src/intel/tools/intel_dump_gpu.c | 762 +-
src/intel/tools/meson.build | 2 +-
4 files changed, 862 insertions(+), 762 deletions(-)
create mode 100644 src/intel/tools/aub_write.c
create mode 100644 src/intel/tools/aub_write.h
diff --git a/src/intel/tools/aub_write.c b/src/intel/tools/aub_write.c
new file mode 100644
index 000..2ec045830a8
--- /dev/null
+++ b/src/intel/tools/aub_write.c
@@ -0,0 +1,764 @@
+/*
+ * Copyright © 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "aub_write.h"
+
+#include
+#include
+#include
+#include
+
+#include "i915_drm.h"
+#include "intel_aub.h"
+
+#ifndef ALIGN
+#define ALIGN(x, y) (((x) + (y)-1) & ~((y)-1))
+#endif
+
+#define MI_LOAD_REGISTER_IMM_n(n) ((0x22 << 23) | (2 * (n) - 1))
+#define MI_LRI_FORCE_POSTED (1<<12)
+
+#define MI_BATCH_NON_SECURE_I965 (1 << 8)
+
+#define MI_BATCH_BUFFER_END (0xA << 23)
+
+#define min(a, b) ({\
+ __typeof(a) _a = (a); \
+ __typeof(b) _b = (b); \
+ _a < _b ? _a : _b; \
+ })
+
+#define max(a, b) ({\
+ __typeof(a) _a = (a); \
+ __typeof(b) _b = (b); \
+ _a > _b ? _a : _b; \
+ })
+
+#define HWS_PGA_RCSUNIT 0x02080
+#define HWS_PGA_VCSUNIT0 0x12080
+#define HWS_PGA_BCSUNIT 0x22080
+
+#define GFX_MODE_RCSUNIT 0x0229c
+#define GFX_MODE_VCSUNIT0 0x1229c
+#define GFX_MODE_BCSUNIT 0x2229c
+
+#define EXECLIST_SUBMITPORT_RCSUNIT 0x02230
+#define EXECLIST_SUBMITPORT_VCSUNIT0 0x12230
+#define EXECLIST_SUBMITPORT_BCSUNIT 0x22230
+
+#define EXECLIST_STATUS_RCSUNIT 0x02234
+#define EXECLIST_STATUS_VCSUNIT0 0x12234
+#define EXECLIST_STATUS_BCSUNIT 0x22234
+
+#define EXECLIST_SQ_CONTENTS0_RCSUNIT 0x02510
+#define EXECLIST_SQ_CONTENTS0_VCSUNIT0 0x12510
+#define EXECLIST_SQ_CONTENTS0_BCSUNIT 0x22510
+
+#define EXECLIST_CONTROL_RCSUNIT 0x02550
+#define EXECLIST_CONTROL_VCSUNIT0 0x12550
+#define EXECLIST_CONTROL_BCSUNIT 0x22550
+
+#define MEMORY_MAP_SIZE (64 /* MiB */ * 1024 * 1024)
+
+#define PTE_SIZE 4
+#define GEN8_PTE_SIZE 8
+
+#define NUM_PT_ENTRIES (ALIGN(MEMORY_MAP_SIZE, 4096) / 4096)
+#define PT_SIZE ALIGN(NUM_PT_ENTRIES * GEN8_PTE_SIZE, 4096)
+
+#define RING_SIZE (1 * 4096)
+#define PPHWSP_SIZE (1 * 4096)
+#define GEN11_LR_CONTEXT_RENDER_SIZE(14 * 4096)
+#define GEN10_LR_CONTEXT_RENDER_SIZE(19 * 4096)
+#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * 4096)
+#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * 4096)
+#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * 4096)
+
+
+#define STATIC_GGTT_MAP_START 0
+
+#define RENDER_RING_ADDR STATIC_GGTT_MAP_START
+#define RENDER_CONTEXT_ADDR (RENDER_RING_ADDR + RING_SIZE)
+
+#define BLITTER_RING_ADDR (RENDER_CONTEXT_ADDR + PPHWSP_SIZE +
GEN10_LR_CONTEXT_RENDER_SIZE)
+#define BLITTER_CONTEXT_ADDR (BLITTER_RING_ADDR + RING_SIZE)
+
+#define VIDEO_RING_ADDR (BLITTER_CONTEXT_ADDR + PPHWSP_SIZE +
GEN8_LR_CONTEXT_OTHER_SIZE)
+#define VIDEO_CONTEXT_ADDR (VIDEO_RING_ADDR + RING_SIZE)
+
+#define STATIC_GGTT_MAP_END (VIDEO_CONTEXT_ADDR + PPHWSP_SIZE +
GEN8_LR_CONTEXT_OTHER_SIZE)
+#define STATIC_GGTT_MAP_SIZE (STATIC_GGTT_MAP_END - STATIC_GGTT_MAP_START)
+
+#define PML4_PHYS_ADDR ((uint64_t)(STATIC_GGTT_MAP_END))
+
+#define CONTEXT_FLAGS (0x339) /* Normal Priority | L3-LLC Coherency |
+ * PPGTT Enabled |
+ * Legacy Context with 64 bit VA support |
+ * Valid
+ */
+
+#define RENDER_CONTEXT_DESCRIPTOR ((uint64_t)1 << 62 | RENDER_CONTEXT_ADDR |
CON
