Both gen6 and gen7+ were moved into the same function, but the code is still quite split.
In order to make both functions have the same signature, I moved the logic from upload_urb on gen6 that sets gs_size to vs_size into genX(upload_urb), so we don't have to pass gs_size to that function anymore. Signed-off-by: Rafael Antognolli <rafael.antogno...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.h | 10 +- src/mesa/drivers/dri/i965/brw_state.h | 2 - src/mesa/drivers/dri/i965/gen6_urb.c | 152 --------------------- src/mesa/drivers/dri/i965/gen7_urb.c | 92 ------------- src/mesa/drivers/dri/i965/genX_blorp_exec.c | 6 +- src/mesa/drivers/dri/i965/genX_state_upload.c | 181 +++++++++++++++++++++++++- 6 files changed, 184 insertions(+), 259 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 1f61e5f..505068a 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1551,13 +1551,6 @@ gen7_emit_push_constant_state(struct brw_context *brw, unsigned vs_size, unsigned hs_size, unsigned ds_size, unsigned gs_size, unsigned fs_size); -void -gen6_upload_urb(struct brw_context *brw, unsigned vs_size, - bool gs_present, unsigned gs_size); -void -gen7_upload_urb(struct brw_context *brw, unsigned vs_size, - bool gs_present, bool tess_present); - #define GENX_DECL(_ret, _name, ...) \ _ret gen4_##_name(__VA_ARGS__); \ _ret gen45_##_name(__VA_ARGS__); \ @@ -1569,6 +1562,9 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size, _ret gen9_##_name(__VA_ARGS__); \ typedef _ret (* _name ## _ptr)(__VA_ARGS__); +GENX_DECL(void, upload_urb, struct brw_context *brw, unsigned vs_size, + bool gs_present, bool tess_present); + /* brw_reset.c */ extern GLenum brw_get_graphics_reset_status(struct gl_context *ctx); diff --git a/src/mesa/drivers/dri/i965/brw_state.h b/src/mesa/drivers/dri/i965/brw_state.h index 954969c..de0fa0b 100644 --- a/src/mesa/drivers/dri/i965/brw_state.h +++ b/src/mesa/drivers/dri/i965/brw_state.h @@ -106,11 +106,9 @@ extern const struct brw_tracked_state gen6_renderbuffer_surfaces; extern const struct brw_tracked_state gen6_sampler_state; extern const struct brw_tracked_state gen6_sol_surface; extern const struct brw_tracked_state gen6_sf_vp; -extern const struct brw_tracked_state gen6_urb; extern const struct brw_tracked_state gen7_depthbuffer; extern const struct brw_tracked_state gen7_l3_state; extern const struct brw_tracked_state gen7_push_constant_space; -extern const struct brw_tracked_state gen7_urb; extern const struct brw_tracked_state gen8_pma_fix; extern const struct brw_tracked_state brw_cs_work_groups_surface; diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c b/src/mesa/drivers/dri/i965/gen6_urb.c index 8938035..e69de29 100644 --- a/src/mesa/drivers/dri/i965/gen6_urb.c +++ b/src/mesa/drivers/dri/i965/gen6_urb.c @@ -1,152 +0,0 @@ -/* - * Copyright © 2009 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - * - * Authors: - * Eric Anholt <e...@anholt.net> - * - */ - -#include "main/macros.h" -#include "intel_batchbuffer.h" -#include "brw_context.h" -#include "brw_state.h" -#include "brw_defines.h" - -/** - * When the GS is not in use, we assign the entire URB space to the VS. When - * the GS is in use, we split the URB space evenly between the VS and the GS. - * This is not ideal, but it's simple. - * - * URB size / 2 URB size / 2 - * _____________-______________ _____________-______________ - * / \ / \ - * +-------------------------------------------------------------+ - * | Vertex Shader Entries | Geometry Shader Entries | - * +-------------------------------------------------------------+ - * - * Sandybridge GT1 has 32kB of URB space, while GT2 has 64kB. - * (See the Sandybridge PRM, Volume 2, Part 1, Section 1.4.7: 3DSTATE_URB.) - */ -void -gen6_upload_urb(struct brw_context *brw, unsigned vs_size, - bool gs_present, unsigned gs_size) -{ - int nr_vs_entries, nr_gs_entries; - int total_urb_size = brw->urb.size * 1024; /* in bytes */ - const struct gen_device_info *devinfo = &brw->screen->devinfo; - - /* Calculate how many entries fit in each stage's section of the URB */ - if (gs_present) { - nr_vs_entries = (total_urb_size/2) / (vs_size * 128); - nr_gs_entries = (total_urb_size/2) / (gs_size * 128); - } else { - nr_vs_entries = total_urb_size / (vs_size * 128); - nr_gs_entries = 0; - } - - /* Then clamp to the maximum allowed by the hardware */ - if (nr_vs_entries > devinfo->urb.max_entries[MESA_SHADER_VERTEX]) - nr_vs_entries = devinfo->urb.max_entries[MESA_SHADER_VERTEX]; - - if (nr_gs_entries > devinfo->urb.max_entries[MESA_SHADER_GEOMETRY]) - nr_gs_entries = devinfo->urb.max_entries[MESA_SHADER_GEOMETRY]; - - /* Finally, both must be a multiple of 4 (see 3DSTATE_URB in the PRM). */ - brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); - brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); - - assert(brw->urb.nr_vs_entries >= - devinfo->urb.min_entries[MESA_SHADER_VERTEX]); - assert(brw->urb.nr_vs_entries % 4 == 0); - assert(brw->urb.nr_gs_entries % 4 == 0); - assert(vs_size >= 1 && vs_size <= 5); - assert(gs_size >= 1 && gs_size <= 5); - - BEGIN_BATCH(3); - OUT_BATCH(_3DSTATE_URB << 16 | (3 - 2)); - OUT_BATCH(((vs_size - 1) << GEN6_URB_VS_SIZE_SHIFT) | - ((brw->urb.nr_vs_entries) << GEN6_URB_VS_ENTRIES_SHIFT)); - OUT_BATCH(((gs_size - 1) << GEN6_URB_GS_SIZE_SHIFT) | - ((brw->urb.nr_gs_entries) << GEN6_URB_GS_ENTRIES_SHIFT)); - ADVANCE_BATCH(); - - /* From the PRM Volume 2 part 1, section 1.4.7: - * - * Because of a urb corruption caused by allocating a previous gsunit’s - * urb entry to vsunit software is required to send a "GS NULL - * Fence"(Send URB fence with VS URB size == 1 and GS URB size == 0) plus - * a dummy DRAW call before any case where VS will be taking over GS URB - * space. - * - * It is not clear exactly what this means ("URB fence" is a command that - * doesn't exist on Gen6). So for now we just do a full pipeline flush as - * a workaround. - */ - if (brw->urb.gs_present && !gs_present) - brw_emit_mi_flush(brw); - brw->urb.gs_present = gs_present; -} - -static void -upload_urb(struct brw_context *brw) -{ - /* BRW_NEW_VS_PROG_DATA */ - const struct brw_vue_prog_data *vs_vue_prog_data = - brw_vue_prog_data(brw->vs.base.prog_data); - const unsigned vs_size = MAX2(vs_vue_prog_data->urb_entry_size, 1); - - /* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */ - const bool gs_present = brw->ff_gs.prog_active || brw->geometry_program; - - /* Whe using GS to do transform feedback only we use the same VUE layout for - * VS outputs and GS outputs (as it's what the SF and Clipper expect), so we - * can simply make the GS URB entry size the same as for the VS. This may - * technically be too large in cases where we have few vertex attributes and - * a lot of varyings, since the VS size is determined by the larger of the - * two. For now, it's safe. - * - * For user-provided GS the assumption above does not hold since the GS - * outputs can be different from the VS outputs. - */ - unsigned gs_size = vs_size; - if (brw->geometry_program) { - const struct brw_vue_prog_data *gs_vue_prog_data = - brw_vue_prog_data(brw->gs.base.prog_data); - gs_size = gs_vue_prog_data->urb_entry_size; - assert(gs_size >= 1); - } - - gen6_upload_urb(brw, vs_size, gs_present, gs_size); -} - -const struct brw_tracked_state gen6_urb = { - .dirty = { - .mesa = 0, - .brw = BRW_NEW_BLORP | - BRW_NEW_CONTEXT | - BRW_NEW_FF_GS_PROG_DATA | - BRW_NEW_GEOMETRY_PROGRAM | - BRW_NEW_GS_PROG_DATA | - BRW_NEW_VS_PROG_DATA, - }, - .emit = upload_urb, -}; diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index 028161d..3a08c90 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -152,95 +152,3 @@ const struct brw_tracked_state gen7_push_constant_space = { }, .emit = gen7_allocate_push_constants, }; - -static void -upload_urb(struct brw_context *brw) -{ - /* BRW_NEW_VS_PROG_DATA */ - const struct brw_vue_prog_data *vs_vue_prog_data = - brw_vue_prog_data(brw->vs.base.prog_data); - const unsigned vs_size = MAX2(vs_vue_prog_data->urb_entry_size, 1); - /* BRW_NEW_GS_PROG_DATA */ - const bool gs_present = brw->gs.base.prog_data; - /* BRW_NEW_TES_PROG_DATA */ - const bool tess_present = brw->tes.base.prog_data; - - gen7_upload_urb(brw, vs_size, gs_present, tess_present); -} - -void -gen7_upload_urb(struct brw_context *brw, unsigned vs_size, - bool gs_present, bool tess_present) -{ - const struct gen_device_info *devinfo = &brw->screen->devinfo; - const int push_size_kB = - (brw->gen >= 8 || (brw->is_haswell && brw->gt == 3)) ? 32 : 16; - - /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */ - struct brw_vue_prog_data *prog_data[4] = { - [MESA_SHADER_VERTEX] = - brw_vue_prog_data(brw->vs.base.prog_data), - [MESA_SHADER_TESS_CTRL] = - tess_present ? brw_vue_prog_data(brw->tcs.base.prog_data) : NULL, - [MESA_SHADER_TESS_EVAL] = - tess_present ? brw_vue_prog_data(brw->tes.base.prog_data) : NULL, - [MESA_SHADER_GEOMETRY] = - gs_present ? brw_vue_prog_data(brw->gs.base.prog_data) : NULL, - }; - - unsigned entry_size[4]; - entry_size[MESA_SHADER_VERTEX] = vs_size; - for (int i = MESA_SHADER_TESS_CTRL; i <= MESA_SHADER_GEOMETRY; i++) { - entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1; - } - - /* If we're just switching between programs with the same URB requirements, - * skip the rest of the logic. - */ - if (!(brw->ctx.NewDriverState & BRW_NEW_CONTEXT) && - !(brw->ctx.NewDriverState & BRW_NEW_URB_SIZE) && - brw->urb.vsize == entry_size[MESA_SHADER_VERTEX] && - brw->urb.gs_present == gs_present && - brw->urb.gsize == entry_size[MESA_SHADER_GEOMETRY] && - brw->urb.tess_present == tess_present && - brw->urb.hsize == entry_size[MESA_SHADER_TESS_CTRL] && - brw->urb.dsize == entry_size[MESA_SHADER_TESS_EVAL]) { - return; - } - brw->urb.vsize = entry_size[MESA_SHADER_VERTEX]; - brw->urb.gs_present = gs_present; - brw->urb.gsize = entry_size[MESA_SHADER_GEOMETRY]; - brw->urb.tess_present = tess_present; - brw->urb.hsize = entry_size[MESA_SHADER_TESS_CTRL]; - brw->urb.dsize = entry_size[MESA_SHADER_TESS_EVAL]; - - unsigned entries[4]; - unsigned start[4]; - gen_get_urb_config(devinfo, 1024 * push_size_kB, 1024 * brw->urb.size, - tess_present, gs_present, entry_size, entries, start); - - if (brw->gen == 7 && !brw->is_haswell && !brw->is_baytrail) - gen7_emit_vs_workaround_flush(brw); - - BEGIN_BATCH(8); - for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { - OUT_BATCH((_3DSTATE_URB_VS + i) << 16 | (2 - 2)); - OUT_BATCH(entries[i] | - ((entry_size[i] - 1) << GEN7_URB_ENTRY_SIZE_SHIFT) | - (start[i] << GEN7_URB_STARTING_ADDRESS_SHIFT)); - } - ADVANCE_BATCH(); -} - -const struct brw_tracked_state gen7_urb = { - .dirty = { - .mesa = 0, - .brw = BRW_NEW_CONTEXT | - BRW_NEW_URB_SIZE | - BRW_NEW_GS_PROG_DATA | - BRW_NEW_TCS_PROG_DATA | - BRW_NEW_TES_PROG_DATA | - BRW_NEW_VS_PROG_DATA, - }, - .emit = upload_urb, -}; diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index 5ee5435..f822328 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -166,11 +166,9 @@ blorp_emit_urb_config(struct blorp_batch *batch, unsigned vs_entry_size) return; brw->ctx.NewDriverState |= BRW_NEW_URB_SIZE; - - gen7_upload_urb(brw, vs_entry_size, false, false); -#else - gen6_upload_urb(brw, vs_entry_size, false, 1); #endif + + genX(upload_urb)(brw, vs_entry_size, false, false); } void diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 3921a6f..30a29a0 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -24,6 +24,7 @@ #include <assert.h> #include "common/gen_device_info.h" +#include "common/gen_l3_config.h" #include "common/gen_sample_positions.h" #include "genxml/gen_macros.h" @@ -2858,6 +2859,182 @@ static const struct brw_tracked_state genX(color_calc_state) = { /* ---------------------------------------------------------------------- */ +#if GEN_GEN >= 6 +void +genX(upload_urb)(struct brw_context *brw, unsigned vs_size, + bool gs_present, bool tess_present) +{ + const struct gen_device_info *devinfo = &brw->screen->devinfo; + + /* BRW_NEW_{VS,TCS,TES,GS}_PROG_DATA */ + struct brw_vue_prog_data *prog_data[4] = { + [MESA_SHADER_VERTEX] = + brw_vue_prog_data(brw->vs.base.prog_data), + [MESA_SHADER_TESS_CTRL] = + tess_present ? brw_vue_prog_data(brw->tcs.base.prog_data) : NULL, + [MESA_SHADER_TESS_EVAL] = + tess_present ? brw_vue_prog_data(brw->tes.base.prog_data) : NULL, + [MESA_SHADER_GEOMETRY] = + gs_present ? brw_vue_prog_data(brw->gs.base.prog_data) : NULL, + }; + + unsigned entry_size[4]; + entry_size[MESA_SHADER_VERTEX] = vs_size; + for (int i = MESA_SHADER_TESS_CTRL; i <= MESA_SHADER_GEOMETRY; i++) { + entry_size[i] = prog_data[i] ? prog_data[i]->urb_entry_size : 1; + } + + if (GEN_GEN == 7 && !GEN_IS_HASWELL && !brw->is_baytrail) + gen7_emit_vs_workaround_flush(brw); + +#if GEN_GEN < 7 + int nr_vs_entries, nr_gs_entries; + const int total_urb_size = brw->urb.size * 1024; /* in bytes */ + unsigned gs_size = vs_size; + + /* Whe using GS to do transform feedback only we use the same VUE layout for + * VS outputs and GS outputs (as it's what the SF and Clipper expect), so we + * can simply make the GS URB entry size the same as for the VS. This may + * technically be too large in cases where we have few vertex attributes and + * a lot of varyings, since the VS size is determined by the larger of the + * two. For now, it's safe. + * + * For user-provided GS the assumption above does not hold since the GS + * outputs can be different from the VS outputs. + */ + if (prog_data[MESA_SHADER_GEOMETRY]) + gs_size = entry_size[MESA_SHADER_GEOMETRY]; + + /* Calculate how many entries fit in each stage's section of the URB */ + if (gs_present) { + nr_vs_entries = (total_urb_size / 2) / (vs_size * 128); + nr_gs_entries = (total_urb_size / 2) / (gs_size * 128); + } else { + nr_vs_entries = total_urb_size / (vs_size * 128); + nr_gs_entries = 0; + } + + /* Then clamp to the maximum allowed by the hardware */ + if (nr_vs_entries > devinfo->urb.max_entries[MESA_SHADER_VERTEX]) + nr_vs_entries = devinfo->urb.max_entries[MESA_SHADER_VERTEX]; + + if (nr_gs_entries > devinfo->urb.max_entries[MESA_SHADER_GEOMETRY]) + nr_gs_entries = devinfo->urb.max_entries[MESA_SHADER_GEOMETRY]; + + /* Finally, both must be a multiple of 4 (see 3DSTATE_URB in the PRM). */ + brw->urb.nr_vs_entries = ROUND_DOWN_TO(nr_vs_entries, 4); + brw->urb.nr_gs_entries = ROUND_DOWN_TO(nr_gs_entries, 4); + + assert(brw->urb.nr_vs_entries >= + devinfo->urb.min_entries[MESA_SHADER_VERTEX]); + assert(brw->urb.nr_vs_entries % 4 == 0); + assert(brw->urb.nr_gs_entries % 4 == 0); + assert(vs_size >= 1 && vs_size <= 5); + assert(gs_size <= 5); + + brw_batch_emit(brw, GENX(3DSTATE_URB), urb) { + urb.VSURBEntryAllocationSize = vs_size - 1; + urb.VSNumberofURBEntries = brw->urb.nr_vs_entries; + urb.GSURBEntryAllocationSize = gs_size - 1; + urb.GSNumberofURBEntries = brw->urb.nr_gs_entries; + } + + /* From the PRM Volume 2 part 1, section 1.4.7: + * + * Because of a urb corruption caused by allocating a previous gsunit’s + * urb entry to vsunit software is required to send a "GS NULL + * Fence"(Send URB fence with VS URB size == 1 and GS URB size == 0) plus + * a dummy DRAW call before any case where VS will be taking over GS URB + * space. + * + * It is not clear exactly what this means ("URB fence" is a command that + * doesn't exist on Gen6). So for now we just do a full pipeline flush as + * a workaround. + */ + if (brw->urb.gs_present && !gs_present) + brw_emit_mi_flush(brw); + brw->urb.gs_present = gs_present; +#else + unsigned entries[4]; + unsigned start[4]; + + const int push_size_kB = (GEN_GEN >= 8 || + (GEN_IS_HASWELL && brw->gt == 3)) ? 32 : 16; + + gen_get_urb_config(devinfo, 1024 * push_size_kB, 1024 * brw->urb.size, + tess_present, gs_present, entry_size, entries, start); + /* If we're just switching between programs with the same URB requirements, + * skip the rest of the logic. + */ + if (!(brw->ctx.NewDriverState & BRW_NEW_CONTEXT) && + !(brw->ctx.NewDriverState & BRW_NEW_URB_SIZE) && + brw->urb.vsize == entry_size[MESA_SHADER_VERTEX] && + brw->urb.gs_present == gs_present && + brw->urb.gsize == entry_size[MESA_SHADER_GEOMETRY] && + brw->urb.tess_present == tess_present && + brw->urb.hsize == entry_size[MESA_SHADER_TESS_CTRL] && + brw->urb.dsize == entry_size[MESA_SHADER_TESS_EVAL]) { + return; + } + + brw->urb.vsize = entry_size[MESA_SHADER_VERTEX]; + brw->urb.gs_present = gs_present; + brw->urb.gsize = entry_size[MESA_SHADER_GEOMETRY]; + brw->urb.tess_present = tess_present; + brw->urb.hsize = entry_size[MESA_SHADER_TESS_CTRL]; + brw->urb.dsize = entry_size[MESA_SHADER_TESS_EVAL]; + + + for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) { + brw_batch_emit(brw, GENX(3DSTATE_URB_VS), urb) { + urb._3DCommandSubOpcode += i; + urb.VSNumberofURBEntries = entries[i]; + urb.VSURBStartingAddress = start[i]; + urb.VSURBEntryAllocationSize = entry_size[i] - 1; + } + } +#endif +} + +static void +upload_urb(struct brw_context *brw) +{ + /* BRW_NEW_VS_PROG_DATA */ + const struct brw_vue_prog_data *vs_vue_prog_data = + brw_vue_prog_data(brw->vs.base.prog_data); + const unsigned vs_size = MAX2(vs_vue_prog_data->urb_entry_size, 1); + + /* BRW_NEW_GEOMETRY_PROGRAM, BRW_NEW_GS_PROG_DATA */ + const bool gs_present = GEN_GEN < 7 ? + (brw->ff_gs.prog_active || brw->geometry_program) : + (!!brw->gs.base.prog_data); + + /* BRW_NEW_TES_PROG_DATA */ + const bool tess_present = brw->tes.base.prog_data; + + genX(upload_urb)(brw, vs_size, gs_present, tess_present); +} + +static const struct brw_tracked_state genX(urb) = { + .dirty = { + .mesa = 0, + .brw = BRW_NEW_CONTEXT | + BRW_NEW_GS_PROG_DATA | + BRW_NEW_VS_PROG_DATA | + (GEN_GEN < 7 ? (BRW_NEW_BLORP | + BRW_NEW_FF_GS_PROG_DATA | + BRW_NEW_GEOMETRY_PROGRAM) + : (BRW_NEW_URB_SIZE | + BRW_NEW_TCS_PROG_DATA | + BRW_NEW_TES_PROG_DATA)), + }, + .emit = upload_urb, +}; + +#endif + +/* ---------------------------------------------------------------------- */ + #if GEN_GEN >= 7 static void genX(upload_sbe)(struct brw_context *brw) @@ -4237,7 +4414,7 @@ genX(init_atoms)(struct brw_context *brw) &gen7_l3_state, &gen7_push_constant_space, - &gen7_urb, + &genX(urb), &genX(blend_state), /* must do before cc unit */ &genX(color_calc_state), /* must do before cc unit */ &genX(depth_stencil_state), /* must do before cc unit */ @@ -4327,7 +4504,7 @@ genX(init_atoms)(struct brw_context *brw) &gen7_l3_state, &gen7_push_constant_space, - &gen7_urb, + &genX(urb), &genX(blend_state), &genX(color_calc_state), -- 2.9.3 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev