Re: [Mesa-dev] [PATCH 5/6] R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.

2013-02-19 Thread Tom Stellard 
On Mon, Feb 18, 2013 at 05:27:29PM +0100, Vincent Lejeune wrote:
 Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case
 and taking them in account for scheduling is difficult for no real benefit.
 ---
  lib/Target/R600/AMDGPU.h|   1 -
  lib/Target/R600/AMDGPUTargetMachine.cpp |   1 -
  lib/Target/R600/R600ISelLowering.cpp|   8 +-
  lib/Target/R600/R600Instructions.td |   7 +-
  lib/Target/R600/R600LowerConstCopy.cpp  | 222 
 

Don't forget to remove this file from CMakeLists.txt

  5 files changed, 11 insertions(+), 228 deletions(-)
  delete mode 100644 lib/Target/R600/R600LowerConstCopy.cpp
 
 diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h
 index ba87918..67073ab 100644
 --- a/lib/Target/R600/AMDGPU.h
 +++ b/lib/Target/R600/AMDGPU.h
 @@ -23,7 +23,6 @@ class AMDGPUTargetMachine;
  // R600 Passes
  FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
  FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine tm);
 -FunctionPass *createR600LowerConstCopy(TargetMachine tm);
  
  // SI Passes
  FunctionPass *createSIAnnotateControlFlowPass();
 diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp 
 b/lib/Target/R600/AMDGPUTargetMachine.cpp
 index e2f00be..70b34b0 100644
 --- a/lib/Target/R600/AMDGPUTargetMachine.cpp
 +++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
 @@ -143,7 +143,6 @@ bool AMDGPUPassConfig::addPreEmitPass() {
  addPass(createAMDGPUCFGStructurizerPass(*TM));
  addPass(createR600ExpandSpecialInstrsPass(*TM));
  addPass(FinalizeMachineBundlesID);
 -addPass(createR600LowerConstCopy(*TM));
} else {
  addPass(createSILowerControlFlowPass(*TM));
}
 diff --git a/lib/Target/R600/R600ISelLowering.cpp 
 b/lib/Target/R600/R600ISelLowering.cpp
 index ece0b9a..f25ced1 100644
 --- a/lib/Target/R600/R600ISelLowering.cpp
 +++ b/lib/Target/R600/R600ISelLowering.cpp
 @@ -150,7 +150,13 @@ MachineBasicBlock * 
 R600TargetLowering::EmitInstrWithCustomInserter(
  TII-buildMovImm(*BB, I, MI-getOperand(0).getReg(),
   MI-getOperand(1).getImm());
  break;
 -
 +  case AMDGPU::CONST_COPY: {
 +MachineInstr *NewMI = TII-buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
 +MI-getOperand(0).getReg(), AMDGPU::ALU_CONST);
 +TII-setImmOperand(NewMI, R600Operands::SRC0_SEL,
 +MI-getOperand(1).getImm());
 +break;
 +  }
  
case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
 diff --git a/lib/Target/R600/R600Instructions.td 
 b/lib/Target/R600/R600Instructions.td
 index 74106c9..10bcdcf 100644
 --- a/lib/Target/R600/R600Instructions.td
 +++ b/lib/Target/R600/R600Instructions.td
 @@ -1650,17 +1650,18 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, 
 hasCtrlDep = 1,
  // Constant Buffer Addressing Support
  
 //===--===//
  
 -let isCodeGenOnly = 1, isPseudo = 1, Namespace = AMDGPU  in {
 +let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = 
 AMDGPU  in {
  def CONST_COPY : Instruction {
let OutOperandList = (outs R600_Reg32:$dst);
let InOperandList = (ins i32imm:$src);
 -  let Pattern = [(set R600_Reg32:$dst, (CONST_ADDRESS 
 ADDRGA_CONST_OFFSET:$src))];
 +  let Pattern =
 +  [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
let AsmString = CONST_COPY;
let neverHasSideEffects = 1;
let isAsCheapAsAMove = 1;
let Itinerary = NullALU;
  }
 -} // end isCodeGenOnly = 1, isPseudo = 1, Namespace = AMDGPU
 +} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace 
 = AMDGPU
  
  def TEX_VTX_CONSTBUF :
InstR600ISA (outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), 
 VTX_READ_eg $dst, $ptr,
 diff --git a/lib/Target/R600/R600LowerConstCopy.cpp 
 b/lib/Target/R600/R600LowerConstCopy.cpp
 deleted file mode 100644
 index 3ebe653..000
 --- a/lib/Target/R600/R600LowerConstCopy.cpp
 +++ /dev/null
 @@ -1,222 +0,0 @@
 -//===-- R600LowerConstCopy.cpp - Propagate ConstCopy / lower them to 
 MOV---===//
 -//
 -// The LLVM Compiler Infrastructure
 -//
 -// This file is distributed under the University of Illinois Open Source
 -// License. See LICENSE.TXT for details.
 -//
 -//===--===//
 -//
 -/// \file
 -/// This pass is intended to handle remaining ConstCopy pseudo MachineInstr.
 -/// ISel will fold each Const Buffer read inside scalar ALU. However it 
 cannot
 -/// fold them inside vector instruction, like DOT4 or Cube ; ISel emits
 -/// ConstCopy instead. This pass (executed after ExpandingSpecialInstr) will 
 try
 -/// to fold them if possible or replace them by MOV otherwise.
 -//
 -//===--===//
 -
 -#include AMDGPU.h
 -#include R600InstrInfo.h
 -#include llvm/CodeGen/MachineFunction.h

[Mesa-dev] [PATCH 5/6] R600: Remove LowerConstCopyPass and lower CONST_COPY right after ISel.

2013-02-18 Thread Vincent Lejeune 
Maintaining CONST_COPY Instructions until Pre Emit may prevent some ifcvt case
and taking them in account for scheduling is difficult for no real benefit.
---
 lib/Target/R600/AMDGPU.h|   1 -
 lib/Target/R600/AMDGPUTargetMachine.cpp |   1 -
 lib/Target/R600/R600ISelLowering.cpp|   8 +-
 lib/Target/R600/R600Instructions.td |   7 +-
 lib/Target/R600/R600LowerConstCopy.cpp  | 222 
 5 files changed, 11 insertions(+), 228 deletions(-)
 delete mode 100644 lib/Target/R600/R600LowerConstCopy.cpp

diff --git a/lib/Target/R600/AMDGPU.h b/lib/Target/R600/AMDGPU.h
index ba87918..67073ab 100644
--- a/lib/Target/R600/AMDGPU.h
+++ b/lib/Target/R600/AMDGPU.h
@@ -23,7 +23,6 @@ class AMDGPUTargetMachine;
 // R600 Passes
 FunctionPass* createR600KernelParametersPass(const DataLayout *TD);
 FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine tm);
-FunctionPass *createR600LowerConstCopy(TargetMachine tm);
 
 // SI Passes
 FunctionPass *createSIAnnotateControlFlowPass();
diff --git a/lib/Target/R600/AMDGPUTargetMachine.cpp 
b/lib/Target/R600/AMDGPUTargetMachine.cpp
index e2f00be..70b34b0 100644
--- a/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -143,7 +143,6 @@ bool AMDGPUPassConfig::addPreEmitPass() {
 addPass(createAMDGPUCFGStructurizerPass(*TM));
 addPass(createR600ExpandSpecialInstrsPass(*TM));
 addPass(FinalizeMachineBundlesID);
-addPass(createR600LowerConstCopy(*TM));
   } else {
 addPass(createSILowerControlFlowPass(*TM));
   }
diff --git a/lib/Target/R600/R600ISelLowering.cpp 
b/lib/Target/R600/R600ISelLowering.cpp
index ece0b9a..f25ced1 100644
--- a/lib/Target/R600/R600ISelLowering.cpp
+++ b/lib/Target/R600/R600ISelLowering.cpp
@@ -150,7 +150,13 @@ MachineBasicBlock * 
R600TargetLowering::EmitInstrWithCustomInserter(
 TII-buildMovImm(*BB, I, MI-getOperand(0).getReg(),
  MI-getOperand(1).getImm());
 break;
-
+  case AMDGPU::CONST_COPY: {
+MachineInstr *NewMI = TII-buildDefaultInstruction(*BB, MI, AMDGPU::MOV,
+MI-getOperand(0).getReg(), AMDGPU::ALU_CONST);
+TII-setImmOperand(NewMI, R600Operands::SRC0_SEL,
+MI-getOperand(1).getImm());
+break;
+  }
 
   case AMDGPU::RAT_WRITE_CACHELESS_32_eg:
   case AMDGPU::RAT_WRITE_CACHELESS_128_eg: {
diff --git a/lib/Target/R600/R600Instructions.td 
b/lib/Target/R600/R600Instructions.td
index 74106c9..10bcdcf 100644
--- a/lib/Target/R600/R600Instructions.td
+++ b/lib/Target/R600/R600Instructions.td
@@ -1650,17 +1650,18 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1, 
hasCtrlDep = 1,
 // Constant Buffer Addressing Support
 
//===--===//
 
-let isCodeGenOnly = 1, isPseudo = 1, Namespace = AMDGPU  in {
+let usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = 
AMDGPU  in {
 def CONST_COPY : Instruction {
   let OutOperandList = (outs R600_Reg32:$dst);
   let InOperandList = (ins i32imm:$src);
-  let Pattern = [(set R600_Reg32:$dst, (CONST_ADDRESS 
ADDRGA_CONST_OFFSET:$src))];
+  let Pattern =
+  [(set R600_Reg32:$dst, (CONST_ADDRESS ADDRGA_CONST_OFFSET:$src))];
   let AsmString = CONST_COPY;
   let neverHasSideEffects = 1;
   let isAsCheapAsAMove = 1;
   let Itinerary = NullALU;
 }
-} // end isCodeGenOnly = 1, isPseudo = 1, Namespace = AMDGPU
+} // end usesCustomInserter = 1, isCodeGenOnly = 1, isPseudo = 1, Namespace = 
AMDGPU
 
 def TEX_VTX_CONSTBUF :
   InstR600ISA (outs R600_Reg128:$dst), (ins MEMxi:$ptr, i32imm:$BUFFER_ID), 
VTX_READ_eg $dst, $ptr,
diff --git a/lib/Target/R600/R600LowerConstCopy.cpp 
b/lib/Target/R600/R600LowerConstCopy.cpp
deleted file mode 100644
index 3ebe653..000
--- a/lib/Target/R600/R600LowerConstCopy.cpp
+++ /dev/null
@@ -1,222 +0,0 @@
-//===-- R600LowerConstCopy.cpp - Propagate ConstCopy / lower them to 
MOV---===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===--===//
-//
-/// \file
-/// This pass is intended to handle remaining ConstCopy pseudo MachineInstr.
-/// ISel will fold each Const Buffer read inside scalar ALU. However it cannot
-/// fold them inside vector instruction, like DOT4 or Cube ; ISel emits
-/// ConstCopy instead. This pass (executed after ExpandingSpecialInstr) will 
try
-/// to fold them if possible or replace them by MOV otherwise.
-//
-//===--===//
-
-#include AMDGPU.h
-#include R600InstrInfo.h
-#include llvm/CodeGen/MachineFunction.h
-#include llvm/CodeGen/MachineFunctionPass.h
-#include llvm/CodeGen/MachineInstrBuilder.h
-#include llvm/IR/GlobalValue.h
-
-namespace llvm {
-
-class R600LowerConstCopy : public MachineFunctionPass {
-private:
-  static char ID;
-  const