r-b
On Thu, Jun 20, 2019 at 6:20 AM Marek Olšák wrote:
>
> From: Marek Olšák
>
> ---
> .../drivers/radeonsi/si_state_binning.c| 18 --
> 1 file changed, 4 insertions(+), 14 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_state_binning.c
> b/src/gallium/drivers/radeonsi/si_state_binning.c
> index 6285ccc28c2..a6b1830b661 100644
> --- a/src/gallium/drivers/radeonsi/si_state_binning.c
> +++ b/src/gallium/drivers/radeonsi/si_state_binning.c
> @@ -395,34 +395,24 @@ void si_emit_dpbb_state(struct si_context *sctx)
> punchout_mode = V_028060_AUTO;
> disable_start_of_prim = (cb_target_enabled_4bit &
> blend->blend_enable_4bit) != 0;
> }
>
> /* Tunable parameters. Also test with DFSM enabled/disabled. */
> unsigned context_states_per_bin; /* allowed range: [0, 5] */
> unsigned persistent_states_per_bin; /* allowed range: [0, 31] */
> unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
>
> - switch (sctx->family) {
> - case CHIP_VEGA10:
> - case CHIP_VEGA12:
> - case CHIP_VEGA20:
> - case CHIP_RAVEN:
> - case CHIP_RAVEN2:
> - /* Tuned for Raven. Vega might need different values. */
> - context_states_per_bin = 5;
> - persistent_states_per_bin = 31;
> - fpovs_per_batch = 63;
> - break;
> - default:
> - assert(0);
> - }
> + /* Tuned for Raven. Vega might need different values. */
> + context_states_per_bin = 5;
> + persistent_states_per_bin = 31;
> + fpovs_per_batch = 63;
>
> /* Emit registers. */
> struct uvec2 bin_size_extend = {};
> if (bin_size.x >= 32)
> bin_size_extend.x = util_logbase2(bin_size.x) - 5;
> if (bin_size.y >= 32)
> bin_size_extend.y = util_logbase2(bin_size.y) - 5;
>
> unsigned initial_cdw = sctx->gfx_cs->current.cdw;
> radeon_opt_set_context_reg(
> --
> 2.17.1
>
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