Re: [Mesa-dev] [PATCH v2 013/103] i965/vec4: set correct register regions for 32-bit and 64-bit

[Ian Romanick]

On 10/11/2016 02:01 AM, Iago Toral Quiroga wrote:
> For 32-bit instructions we want to use <4,4,1> regions for VGRF
> sources so we should really set a width of 4 (we were setting 8).
> 
> For 64-bit instructions we want to use a width of 2 because the
> hardware uses 32-bit swizzles, meaning that we can only address 2
> consecutive 64-bit components in a row. Also, Curro suggested that
> the hardware is probably fixing the width to 2 for 64-bit instructions
> anyway, so just go with that and use <2,2,1>.
> 
> v2:
>  - No need to explicitly set the vertical stride of 64-bit regions to 2,
>brw_vecn_grf with a width of 2 will do that for us.
>  - No need to adjust the width of dst registers.
> 
> Signed-off-by: Connor Abbott 
> ---
>  src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
> b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> index 32c04b2..40f8702 100644
> --- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
> @@ -1873,20 +1873,24 @@ vec4_visitor::convert_to_hw_regs()
>   struct src_reg  = inst->src[i];
>   struct brw_reg reg;
>   switch (src.file) {
> - case VGRF:
> -reg = byte_offset(brw_vec8_grf(src.nr, 0), src.offset);
> + case VGRF: {
> +unsigned type_size = type_sz(src.type);
> +unsigned width = REG_SIZE / 2 / MAX2(4, type_size);

constify these

> +reg = byte_offset(brw_vecn_grf(width, src.nr, 0), src.offset);
>  reg.type = src.type;
>  reg.swizzle = src.swizzle;
>  reg.abs = src.abs;
>  reg.negate = src.negate;
>  break;
> + }
>  
> - case UNIFORM:
> + case UNIFORM: {
> +unsigned width = REG_SIZE / 2 / MAX2(4, type_sz(src.type));

constify this one too, and this patch is

Reviewed-by: Ian Romanick 

>  reg = stride(byte_offset(brw_vec4_grf(
>  
> prog_data->base.dispatch_grf_start_reg +
>  src.nr / 2, src.nr % 2 * 4),
>   src.offset),
> - 0, 4, 1);
> + 0, width, 1);
>  reg.type = src.type;
>  reg.swizzle = src.swizzle;
>  reg.abs = src.abs;
> @@ -1895,6 +1899,7 @@ vec4_visitor::convert_to_hw_regs()
>  /* This should have been moved to pull constants. */
>  assert(!src.reladdr);
>  break;
> + }
>  
>   case ARF:
>   case FIXED_GRF:
> 

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[Mesa-dev] [PATCH v2 013/103] i965/vec4: set correct register regions for 32-bit and 64-bit

[Iago Toral Quiroga]

For 32-bit instructions we want to use <4,4,1> regions for VGRF
sources so we should really set a width of 4 (we were setting 8).

For 64-bit instructions we want to use a width of 2 because the
hardware uses 32-bit swizzles, meaning that we can only address 2
consecutive 64-bit components in a row. Also, Curro suggested that
the hardware is probably fixing the width to 2 for 64-bit instructions
anyway, so just go with that and use <2,2,1>.

v2:
 - No need to explicitly set the vertical stride of 64-bit regions to 2,
   brw_vecn_grf with a width of 2 will do that for us.
 - No need to adjust the width of dst registers.

Signed-off-by: Connor Abbott 
---
 src/mesa/drivers/dri/i965/brw_vec4.cpp | 13 +
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 32c04b2..40f8702 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1873,20 +1873,24 @@ vec4_visitor::convert_to_hw_regs()
  struct src_reg  = inst->src[i];
  struct brw_reg reg;
  switch (src.file) {
- case VGRF:
-reg = byte_offset(brw_vec8_grf(src.nr, 0), src.offset);
+ case VGRF: {
+unsigned type_size = type_sz(src.type);
+unsigned width = REG_SIZE / 2 / MAX2(4, type_size);
+reg = byte_offset(brw_vecn_grf(width, src.nr, 0), src.offset);
 reg.type = src.type;
 reg.swizzle = src.swizzle;
 reg.abs = src.abs;
 reg.negate = src.negate;
 break;
+ }
 
- case UNIFORM:
+ case UNIFORM: {
+unsigned width = REG_SIZE / 2 / MAX2(4, type_sz(src.type));
 reg = stride(byte_offset(brw_vec4_grf(
 prog_data->base.dispatch_grf_start_reg 
+
 src.nr / 2, src.nr % 2 * 4),
  src.offset),
- 0, 4, 1);
+ 0, width, 1);
 reg.type = src.type;
 reg.swizzle = src.swizzle;
 reg.abs = src.abs;
@@ -1895,6 +1899,7 @@ vec4_visitor::convert_to_hw_regs()
 /* This should have been moved to pull constants. */
 assert(!src.reladdr);
 break;
+ }
 
  case ARF:
  case FIXED_GRF:
-- 
2.7.4

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