Re: [Mesa-dev] [PATCH v3 31/48] intel/cs: Re-run final NIR optimizations for each SIMD size

[Jason Ekstrand]

On Fri, Oct 27, 2017 at 3:03 AM, Iago Toral  wrote:

> This should be squashed into the previous commit
>

Oops... Fixed.


> On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
> > With the advent of SPIR-V subgroup operations, compute shaders will
> > have
> > to be slightly different depending on the SIMD size at which they
> > execute.  In order to allow us to do dispatch-width specific things
> > in
> > NIR, we re-run the final NIR stages for each sIMD width.
> >
> > As a side-effect of this change, we start using ralloc on fs_visitor
> > so
> > we need to add DECLARE_RALLOC_OPERATORS to fs_visitor.
> > ---
> >  src/intel/compiler/brw_fs.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/src/intel/compiler/brw_fs.h
> > b/src/intel/compiler/brw_fs.h
> > index d3ab385..9ff06b6 100644
> > --- a/src/intel/compiler/brw_fs.h
> > +++ b/src/intel/compiler/brw_fs.h
> > @@ -60,7 +60,7 @@ offset(const fs_reg , const brw::fs_builder
> > , unsigned delta)
> >  class fs_visitor : public backend_shader
> >  {
> >  public:
> > -   DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
> > +   DECLARE_RALLOC_CXX_OPERATORS(fs_visitor)
> >
> > fs_visitor(const struct brw_compiler *compiler, void *log_data,
> >void *mem_ctx,
>
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Re: [Mesa-dev] [PATCH v3 31/48] intel/cs: Re-run final NIR optimizations for each SIMD size

[Iago Toral]

This should be squashed into the previous commit

On Wed, 2017-10-25 at 16:26 -0700, Jason Ekstrand wrote:
> With the advent of SPIR-V subgroup operations, compute shaders will
> have
> to be slightly different depending on the SIMD size at which they
> execute.  In order to allow us to do dispatch-width specific things
> in
> NIR, we re-run the final NIR stages for each sIMD width.
> 
> As a side-effect of this change, we start using ralloc on fs_visitor
> so
> we need to add DECLARE_RALLOC_OPERATORS to fs_visitor.
> ---
>  src/intel/compiler/brw_fs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/src/intel/compiler/brw_fs.h
> b/src/intel/compiler/brw_fs.h
> index d3ab385..9ff06b6 100644
> --- a/src/intel/compiler/brw_fs.h
> +++ b/src/intel/compiler/brw_fs.h
> @@ -60,7 +60,7 @@ offset(const fs_reg , const brw::fs_builder
> , unsigned delta)
>  class fs_visitor : public backend_shader
>  {
>  public:
> -   DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
> +   DECLARE_RALLOC_CXX_OPERATORS(fs_visitor)
>  
> fs_visitor(const struct brw_compiler *compiler, void *log_data,
>    void *mem_ctx,
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[Mesa-dev] [PATCH v3 31/48] intel/cs: Re-run final NIR optimizations for each SIMD size

[Jason Ekstrand]

With the advent of SPIR-V subgroup operations, compute shaders will have
to be slightly different depending on the SIMD size at which they
execute.  In order to allow us to do dispatch-width specific things in
NIR, we re-run the final NIR stages for each sIMD width.

As a side-effect of this change, we start using ralloc on fs_visitor so
we need to add DECLARE_RALLOC_OPERATORS to fs_visitor.
---
 src/intel/compiler/brw_fs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h
index d3ab385..9ff06b6 100644
--- a/src/intel/compiler/brw_fs.h
+++ b/src/intel/compiler/brw_fs.h
@@ -60,7 +60,7 @@ offset(const fs_reg , const brw::fs_builder , 
unsigned delta)
 class fs_visitor : public backend_shader
 {
 public:
-   DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
+   DECLARE_RALLOC_CXX_OPERATORS(fs_visitor)
 
fs_visitor(const struct brw_compiler *compiler, void *log_data,
   void *mem_ctx,
-- 
2.5.0.400.gff86faf

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