Re: [Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

[Jason Ekstrand]

Assuming the changes you describe below, this patch would get a

Reviewed-by: Jason Ekstrand 

I think that's enough for you to land the UBO/SSBO portion of 16bit
storage.  Feel free to send v2 versions of any patches you want me to look
at again before you push but I think it's in pretty good shape.

--Jason

On Fri, Dec 1, 2017 at 1:21 PM, Chema Casanova 
wrote:

> On 30/11/17 21:42, Jason Ekstrand wrote:
> > On Wed, Nov 29, 2017 at 6:08 PM, Jose Maria Casanova Crespo
> > > wrote:
> >
> > v2: (Jason Ekstrand)
> > - Enable bit_size parameter to scattered messages to enable
> > different
> >   bitsizes byte/word/dword.
> > - Remove use of brw_send_indirect_scattered_message in favor of
> >   brw_send_indirect_surface_message.
> > - Move scattered messages to surface messages namespace.
> > - Assert align1 for scattered messages and assume Gen8+.
> > - Inline brw_set_dp_byte_scattered_write.
> >
> > Signed-off-by: Jose Maria Casanova Crespo  > >
> > Signed-off-by: Alejandro Piñeiro  > >
> > ---
> >  src/intel/compiler/brw_eu.h|  7 +
> >  src/intel/compiler/brw_eu_defines.h| 17 +++
> >  src/intel/compiler/brw_eu_emit.c   | 42
> > ++
> >  src/intel/compiler/brw_fs.cpp  | 14 +
> >  src/intel/compiler/brw_fs_copy_propagation.cpp |  2 ++
> >  src/intel/compiler/brw_fs_generator.cpp|  6 
> >  src/intel/compiler/brw_fs_surface_builder.cpp  | 11 +++
> >  src/intel/compiler/brw_fs_surface_builder.h|  7 +
> >  src/intel/compiler/brw_shader.cpp  |  7 +
> >  9 files changed, 113 insertions(+)
> >
> > diff --git a/src/intel/compiler/brw_eu.h
> b/src/intel/compiler/brw_eu.h
> > index 343dcd867d..3ac3b4342a 100644
> > --- a/src/intel/compiler/brw_eu.h
> > +++ b/src/intel/compiler/brw_eu.h
> > @@ -485,6 +485,13 @@ brw_typed_surface_write(struct brw_codegen *p,
> >  unsigned msg_length,
> >  unsigned num_channels);
> >
> > +void
> > +brw_byte_scattered_write(struct brw_codegen *p,
> > + struct brw_reg payload,
> > + struct brw_reg surface,
> > + unsigned msg_length,
> > + unsigned bit_size);
> > +
> >  void
> >  brw_memory_fence(struct brw_codegen *p,
> >   struct brw_reg dst);
> > diff --git a/src/intel/compiler/brw_eu_defines.h
> > b/src/intel/compiler/brw_eu_defines.h
> > index 9d5cf05c86..de6330ee54 100644
> > --- a/src/intel/compiler/brw_eu_defines.h
> > +++ b/src/intel/compiler/brw_eu_defines.h
> > @@ -402,6 +402,16 @@ enum opcode {
> >
> > SHADER_OPCODE_RND_MODE,
> >
> > +   /**
> > +* Byte scattered write/read opcodes.
> > +*
> > +* LOGICAL opcodes are eventually translated to the matching
> > non-LOGICAL
> > +* opcode, but instead of taking a single payload blog they
> > expect their
> > +* arguments separately as individual sources, like untyped
> > write/read.
> > +*/
> > +   SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> > +   SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
> > +
> > SHADER_OPCODE_MEMORY_FENCE,
> >
> > SHADER_OPCODE_GEN4_SCRATCH_READ,
> > @@ -1255,4 +1265,11 @@ enum PACKED brw_rnd_mode {
> > BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
> >  };
> >
> > +/* MDC_DS - Data Size Message Descriptor Control Field */
> > +enum PACKED brw_data_size {
> >
> >
> > I'm not sure how I feel about this being an enum with such a generic
> name.
>
> Right, PRM use a more exactly "Data Elements" but this field only used
> byte_scattered/scaled writes/reads. As I will follow your next
> suggestion of using #define, I'm chaging the name to:
>
> #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE  0
> #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD  1
> #define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2
>
> I'll include in the comment about MSC_DS
> "Specifies the number of Bytes to be read or written per Dword used at
> byte_scattered read/write and byte_scaled read/write messages."
>
> >
> >
> > +   GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE = 0,
> > +   GEN7_BYTE_SCATTERED_DATA_SIZE_WORD = 1,
> > +   GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD = 2
> > +};
> > +
> >  #endif /* BRW_EU_DEFINES_H */
> > diff --git a/src/intel/compiler/brw_eu_emit.c
> > b/src/intel/compiler/brw_eu_emit.c
> > index ca97ff7325..ded7e228cf 100644
> > --- 

Re: [Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

[Chema Casanova]

On 30/11/17 21:42, Jason Ekstrand wrote:
> On Wed, Nov 29, 2017 at 6:08 PM, Jose Maria Casanova Crespo
> > wrote:
> 
> v2: (Jason Ekstrand)
>     - Enable bit_size parameter to scattered messages to enable
> different
>       bitsizes byte/word/dword.
>     - Remove use of brw_send_indirect_scattered_message in favor of
>       brw_send_indirect_surface_message.
>     - Move scattered messages to surface messages namespace.
>     - Assert align1 for scattered messages and assume Gen8+.
>     - Inline brw_set_dp_byte_scattered_write.
> 
> Signed-off-by: Jose Maria Casanova Crespo  >
> Signed-off-by: Alejandro Piñeiro  >
> ---
>  src/intel/compiler/brw_eu.h                    |  7 +
>  src/intel/compiler/brw_eu_defines.h            | 17 +++
>  src/intel/compiler/brw_eu_emit.c               | 42
> ++
>  src/intel/compiler/brw_fs.cpp                  | 14 +
>  src/intel/compiler/brw_fs_copy_propagation.cpp |  2 ++
>  src/intel/compiler/brw_fs_generator.cpp        |  6 
>  src/intel/compiler/brw_fs_surface_builder.cpp  | 11 +++
>  src/intel/compiler/brw_fs_surface_builder.h    |  7 +
>  src/intel/compiler/brw_shader.cpp              |  7 +
>  9 files changed, 113 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 343dcd867d..3ac3b4342a 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -485,6 +485,13 @@ brw_typed_surface_write(struct brw_codegen *p,
>                          unsigned msg_length,
>                          unsigned num_channels);
> 
> +void
> +brw_byte_scattered_write(struct brw_codegen *p,
> +                         struct brw_reg payload,
> +                         struct brw_reg surface,
> +                         unsigned msg_length,
> +                         unsigned bit_size);
> +
>  void
>  brw_memory_fence(struct brw_codegen *p,
>                   struct brw_reg dst);
> diff --git a/src/intel/compiler/brw_eu_defines.h
> b/src/intel/compiler/brw_eu_defines.h
> index 9d5cf05c86..de6330ee54 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -402,6 +402,16 @@ enum opcode {
> 
>     SHADER_OPCODE_RND_MODE,
> 
> +   /**
> +    * Byte scattered write/read opcodes.
> +    *
> +    * LOGICAL opcodes are eventually translated to the matching
> non-LOGICAL
> +    * opcode, but instead of taking a single payload blog they
> expect their
> +    * arguments separately as individual sources, like untyped
> write/read.
> +    */
> +   SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> +   SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
> +
>     SHADER_OPCODE_MEMORY_FENCE,
> 
>     SHADER_OPCODE_GEN4_SCRATCH_READ,
> @@ -1255,4 +1265,11 @@ enum PACKED brw_rnd_mode {
>     BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
>  };
> 
> +/* MDC_DS - Data Size Message Descriptor Control Field */
> +enum PACKED brw_data_size {
> 
> 
> I'm not sure how I feel about this being an enum with such a generic name.

Right, PRM use a more exactly "Data Elements" but this field only used
byte_scattered/scaled writes/reads. As I will follow your next
suggestion of using #define, I'm chaging the name to:

#define GEN7_BYTE_SCATTERED_DATA_ELEMENT_BYTE  0
#define GEN7_BYTE_SCATTERED_DATA_ELEMENT_WORD  1
#define GEN7_BYTE_SCATTERED_DATA_ELEMENT_DWORD 2

I'll include in the comment about MSC_DS
"Specifies the number of Bytes to be read or written per Dword used at
byte_scattered read/write and byte_scaled read/write messages."

>  
> 
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE = 0,
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_WORD = 1,
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD = 2
> +};
> +
>  #endif /* BRW_EU_DEFINES_H */
> diff --git a/src/intel/compiler/brw_eu_emit.c
> b/src/intel/compiler/brw_eu_emit.c
> index ca97ff7325..ded7e228cf 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2580,6 +2580,7 @@ brw_send_indirect_surface_message(struct
> brw_codegen *p,
>     return insn;
>  }
> 
> +
>  static bool
>  while_jumps_before_offset(const struct gen_device_info *devinfo,
>                            brw_inst *insn, int while_offset, int
> start_offset)
> @@ -2983,6 +2984,47 @@ brw_untyped_surface_write(struct brw_codegen *p,
>        p, insn, num_channels);
>  }
> 
> +static enum brw_data_size brw_data_size_from_bit_size(unsigned
> bit_size)
> 
> 
> Please put the return type on 

Re: [Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

[Pohjolainen, Topi]

On Thu, Nov 30, 2017 at 03:08:02AM +0100, Jose Maria Casanova Crespo wrote:
> v2: (Jason Ekstrand)
> - Enable bit_size parameter to scattered messages to enable different
>   bitsizes byte/word/dword.
> - Remove use of brw_send_indirect_scattered_message in favor of
>   brw_send_indirect_surface_message.
> - Move scattered messages to surface messages namespace.
> - Assert align1 for scattered messages and assume Gen8+.
> - Inline brw_set_dp_byte_scattered_write.
> 
> Signed-off-by: Jose Maria Casanova Crespo 
> Signed-off-by: Alejandro Piñeiro 
> ---
>  src/intel/compiler/brw_eu.h|  7 +
>  src/intel/compiler/brw_eu_defines.h| 17 +++
>  src/intel/compiler/brw_eu_emit.c   | 42 
> ++
>  src/intel/compiler/brw_fs.cpp  | 14 +
>  src/intel/compiler/brw_fs_copy_propagation.cpp |  2 ++
>  src/intel/compiler/brw_fs_generator.cpp|  6 
>  src/intel/compiler/brw_fs_surface_builder.cpp  | 11 +++
>  src/intel/compiler/brw_fs_surface_builder.h|  7 +
>  src/intel/compiler/brw_shader.cpp  |  7 +
>  9 files changed, 113 insertions(+)
> 
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 343dcd867d..3ac3b4342a 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -485,6 +485,13 @@ brw_typed_surface_write(struct brw_codegen *p,
>  unsigned msg_length,
>  unsigned num_channels);
>  
> +void
> +brw_byte_scattered_write(struct brw_codegen *p,
> + struct brw_reg payload,
> + struct brw_reg surface,
> + unsigned msg_length,
> + unsigned bit_size);
> +
>  void
>  brw_memory_fence(struct brw_codegen *p,
>   struct brw_reg dst);
> diff --git a/src/intel/compiler/brw_eu_defines.h 
> b/src/intel/compiler/brw_eu_defines.h
> index 9d5cf05c86..de6330ee54 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -402,6 +402,16 @@ enum opcode {
>  
> SHADER_OPCODE_RND_MODE,
>  
> +   /**
> +* Byte scattered write/read opcodes.
> +*
> +* LOGICAL opcodes are eventually translated to the matching non-LOGICAL
> +* opcode, but instead of taking a single payload blog they expect their
> +* arguments separately as individual sources, like untyped write/read.
> +*/
> +   SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> +   SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
> +
> SHADER_OPCODE_MEMORY_FENCE,
>  
> SHADER_OPCODE_GEN4_SCRATCH_READ,
> @@ -1255,4 +1265,11 @@ enum PACKED brw_rnd_mode {
> BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
>  };
>  
> +/* MDC_DS - Data Size Message Descriptor Control Field */
> +enum PACKED brw_data_size {
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE = 0,
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_WORD = 1,
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD = 2
> +};
> +
>  #endif /* BRW_EU_DEFINES_H */
> diff --git a/src/intel/compiler/brw_eu_emit.c 
> b/src/intel/compiler/brw_eu_emit.c
> index ca97ff7325..ded7e228cf 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2580,6 +2580,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
> return insn;
>  }
>  
> +

Leftover?

>  static bool
>  while_jumps_before_offset(const struct gen_device_info *devinfo,
>brw_inst *insn, int while_offset, int start_offset)
> @@ -2983,6 +2984,47 @@ brw_untyped_surface_write(struct brw_codegen *p,
>p, insn, num_channels);
>  }
>  
> +static enum brw_data_size brw_data_size_from_bit_size(unsigned bit_size)
> +{
> +   switch (bit_size) {
> +   case 8:
> +  return GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE;
> +   case 16:
> +  return GEN7_BYTE_SCATTERED_DATA_SIZE_WORD;
> +   case 32:
> +  return GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD;
> +   default:
> +  unreachable("Unsupported bit_size for byte scattered messages");
> +   }
> +}
> +
> +void
> +brw_byte_scattered_write(struct brw_codegen *p,
> + struct brw_reg payload,
> + struct brw_reg surface,
> + unsigned msg_length,
> + unsigned bit_size)
> +{
> +   assert(brw_inst_access_mode(p->devinfo, p->current) == BRW_ALIGN_1);
> +   const struct gen_device_info *devinfo = p->devinfo;
> +   const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
> +
> +   struct brw_inst *insn = brw_send_indirect_surface_message(
> +  p, sfid, brw_writemask(brw_null_reg(), WRITEMASK_XYZW),
> +  payload, surface, msg_length, 0, true);
> +
> +   unsigned msg_control = brw_data_size_from_bit_size(bit_size) << 2;
> +
> +   if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)
> +  msg_control |= 1;
> +   else
> +

Re: [Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

[Jason Ekstrand]

On Wed, Nov 29, 2017 at 6:08 PM, Jose Maria Casanova Crespo <
jmcasan...@igalia.com> wrote:

> v2: (Jason Ekstrand)
> - Enable bit_size parameter to scattered messages to enable different
>   bitsizes byte/word/dword.
> - Remove use of brw_send_indirect_scattered_message in favor of
>   brw_send_indirect_surface_message.
> - Move scattered messages to surface messages namespace.
> - Assert align1 for scattered messages and assume Gen8+.
> - Inline brw_set_dp_byte_scattered_write.
>
> Signed-off-by: Jose Maria Casanova Crespo 
> Signed-off-by: Alejandro Piñeiro 
> ---
>  src/intel/compiler/brw_eu.h|  7 +
>  src/intel/compiler/brw_eu_defines.h| 17 +++
>  src/intel/compiler/brw_eu_emit.c   | 42
> ++
>  src/intel/compiler/brw_fs.cpp  | 14 +
>  src/intel/compiler/brw_fs_copy_propagation.cpp |  2 ++
>  src/intel/compiler/brw_fs_generator.cpp|  6 
>  src/intel/compiler/brw_fs_surface_builder.cpp  | 11 +++
>  src/intel/compiler/brw_fs_surface_builder.h|  7 +
>  src/intel/compiler/brw_shader.cpp  |  7 +
>  9 files changed, 113 insertions(+)
>
> diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
> index 343dcd867d..3ac3b4342a 100644
> --- a/src/intel/compiler/brw_eu.h
> +++ b/src/intel/compiler/brw_eu.h
> @@ -485,6 +485,13 @@ brw_typed_surface_write(struct brw_codegen *p,
>  unsigned msg_length,
>  unsigned num_channels);
>
> +void
> +brw_byte_scattered_write(struct brw_codegen *p,
> + struct brw_reg payload,
> + struct brw_reg surface,
> + unsigned msg_length,
> + unsigned bit_size);
> +
>  void
>  brw_memory_fence(struct brw_codegen *p,
>   struct brw_reg dst);
> diff --git a/src/intel/compiler/brw_eu_defines.h
> b/src/intel/compiler/brw_eu_defines.h
> index 9d5cf05c86..de6330ee54 100644
> --- a/src/intel/compiler/brw_eu_defines.h
> +++ b/src/intel/compiler/brw_eu_defines.h
> @@ -402,6 +402,16 @@ enum opcode {
>
> SHADER_OPCODE_RND_MODE,
>
> +   /**
> +* Byte scattered write/read opcodes.
> +*
> +* LOGICAL opcodes are eventually translated to the matching
> non-LOGICAL
> +* opcode, but instead of taking a single payload blog they expect
> their
> +* arguments separately as individual sources, like untyped write/read.
> +*/
> +   SHADER_OPCODE_BYTE_SCATTERED_WRITE,
> +   SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
> +
> SHADER_OPCODE_MEMORY_FENCE,
>
> SHADER_OPCODE_GEN4_SCRATCH_READ,
> @@ -1255,4 +1265,11 @@ enum PACKED brw_rnd_mode {
> BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
>  };
>
> +/* MDC_DS - Data Size Message Descriptor Control Field */
> +enum PACKED brw_data_size {
>

I'm not sure how I feel about this being an enum with such a generic name.


> +   GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE = 0,
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_WORD = 1,
> +   GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD = 2
> +};
> +
>  #endif /* BRW_EU_DEFINES_H */
> diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_
> emit.c
> index ca97ff7325..ded7e228cf 100644
> --- a/src/intel/compiler/brw_eu_emit.c
> +++ b/src/intel/compiler/brw_eu_emit.c
> @@ -2580,6 +2580,7 @@ brw_send_indirect_surface_message(struct
> brw_codegen *p,
> return insn;
>  }
>
> +
>  static bool
>  while_jumps_before_offset(const struct gen_device_info *devinfo,
>brw_inst *insn, int while_offset, int
> start_offset)
> @@ -2983,6 +2984,47 @@ brw_untyped_surface_write(struct brw_codegen *p,
>p, insn, num_channels);
>  }
>
> +static enum brw_data_size brw_data_size_from_bit_size(unsigned bit_size)
>

Please put the return type on it's own line.


> +{
> +   switch (bit_size) {
> +   case 8:
> +  return GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE;
> +   case 16:
> +  return GEN7_BYTE_SCATTERED_DATA_SIZE_WORD;
> +   case 32:
> +  return GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD;
> +   default:
> +  unreachable("Unsupported bit_size for byte scattered messages");
> +   }
> +}
> +
> +void
> +brw_byte_scattered_write(struct brw_codegen *p,
> + struct brw_reg payload,
> + struct brw_reg surface,
> + unsigned msg_length,
> + unsigned bit_size)
> +{
> +   assert(brw_inst_access_mode(p->devinfo, p->current) == BRW_ALIGN_1);
> +   const struct gen_device_info *devinfo = p->devinfo;
> +   const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
> +
> +   struct brw_inst *insn = brw_send_indirect_surface_message(
> +  p, sfid, brw_writemask(brw_null_reg(), WRITEMASK_XYZW),
> +  payload, surface, msg_length, 0, true);
> +
> +   unsigned msg_control = 

[Mesa-dev] [PATCH v4 18/44] i965/fs: Add byte scattered write message and fs support

[Jose Maria Casanova Crespo]

v2: (Jason Ekstrand)
- Enable bit_size parameter to scattered messages to enable different
  bitsizes byte/word/dword.
- Remove use of brw_send_indirect_scattered_message in favor of
  brw_send_indirect_surface_message.
- Move scattered messages to surface messages namespace.
- Assert align1 for scattered messages and assume Gen8+.
- Inline brw_set_dp_byte_scattered_write.

Signed-off-by: Jose Maria Casanova Crespo 
Signed-off-by: Alejandro Piñeiro 
---
 src/intel/compiler/brw_eu.h|  7 +
 src/intel/compiler/brw_eu_defines.h| 17 +++
 src/intel/compiler/brw_eu_emit.c   | 42 ++
 src/intel/compiler/brw_fs.cpp  | 14 +
 src/intel/compiler/brw_fs_copy_propagation.cpp |  2 ++
 src/intel/compiler/brw_fs_generator.cpp|  6 
 src/intel/compiler/brw_fs_surface_builder.cpp  | 11 +++
 src/intel/compiler/brw_fs_surface_builder.h|  7 +
 src/intel/compiler/brw_shader.cpp  |  7 +
 9 files changed, 113 insertions(+)

diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 343dcd867d..3ac3b4342a 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -485,6 +485,13 @@ brw_typed_surface_write(struct brw_codegen *p,
 unsigned msg_length,
 unsigned num_channels);
 
+void
+brw_byte_scattered_write(struct brw_codegen *p,
+ struct brw_reg payload,
+ struct brw_reg surface,
+ unsigned msg_length,
+ unsigned bit_size);
+
 void
 brw_memory_fence(struct brw_codegen *p,
  struct brw_reg dst);
diff --git a/src/intel/compiler/brw_eu_defines.h 
b/src/intel/compiler/brw_eu_defines.h
index 9d5cf05c86..de6330ee54 100644
--- a/src/intel/compiler/brw_eu_defines.h
+++ b/src/intel/compiler/brw_eu_defines.h
@@ -402,6 +402,16 @@ enum opcode {
 
SHADER_OPCODE_RND_MODE,
 
+   /**
+* Byte scattered write/read opcodes.
+*
+* LOGICAL opcodes are eventually translated to the matching non-LOGICAL
+* opcode, but instead of taking a single payload blog they expect their
+* arguments separately as individual sources, like untyped write/read.
+*/
+   SHADER_OPCODE_BYTE_SCATTERED_WRITE,
+   SHADER_OPCODE_BYTE_SCATTERED_WRITE_LOGICAL,
+
SHADER_OPCODE_MEMORY_FENCE,
 
SHADER_OPCODE_GEN4_SCRATCH_READ,
@@ -1255,4 +1265,11 @@ enum PACKED brw_rnd_mode {
BRW_RND_MODE_UNSPECIFIED,  /* Unspecified rounding mode */
 };
 
+/* MDC_DS - Data Size Message Descriptor Control Field */
+enum PACKED brw_data_size {
+   GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE = 0,
+   GEN7_BYTE_SCATTERED_DATA_SIZE_WORD = 1,
+   GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD = 2
+};
+
 #endif /* BRW_EU_DEFINES_H */
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index ca97ff7325..ded7e228cf 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -2580,6 +2580,7 @@ brw_send_indirect_surface_message(struct brw_codegen *p,
return insn;
 }
 
+
 static bool
 while_jumps_before_offset(const struct gen_device_info *devinfo,
   brw_inst *insn, int while_offset, int start_offset)
@@ -2983,6 +2984,47 @@ brw_untyped_surface_write(struct brw_codegen *p,
   p, insn, num_channels);
 }
 
+static enum brw_data_size brw_data_size_from_bit_size(unsigned bit_size)
+{
+   switch (bit_size) {
+   case 8:
+  return GEN7_BYTE_SCATTERED_DATA_SIZE_BYTE;
+   case 16:
+  return GEN7_BYTE_SCATTERED_DATA_SIZE_WORD;
+   case 32:
+  return GEN7_BYTE_SCATTERED_DATA_SIZE_DWORD;
+   default:
+  unreachable("Unsupported bit_size for byte scattered messages");
+   }
+}
+
+void
+brw_byte_scattered_write(struct brw_codegen *p,
+ struct brw_reg payload,
+ struct brw_reg surface,
+ unsigned msg_length,
+ unsigned bit_size)
+{
+   assert(brw_inst_access_mode(p->devinfo, p->current) == BRW_ALIGN_1);
+   const struct gen_device_info *devinfo = p->devinfo;
+   const unsigned sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
+
+   struct brw_inst *insn = brw_send_indirect_surface_message(
+  p, sfid, brw_writemask(brw_null_reg(), WRITEMASK_XYZW),
+  payload, surface, msg_length, 0, true);
+
+   unsigned msg_control = brw_data_size_from_bit_size(bit_size) << 2;
+
+   if (brw_inst_exec_size(devinfo, p->current) == BRW_EXECUTE_16)
+  msg_control |= 1;
+   else
+  msg_control |= 0;
+
+   brw_inst_set_dp_msg_type(devinfo, insn,
+HSW_DATAPORT_DC_PORT0_BYTE_SCATTERED_WRITE);
+   brw_inst_set_dp_msg_control(devinfo, insn, msg_control);
+}
+
 static void
 brw_set_dp_typed_atomic_message(struct brw_codegen *p,
 struct brw_inst *insn,
diff --git