Re: [Mesa-dev] [PATCH] intel/blorp: Use the hardware op for CCS ambiguate on gen10+

[Jason Ekstrand]

On Fri, Feb 2, 2018 at 6:47 PM, Nanley Chery  wrote:

> On Tue, Jan 30, 2018 at 05:20:07PM -0800, Jason Ekstrand wrote:
> > Completely untested.
>
> The message in your fdo branch looks good.
>
> > ---
> >  src/intel/blorp/blorp_clear.c | 12 +++-
> >  src/intel/blorp/blorp_genX_exec.h |  6 ++
> >  2 files changed, 17 insertions(+), 1 deletion(-)
> >
> > diff --git a/src/intel/blorp/blorp_clear.c
> b/src/intel/blorp/blorp_clear.c
> > index dd29d9e..32ec31b 100644
> > --- a/src/intel/blorp/blorp_clear.c
> > +++ b/src/intel/blorp/blorp_clear.c
> > @@ -758,7 +758,11 @@ blorp_ccs_resolve(struct blorp_batch *batch,
> > params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
> > params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
> >
> > -   if (batch->blorp->isl_dev->info->gen >= 9) {
> > +   if (batch->blorp->isl_dev->info->gen >= 10) {
> > +  assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
> > + resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
> > + resolve_op == ISL_AUX_OP_AMBIGUATE);
> > +   } else if (batch->blorp->isl_dev->info->gen >= 9) {
> >assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
> >   resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
> > } else {
> > @@ -893,6 +897,12 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
> >  struct blorp_surf *surf,
> >  uint32_t level, uint32_t layer)
> >  {
> > +   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
> > +  /* On gen10 and above, we have a hardware resolve op for this */
> > +  return blorp_ccs_resolve(batch, surf, level, layer, 1,
> > +   surf->surf->format,
> ISL_AUX_OP_AMBIGUATE);
>
> The HW docs describe the fast-clear-to-0 as occuring during a clear pass.
> Why are we doing it in a resolve pass?
>

The only difference between the two for CCS is that we have a bit of extra
alignment for fast-clears.  I've combed through all the docs I can find in
the bspec and I can't find the alignment requirement anymore.  In fact, I
found a nice little SKL+ line that says "The Resolve Rectangle size is same
as Clear Rectangle size from SKL+".  The extra alignment isn't hurting
anything but it also means that there's no real difference between clears
and resolves anymore.

--Jason



> > +   }
> > +
> > struct blorp_params params;
> > blorp_params_init();
> >
> > diff --git a/src/intel/blorp/blorp_genX_exec.h
> b/src/intel/blorp/blorp_genX_exec.h
> > index 5e1312a..85abf6b 100644
> > --- a/src/intel/blorp/blorp_genX_exec.h
> > +++ b/src/intel/blorp/blorp_genX_exec.h
> > @@ -752,6 +752,12 @@ blorp_emit_ps_config(struct blorp_batch *batch,
> >switch (params->fast_clear_op) {
> >case ISL_AUX_OP_NONE:
> >   break;
> > +#if GEN_GEN >= 10
> > +  case ISL_AUX_OP_AMBIGUATE:
> > + ps.RenderTargetFastClearEnable = true;
> > + ps.RenderTargetResolveType = FAST_CLEAR_0;
> > + break;
> > +#endif
> >  #if GEN_GEN >= 9
> >case ISL_AUX_OP_PARTIAL_RESOLVE:
> >   ps.RenderTargetResolveType = RESOLVE_PARTIAL;
> > --
> > 2.5.0.400.gff86faf
> >
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> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
>
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Re: [Mesa-dev] [PATCH] intel/blorp: Use the hardware op for CCS ambiguate on gen10+

[Nanley Chery]

On Tue, Jan 30, 2018 at 05:20:07PM -0800, Jason Ekstrand wrote:
> Completely untested.

The message in your fdo branch looks good.

> ---
>  src/intel/blorp/blorp_clear.c | 12 +++-
>  src/intel/blorp/blorp_genX_exec.h |  6 ++
>  2 files changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
> index dd29d9e..32ec31b 100644
> --- a/src/intel/blorp/blorp_clear.c
> +++ b/src/intel/blorp/blorp_clear.c
> @@ -758,7 +758,11 @@ blorp_ccs_resolve(struct blorp_batch *batch,
> params.x1 = ALIGN(params.x1, x_scaledown) / x_scaledown;
> params.y1 = ALIGN(params.y1, y_scaledown) / y_scaledown;
>  
> -   if (batch->blorp->isl_dev->info->gen >= 9) {
> +   if (batch->blorp->isl_dev->info->gen >= 10) {
> +  assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
> + resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE ||
> + resolve_op == ISL_AUX_OP_AMBIGUATE);
> +   } else if (batch->blorp->isl_dev->info->gen >= 9) {
>assert(resolve_op == ISL_AUX_OP_FULL_RESOLVE ||
>   resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
> } else {
> @@ -893,6 +897,12 @@ blorp_ccs_ambiguate(struct blorp_batch *batch,
>  struct blorp_surf *surf,
>  uint32_t level, uint32_t layer)
>  {
> +   if (ISL_DEV_GEN(batch->blorp->isl_dev) >= 10) {
> +  /* On gen10 and above, we have a hardware resolve op for this */
> +  return blorp_ccs_resolve(batch, surf, level, layer, 1,
> +   surf->surf->format, ISL_AUX_OP_AMBIGUATE);

The HW docs describe the fast-clear-to-0 as occuring during a clear pass.
Why are we doing it in a resolve pass?

> +   }
> +
> struct blorp_params params;
> blorp_params_init();
>  
> diff --git a/src/intel/blorp/blorp_genX_exec.h 
> b/src/intel/blorp/blorp_genX_exec.h
> index 5e1312a..85abf6b 100644
> --- a/src/intel/blorp/blorp_genX_exec.h
> +++ b/src/intel/blorp/blorp_genX_exec.h
> @@ -752,6 +752,12 @@ blorp_emit_ps_config(struct blorp_batch *batch,
>switch (params->fast_clear_op) {
>case ISL_AUX_OP_NONE:
>   break;
> +#if GEN_GEN >= 10
> +  case ISL_AUX_OP_AMBIGUATE:
> + ps.RenderTargetFastClearEnable = true;
> + ps.RenderTargetResolveType = FAST_CLEAR_0;
> + break;
> +#endif
>  #if GEN_GEN >= 9
>case ISL_AUX_OP_PARTIAL_RESOLVE:
>   ps.RenderTargetResolveType = RESOLVE_PARTIAL;
> -- 
> 2.5.0.400.gff86faf
> 
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