Re: [Mesa-dev] [PATCH] intel: decoder: unify MI_BB_START field naming
I think I have a similar patch laying around in my 2nd level batch buffer
branch. :)
Reviewed-by: Jason Ekstrand
On Tue, Aug 14, 2018 at 5:26 AM Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> The batch decoder looks for a field with a particular name to decide
> whether an MI_BB_START leads into a second batch buffer level. Because
> the names are different between Gen7.5/8 and the newer generation we
> fail that test and keep on reading (invalid) instructions.
>
> Signed-off-by: Lionel Landwerlin
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107544
> ---
> src/intel/genxml/gen75.xml | 6 +++---
> src/intel/genxml/gen8.xml | 6 +++---
> src/intel/vulkan/anv_batch_chain.c | 2 +-
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
> index 5b01fd45400..dfc3d891498 100644
> --- a/src/intel/genxml/gen75.xml
> +++ b/src/intel/genxml/gen75.xml
> @@ -2314,9 +2314,9 @@
>
> default="0"/>
> default="49"/>
> -
> -
> -
> + type="uint">
> +
> +
>
>
>
> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
> index 4ed41d15612..330366b7ed0 100644
> --- a/src/intel/genxml/gen8.xml
> +++ b/src/intel/genxml/gen8.xml
> @@ -2553,9 +2553,9 @@
>
> default="0"/>
> default="49"/>
> -
> -
> -
> + type="uint">
> +
> +
>
>
>
> diff --git a/src/intel/vulkan/anv_batch_chain.c
> b/src/intel/vulkan/anv_batch_chain.c
> index c47a81c8a4d..0f7c8325ea4 100644
> --- a/src/intel/vulkan/anv_batch_chain.c
> +++ b/src/intel/vulkan/anv_batch_chain.c
> @@ -531,7 +531,7 @@ emit_batch_buffer_start(struct anv_cmd_buffer
> *cmd_buffer,
> anv_batch_emit(_buffer->batch, GEN8_MI_BATCH_BUFFER_START, bbs) {
>bbs.DWordLength = cmd_buffer->device->info.gen < 8 ?
>gen7_length : gen8_length;
> - bbs._2ndLevelBatchBuffer = _1stlevelbatch;
> + bbs.SecondLevelBatchBuffer= Firstlevelbatch;
>bbs.AddressSpaceIndicator = ASI_PPGTT;
>bbs.BatchBufferStartAddress = (struct anv_address) { bo, offset };
> }
> --
> 2.18.0
>
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Re: [Mesa-dev] [PATCH] radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
On 8/15/18 11:49 AM, Jason Ekstrand wrote:
On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
mailto:samuel.pitoi...@gmail.com>> wrote:
Reviewed-by: Samuel Pitoiset mailto:samuel.pitoi...@gmail.com>>
On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
> Behavior wrt firstInstance got changed, and a divisor of 0 has been
> disallowed.
>
> The new version of the ext got published in specification 1.1.81.
> ---
> src/amd/vulkan/radv_extensions.py | 2 +-
> src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
> index a5fbffac33b..d02042e5647 100644
> --- a/src/amd/vulkan/radv_extensions.py
> +++ b/src/amd/vulkan/radv_extensions.py
> @@ -104,7 +104,7 @@ EXTENSIONS = [
> Extension('VK_EXT_sampler_filter_minmax', 1,
'device->rad_info.chip_class >= CIK'),
> Extension('VK_EXT_shader_viewport_index_layer', 1, True),
> Extension('VK_EXT_shader_stencil_export', 1, True),
> - Extension('VK_EXT_vertex_attribute_divisor', 1, True),
> + Extension('VK_EXT_vertex_attribute_divisor', 2, True),
> Extension('VK_AMD_draw_indirect_count', 1, True),
> Extension('VK_AMD_gcn_shader', 1, True),
> Extension('VK_AMD_rasterization_order', 1,
'device->has_out_of_order_rast'),
> diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
> index c7d772fa652..d12ef09c9f3 100644
> --- a/src/amd/vulkan/radv_nir_to_llvm.c
> +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> @@ -1984,8 +1984,7 @@ handle_vs_input_decl(struct
radv_shader_context *ctx,
> uint32_t divisor =
ctx->options->key.vs.instance_rate_divisors[attrib_index];
>
> if (divisor) {
> - buffer_index =
LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
> -
ctx->abi.start_instance, "");
> + buffer_index = ctx->abi.instance_id;
>
> if (divisor != 1) {
> buffer_index =
LLVMBuildUDiv(ctx->ac.builder, buffer_index,
> @@ -2000,8 +1999,10 @@ handle_vs_input_decl(struct
radv_shader_context *ctx,
> MAX2(1,
ctx->shader_info->vs.vgpr_comp_cnt);
> }
> } else {
> - buffer_index = ctx->ac.i32_0;
> + unreachable("Invalid vertex
attribute divisor of 0.");
You'll want to leave this alone. zero is coming back... Yeah, I know
it's annoying but I'm really trying to get this settled out as quickly
as possible. In the mean time, reports are that zero is useful for some
DXVK apps so it's best to just silently support it rather than breaking
stuff.
Yeah, you are right. I have just reached that assertion with a DXVK app...
> }
> +
> + buffer_index =
LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index,
"");
> } else
> buffer_index =
LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
>
ctx->abi.base_vertex, "");
>
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[Mesa-dev] [PATCH] Add NV_fragment_shader_interlock support.
From: Kevin Rogovin
The main purpose for having NV_fragment_shader_interlock
extension is because that extension is also for GLES31 while
the ARB extension is for GL only.
---
src/compiler/glsl/builtin_functions.cpp | 18 ++
src/compiler/glsl/glsl_parser.yy | 6 --
src/compiler/glsl/glsl_parser_extras.cpp | 1 +
src/compiler/glsl/glsl_parser_extras.h | 2 ++
src/mesa/main/extensions_table.h | 1 +
5 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl/builtin_functions.cpp
b/src/compiler/glsl/builtin_functions.cpp
index 7119903795..e7b78c0158 100644
--- a/src/compiler/glsl/builtin_functions.cpp
+++ b/src/compiler/glsl/builtin_functions.cpp
@@ -519,6 +519,12 @@ supports_arb_fragment_shader_interlock(const
_mesa_glsl_parse_state *state)
return state->ARB_fragment_shader_interlock_enable;
}
+static bool
+supports_nv_fragment_shader_interlock(const _mesa_glsl_parse_state *state)
+{
+ return state->NV_fragment_shader_interlock_enable;
+}
+
static bool
shader_clock(const _mesa_glsl_parse_state *state)
{
@@ -3331,6 +3337,18 @@ builtin_builder::create_builtins()
supports_arb_fragment_shader_interlock),
NULL);
+ add_function("beginInvocationInterlockNV",
+_invocation_interlock(
+ "__intrinsic_begin_invocation_interlock",
+ supports_nv_fragment_shader_interlock),
+NULL);
+
+ add_function("endInvocationInterlockNV",
+_invocation_interlock(
+ "__intrinsic_end_invocation_interlock",
+ supports_nv_fragment_shader_interlock),
+NULL);
+
add_function("anyInvocationARB",
_vote("__intrinsic_vote_any", vote),
NULL);
diff --git a/src/compiler/glsl/glsl_parser.yy b/src/compiler/glsl/glsl_parser.yy
index cb7376995d..bc2571b684 100644
--- a/src/compiler/glsl/glsl_parser.yy
+++ b/src/compiler/glsl/glsl_parser.yy
@@ -1450,10 +1450,12 @@ layout_qualifier_id:
"only valid in fragment shader input layout
declaration.");
} else if (pixel_interlock_ordered + pixel_interlock_unordered +
sample_interlock_ordered + sample_interlock_unordered > 0 &&
- !state->ARB_fragment_shader_interlock_enable) {
+ !state->ARB_fragment_shader_interlock_enable &&
+ !state->NV_fragment_shader_interlock_enable) {
_mesa_glsl_error(& @1, state,
"interlock layout qualifier present, but the "
- "GL_ARB_fragment_shader_interlock extension is not "
+ "GL_ARB_fragment_shader_interlock or "
+ "GL_NV_fragment_shader_interlock extension is not "
"enabled.");
} else {
$$.flags.q.pixel_interlock_ordered = pixel_interlock_ordered;
diff --git a/src/compiler/glsl/glsl_parser_extras.cpp
b/src/compiler/glsl/glsl_parser_extras.cpp
index 6d92f24ea2..393942b62c 100644
--- a/src/compiler/glsl/glsl_parser_extras.cpp
+++ b/src/compiler/glsl/glsl_parser_extras.cpp
@@ -724,6 +724,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT_AEP(EXT_texture_cube_map_array),
EXT(INTEL_conservative_rasterization),
EXT(MESA_shader_integer_functions),
+ EXT(NV_fragment_shader_interlock),
EXT(NV_image_formats),
};
diff --git a/src/compiler/glsl/glsl_parser_extras.h
b/src/compiler/glsl/glsl_parser_extras.h
index 59a173418b..3b17b54f0a 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -810,6 +810,8 @@ struct _mesa_glsl_parse_state {
bool INTEL_conservative_rasterization_warn;
bool MESA_shader_integer_functions_enable;
bool MESA_shader_integer_functions_warn;
+ bool NV_fragment_shader_interlock_enable;
+ bool NV_fragment_shader_interlock_warn;
bool NV_image_formats_enable;
bool NV_image_formats_warn;
/*@}*/
diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index af5ce118da..746e821886 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -346,6 +346,7 @@ EXT(NV_draw_buffers , dummy_true
EXT(NV_fbo_color_attachments, dummy_true
, x , x , x , ES2, 2010)
EXT(NV_fill_rectangle , NV_fill_rectangle
, GLL, GLC, x , x , 2015)
EXT(NV_fog_distance , NV_fog_distance
, GLL, x , x , x , 2001)
+EXT(NV_fragment_shader_interlock, ARB_fragment_shader_interlock
, GLL, GLC, x , 31, 2015)
EXT(NV_image_formats, ARB_shader_image_load_store
, x , x , x , 31, 2014)
EXT(NV_light_max_exponent , dummy_true
Re: [Mesa-dev] [PATCH] radv/meta_decompress: fix pointer to integer conversion
Hi Bas,
Il giorno mar 14 ago 2018 alle ore 23:10 Bas Nieuwenhuizen <
b...@basnieuwenhuizen.nl> ha scritto:
> On Tue, Aug 14, 2018 at 10:48 PM, Mauro Rossi
> wrote:
> > (VkShaderModule) cast is added before NULL to avoid following building
> error:
> >
> > external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error:
> > incompatible pointer to integer conversion passing 'void *' to parameter
> > of type 'VkShaderModule' (aka 'unsigned long long')
> [-Werror,-Wint-conversion]
> > VkResult ret = create_pipeline(cmd_buffer->device, NULL,
> samples,
> >^~~~
> >
> prebuilts/clang/host/linux-x86/clang-4053586/lib64/clang/5.0.300080/include/stddef.h:105:16:
> > note: expanded from macro 'NULL'
> > # define NULL ((void*)0)
> >^~
> > external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32:
> > note: passing argument to parameter 'vs_module_h' here
> > VkShaderModule vs_module_h,
> >^
> > 1 error generated.
> >
> > Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in
> shaders.")
> > Signed-off-by: Mauro Rossi
> > ---
> > src/amd/vulkan/radv_meta_decompress.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/src/amd/vulkan/radv_meta_decompress.c
> b/src/amd/vulkan/radv_meta_decompress.c
> > index 41ed7b6d04..183be1fd88 100644
> > --- a/src/amd/vulkan/radv_meta_decompress.c
> > +++ b/src/amd/vulkan/radv_meta_decompress.c
> > @@ -362,7 +362,7 @@ static void radv_process_depth_image_inplace(struct
> radv_cmd_buffer *cmd_buffer,
> > return;
> >
> > if (!meta_state->depth_decomp[samples_log2].decompress_pipeline)
> {
> > - VkResult ret = create_pipeline(cmd_buffer->device, NULL,
> samples,
> > + VkResult ret = create_pipeline(cmd_buffer->device,
> (VkShaderModule) NULL, samples,
>
> Instead of the cast, use VK_NULL_HANDLE.
>
I've applied that change and it is working.
Do you prefer I send a v2 patch version to mesa-dev ML or may I apply to
gitlab master with your Reviewed-by ?
Thanks
Mauro
>
> >
> meta_state->depth_decomp[samples_log2].pass,
> >
> meta_state->depth_decomp[samples_log2].p_layout,
> >
> _state->depth_decomp[samples_log2].decompress_pipeline,
> > --
> > 2.17.1
> >
>
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Re: [Mesa-dev] [PATCH v2] intel/decoder: fix the possible out of bounds group_iter
Hi all,
Thanks for your reply.
We shouldn't even get to use the iterator if it's an unknown instruction.
> The decoder should just advance dword by dword until it finds something
> that
> makes sense again.
>
Got it)
So this is an expected behavior there:
return iter_group_offset_bits(iter, iter->group_iter + 1) <
> (gen_group_get_length(iter->group, iter->p) * 32);
>
when we convert a negative *int* to *uint* to return true to continue our
loop.
return iter_group_offset_bits(iter, iter->group_iter + 1) <
> (*0xFFE0U*);
>
Do you think it is good idea to add comment or something like this into the
"iter_more_groups" function:
int *length* = gen_group_get_length(iter->group, iter->p);
>
return *length < 0 ||*
>iter_group_offset_bits(iter, iter->group_iter + 1) <
> (*length* * 32);
>
to show more explicitly here that we want to return true to continue our
loop
when the -1 is returned from the "gen_group_get_length" function
because at the moment it is a bit implicit)
Please let me know if I am incorrect.
Regards,
Andrii.
On Tue, Aug 14, 2018 at 7:08 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> On 14/08/18 16:16, Rafael Antognolli wrote:
>
>> On Tue, Aug 14, 2018 at 03:36:18PM +0100, Lionel Landwerlin wrote:
>>
>>> On 14/08/18 12:55, asimiklit.work wrote:
>>>
Hi Lionel,
> Hi Andrii,
>
> Again sorry, I don't think this is the right fix.
> I'm sending another patch to fix the parsing of
> MI_BATCH_BUFFER_START which seems to be the actual issue.
>
> Thanks for working on this,
>
Thanks for your fast reply.
I agree that it is not correct patch for this issue but anyway
"iter_more_groups" function will still work incorrectly
for unknown instructions when the "iter->group->variable" field is true.
I guess that this case should be fixed.
Please let me know if I am incorrect.
>>> Hey Andrii,
>>>
>>> We shouldn't even get to use the iterator if it's an unknown instruction.
>>> The decoder should just advance dword by dword until it finds something
>>> that
>>> makes sense again.
>>>
>>> If we run into that problem, I think we should fix the caller.
>>>
>> In that case, would an unreachable() or assert be a good thing to do?
>>
>
> Yep, I guess assert in gen_field_iterator_init() should be a good thing.
>
>
>> Regards,
Andrii.
On 2018-08-14 1:26 PM, Lionel Landwerlin wrote:
> Hi Andrii,
>
> Again sorry, I don't think this is the right fix.
> I'm sending another patch to fix the parsing of
> MI_BATCH_BUFFER_START which seems to be the actual issue.
>
> Thanks for working on this,
>
> -
> Lionel
>
> On 14/08/18 10:04, asimiklit.w...@gmail.com wrote:
>
>> From: Andrii Simiklit
>>
>> The "gen_group_get_length" function can return a negative value
>> and it can lead to the out of bounds group_iter.
>>
>> v2: printing of "unknown command type" was added
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107544
>> Signed-off-by: Andrii Simiklit
>> ---
>>src/intel/common/gen_decoder.c | 13 +++--
>>1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/src/intel/common/gen_decoder.c
>> b/src/intel/common/gen_decoder.c
>> index ec0a486..b36facf 100644
>> --- a/src/intel/common/gen_decoder.c
>> +++ b/src/intel/common/gen_decoder.c
>> @@ -770,6 +770,13 @@ gen_group_get_length(struct gen_group
>> *group, const uint32_t *p)
>>return -1;
>> }
>> }
>> + default: {
>> + fprintf(stderr, "Unknown command type %u in '%s::%s'\n",
>> +type,
>> +(group->parent && group->parent->name) ?
>> group->parent->name : "UNKNOWN",
>> +group->name ? group->name : "UNKNOWN");
>> + break;
>> + }
>> }
>> return -1;
>> @@ -803,8 +810,10 @@ static bool
>>iter_more_groups(const struct gen_field_iterator *iter)
>>{
>> if (iter->group->variable) {
>> - return iter_group_offset_bits(iter, iter->group_iter + 1) <
>> - (gen_group_get_length(iter->group, iter->p) * 32);
>> + const int length = gen_group_get_length(iter->group, iter->p);
>> + return length > 0 &&
>> +iter_group_offset_bits(iter, iter->group_iter + 1) <
>> + (length * 32);
>> } else {
>> return (iter->group_iter + 1) < iter->group->group_count ||
>> iter->group->next != NULL;
>>
>
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>>>
>>>
>
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Re: [Mesa-dev] [PATCH 09/21] mesa: remove legacy TCL dri config options
On 2018-08-15 12:13 PM, Timothy Arceri wrote: > Use enviroment var overrides in legacy drivers instead. This could break existing user configurations using the driconf tcl_mode option. Apart from this, I like the idea of this series. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] egl/android: fix regression in drm_gralloc path
On 15 August 2018 at 09:13, Mauro Rossi wrote:
> Hi Robert,
> Il giorno mer 15 ago 2018 alle ore 09:37 Robert Foss
> ha scritto:
>>
>> Hey Mauro,
>>
>> Thanks for catching this.
>>
>> On 14/08/2018 22.27, Mauro Rossi wrote:
>> > This patch fixes a regression in mesa 18.2 and mesa-dev branches
>> > for HAVE_DRM_GRALLOC code path which is causing black screen on Android
>> > and prevents boot due to SIGSEGV MAPERR crash related to unproper
>> > handling
>> > of drm_gralloc drm FD in new droid_open_device() path.
>> >
>> > The problem due to c7bb82136b ("egl/android: Add DRM node probing and
>> > filtering")
>> >
>> > ... 3173 3307 D GRALLOC-DRM: drmOpen radeon: 71
>> > ... 3173 3307 I GRALLOC-RADEON: detected chipset 0x6841 family 0x31
>> > (vram size 238MiB, gart size 1021MiB)
>> > ... 3173 3307 I GRALLOC-DRM: create radeon for driver radeon
>> > ... 3173 3307 W EGL-MAIN: Could not get native buffer FD
>> > - beginning of crash
>> > ... 3173 3307 F libc: Fatal signal 11 (SIGSEGV), code 1, fault
>> > addr 0x18 in tid 3307 (RenderThread), pid 3173 (ndroid.systemui)
>> > ... 0 0 D : [drm:radeon_crtc_page_flip_target [radeon]]
>> > flip-ioctl() cur_rbo = 3512328a, new_rbo = 00
>> > ... 3420 3420 I crash_dump64: performing dump of process 3173 (target
>> > tid = 3307)
>> > ... 3420 3420 F DEBUG : *** *** *** *** *** *** *** *** *** *** ***
>> > *** *** *** *** ***
>> > ... 3420 3420 F DEBUG : Build fingerprint:
>> > 'Android-x86/android_x86_64/x86_64:8.1.0/OPM6.171019.030.E1/uten07210645:userdebug/test-keys'
>> > ... 3420 3420 F DEBUG : Revision: '0'
>> > ... 3420 3420 F DEBUG : ABI: 'x86_64'
>> > ... 3420 3420 F DEBUG : pid: 3173, tid: 3307, name: RenderThread
>> > >>> com.android.systemui <<<
>> > ... 3420 3420 F DEBUG : signal 11 (SIGSEGV), code 1 (SEGV_MAPERR),
>> > fault addr 0x18
>> > ... 3420 3420 F DEBUG : Cause: null pointer dereference
>> > ... 3420 3420 F DEBUG : rax rbx
>> > 7c6ac3a3eee0 rcx rdx 0038
>> > ... 3420 3420 F DEBUG : rsi rdi
>> > 7c6ab5bfeaa0
>> > ... 3420 3420 F DEBUG : r8 7c6ab04c16e4 r9
>> > 7c6b4ee6a220 r10 r11 0200
>> > ... 3420 3420 F DEBUG : r12 r13
>> > r14 0001 r15 7c6ab04c1600
>> > ... 3420 3420 F DEBUG : cs 0033 ss
>> > 002b
>> > ... 3420 3420 F DEBUG : rip 7c6ab0cee444 rbp
>> > 7c6ac3ae8400 rsp 7c6ab5bfea80 eflags 00010246
>> > ... 3420 3420 F DEBUG :
>> > ... 3420 3420 F DEBUG : backtrace:
>> > ... 3420 3420 F DEBUG : #00 pc 0056b444
>> > /system/vendor/lib64/dri/gallium_dri.so (st_update_framebuffer_state+660)
>> > ... 3420 3420 F DEBUG : #01 pc 00569d61
>> > /system/vendor/lib64/dri/gallium_dri.so (st_validate_state+561)
>> > ... 3420 3420 F DEBUG : #02 pc 00572374
>> > /system/vendor/lib64/dri/gallium_dri.so (st_Clear+116)
>> > ... 3420 3420 F DEBUG : #03 pc 0004a9c0
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #04 pc 00085cab
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #05 pc 00085f31
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #06 pc 0006e8c1
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #07 pc 0006e3d9
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #08 pc 0006c4e3
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #09 pc 000704c8
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #10 pc 00077fb9
>> > /android/system/lib64/libhwui.so
>> > ... 3420 3420 F DEBUG : #11 pc 000117fa
>> > /android/system/lib64/libutils.so
>> > ... 3420 3420 F DEBUG : #12 pc 000ba193
>> > /android/system/lib64/libandroid_runtime.so
>> > ... 3420 3420 F DEBUG : #13 pc 00079f0b
>> > /android/system/lib64/libc.so
>> > ... 3420 3420 F DEBUG : #14 pc 00028c5d
>> > /android/system/lib64/libc.so
>> > ... 3420 3420 F DEBUG : #15 pc 00027555
>> > /android/system/lib64/libc.so
>> >
>> > To avoid the crash the former existing working droid_open_device() is
>> > restored,
>> > renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC
>> > braces.
>> >
>> > NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD
>> > is not necessary and it is actually causing a redefinition building
>> > error,
>> > because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported
>> > by libgralloc_drm which is currently still a dependency.
>> >
>> > Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation
>> > and Androdi GUI booting is fixed
Re: [Mesa-dev] [PATCH] radv: add Doom workaround
Do you need the game name here, isn't that set in driconf?
On Wed, 15 Aug 2018 at 12:12 Timothy Arceri wrote:
> Cc:
> ---
> src/amd/vulkan/radv_device.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 33f24b9d302..cc88abb57a8 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -480,6 +480,9 @@ radv_handle_per_app_options(struct radv_instance
> *instance,
> */
> instance->perftest_flags |= RADV_PERFTEST_SISCHED;
> }
> + } else if (!strcmp(name, "DOOM_VFR")) {
> + /* Work around a Doom VFR game bug */
> + instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
> }
> }
>
> --
> 2.17.1
>
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Re: [Mesa-dev] [PATCH v5 1/2] intel/ppgtt: memory address alignment
On 15/08/18 12:23, Sergii Romantsov wrote:
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to
brw_bufmgr.)
Signed-off-by: Sergii Romantsov
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..19e2d14 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
uint32_t stride)
{
struct brw_bo *bo;
- unsigned int page_size = getpagesize();
int ret;
struct bo_cache_bucket *bucket;
bool alloc_from_cache;
@@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
* allocation up.
*/
if (bucket == NULL) {
- bo_size = size;
- if (bo_size < page_size)
- bo_size = page_size;
+ unsigned int page_size = getpagesize();
+ bo_size = size == 0 ? page_size : ALIGN(size, page_size);
You could even have :
bo_size = MIN(page_size, ALIGN(size, page_size));
Let me run this through the CI.
Thanks,
-
Lionel
} else {
bo_size = bucket->size;
}
+ assert(bo_size);
mtx_lock(>lock);
/* Get a buffer out of the cache if available */
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[Mesa-dev] [PATCH] radv: disable the auto-waitcnt-before-barrier LLVM option
This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.
Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_llvm_util.c | 3 ++-
src/amd/common/ac_llvm_util.h | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 10e1ca99d4..008a2cfa4e 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -149,7 +149,8 @@ static LLVMTargetMachineRef ac_create_target_machine(enum
radeon_family family,
char features[256];
const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ?
"amdgcn-mesa-mesa3d" : "amdgcn--";
LLVMTargetRef target = ac_get_llvm_target(triple);
- bool barrier_does_waitcnt = family != CHIP_VEGA20;
+ bool barrier_does_waitcnt = tm_options &
AC_TM_AUTO_WAITCNT_BEFORE_BARRIER &&
+ family != CHIP_VEGA20;
snprintf(features, sizeof(features),
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index eaf5f21876..e252bed3bb 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -65,6 +65,7 @@ enum ac_target_machine_options {
AC_TM_CHECK_IR = (1 << 5),
AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
AC_TM_CREATE_LOW_OPT = (1 << 7),
+ AC_TM_AUTO_WAITCNT_BEFORE_BARRIER = (1 << 8),
};
enum ac_float_mode {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 13fcf1f3ae..4327a3f749 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -115,6 +115,7 @@ static void si_init_compiler(struct si_screen *sscreen,
sscreen->info.chip_class <= VI;
enum ac_target_machine_options tm_options =
+ AC_TM_AUTO_WAITCNT_BEFORE_BARRIER |
(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
(sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL :
0) |
(sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK :
0) |
--
2.18.0
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[Mesa-dev] [PATCH] egl/android: do not indent HAVE_DRM_GRALLOC preprocessor directive
Fixes: 3f7bca44d9 ("egl/android: #ifdef out flink name support")
Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering")
Signed-off-by: Mauro Rossi
---
src/egl/drivers/dri2/platform_android.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 834bbd258e..f8c85f97cf 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -1226,7 +1226,7 @@ droid_load_driver(_EGLDisplay *disp)
dri2_dpy->is_render_node = drmGetNodeTypeFromFd(dri2_dpy->fd) ==
DRM_NODE_RENDER;
if (!dri2_dpy->is_render_node) {
- #ifdef HAVE_DRM_GRALLOC
+#ifdef HAVE_DRM_GRALLOC
/* Handle control nodes using __DRI_DRI2_LOADER extension and GEM names
* for backwards compatibility with drm_gralloc. (Do not use on new
* systems.) */
@@ -1235,10 +1235,10 @@ droid_load_driver(_EGLDisplay *disp)
err = "DRI2: failed to load driver";
goto error;
}
- #else
+#else
err = "DRI2: handle is not for a render node";
goto error;
- #endif
+#endif
} else {
dri2_dpy->loader_extensions = droid_image_loader_extensions;
if (!dri2_load_driver_dri3(disp)) {
--
2.17.1
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Re: [Mesa-dev] [PATCH v3 1/6] xmlconfig: refine driParseConfigFiles to use parseOneConfigFile
On 2018-08-06 05:19 AM, Qiang Yu wrote:
> Also prepare for the usage of following parseConfigDir patch.
>
> Signed-off-by: Qiang Yu
> ---
> src/util/xmlconfig.c | 62
>
> 1 file changed, 28 insertions(+), 34 deletions(-)
>
> diff --git a/src/util/xmlconfig.c b/src/util/xmlconfig.c
> index d384791..50beede 100644
> --- a/src/util/xmlconfig.c
> +++ b/src/util/xmlconfig.c
> @@ -866,9 +866,8 @@ initOptionCache(driOptionCache *cache, const
> driOptionCache *info)
> }
> }
>
> -/** \brief Parse the named configuration file */
> static void
> -parseOneConfigFile(XML_Parser p)
> +_parseOneConfigFile(XML_Parser p)
> {
> #define BUF_SIZE 0x1000
> struct OptConfData *data = (struct OptConfData *)XML_GetUserData (p);
> @@ -907,6 +906,28 @@ parseOneConfigFile(XML_Parser p)
> #undef BUF_SIZE
> }
>
> +/** \brief Parse the named configuration file */
> +static void
> +parseOneConfigFile(struct OptConfData *data, const char *filename)
> +{
> +XML_Parser p;
> +
> +p = XML_ParserCreate (NULL); /* use encoding specified by file */
> +XML_SetElementHandler (p, optConfStartElem, optConfEndElem);
> +XML_SetUserData (p, data);
> +data->parser = p;
> +data->name = filename;
> +data->ignoringDevice = 0;
> +data->ignoringApp = 0;
> +data->inDriConf = 0;
> +data->inDevice = 0;
> +data->inApp = 0;
> +data->inOption = 0;
> +
> +_parseOneConfigFile (p);
> +XML_ParserFree (p);
> +}
What's the point of having the separate _parseOneConfigFile function?
It's not used outside of parseOneConfigFile AFAICT.
Apart from this, the series is
Acked-by: Michel Dänzer
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Mesa and X developer
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Re: [Mesa-dev] [PATCH 0/8] Easy OpenGL extensions
Ah, with 'latest' stuff only #8 choke. Dieter Am 15.08.2018 11:21, schrieb Dieter Nützel: Hello Marek, sadly this series didn't apply on top of current git master. Dieter Am 09.08.2018 04:12, schrieb Marek Olšák: Hi, This series adds these extensions: - AMD_gpu_shader_int64 - AMD_multi_draw_indirect - AMD_query_buffer_object - AMD_texture_texture4 - EXT_vertex_attrib_64bit It also exposes these extensions for gallium (radeonsi): - EXT_disjoint_timer_query - KHR_texture_compression_astc_sliced_3d It also allows this in the Compatibility profile: - ARB_post_depth_coverage (not supported by radeonsi) Please review. Thanks, Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/5] nir: Lower flrp(1.0, b, c) and flrp(a, 1.0, c) differently
re-associating based on whether or not something has a constant value of
1.0 seems a bit sneaky. I think it's well within the rules but it seems
like something that could bite you.
On Mon, Aug 13, 2018 at 6:35 PM Ian Romanick wrote:
> From: Ian Romanick
>
> Instead of lowering as (a + c(b - a)), lower as (a(1 - c) + bc). Since
> either a or b is 1.0, some of the multiplications drop out.
>
> I am CC'ing people who are responsible for drivers that set lower_flrp32
> as this patch will likely affect shader-db results for those drivers.
>
> No changes on any Gen6+ platform.
>
> Iron Lake
> total instructions in shared programs: 7745041 -> 7731595 (-0.17%)
> instructions in affected programs: 1647106 -> 1633660 (-0.82%)
> helped: 5522
> HURT: 281
> helped stats (abs) min: 1 max: 12 x̄: 2.53 x̃: 2
> helped stats (rel) min: 0.14% max: 12.00% x̄: 1.45% x̃: 0.99%
> HURT stats (abs) min: 1 max: 5 x̄: 1.94 x̃: 2
> HURT stats (rel) min: 0.13% max: 4.17% x̄: 0.74% x̃: 0.68%
> 95% mean confidence interval for instructions value: -2.35 -2.28
> 95% mean confidence interval for instructions %-change: -1.38% -1.31%
> Instructions are helped.
>
> total cycles in shared programs: 178004318 -> 177937186 (-0.04%)
> cycles in affected programs: 31813800 -> 31746668 (-0.21%)
> helped: 5420
> HURT: 631
> helped stats (abs) min: 2 max: 168 x̄: 13.15 x̃: 12
> helped stats (rel) min: 0.01% max: 6.37% x̄: 0.67% x̃: 0.30%
> HURT stats (abs) min: 2 max: 328 x̄: 6.57 x̃: 4
> HURT stats (rel) min: 0.01% max: 2.78% x̄: 0.16% x̃: 0.11%
> 95% mean confidence interval for cycles value: -11.35 -10.84
> 95% mean confidence interval for cycles %-change: -0.60% -0.56%
> Cycles are helped.
>
> GM45
> total instructions in shared programs: 4777279 -> 4770160 (-0.15%)
> instructions in affected programs: 928555 -> 921436 (-0.77%)
> helped: 2902
> HURT: 149
> helped stats (abs) min: 1 max: 12 x̄: 2.55 x̃: 2
> helped stats (rel) min: 0.14% max: 11.11% x̄: 1.38% x̃: 0.91%
> HURT stats (abs) min: 1 max: 5 x̄: 1.93 x̃: 2
> HURT stats (rel) min: 0.13% max: 4.00% x̄: 0.72% x̃: 0.68%
> 95% mean confidence interval for instructions value: -2.38 -2.28
> 95% mean confidence interval for instructions %-change: -1.33% -1.23%
> Instructions are helped.
>
> total cycles in shared programs: 122063992 -> 122021958 (-0.03%)
> cycles in affected programs: 20838672 -> 20796638 (-0.20%)
> helped: 2921
> HURT: 454
> helped stats (abs) min: 2 max: 168 x̄: 15.40 x̃: 14
> helped stats (rel) min: 0.01% max: 6.37% x̄: 0.67% x̃: 0.29%
> HURT stats (abs) min: 2 max: 328 x̄: 6.49 x̃: 4
> HURT stats (rel) min: 0.02% max: 2.78% x̄: 0.16% x̃: 0.11%
> 95% mean confidence interval for cycles value: -12.86 -12.04
> 95% mean confidence interval for cycles %-change: -0.59% -0.53%
> Cycles are helped.
>
> Signed-off-by: Ian Romanick
> Cc: Marek Olšák
> Cc: Rob Clark
> Cc: Eric Anholt
> ---
> src/compiler/nir/nir_opt_algebraic.py | 6 ++
> 1 file changed, 6 insertions(+)
>
> diff --git a/src/compiler/nir/nir_opt_algebraic.py
> b/src/compiler/nir/nir_opt_algebraic.py
> index e770a61d9ff..f11a987c462 100644
> --- a/src/compiler/nir/nir_opt_algebraic.py
> +++ b/src/compiler/nir/nir_opt_algebraic.py
> @@ -116,6 +116,10 @@ optimizations = [
> (('~flrp', 0.0, a, b), ('fmul', a, b)),
> (('~flrp', a, b, ('b2f', c)), ('bcsel', c, b, a),
> 'options->lower_flrp32'),
> (('~flrp', a, 0.0, c), ('fadd', ('fmul', ('fneg', a), c), a)),
> + (('flrp@32', 1.0, b, c), ('fadd', ('fsub', 1.0, c), ('fmul', b, c)),
> 'options->lower_flrp32'),
> + (('flrp@64', 1.0, b, c), ('fadd', ('fsub', 1.0, c), ('fmul', b, c)),
> 'options->lower_flrp64'),
> + (('flrp@32', a, 1.0, c), ('fadd', a, ('fmul', c, ('fsub', 1.0, a))),
> 'options->lower_flrp32'),
> + (('flrp@64', a, 1.0, c), ('fadd', a, ('fmul', c, ('fsub', 1.0, a))),
> 'options->lower_flrp64'),
> (('flrp@32', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a),
> 'options->lower_flrp32'),
> (('flrp@64', a, b, c), ('fadd', ('fmul', c, ('fsub', b, a)), a),
> 'options->lower_flrp64'),
> (('ffract', a), ('fsub', a, ('ffloor', a)), 'options->lower_ffract'),
> @@ -125,6 +129,8 @@ optimizations = [
> (('~fadd', a, ('fmul', ('b2f', c), ('fadd', b, ('fneg', a,
> ('bcsel', c, b, a), 'options->lower_flrp32'),
> (('~fadd@32', a, ('fmul', c , ('fadd', b, ('fneg', a,
> ('flrp', a, b, c), '!options->lower_flrp32'),
> (('~fadd@64', a, ('fmul', c , ('fadd', b, ('fneg', a,
> ('flrp', a, b, c), '!options->lower_flrp64'),
> + (('~fadd@32', 1.0, ('fmul', c , ('fadd', b, -1.0 ))),
> ('fadd', ('fsub', 1.0, c), ('fmul', b, c)), 'options->lower_flrp32'),
> + (('~fadd@64', 1.0, ('fmul', c , ('fadd', b, -1.0 ))),
> ('fadd', ('fsub', 1.0, c), ('fmul', b, c)), 'options->lower_flrp64'),
> (('ffma', a, b, c), ('fadd', ('fmul', a, b), c),
> 'options->lower_ffma'),
> (('~fadd', ('fmul', a, b), c), ('ffma', a, b, c),
> 'options->fuse_ffma'),
>
> --
> 2.14.4
>
>
[Mesa-dev] [PATCH 11/21] mesa: move legacy dri config option dither_mode
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 12
src/util/xmlpool/ca.po | 16
src/util/xmlpool/de.po | 16
src/util/xmlpool/es.po | 16
src/util/xmlpool/fr.po | 16
src/util/xmlpool/nl.po | 16
src/util/xmlpool/t_options.h| 12
7 files changed, 12 insertions(+), 92 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index e684025216f..77c3c57f85a 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -57,6 +57,18 @@ DRI_CONF_OPT_BEGIN_V(color_reduction,enum,def,"0:1") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_DITHER_XERRORDIFF 0
+#define DRI_CONF_DITHER_XERRORDIFFRESET 1
+#define DRI_CONF_DITHER_ORDERED 2
+#define DRI_CONF_DITHER_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(dither_mode,enum,def,"0:2") \
+ DRI_CONF_DESC_BEGIN(en,"Color dithering method") \
+DRI_CONF_ENUM(0,"Horizontal error diffusion") \
+DRI_CONF_ENUM(1,"Horizontal error diffusion, reset error at
line start") \
+DRI_CONF_ENUM(2,"Ordered 2D color dithering") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
typedef struct {
drm_handle_t handle;/* Handle to the DRM region */
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index d9e0853f1c1..6177e416b56 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -131,22 +131,6 @@ msgstr "Arrodoneix els components de color a baix"
msgid "Round to nearest color"
msgstr "Arrodoneix al color més proper"
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Mètode de tramat de color"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Difusió d'error horitzontal"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Difusió d'error horitzontal, reinicia l'error a l'inici de la línia"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Tramat de color 2D ordenat"
-
#: t_options.h:190
msgid "Floating point depth buffer"
msgstr "Buffer de profunditat de punt flotant"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 6d07365cdd0..aeead969c28 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -106,22 +106,6 @@ msgstr "Farbkomponenten abrunden"
msgid "Round to nearest color"
msgstr "Zur ähnlichsten Farbe runden"
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Farbrasterungsmethode"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Horizontale Fehlerstreuung"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Horizontale Fehlerstreuung, Fehler am Zeilenanfang zurücksetzen"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Geordnete 2D Farbrasterung"
-
#: t_options.h:190
msgid "Floating point depth buffer"
msgstr "Fließkomma z-Puffer"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index d843eea436e..eb52a60204e 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -113,22 +113,6 @@ msgstr "Redondear hacia abajo los componentes de color"
msgid "Round to nearest color"
msgstr "Redondear al color más cercano"
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Método de suavizado de color"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Difusión de error horizontal"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Difusión de error horizontal, reiniciar error al comienzo de línea"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Suavizado de color 2D ordenado"
-
#: t_options.h:190
msgid "Floating point depth buffer"
msgstr "Búfer de profundidad en coma flotante"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index efeebb45f13..611e9ed46fe 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -104,22 +104,6 @@ msgstr "Arrondi à l'inférieur"
msgid "Round to nearest color"
msgstr "Arrondi au plus proche"
-#: t_options.h:181
-msgid "Color dithering method"
-msgstr "Méthode de tramage"
-
-#: t_options.h:182
-msgid "Horizontal error diffusion"
-msgstr "Diffusion d'erreur horizontale"
-
-#: t_options.h:183
-msgid "Horizontal error diffusion, reset error at line start"
-msgstr "Diffusion d'erreur horizontale, réinitialisé pour chaque ligne"
-
-#: t_options.h:184
-msgid "Ordered 2D color dithering"
-msgstr "Tramage ordonné des couleurs"
-
#: t_options.h:190
msgid "Floating point depth buffer"
msgstr "Z-buffer en virgule flottante"
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index ddf3ea2cdac..51e7050b2eb 100644
--- a/src/util/xmlpool/nl.po
+++
[Mesa-dev] [PATCH 13/21] mesa: move legacy dri config option texture_blend_quality
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 6 ++
src/util/xmlpool/ca.po | 6 --
src/util/xmlpool/de.po | 6 --
src/util/xmlpool/es.po | 6 --
src/util/xmlpool/fr.po | 5 -
src/util/xmlpool/nl.po | 6 --
src/util/xmlpool/sv.po | 6 --
src/util/xmlpool/t_options.h| 5 -
8 files changed, 6 insertions(+), 40 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 0a6aa5109b4..2dd29aeab09 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -98,6 +98,12 @@ DRI_CONF_END
};
#elif defined(RADEON_R200)
+
+#define DRI_CONF_TEXTURE_BLEND_QUALITY(def,range) \
+DRI_CONF_OPT_BEGIN_V(texture_blend_quality,float,def,range) \
+ DRI_CONF_DESC(en,"Texture filtering quality vs. speed, AKA “brilinear”
texture filtering") \
+DRI_CONF_OPT_END
+
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
.xml =
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 0351ff16355..363464c927f 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -211,12 +211,6 @@ msgstr ""
msgid "Number of texture units used"
msgstr "Nombre d'unitats de textura utilitzades"
-#: t_options.h:286
-msgid "Texture filtering quality vs. speed, AKA “brilinear” texture filtering"
-msgstr ""
-"Qualitat vs. velocitat de filtració de textura, àlies filtració \"brilinear"
-"\" de textura"
-
#: t_options.h:294
msgid "Used types of texture memory"
msgstr "Tipus utilitzats de memòria de textura"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 5b30d890b40..3e1b70f8b37 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -186,12 +186,6 @@ msgstr ""
msgid "Number of texture units used"
msgstr "Anzahl der benutzten Textureinheiten"
-#: t_options.h:286
-msgid "Texture filtering quality vs. speed, AKA “brilinear” texture filtering"
-msgstr ""
-"Texturfilterqualität versus -geschwindigkeit, auch bekannt als „brilineare“ "
-"Texturfilterung"
-
#: t_options.h:294
msgid "Used types of texture memory"
msgstr "Benutzte Arten von Texturspeicher"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index a223da041eb..01d3ca3c178 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -195,12 +195,6 @@ msgstr ""
msgid "Number of texture units used"
msgstr "Número de unidades de textura usadas"
-#: t_options.h:286
-msgid "Texture filtering quality vs. speed, AKA “brilinear” texture filtering"
-msgstr ""
-"Calidad de filtrado de textura vs. velocidad, alias filtrado \"brilinear\" "
-"de textura"
-
#: t_options.h:294
msgid "Used types of texture memory"
msgstr "Tipos de memoria de textura usados"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index e4a963af62e..7c631fce9e6 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -184,11 +184,6 @@ msgstr ""
msgid "Number of texture units used"
msgstr "Nombre d'unités de texture"
-#: t_options.h:286
-msgid "Texture filtering quality vs. speed, AKA “brilinear” texture filtering"
-msgstr ""
-"Qualité/performance du filtrage trilinéaire de texture (filtrage brilinéaire)"
-
#: t_options.h:294
msgid "Used types of texture memory"
msgstr "Types de mémoire de texture"
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index a91ad89ac4a..ddd7a24a0e0 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -183,12 +183,6 @@ msgstr ""
msgid "Number of texture units used"
msgstr "Aantal textuureenheden in gebruik"
-#: t_options.h:286
-msgid "Texture filtering quality vs. speed, AKA “brilinear” texture filtering"
-msgstr ""
-"Textuurfilterkwaliteit versus -snelheid, ookwel bekend als “brilineaire” "
-"textuurfiltering"
-
#: t_options.h:294
msgid "Used types of texture memory"
msgstr "Gebruikte soorten textuurgeheugen"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index c2d640b2141..bc4f5326afa 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -194,12 +194,6 @@ msgstr ""
msgid "Number of texture units used"
msgstr "Antal använda texturenheter"
-#: t_options.h:286
-msgid "Texture filtering quality vs. speed, AKA “brilinear” texture filtering"
-msgstr ""
-"Texturfiltreringskvalitet mot hastighet, även kallad \"brilinear\"-"
-"texturfiltrering"
-
#: t_options.h:294
msgid "Used types of texture memory"
msgstr "Använda typer av texturminne"
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 8f96ae4373e..58fc3a9b0c6 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -256,11 +256,6 @@ DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" #
max ) \
DRI_CONF_DESC(en,gettext("Number of texture units used")) \
DRI_CONF_OPT_END
[Mesa-dev] [PATCH 12/21] util: remove unused S3TC translation for dri config
--- src/util/xmlpool/ca.po | 7 --- src/util/xmlpool/de.po | 7 --- src/util/xmlpool/es.po | 7 --- src/util/xmlpool/fr.po | 6 -- src/util/xmlpool/nl.po | 7 --- src/util/xmlpool/sv.po | 5 - 6 files changed, 39 deletions(-) diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po index 6177e416b56..0351ff16355 100644 --- a/src/util/xmlpool/ca.po +++ b/src/util/xmlpool/ca.po @@ -112,13 +112,6 @@ msgstr "" "Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les " "textures" -#: t_options.h:153 -msgid "" -"Enable S3TC texture compression even if software support is not available" -msgstr "" -"Habilita la compressió de textures S3TC encara que el suport de programari " -"no estigui disponible" - #: t_options.h:170 msgid "Color rounding method" msgstr "Mètode d'arrodoniment de color" diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po index aeead969c28..5b30d890b40 100644 --- a/src/util/xmlpool/de.po +++ b/src/util/xmlpool/de.po @@ -87,13 +87,6 @@ msgstr "Initialer Maximalwert für anisotropische Texturfilterung" msgid "Forbid negative texture LOD bias" msgstr "Verbiete negative Textur-Detailgradverschiebung" -#: t_options.h:153 -msgid "" -"Enable S3TC texture compression even if software support is not available" -msgstr "" -"Aktiviere S3TC Texturkomprimierung auch wenn die nötige " -"Softwareunterstützung fehlt" - #: t_options.h:170 msgid "Color rounding method" msgstr "Farbrundungsmethode" diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po index eb52a60204e..a223da041eb 100644 --- a/src/util/xmlpool/es.po +++ b/src/util/xmlpool/es.po @@ -94,13 +94,6 @@ msgstr "Valor máximo inicial para filtrado anisotrópico de textura" msgid "Forbid negative texture LOD bias" msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas" -#: t_options.h:153 -msgid "" -"Enable S3TC texture compression even if software support is not available" -msgstr "" -"Habilitar la compresión de texturas S3TC incluso si el soporte por software " -"no está disponible" - #: t_options.h:170 msgid "Color rounding method" msgstr "Método de redondeo de colores" diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po index 611e9ed46fe..e4a963af62e 100644 --- a/src/util/xmlpool/fr.po +++ b/src/util/xmlpool/fr.po @@ -86,12 +86,6 @@ msgstr "Valeur maximale initiale pour le filtrage anisotropique de texture" msgid "Forbid negative texture LOD bias" msgstr "Interdire le LOD bias negatif" -#: t_options.h:153 -msgid "" -"Enable S3TC texture compression even if software support is not available" -msgstr "" -"Activer la compression de texture S3TC même si le support logiciel est absent" - #: t_options.h:170 msgid "Color rounding method" msgstr "Méthode d'arrondi des couleurs" diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po index 51e7050b2eb..a91ad89ac4a 100644 --- a/src/util/xmlpool/nl.po +++ b/src/util/xmlpool/nl.po @@ -86,13 +86,6 @@ msgstr "Initïele maximum waarde voor anisotrophische textuur filtering" msgid "Forbid negative texture LOD bias" msgstr "Verbied negatief niveau detailonderscheid (LOD) van texturen" -#: t_options.h:153 -msgid "" -"Enable S3TC texture compression even if software support is not available" -msgstr "" -"Schakel S3TC textuurcompressie in, zelfs als softwareondersteuning niet " -"aanwezig is" - #: t_options.h:182 msgid "Horizontal error diffusion" msgstr "Horizontale foutdiffusie" diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po index f7430625a24..c2d640b2141 100644 --- a/src/util/xmlpool/sv.po +++ b/src/util/xmlpool/sv.po @@ -86,11 +86,6 @@ msgstr "Initialt maximalt värde för anisotropisk texturfiltrering" msgid "Forbid negative texture LOD bias" msgstr "Förbjud negativ LOD-kompensation för texturer" -#: t_options.h:153 -msgid "" -"Enable S3TC texture compression even if software support is not available" -msgstr "Aktivera S3TC-texturkomprimering även om programvarustöd saknas" - #: t_options.h:170 msgid "Color rounding method" msgstr "Färgavrundningsmetod" -- 2.17.1 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 09/21] mesa: remove legacy TCL dri config options
Use enviroment var overrides in legacy drivers instead.
---
src/mesa/drivers/dri/r200/r200_context.c | 4 +---
src/mesa/drivers/dri/radeon/radeon_context.c | 5 ++---
src/mesa/drivers/dri/radeon/radeon_screen.c | 2 --
src/util/xmlpool/ca.po | 23
src/util/xmlpool/de.po | 23
src/util/xmlpool/es.po | 23
src/util/xmlpool/fr.po | 23
src/util/xmlpool/nl.po | 23
src/util/xmlpool/sv.po | 22 ---
src/util/xmlpool/t_options.h | 14
10 files changed, 3 insertions(+), 159 deletions(-)
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 1ab7da8ef50..b80b92410c7 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -184,7 +184,6 @@ GLboolean r200CreateContext( gl_api api,
r200ContextPtr rmesa;
struct gl_context *ctx;
int i;
- int tcl_mode;
if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
@@ -382,12 +381,11 @@ GLboolean r200CreateContext( gl_api api,
rmesa->prefer_gart_client_texturing =
(getenv("R200_GART_CLIENT_TEXTURES") != 0);
- tcl_mode = driQueryOptioni(>radeon.optionCache, "tcl_mode");
if (getenv("R200_NO_RAST")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, R200_FALLBACK_DISABLE, 1);
}
- else if (tcl_mode == DRI_CONF_TCL_SW || getenv("R200_NO_TCL") ||
+ else if (getenv("R200_NO_TCL") ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
diff --git a/src/mesa/drivers/dri/radeon/radeon_context.c
b/src/mesa/drivers/dri/radeon/radeon_context.c
index 6d29182ee9e..370c33dd226 100644
--- a/src/mesa/drivers/dri/radeon/radeon_context.c
+++ b/src/mesa/drivers/dri/radeon/radeon_context.c
@@ -150,7 +150,7 @@ r100CreateContext( gl_api api,
r100ContextPtr rmesa;
struct gl_context *ctx;
int i;
- int tcl_mode, fthrottle_mode;
+ int fthrottle_mode;
if (ctx_config->flags & ~(__DRI_CTX_FLAG_DEBUG | __DRI_CTX_FLAG_NO_ERROR)) {
*error = __DRI_CTX_ERROR_UNKNOWN_FLAG;
@@ -331,11 +331,10 @@ r100CreateContext( gl_api api,
rmesa->radeon.do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
- tcl_mode = driQueryOptioni(>radeon.optionCache, "tcl_mode");
if (getenv("RADEON_NO_RAST")) {
fprintf(stderr, "disabling 3D acceleration\n");
FALLBACK(rmesa, RADEON_FALLBACK_DISABLE, 1);
- } else if (tcl_mode == DRI_CONF_TCL_SW ||
+ } else if (getenv("RADEON_NO_TCL") ||
!(rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL)) {
if (rmesa->radeon.radeonScreen->chip_flags & RADEON_CHIPSET_TCL) {
rmesa->radeon.radeonScreen->chip_flags &= ~RADEON_CHIPSET_TCL;
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index f920da1f465..0a6aa5109b4 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -81,7 +81,6 @@ static const __DRIconfigOptionsExtension
radeon_config_options = {
.xml =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
-DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_MAX_TEXTURE_UNITS(3,2,3)
DRI_CONF_HYPERZ("false")
@@ -104,7 +103,6 @@ static const __DRIconfigOptionsExtension
radeon_config_options = {
.xml =
DRI_CONF_BEGIN
DRI_CONF_SECTION_PERFORMANCE
-DRI_CONF_TCL_MODE(DRI_CONF_TCL_CODEGEN)
DRI_CONF_FTHROTTLE_MODE(DRI_CONF_FTHROTTLE_IRQS)
DRI_CONF_MAX_TEXTURE_UNITS(6,2,6)
DRI_CONF_HYPERZ("false")
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 50fef0fd757..f8f564c17fd 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -200,29 +200,6 @@ msgstr ""
msgid "Performance"
msgstr "Rendiment"
-#: t_options.h:238
-msgid "TCL mode (Transformation, Clipping, Lighting)"
-msgstr "Mode TCL (Transformació, Retall, Il·luminació)"
-
-#: t_options.h:239
-msgid "Use software TCL pipeline"
-msgstr "Utilitza la canonada TCL de programari"
-
-#: t_options.h:240
-msgid "Use hardware TCL as first TCL pipeline stage"
-msgstr "Utilitza el TCL de maquinari com a la primera fase de la canonada TCL"
-
-#: t_options.h:241
-msgid "Bypass the TCL pipeline"
-msgstr "Passa per alt la canonada TCL"
-
-#: t_options.h:242
-msgid ""
-"Bypass the TCL pipeline with state-based machine code generated on-the-fly"
-msgstr ""
-"Passa per alt la canonada TCL amb codi de màquina basat en
[Mesa-dev] [PATCH 14/21] mesa: remove unused dri config option texture_heaps
This seems to have only been used by DRI1 drivers which were removed with e4344161bde2. --- src/util/xmlpool/ca.po | 16 src/util/xmlpool/de.po | 16 src/util/xmlpool/es.po | 16 src/util/xmlpool/fr.po | 16 src/util/xmlpool/nl.po | 16 src/util/xmlpool/sv.po | 16 src/util/xmlpool/t_options.h | 12 7 files changed, 108 deletions(-) diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po index 363464c927f..36e44a21553 100644 --- a/src/util/xmlpool/ca.po +++ b/src/util/xmlpool/ca.po @@ -211,22 +211,6 @@ msgstr "" msgid "Number of texture units used" msgstr "Nombre d'unitats de textura utilitzades" -#: t_options.h:294 -msgid "Used types of texture memory" -msgstr "Tipus utilitzats de memòria de textura" - -#: t_options.h:295 -msgid "All available memory" -msgstr "Tota la memòria disponible" - -#: t_options.h:296 -msgid "Only card memory (if available)" -msgstr "Només memòria de targeta (si està disponible)" - -#: t_options.h:297 -msgid "Only GART (AGP/PCIE) memory (if available)" -msgstr "Només memòria GART (AGP/PCIE) (si està disponible)" - #: t_options.h:323 msgid "Miscellaneous" msgstr "Miscel·lània" diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po index 3e1b70f8b37..0b7a29980a6 100644 --- a/src/util/xmlpool/de.po +++ b/src/util/xmlpool/de.po @@ -186,22 +186,6 @@ msgstr "" msgid "Number of texture units used" msgstr "Anzahl der benutzten Textureinheiten" -#: t_options.h:294 -msgid "Used types of texture memory" -msgstr "Benutzte Arten von Texturspeicher" - -#: t_options.h:295 -msgid "All available memory" -msgstr "Aller verfügbarer Speicher" - -#: t_options.h:296 -msgid "Only card memory (if available)" -msgstr "Nur Grafikspeicher (falls verfügbar)" - -#: t_options.h:297 -msgid "Only GART (AGP/PCIE) memory (if available)" -msgstr "Nur GART-Speicher (AGP/PCIE) (falls verfügbar)" - #: t_options.h:323 msgid "Miscellaneous" msgstr "" diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po index 01d3ca3c178..1230194c14c 100644 --- a/src/util/xmlpool/es.po +++ b/src/util/xmlpool/es.po @@ -195,22 +195,6 @@ msgstr "" msgid "Number of texture units used" msgstr "Número de unidades de textura usadas" -#: t_options.h:294 -msgid "Used types of texture memory" -msgstr "Tipos de memoria de textura usados" - -#: t_options.h:295 -msgid "All available memory" -msgstr "Toda la memoria disponible" - -#: t_options.h:296 -msgid "Only card memory (if available)" -msgstr "Solo memoria de tarjeta (si está disponible)" - -#: t_options.h:297 -msgid "Only GART (AGP/PCIE) memory (if available)" -msgstr "Solo memoria GART (AGP/PCIE) (si está disponible)" - #: t_options.h:323 msgid "Miscellaneous" msgstr "Misceláneos" diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po index 7c631fce9e6..92d31e54488 100644 --- a/src/util/xmlpool/fr.po +++ b/src/util/xmlpool/fr.po @@ -184,22 +184,6 @@ msgstr "" msgid "Number of texture units used" msgstr "Nombre d'unités de texture" -#: t_options.h:294 -msgid "Used types of texture memory" -msgstr "Types de mémoire de texture" - -#: t_options.h:295 -msgid "All available memory" -msgstr "Utiliser toute la mémoire disponible" - -#: t_options.h:296 -msgid "Only card memory (if available)" -msgstr "Utiliser uniquement la mémoire graphique (si disponible)" - -#: t_options.h:297 -msgid "Only GART (AGP/PCIE) memory (if available)" -msgstr "Utiliser uniquement la mémoire GART (AGP/PCIE) (si disponible)" - #: t_options.h:323 msgid "Miscellaneous" msgstr "" diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po index ddd7a24a0e0..80f162c5e58 100644 --- a/src/util/xmlpool/nl.po +++ b/src/util/xmlpool/nl.po @@ -183,22 +183,6 @@ msgstr "" msgid "Number of texture units used" msgstr "Aantal textuureenheden in gebruik" -#: t_options.h:294 -msgid "Used types of texture memory" -msgstr "Gebruikte soorten textuurgeheugen" - -#: t_options.h:295 -msgid "All available memory" -msgstr "Al het beschikbaar geheugen" - -#: t_options.h:296 -msgid "Only card memory (if available)" -msgstr "Alleen geheugen op de kaart (als het aanwezig is)" - -#: t_options.h:297 -msgid "Only GART (AGP/PCIE) memory (if available)" -msgstr "Alleen GART (AGP/PCIE) geheugen (als het aanwezig is)" - #: t_options.h:323 msgid "Miscellaneous" msgstr "" diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po index bc4f5326afa..f26332777bc 100644 --- a/src/util/xmlpool/sv.po +++ b/src/util/xmlpool/sv.po @@ -194,22 +194,6 @@ msgstr "" msgid "Number of texture units used" msgstr "Antal använda texturenheter" -#: t_options.h:294 -msgid "Used types of texture memory" -msgstr "Använda typer av texturminne" - -#: t_options.h:295 -msgid "All available memory" -msgstr "Allt tillgängligt minne" - -#: t_options.h:296 -msgid "Only card memory (if available)" -msgstr "Endast kortminne (om tillgängligt)" - -#: t_options.h:297 -msgid "Only
[Mesa-dev] [PATCH 19/21] mesa: move legacy dri config option def_max_anisotropy
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po | 4
src/util/xmlpool/sv.po | 4
src/util/xmlpool/t_options.h| 5 -
8 files changed, 5 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index d830e410685..c1af595f927 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -85,6 +85,11 @@ DRI_CONF_OPT_BEGIN_B(no_neg_lod_bias, def) \
DRI_CONF_DESC(en,"Forbid negative texture LOD bias") \
DRI_CONF_OPT_END
+#define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \
+DRI_CONF_OPT_BEGIN_V(def_max_anisotropy,float,def,range) \
+DRI_CONF_DESC(en,"Initial maximum value for anisotropic texture
filtering") \
+DRI_CONF_OPT_END
+
#if defined(RADEON_R100) /* R100 */
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 7760da13ac2..e8ff8af1bb4 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -102,10 +102,6 @@ msgstr "Prefereix 16 bits per texel"
msgid "Force 16 bits per texel"
msgstr "Força 16 bits per texel"
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Valor màxim inicial per a la filtració de textura anisòtropa"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 9e466f7620a..8d5804f4433 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -79,10 +79,6 @@ msgstr "Bevorzuge 16 bits pro Texel"
msgid "Force 16 bits per texel"
msgstr "Erzwinge 16 bits pro Texel"
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Initialer Maximalwert für anisotropische Texturfilterung"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index cd76fa39b4a..c79191f6c8b 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -86,10 +86,6 @@ msgstr "Preferir 16 bits por texel"
msgid "Force 16 bits per texel"
msgstr "Forzar a 16 bits por texel"
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Valor máximo inicial para filtrado anisotrópico de textura"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index d086b44a4b0..c1856aa0fd3 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -78,10 +78,6 @@ msgstr "Prérérer 16 bits par texel"
msgid "Force 16 bits per texel"
msgstr "Forcer 16 bits par texel"
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Valeur maximale initiale pour le filtrage anisotropique de texture"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 38473fdc2de..50fb346 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -78,10 +78,6 @@ msgstr "Prefereer 16 bits per texel"
msgid "Force 16 bits per texel"
msgstr "Dwing 16 bits per texel af"
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Initïele maximum waarde voor anisotrophische textuur filtering"
-
#: t_options.h:182
msgid "Horizontal error diffusion"
msgstr "Horizontale foutdiffusie"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index 8c3bca72e68..3e11072ea89 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -78,10 +78,6 @@ msgstr "Föredra 16 bitar per texel"
msgid "Force 16 bits per texel"
msgstr "Tvinga 16 bitar per texel"
-#: t_options.h:143
-msgid "Initial maximum value for anisotropic texture filtering"
-msgstr "Initialt maximalt värde för anisotropisk texturfiltrering"
-
#: t_options.h:181
msgid "Color dithering method"
msgstr "Färgutjämningsmetod"
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 68ba7413129..d17bcd1971c 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -156,11 +156,6 @@ DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
-#define DRI_CONF_DEF_MAX_ANISOTROPY(def,range) \
[Mesa-dev] [PATCH 17/21] mesa: move legacy dri config option round_mode
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++
src/util/xmlpool/ca.po | 12
src/util/xmlpool/de.po | 12
src/util/xmlpool/es.po | 12
src/util/xmlpool/fr.po | 12
src/util/xmlpool/sv.po | 12
src/util/xmlpool/t_options.h| 10 --
7 files changed, 10 insertions(+), 70 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 77c3c57f85a..878f6793926 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -69,6 +69,16 @@ DRI_CONF_OPT_BEGIN_V(dither_mode,enum,def,"0:2") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_ROUND_TRUNC 0
+#define DRI_CONF_ROUND_ROUND 1
+#define DRI_CONF_ROUND_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
+ DRI_CONF_DESC_BEGIN(en,"Color rounding method") \
+DRI_CONF_ENUM(0,"Round color components downward") \
+DRI_CONF_ENUM(1,"Round to nearest color") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
typedef struct {
drm_handle_t handle;/* Handle to the DRM region */
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index c588832b5d9..1710a2ce199 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -112,18 +112,6 @@ msgstr ""
"Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les "
"textures"
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Mètode d'arrodoniment de color"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Arrodoneix els components de color a baix"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Arrodoneix al color més proper"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index f40a39fff59..5581725a251 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -87,18 +87,6 @@ msgstr "Initialer Maximalwert für anisotropische
Texturfilterung"
msgid "Forbid negative texture LOD bias"
msgstr "Verbiete negative Textur-Detailgradverschiebung"
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Farbrundungsmethode"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Farbkomponenten abrunden"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Zur ähnlichsten Farbe runden"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index e371834070b..85288bfbe8a 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -94,18 +94,6 @@ msgstr "Valor máximo inicial para filtrado anisotrópico de
textura"
msgid "Forbid negative texture LOD bias"
msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas"
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Método de redondeo de colores"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Redondear hacia abajo los componentes de color"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Redondear al color más cercano"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index b898e3423dd..1f2d04cd396 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -86,18 +86,6 @@ msgstr "Valeur maximale initiale pour le filtrage
anisotropique de texture"
msgid "Forbid negative texture LOD bias"
msgstr "Interdire le LOD bias negatif"
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Méthode d'arrondi des couleurs"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Arrondi à l'inférieur"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Arrondi au plus proche"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index e340ed5df60..61d735b86c1 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -86,18 +86,6 @@ msgstr "Initialt maximalt värde för anisotropisk
texturfiltrering"
msgid "Forbid negative texture LOD bias"
msgstr "Förbjud negativ LOD-kompensation för texturer"
-#: t_options.h:170
-msgid "Color rounding method"
-msgstr "Färgavrundningsmetod"
-
-#: t_options.h:171
-msgid "Round color components downward"
-msgstr "Avrunda färdkomponenter nedåt"
-
-#: t_options.h:172
-msgid "Round to nearest color"
-msgstr "Avrunda till närmsta färg"
-
#: t_options.h:181
[Mesa-dev] [PATCH 16/21] mesa: remove unused dri option float_depth
This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po | 4
src/util/xmlpool/sv.po | 4
src/util/xmlpool/t_options.h | 5 -
7 files changed, 29 deletions(-)
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 5f78915b544..c588832b5d9 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -124,10 +124,6 @@ msgstr "Arrodoneix els components de color a baix"
msgid "Round to nearest color"
msgstr "Arrodoneix al color més proper"
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Buffer de profunditat de punt flotant"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 2ef0607cbb2..f40a39fff59 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -99,10 +99,6 @@ msgstr "Farbkomponenten abrunden"
msgid "Round to nearest color"
msgstr "Zur ähnlichsten Farbe runden"
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Fließkomma z-Puffer"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index cfb6c0eb18d..e371834070b 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -106,10 +106,6 @@ msgstr "Redondear hacia abajo los componentes de color"
msgid "Round to nearest color"
msgstr "Redondear al color más cercano"
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Búfer de profundidad en coma flotante"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 94a248069a0..b898e3423dd 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -98,10 +98,6 @@ msgstr "Arrondi à l'inférieur"
msgid "Round to nearest color"
msgstr "Arrondi au plus proche"
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Z-buffer en virgule flottante"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 9beafb42224..21845ce879c 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -98,10 +98,6 @@ msgstr "Horizontale foutdiffusie, zet fout bij lijnbegin
terug"
msgid "Ordered 2D color dithering"
msgstr "Geordende 2D kleurrasterisering"
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Dieptebuffer als commagetal"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index d952d5d8388..e340ed5df60 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -114,10 +114,6 @@ msgstr "Horisontell felspridning, återställ fel vid
radbörjan"
msgid "Ordered 2D color dithering"
msgstr "Ordnad 2D-färgutjämning"
-#: t_options.h:190
-msgid "Floating point depth buffer"
-msgstr "Buffert för flytande punktdjup"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr ""
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index eed7dc4f315..2f08921cd5f 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -181,11 +181,6 @@ DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
-#define DRI_CONF_FLOAT_DEPTH(def) \
-DRI_CONF_OPT_BEGIN_B(float_depth, def) \
-DRI_CONF_DESC(en,gettext("Floating point depth buffer")) \
-DRI_CONF_OPT_END
-
#define DRI_CONF_PP_CELSHADE(def) \
DRI_CONF_OPT_BEGIN_V(pp_celshade,enum,def,"0:1") \
DRI_CONF_DESC(en,gettext("A post-processing filter to cel-shade the
output")) \
--
2.17.1
___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/21] mesa: remove unused dri config option excess_mipmap
This seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/t_options.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 3e5993caf78..f0dc78dd595 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -142,11 +142,6 @@ DRI_CONF_OPT_END
DRI_CONF_SECTION_BEGIN \
DRI_CONF_DESC(en,gettext("Image Quality"))
-#define DRI_CONF_EXCESS_MIPMAP(def) \
-DRI_CONF_OPT_BEGIN_B(excess_mipmap, def) \
- DRI_CONF_DESC(en,"Enable extra mipmap level") \
-DRI_CONF_OPT_END
-
#define DRI_CONF_TEXTURE_DEPTH_FB 0
#define DRI_CONF_TEXTURE_DEPTH_32 1
#define DRI_CONF_TEXTURE_DEPTH_16 2
--
2.17.1
___
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mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 10/21] mesa: move legacy dri config option color_reduction
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 10 ++
src/util/xmlpool/ca.po | 12
src/util/xmlpool/de.po | 12
src/util/xmlpool/es.po | 12
src/util/xmlpool/fr.po | 12
src/util/xmlpool/nl.po | 12
src/util/xmlpool/sv.po | 12
src/util/xmlpool/t_options.h| 10 --
8 files changed, 10 insertions(+), 82 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index efb2e6016b7..e684025216f 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -47,6 +47,16 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#include "radeon_reg.h"
#include "util/xmlconfig.h"
+#define DRI_CONF_COLOR_REDUCTION_ROUND 0
+#define DRI_CONF_COLOR_REDUCTION_DITHER 1
+#define DRI_CONF_COLOR_REDUCTION(def) \
+DRI_CONF_OPT_BEGIN_V(color_reduction,enum,def,"0:1") \
+DRI_CONF_DESC_BEGIN(en,"Initial color reduction method") \
+DRI_CONF_ENUM(0,"Round colors") \
+DRI_CONF_ENUM(1,"Dither colors") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
typedef struct {
drm_handle_t handle;/* Handle to the DRM region */
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index f8f564c17fd..d9e0853f1c1 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -119,18 +119,6 @@ msgstr ""
"Habilita la compressió de textures S3TC encara que el suport de programari "
"no estigui disponible"
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Mètode inicial de reducció de color"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Colors arrodonits"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Colors tramats"
-
#: t_options.h:170
msgid "Color rounding method"
msgstr "Mètode d'arrodoniment de color"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 08147351ee0..6d07365cdd0 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -94,18 +94,6 @@ msgstr ""
"Aktiviere S3TC Texturkomprimierung auch wenn die nötige "
"Softwareunterstützung fehlt"
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Initiale Farbreduktionsmethode"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Farben runden"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Farben rastern"
-
#: t_options.h:170
msgid "Color rounding method"
msgstr "Farbrundungsmethode"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 317e848169a..d843eea436e 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -101,18 +101,6 @@ msgstr ""
"Habilitar la compresión de texturas S3TC incluso si el soporte por software "
"no está disponible"
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Método inicial de reducción de color"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Colores redondeados"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Colores suavizados"
-
#: t_options.h:170
msgid "Color rounding method"
msgstr "Método de redondeo de colores"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 86f5927293b..efeebb45f13 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -92,18 +92,6 @@ msgid ""
msgstr ""
"Activer la compression de texture S3TC même si le support logiciel est absent"
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Technique de réduction de couleurs"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Arrondir les valeurs de couleur"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Tramer les couleurs"
-
#: t_options.h:170
msgid "Color rounding method"
msgstr "Méthode d'arrondi des couleurs"
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 4c202d65a8c..ddf3ea2cdac 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -93,18 +93,6 @@ msgstr ""
"Schakel S3TC textuurcompressie in, zelfs als softwareondersteuning niet "
"aanwezig is"
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Initïele kleurreductie methode"
-
-#: t_options.h:161
-msgid "Round colors"
-msgstr "Rond kleuren af"
-
-#: t_options.h:162
-msgid "Dither colors"
-msgstr "Rasteriseer kleuren"
-
#: t_options.h:170
msgid "Color rounding method"
msgstr "Kleurafrondingmethode"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index d71953cd149..f7430625a24 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -91,18 +91,6 @@ msgid ""
"Enable S3TC texture compression even if software support is not available"
msgstr "Aktivera S3TC-texturkomprimering även om programvarustöd saknas"
-#: t_options.h:160
-msgid "Initial color reduction method"
-msgstr "Initial
[Mesa-dev] [PATCH 08/21] mesa: move legacy hyperz option from dri config
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po | 4
src/util/xmlpool/sv.po | 4
src/util/xmlpool/t_options.h| 7 ---
8 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index bca6a45e368..f920da1f465 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -70,6 +70,11 @@ DRI_CONF_OPT_BEGIN_V(command_buffer_size,int,def, # min ":"
# max ) \
DRI_CONF_DESC(de,"Grösse des Befehlspuffers (in KB)") \
DRI_CONF_OPT_END
+#define DRI_CONF_HYPERZ(def) \
+DRI_CONF_OPT_BEGIN_B(hyperz, def) \
+DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
+DRI_CONF_OPT_END
+
#if defined(RADEON_R100) /* R100 */
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 36872e2f2ba..50fef0fd757 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -265,10 +265,6 @@ msgstr ""
"Sempre sincronitza amb el refresc vertical, l'aplicació tria l'interval "
"mínim d'intercanvi"
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Utilitza el HyperZ per a augmentar el rendiment"
-
#: t_options.h:281
msgid "Number of texture units used"
msgstr "Nombre d'unitats de textura utilitzades"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 57fa6fb4619..156e6243eb4 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -240,10 +240,6 @@ msgstr ""
"Immer mit der Bildwiederholung synchronisieren, Anwendung wählt das minimale "
"Bildintervall"
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "HyperZ zur Leistungssteigerung verwenden"
-
#: t_options.h:281
msgid "Number of texture units used"
msgstr "Anzahl der benutzten Textureinheiten"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 68824b61af2..b2837944b46 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -249,10 +249,6 @@ msgstr ""
"Sincronizar siempre con el refresco vertical, la aplicación elige el "
"intervalo de intercambio mínimo"
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Usar HyperZ para potenciar rendimiento"
-
#: t_options.h:281
msgid "Number of texture units used"
msgstr "Número de unidades de textura usadas"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index ea5f6812aeb..383e9d4b06d 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -237,10 +237,6 @@ msgstr ""
"Toujours synchroniser avec le balayage vertical, l'application choisit "
"l'intervalle minimal"
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Utiliser le HyperZ pour améliorer les performances"
-
#: t_options.h:281
msgid "Number of texture units used"
msgstr "Nombre d'unités de texture"
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 9dc0428ea63..a4c1e8a6dc1 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -237,10 +237,6 @@ msgstr ""
"Synchroniseer altijd met verticale verversing, de applicatie kiest het "
"minimum omwisselingsinterval"
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Gebruik HyperZ om de prestaties te verbeteren"
-
#: t_options.h:281
msgid "Number of texture units used"
msgstr "Aantal textuureenheden in gebruik"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index d156eba7214..ed671d4456a 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -229,10 +229,6 @@ msgstr ""
"Synkronisera alltid med vertikal uppdatering, programmet väljer den minsta "
"växlingsintervallen"
-#: t_options.h:276
-msgid "Use HyperZ to boost performance"
-msgstr "Använd HyperZ för att maximera prestandan"
-
#: t_options.h:281
msgid "Number of texture units used"
msgstr "Antal använda texturenheter"
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index ee12f104d76..b1bddfb03e8 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -287,13 +287,6 @@ DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
-#define DRI_CONF_HYPERZ_DISABLED 0
-#define DRI_CONF_HYPERZ_ENABLED 1
-#define DRI_CONF_HYPERZ(def) \
-DRI_CONF_OPT_BEGIN_B(hyperz, def) \
-DRI_CONF_DESC(en,gettext("Use HyperZ to boost performance")) \
-DRI_CONF_OPT_END
-
#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
DRI_CONF_DESC(en,gettext("Number of texture units used"))
[Mesa-dev] [PATCH 15/21] mesa: move legacy dri config option texture_units
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 4
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po | 4
src/util/xmlpool/sv.po | 4
src/util/xmlpool/t_options.h| 5 -
8 files changed, 5 insertions(+), 29 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 2dd29aeab09..e19945318b7 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -75,6 +75,11 @@ DRI_CONF_OPT_BEGIN_B(hyperz, def) \
DRI_CONF_DESC(en,"Use HyperZ to boost performance") \
DRI_CONF_OPT_END
+#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
+DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
+DRI_CONF_DESC(en,"Number of texture units used") \
+DRI_CONF_OPT_END
+
#if defined(RADEON_R100) /* R100 */
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 36e44a21553..5f78915b544 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -207,10 +207,6 @@ msgstr ""
"Sempre sincronitza amb el refresc vertical, l'aplicació tria l'interval "
"mínim d'intercanvi"
-#: t_options.h:281
-msgid "Number of texture units used"
-msgstr "Nombre d'unitats de textura utilitzades"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr "Miscel·lània"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 0b7a29980a6..2ef0607cbb2 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -182,10 +182,6 @@ msgstr ""
"Immer mit der Bildwiederholung synchronisieren, Anwendung wählt das minimale "
"Bildintervall"
-#: t_options.h:281
-msgid "Number of texture units used"
-msgstr "Anzahl der benutzten Textureinheiten"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 1230194c14c..cfb6c0eb18d 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -191,10 +191,6 @@ msgstr ""
"Sincronizar siempre con el refresco vertical, la aplicación elige el "
"intervalo de intercambio mínimo"
-#: t_options.h:281
-msgid "Number of texture units used"
-msgstr "Número de unidades de textura usadas"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr "Misceláneos"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 92d31e54488..94a248069a0 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -180,10 +180,6 @@ msgstr ""
"Toujours synchroniser avec le balayage vertical, l'application choisit "
"l'intervalle minimal"
-#: t_options.h:281
-msgid "Number of texture units used"
-msgstr "Nombre d'unités de texture"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 80f162c5e58..9beafb42224 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -179,10 +179,6 @@ msgstr ""
"Synchroniseer altijd met verticale verversing, de applicatie kiest het "
"minimum omwisselingsinterval"
-#: t_options.h:281
-msgid "Number of texture units used"
-msgstr "Aantal textuureenheden in gebruik"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index f26332777bc..d952d5d8388 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -190,10 +190,6 @@ msgstr ""
"Synkronisera alltid med vertikal uppdatering, programmet väljer den minsta "
"växlingsintervallen"
-#: t_options.h:281
-msgid "Number of texture units used"
-msgstr "Antal använda texturenheter"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 4beb03824af..eed7dc4f315 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -251,11 +251,6 @@ DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
-#define DRI_CONF_MAX_TEXTURE_UNITS(def,min,max) \
-DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max ) \
-DRI_CONF_DESC(en,gettext("Number of texture units used")) \
-DRI_CONF_OPT_END
-
#define DRI_CONF_MESA_GLTHREAD(def) \
DRI_CONF_OPT_BEGIN_B(mesa_glthread, def) \
DRI_CONF_DESC(en,gettext("Enable offloading GL driver work to a
separate thread")) \
--
2.17.1
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[Mesa-dev] [PATCH 2/2] glsl: Add an assert when cloning ir_dereference_record with invalid field
Signed-off-by: Danylo Piliaiev
---
src/compiler/glsl/ir_clone.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/compiler/glsl/ir_clone.cpp b/src/compiler/glsl/ir_clone.cpp
index 69441fae7d..e1f4f3b290 100644
--- a/src/compiler/glsl/ir_clone.cpp
+++ b/src/compiler/glsl/ir_clone.cpp
@@ -194,6 +194,7 @@ ir_dereference_array::clone(void *mem_ctx, struct
hash_table *ht) const
ir_dereference_record *
ir_dereference_record::clone(void *mem_ctx, struct hash_table *ht) const
{
+ assert(this->field_idx >= 0);
const char *field_name =
this->record->type->fields.structure[this->field_idx].name;
return new(mem_ctx) ir_dereference_record(this->record->clone(mem_ctx, ht),
--
2.18.0
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[Mesa-dev] [PATCH 1/2] glsl: Avoid propagating incompatible type of initializer
do_assignment validated assigment but when rhs type was not compatible
it proceeded without issues and returned error_emitted = false.
On the other hand process_initializer expected do_assignment to always
return compatible type and never fail.
As a result when variable was initialized with incompatible type
the type of variable changed to the incompatible one.
This manifested in unnecessary error messages and in one case in crash.
Example GLSL:
vec4 tmp = vec2(0.0);
tmp.z -= 1.0;
Past error messages:
initializer of type vec2 cannot be assigned to variable of type vec4
invalid swizzle / mask `z'
type mismatch
operands to arithmetic operators must be numeric
After this patch:
initializer of type vec2 cannot be assigned to variable of type vec4
In the other case when we initialize variable with incompatible struct,
accessing variable's field leaded to a crash. Example:
uniform struct {float field;} data;
...
vec4 tmp = data;
tmp.x -= 1.0;
After the patch there is only error line without a crash:
initializer of type #anon_struct cannot be assigned to variable of
type vec4
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107547
Signed-off-by: Danylo Piliaiev
---
src/compiler/glsl/ast_to_hir.cpp | 62 +---
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 5d3f10b682..93e7c8ec33 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -1012,6 +1012,8 @@ do_assignment(exec_list *instructions, struct
_mesa_glsl_parse_state *state,
mark_whole_array_access(rhs);
mark_whole_array_access(lhs);
}
+ } else {
+ error_emitted = true;
}
/* Most callers of do_assignment (assign, add_assign, pre_inc/dec,
@@ -4562,41 +4564,43 @@ process_initializer(ir_variable *var, ast_declaration
*decl,
/* Never emit code to initialize a uniform.
*/
const glsl_type *initializer_type;
+ bool error_emitted = false;
if (!type->qualifier.flags.q.uniform) {
- do_assignment(initializer_instructions, state,
- NULL,
- lhs, rhs,
- , true,
- true,
- type->get_location());
+ error_emitted =
+do_assignment(initializer_instructions, state,
+ NULL, lhs, rhs,
+ , true, true,
+ type->get_location());
initializer_type = result->type;
} else
initializer_type = rhs->type;
- var->constant_initializer = rhs->constant_expression_value(mem_ctx);
- var->data.has_initializer = true;
+ if (!error_emitted) {
+ var->constant_initializer = rhs->constant_expression_value(mem_ctx);
+ var->data.has_initializer = true;
- /* If the declared variable is an unsized array, it must inherrit
- * its full type from the initializer. A declaration such as
- *
- * uniform float a[] = float[](1.0, 2.0, 3.0, 3.0);
- *
- * becomes
- *
- * uniform float a[4] = float[](1.0, 2.0, 3.0, 3.0);
- *
- * The assignment generated in the if-statement (below) will also
- * automatically handle this case for non-uniforms.
- *
- * If the declared variable is not an array, the types must
- * already match exactly. As a result, the type assignment
- * here can be done unconditionally. For non-uniforms the call
- * to do_assignment can change the type of the initializer (via
- * the implicit conversion rules). For uniforms the initializer
- * must be a constant expression, and the type of that expression
- * was validated above.
- */
- var->type = initializer_type;
+ /* If the declared variable is an unsized array, it must inherrit
+ * its full type from the initializer. A declaration such as
+ *
+ * uniform float a[] = float[](1.0, 2.0, 3.0, 3.0);
+ *
+ * becomes
+ *
+ * uniform float a[4] = float[](1.0, 2.0, 3.0, 3.0);
+ *
+ * The assignment generated in the if-statement (below) will also
+ * automatically handle this case for non-uniforms.
+ *
+ * If the declared variable is not an array, the types must
+ * already match exactly. As a result, the type assignment
+ * here can be done unconditionally. For non-uniforms the call
+ * to do_assignment can change the type of the initializer (via
+ * the implicit conversion rules). For uniforms the initializer
+ * must be a constant expression, and the type of that expression
+ * was validated above.
+ */
+ var->type = initializer_type;
+ }
var->data.read_only = temp;
}
--
2.18.0
Re: [Mesa-dev] [PATCH] i965: Reuse the same single-page bo for all zero sized allocations
Hi,
This is my first attempt to review patch for Mesa, so please take it with a
grain of salt.
On úterý 14. srpna 2018 20:21:40 CEST Chris Wilson wrote:
> @@ -504,6 +506,24 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
> bool busy = false;
> bool zeroed = false;
>
> + /* Reuse the same bo for all zero-sized requests */
> + if (size == 0) {
> + if (bufmgr->bo_zero == NULL) {
> + bo = bo_alloc_internal(bufmgr, "zero", 4096,
> +BRW_MEMZONE_OTHER, BO_ALLOC_BUSY, 0, 0);
> + if (!bo)
> +return NULL;
> +
> + bo->size = 0;
Doesn't this break something once the bo_zero is freed? Either after two
threads raced and one has to cleanup or when the whole bufmgr is destroyed.
The bucket_for_size will choose different bucket for sizes 4096 and 0:
size 4096 -> bucket index 0 -> some bucket (I assume)
size0 -> bucket index 119 -> null bucket (always too big)
So the get_bucket_allocator function will return some bucket when allocating
and null bucket when freeing, so allocation goes thru bucket_vma_alloc and
freeing thru util_vma_heap_free. I did not examine those functions closer, but
it does sound like it would break something.
> +
> + if (p_atomic_cmpxchg(>bo_zero, NULL, bo))
> +brw_bo_unreference(bo);
> + }
Michal
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Re: [Mesa-dev] [PATCH v3 1/6] xmlconfig: refine driParseConfigFiles to use parseOneConfigFile
Thanks, Michel. > What's the point of having the separate _parseOneConfigFile function? > It's not used outside of parseOneConfigFile AFAICT. No particular reason from mine, just move out the inline part. So should be same reason as the original code to separate the parser prepare part and the real file read/parse part. Do you think I have to merge these two functions? Regards, Qiang ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 00/14] Adjusting OpenGL limits and constants
For the series Tested-by: Dieter Nützel Dieter Am 09.08.2018 01:55, schrieb Marek Olšák: Hi, The idea is to expose similar limits as our closed driver. There are also some bug fixes. Please review. Thanks, Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS
On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote: On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset wrote: The last parameter of radeon_set_sh_reg_seq() is the number of dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but it was initialized to 0. COMPUTE_RESOURCE_LIMITS is correctly set when generating compute pipelines, so we don't need to initialize it. Note that there we don't set WAVES_PER_SH. Is that intended? Yeah, I don't think that matters and it wasn't set before anyway. Reviewed-by: Bas Nieuwenhuizen Also a radeonsi patch? Why? Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/si_cmd_buffer.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 2337036c67..2cfa7f4c2c 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -88,9 +88,7 @@ si_emit_compute(struct radv_physical_device *physical_device, radeon_emit(cs, 0); radeon_emit(cs, 0); - radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, - S_00B854_WAVES_PER_SH(0x3)); - radeon_emit(cs, 0); + radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */ radeon_emit(cs, S_00B858_SH0_CU_EN(0x) | S_00B858_SH1_CU_EN(0x)); radeon_emit(cs, S_00B85C_SH0_CU_EN(0x) | S_00B85C_SH1_CU_EN(0x)); -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] i965: Reuse the same single-page bo for all zero sized allocations
Quoting Michal Srb (2018-08-15 09:22:19)
> Hi,
>
> This is my first attempt to review patch for Mesa, so please take it with a
> grain of salt.
>
> On úterý 14. srpna 2018 20:21:40 CEST Chris Wilson wrote:
> > @@ -504,6 +506,24 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
> > bool busy = false;
> > bool zeroed = false;
> >
> > + /* Reuse the same bo for all zero-sized requests */
> > + if (size == 0) {
> > + if (bufmgr->bo_zero == NULL) {
> > + bo = bo_alloc_internal(bufmgr, "zero", 4096,
> > +BRW_MEMZONE_OTHER, BO_ALLOC_BUSY, 0, 0);
> > + if (!bo)
> > +return NULL;
> > +
> > + bo->size = 0;
>
> Doesn't this break something once the bo_zero is freed? Either after two
> threads raced and one has to cleanup or when the whole bufmgr is destroyed.
>
> The bucket_for_size will choose different bucket for sizes 4096 and 0:
> size 4096 -> bucket index 0 -> some bucket (I assume)
> size0 -> bucket index 119 -> null bucket (always too big)
>
> So the get_bucket_allocator function will return some bucket when allocating
> and null bucket when freeing, so allocation goes thru bucket_vma_alloc and
> freeing thru util_vma_heap_free. I did not examine those functions closer,
> but
> it does sound like it would break something.
If it doesn't fit into a bucket, it will be freed immediately. The only
down side is that as it is part of a bucket_vma, it will pin that
bucket_vma forever, but that is not such a big deal as it evaporates
with the bufmgr.
To make the no-bucket more explicit, bo->reusable = false.
-Chris
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Re: [Mesa-dev] [PATCH] radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
wrote:
> Reviewed-by: Samuel Pitoiset
>
> On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
> > Behavior wrt firstInstance got changed, and a divisor of 0 has been
> > disallowed.
> >
> > The new version of the ext got published in specification 1.1.81.
> > ---
> > src/amd/vulkan/radv_extensions.py | 2 +-
> > src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
> > 2 files changed, 5 insertions(+), 4 deletions(-)
> >
> > diff --git a/src/amd/vulkan/radv_extensions.py
> b/src/amd/vulkan/radv_extensions.py
> > index a5fbffac33b..d02042e5647 100644
> > --- a/src/amd/vulkan/radv_extensions.py
> > +++ b/src/amd/vulkan/radv_extensions.py
> > @@ -104,7 +104,7 @@ EXTENSIONS = [
> > Extension('VK_EXT_sampler_filter_minmax', 1,
> 'device->rad_info.chip_class >= CIK'),
> > Extension('VK_EXT_shader_viewport_index_layer', 1, True),
> > Extension('VK_EXT_shader_stencil_export', 1, True),
> > -Extension('VK_EXT_vertex_attribute_divisor', 1, True),
> > +Extension('VK_EXT_vertex_attribute_divisor', 2, True),
> > Extension('VK_AMD_draw_indirect_count', 1, True),
> > Extension('VK_AMD_gcn_shader',1, True),
> > Extension('VK_AMD_rasterization_order', 1,
> 'device->has_out_of_order_rast'),
> > diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
> b/src/amd/vulkan/radv_nir_to_llvm.c
> > index c7d772fa652..d12ef09c9f3 100644
> > --- a/src/amd/vulkan/radv_nir_to_llvm.c
> > +++ b/src/amd/vulkan/radv_nir_to_llvm.c
> > @@ -1984,8 +1984,7 @@ handle_vs_input_decl(struct radv_shader_context
> *ctx,
> > uint32_t divisor =
> ctx->options->key.vs.instance_rate_divisors[attrib_index];
> >
> > if (divisor) {
> > - buffer_index =
> LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
> > -
> ctx->abi.start_instance, "");
> > + buffer_index = ctx->abi.instance_id;
> >
> > if (divisor != 1) {
> > buffer_index =
> LLVMBuildUDiv(ctx->ac.builder, buffer_index,
> > @@ -2000,8 +1999,10 @@ handle_vs_input_decl(struct radv_shader_context
> *ctx,
> > MAX2(1,
> ctx->shader_info->vs.vgpr_comp_cnt);
> > }
> > } else {
> > - buffer_index = ctx->ac.i32_0;
> > + unreachable("Invalid vertex attribute
> divisor of 0.");
>
You'll want to leave this alone. zero is coming back... Yeah, I know it's
annoying but I'm really trying to get this settled out as quickly as
possible. In the mean time, reports are that zero is useful for some DXVK
apps so it's best to just silently support it rather than breaking stuff.
> > }
> > +
> > + buffer_index = LLVMBuildAdd(ctx->ac.builder,
> ctx->abi.start_instance, buffer_index, "");
> > } else
> > buffer_index = LLVMBuildAdd(ctx->ac.builder,
> ctx->abi.vertex_id,
> > ctx->abi.base_vertex,
> "");
> >
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[Mesa-dev] [PATCH v5 1/2] intel/ppgtt: memory address alignment
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to
brw_bufmgr.)
Signed-off-by: Sergii Romantsov
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..19e2d14 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
uint32_t stride)
{
struct brw_bo *bo;
- unsigned int page_size = getpagesize();
int ret;
struct bo_cache_bucket *bucket;
bool alloc_from_cache;
@@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
* allocation up.
*/
if (bucket == NULL) {
- bo_size = size;
- if (bo_size < page_size)
- bo_size = page_size;
+ unsigned int page_size = getpagesize();
+ bo_size = size == 0 ? page_size : ALIGN(size, page_size);
} else {
bo_size = bucket->size;
}
+ assert(bo_size);
mtx_lock(>lock);
/* Get a buffer out of the cache if available */
--
2.7.4
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[Mesa-dev] [PATCH v5 2/2] intel/ppgtt: 4096 replaced by PAGE_SIZE
Usage of number 4096 replaced by PAGE_SIZE.
Signed-off-by: Sergii Romantsov
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 19e2d14..b0f83fb 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -195,7 +195,7 @@ bo_tile_size(struct brw_bufmgr *bufmgr, uint64_t size,
uint32_t tiling)
return size;
/* 965+ just need multiples of page size for tiling */
- return ALIGN(size, 4096);
+ return ALIGN(size, PAGE_SIZE);
}
/*
@@ -1577,12 +1577,12 @@ init_cache_buckets(struct brw_bufmgr *bufmgr)
* width/height alignment and rounding of sizes to pages will
* get us useful cache hit rates anyway)
*/
- add_bucket(bufmgr, 4096);
- add_bucket(bufmgr, 4096 * 2);
- add_bucket(bufmgr, 4096 * 3);
+ add_bucket(bufmgr, PAGE_SIZE);
+ add_bucket(bufmgr, PAGE_SIZE * 2);
+ add_bucket(bufmgr, PAGE_SIZE * 3);
/* Initialize the linked lists for BO reuse cache. */
- for (size = 4 * 4096; size <= cache_max_size; size *= 2) {
+ for (size = 4 * PAGE_SIZE; size <= cache_max_size; size *= 2) {
add_bucket(bufmgr, size);
add_bucket(bufmgr, size + size * 1 / 4);
@@ -1728,7 +1728,7 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
bufmgr->initial_kflags |= EXEC_OBJECT_PINNED;
util_vma_heap_init(>vma_allocator[BRW_MEMZONE_LOW_4G],
-4096, _4GB);
+PAGE_SIZE, _4GB);
util_vma_heap_init(>vma_allocator[BRW_MEMZONE_OTHER],
1 * _4GB, gtt_size - 1 * _4GB);
} else if (devinfo->gen >= 10) {
--
2.7.4
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Re: [Mesa-dev] [PATCH 1/2] egl/android: fix regression in drm_gralloc path
Hey Mauro,
Thanks for catching this.
On 14/08/2018 22.27, Mauro Rossi wrote:
This patch fixes a regression in mesa 18.2 and mesa-dev branches
for HAVE_DRM_GRALLOC code path which is causing black screen on Android
and prevents boot due to SIGSEGV MAPERR crash related to unproper handling
of drm_gralloc drm FD in new droid_open_device() path.
The problem due to c7bb82136b ("egl/android: Add DRM node probing and
filtering")
... 3173 3307 D GRALLOC-DRM: drmOpen radeon: 71
... 3173 3307 I GRALLOC-RADEON: detected chipset 0x6841 family 0x31 (vram
size 238MiB, gart size 1021MiB)
... 3173 3307 I GRALLOC-DRM: create radeon for driver radeon
... 3173 3307 W EGL-MAIN: Could not get native buffer FD
- beginning of crash
... 3173 3307 F libc: Fatal signal 11 (SIGSEGV), code 1, fault addr 0x18
in tid 3307 (RenderThread), pid 3173 (ndroid.systemui)
... 0 0 D : [drm:radeon_crtc_page_flip_target [radeon]]
flip-ioctl() cur_rbo = 3512328a, new_rbo = 00
... 3420 3420 I crash_dump64: performing dump of process 3173 (target tid =
3307)
... 3420 3420 F DEBUG : *** *** *** *** *** *** *** *** *** *** *** *** ***
*** *** ***
... 3420 3420 F DEBUG : Build fingerprint:
'Android-x86/android_x86_64/x86_64:8.1.0/OPM6.171019.030.E1/uten07210645:userdebug/test-keys'
... 3420 3420 F DEBUG : Revision: '0'
... 3420 3420 F DEBUG : ABI: 'x86_64'
... 3420 3420 F DEBUG : pid: 3173, tid: 3307, name: RenderThread >>>
com.android.systemui <<<
... 3420 3420 F DEBUG : signal 11 (SIGSEGV), code 1 (SEGV_MAPERR), fault
addr 0x18
... 3420 3420 F DEBUG : Cause: null pointer dereference
... 3420 3420 F DEBUG : rax rbx 7c6ac3a3eee0 rcx
rdx 0038
... 3420 3420 F DEBUG : rsi rdi 7c6ab5bfeaa0
... 3420 3420 F DEBUG : r8 7c6ab04c16e4 r9 7c6b4ee6a220 r10
r11 0200
... 3420 3420 F DEBUG : r12 r13 r14
0001 r15 7c6ab04c1600
... 3420 3420 F DEBUG : cs 0033 ss 002b
... 3420 3420 F DEBUG : rip 7c6ab0cee444 rbp 7c6ac3ae8400 rsp
7c6ab5bfea80 eflags 00010246
... 3420 3420 F DEBUG :
... 3420 3420 F DEBUG : backtrace:
... 3420 3420 F DEBUG : #00 pc 0056b444
/system/vendor/lib64/dri/gallium_dri.so (st_update_framebuffer_state+660)
... 3420 3420 F DEBUG : #01 pc 00569d61
/system/vendor/lib64/dri/gallium_dri.so (st_validate_state+561)
... 3420 3420 F DEBUG : #02 pc 00572374
/system/vendor/lib64/dri/gallium_dri.so (st_Clear+116)
... 3420 3420 F DEBUG : #03 pc 0004a9c0
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #04 pc 00085cab
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #05 pc 00085f31
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #06 pc 0006e8c1
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #07 pc 0006e3d9
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #08 pc 0006c4e3
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #09 pc 000704c8
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #10 pc 00077fb9
/android/system/lib64/libhwui.so
... 3420 3420 F DEBUG : #11 pc 000117fa
/android/system/lib64/libutils.so
... 3420 3420 F DEBUG : #12 pc 000ba193
/android/system/lib64/libandroid_runtime.so
... 3420 3420 F DEBUG : #13 pc 00079f0b
/android/system/lib64/libc.so
... 3420 3420 F DEBUG : #14 pc 00028c5d
/android/system/lib64/libc.so
... 3420 3420 F DEBUG : #15 pc 00027555
/android/system/lib64/libc.so
To avoid the crash the former existing working droid_open_device() is restored,
renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC braces.
NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD
is not necessary and it is actually causing a redefinition building error,
because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported
by libgralloc_drm which is currently still a dependency.
Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation
and Androdi GUI booting is fixed with i965, nouveau, radeon.
The changes are compatible with gbm_gralloc, I've tested build with hwc too.
I would maybe consider shortening the commit message a little bit, or at least
remove
the crash-logs.
Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering")
Cc: "18.2"
Signed-off-by: Mauro Rossi
---
src/egl/drivers/dri2/platform_android.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index
Re: [Mesa-dev] [PATCH v4 1/2] intel/ppgtt: memory address alignment
Hello, Kenneth.
Thanks for remarks.
Will update patch soon and also will try to look on 3DSTATE_SO_BUFFER.
On Tue, Aug 14, 2018 at 8:39 PM, Kenneth Graunke
wrote:
> Hi Sergii,
>
> This patch causes 2,384 failures in CI. The issue is that we're
> apparently trying to allocate 0 size BOs in some places, which are
> getting rounded up to 4096 with the current code...but with your patch,
> we get ALIGN(0, 4096) == 0, and assert(bo_size) triggers.
>
> We might want to continue rounding up for now. Additionally, we
> probably ought to fix the callers to stop allocating 0 size BOs.
> It looks like most of them come from the 3DSTATE_SO_BUFFER code,
> where one stream has valid transform feedback info, and the other
> 3 are empty. Whoops.
>
> Would you like to fix that, or should I?
>
> --Ken
>
> On Tuesday, August 14, 2018 4:28:35 AM PDT Sergii Romantsov wrote:
> > Hello,
> > seems some part of the World is still may waiting for a possibility to
> play
> > Dying Light... till pushed :)
> >
> > On Mon, Aug 6, 2018 at 4:26 PM, Lionel Landwerlin <
> > lionel.g.landwer...@intel.com> wrote:
> >
> > > On 06/08/18 13:41, Sergii Romantsov wrote:
> > >
> > >> Kernel (for ppgtt) requires memory address to be
> > >> aligned to page size (4096).
> > >>
> > >> -v2: added marking that also fixes initial commit 01058a552294.
> > >> -v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
> > >> instead of alignment of offsets (Chris Wilson).
> > >> -v4: changes related to PAGE_SIZE moved to separate commit
> > >>
> > >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
> > >> Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT
> > >> systems.)
> > >> Fixes: 01058a552294 (i965: Add virtual memory allocator
> infrastructure to
> > >> brw_bufmgr.)
> > >> Signed-off-by: Sergii Romantsov
> > >>
> > >
> > > Reviewed-by: Lionel Landwerlin
> > >
> > > Thanks!
> > >
> > >
> > > ---
> > >> src/mesa/drivers/dri/i965/brw_bufmgr.c | 7 +++
> > >> 1 file changed, 3 insertions(+), 4 deletions(-)
> > >>
> > >> diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > >> b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > >> index 09d45e3..8274c2e 100644
> > >> --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > >> +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
> > >> @@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
> > >> uint32_t stride)
> > >> {
> > >> struct brw_bo *bo;
> > >> - unsigned int page_size = getpagesize();
> > >> int ret;
> > >> struct bo_cache_bucket *bucket;
> > >> bool alloc_from_cache;
> > >> @@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
> > >> * allocation up.
> > >> */
> > >> if (bucket == NULL) {
> > >> - bo_size = size;
> > >> - if (bo_size < page_size)
> > >> - bo_size = page_size;
> > >> + unsigned int page_size = getpagesize();
> > >> + bo_size = ALIGN(size, page_size);
> > >> } else {
> > >> bo_size = bucket->size;
> > >> }
> > >> + assert(bo_size);
> > >>mtx_lock(>lock);
> > >> /* Get a buffer out of the cache if available */
> > >>
> > >
> > >
> > > ___
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> > > mesa-dev@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > >
> >
> >
> >
> >
>
>
--
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GlobalLogic Inc.
www.globallogic.com
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[Mesa-dev] [PATCH 18/21] mesa: move legacy dri config option no_neg_lod_bias
---
src/mesa/drivers/dri/radeon/radeon_screen.c | 5 +
src/util/xmlpool/ca.po | 6 --
src/util/xmlpool/de.po | 4
src/util/xmlpool/es.po | 4
src/util/xmlpool/fr.po | 4
src/util/xmlpool/nl.po | 4
src/util/xmlpool/sv.po | 4
src/util/xmlpool/t_options.h| 5 -
8 files changed, 5 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c
b/src/mesa/drivers/dri/radeon/radeon_screen.c
index e19945318b7..d830e410685 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -80,6 +80,11 @@ DRI_CONF_OPT_BEGIN_V(texture_units,int,def, # min ":" # max
) \
DRI_CONF_DESC(en,"Number of texture units used") \
DRI_CONF_OPT_END
+#define DRI_CONF_NO_NEG_LOD_BIAS(def) \
+DRI_CONF_OPT_BEGIN_B(no_neg_lod_bias, def) \
+DRI_CONF_DESC(en,"Forbid negative texture LOD bias") \
+DRI_CONF_OPT_END
+
#if defined(RADEON_R100) /* R100 */
static const __DRIconfigOptionsExtension radeon_config_options = {
.base = { __DRI_CONFIG_OPTIONS, 1 },
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index 1710a2ce199..7760da13ac2 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -106,12 +106,6 @@ msgstr "Força 16 bits per texel"
msgid "Initial maximum value for anisotropic texture filtering"
msgstr "Valor màxim inicial per a la filtració de textura anisòtropa"
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr ""
-"Prohibeix una parcialitat negativa del Nivell de Detalle (LOD) de les "
-"textures"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 5581725a251..9e466f7620a 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -83,10 +83,6 @@ msgstr "Erzwinge 16 bits pro Texel"
msgid "Initial maximum value for anisotropic texture filtering"
msgstr "Initialer Maximalwert für anisotropische Texturfilterung"
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Verbiete negative Textur-Detailgradverschiebung"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 85288bfbe8a..cd76fa39b4a 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -90,10 +90,6 @@ msgstr "Forzar a 16 bits por texel"
msgid "Initial maximum value for anisotropic texture filtering"
msgstr "Valor máximo inicial para filtrado anisotrópico de textura"
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Prohibir valores negativos de Nivel De Detalle (LOD) de texturas"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 1f2d04cd396..d086b44a4b0 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -82,10 +82,6 @@ msgstr "Forcer 16 bits par texel"
msgid "Initial maximum value for anisotropic texture filtering"
msgstr "Valeur maximale initiale pour le filtrage anisotropique de texture"
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Interdire le LOD bias negatif"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index 21845ce879c..38473fdc2de 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -82,10 +82,6 @@ msgstr "Dwing 16 bits per texel af"
msgid "Initial maximum value for anisotropic texture filtering"
msgstr "Initïele maximum waarde voor anisotrophische textuur filtering"
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Verbied negatief niveau detailonderscheid (LOD) van texturen"
-
#: t_options.h:182
msgid "Horizontal error diffusion"
msgstr "Horizontale foutdiffusie"
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index 61d735b86c1..8c3bca72e68 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -82,10 +82,6 @@ msgstr "Tvinga 16 bitar per texel"
msgid "Initial maximum value for anisotropic texture filtering"
msgstr "Initialt maximalt värde för anisotropisk texturfiltrering"
-#: t_options.h:148
-msgid "Forbid negative texture LOD bias"
-msgstr "Förbjud negativ LOD-kompensation för texturer"
-
#: t_options.h:181
msgid "Color dithering method"
msgstr "Färgutjämningsmetod"
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index 1641f80041d..68ba7413129 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -161,11 +161,6
[Mesa-dev] [PATCH 20/21] mesa: move legacy dri config option fthrottle_mode
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 12
src/util/xmlpool/ca.po | 17 -
src/util/xmlpool/de.po | 17 -
src/util/xmlpool/es.po | 17 -
src/util/xmlpool/fr.po | 16
src/util/xmlpool/nl.po | 19 ---
src/util/xmlpool/sv.po | 16
src/util/xmlpool/t_options.h| 12
8 files changed, 12 insertions(+), 114 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 878f6793926..820c5a1f850 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -79,6 +79,18 @@ DRI_CONF_OPT_BEGIN_V(round_mode,enum,def,"0:1") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_FTHROTTLE_BUSY 0
+#define DRI_CONF_FTHROTTLE_USLEEPS 1
+#define DRI_CONF_FTHROTTLE_IRQS 2
+#define DRI_CONF_FTHROTTLE_MODE(def) \
+DRI_CONF_OPT_BEGIN_V(fthrottle_mode,enum,def,"0:2") \
+DRI_CONF_DESC_BEGIN(en,"Method to limit rendering latency") \
+DRI_CONF_ENUM(0,"Busy waiting for the graphics hardware") \
+DRI_CONF_ENUM(1,"Sleep for brief intervals while waiting for
the graphics hardware") \
+DRI_CONF_ENUM(2,"Let the graphics hardware emit a software
interrupt and sleep") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
+
typedef struct {
drm_handle_t handle;/* Handle to the DRM region */
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index e8ff8af1bb4..ddb37b6dd8f 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -139,23 +139,6 @@ msgstr ""
msgid "Performance"
msgstr "Rendiment"
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Mètode per a limitar la latència de renderització"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Espera activa pel maquinari de gràfics"
-
-#: t_options.h:253
-msgid "Sleep for brief intervals while waiting for the graphics hardware"
-msgstr "Dorm per intervals breus mentre s'espera al maquinari de gràfics"
-
-#: t_options.h:254
-msgid "Let the graphics hardware emit a software interrupt and sleep"
-msgstr ""
-"Deixa que el maquinari de gràfics emeti una interrupció de programari i dormi"
-
#: t_options.h:264
msgid "Synchronization with vertical refresh (swap intervals)"
msgstr "Sincronització amb refresc vertical (intervals d'intercanvi)"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 8d5804f4433..7b5b9510cfc 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -115,23 +115,6 @@ msgstr ""
msgid "Performance"
msgstr "Leistung"
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Methode zur Begrenzung der Bildverzögerung"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Aktives Warten auf die Grafikhardware"
-
-#: t_options.h:253
-msgid "Sleep for brief intervals while waiting for the graphics hardware"
-msgstr "Kurze Schlafintervalle beim Warten auf die Grafikhardware"
-
-#: t_options.h:254
-msgid "Let the graphics hardware emit a software interrupt and sleep"
-msgstr ""
-"Die Grafikhardware eine Softwareunterbrechnung erzeugen lassen und schlafen"
-
#: t_options.h:264
msgid "Synchronization with vertical refresh (swap intervals)"
msgstr "Synchronisation mit der vertikalen Bildwiederholung"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index c79191f6c8b..81106ae7139 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -122,23 +122,6 @@ msgstr ""
msgid "Performance"
msgstr "Rendimiento"
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Método para limitar la latencia de renderización"
-
-#: t_options.h:252
-msgid "Busy waiting for the graphics hardware"
-msgstr "Esperar activamente al hardware gráfico"
-
-#: t_options.h:253
-msgid "Sleep for brief intervals while waiting for the graphics hardware"
-msgstr "Dormir en intervalos cortos mientras se espera al hardware gráfico"
-
-#: t_options.h:254
-msgid "Let the graphics hardware emit a software interrupt and sleep"
-msgstr ""
-"Permitir que el hardware gráfico emita una interrupción de software y duerma"
-
#: t_options.h:264
msgid "Synchronization with vertical refresh (swap intervals)"
msgstr "Sincronización con el refresco vertical (intervalos de intercambio)"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index c1856aa0fd3..f1a2ce0748e 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -110,22 +110,6 @@ msgstr ""
msgid "Performance"
msgstr "Performance"
-#: t_options.h:251
-msgid "Method to limit rendering latency"
-msgstr "Méthode d'attente de la carte graphique"
-
-#: t_options.h:252
-msgid "Busy waiting for the
[Mesa-dev] [PATCH 21/21] mesa: move legacy dri config option texture_depth
---
src/mesa/drivers/dri/radeon/radeon_screen.h | 13 +
src/util/xmlpool/ca.po | 20
src/util/xmlpool/de.po | 20
src/util/xmlpool/es.po | 20
src/util/xmlpool/fr.po | 20
src/util/xmlpool/nl.po | 20
src/util/xmlpool/sv.po | 20
src/util/xmlpool/t_options.h| 14 --
8 files changed, 13 insertions(+), 134 deletions(-)
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h
b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 820c5a1f850..7ac4868a573 100644
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -91,6 +91,19 @@ DRI_CONF_OPT_BEGIN_V(fthrottle_mode,enum,def,"0:2") \
DRI_CONF_DESC_END \
DRI_CONF_OPT_END
+#define DRI_CONF_TEXTURE_DEPTH_FB 0
+#define DRI_CONF_TEXTURE_DEPTH_32 1
+#define DRI_CONF_TEXTURE_DEPTH_16 2
+#define DRI_CONF_TEXTURE_DEPTH_FORCE_16 3
+#define DRI_CONF_TEXTURE_DEPTH(def) \
+DRI_CONF_OPT_BEGIN_V(texture_depth,enum,def,"0:3") \
+ DRI_CONF_DESC_BEGIN(en,"Texture color depth") \
+DRI_CONF_ENUM(0,"Prefer frame buffer color depth") \
+DRI_CONF_ENUM(1,"Prefer 32 bits per texel") \
+DRI_CONF_ENUM(2,"Prefer 16 bits per texel") \
+DRI_CONF_ENUM(3,"Force 16 bits per texel") \
+DRI_CONF_DESC_END \
+DRI_CONF_OPT_END
typedef struct {
drm_handle_t handle;/* Handle to the DRM region */
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index ddb37b6dd8f..91621f2831d 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -82,26 +82,6 @@ msgstr "Permet les directives #extension GLSL en el mitjà
dels shaders"
msgid "Image Quality"
msgstr "Qualitat d'imatge"
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Profunditat de color de textura"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Prefereix profunditat de color del framebuffer"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Prefereix 32 bits per texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Prefereix 16 bits per texel"
-
-#: t_options.h:137
-msgid "Force 16 bits per texel"
-msgstr "Força 16 bits per texel"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtre de postprocessament per a aplicar cel shading a la sortida"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index 7b5b9510cfc..8c1d3df3f11 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -59,26 +59,6 @@ msgstr ""
msgid "Image Quality"
msgstr "Bildqualität"
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Texturfarbtiefe"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Bevorzuge Farbtiefe des Framebuffers"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Bevorzuge 32 bits pro Texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Bevorzuge 16 bits pro Texel"
-
-#: t_options.h:137
-msgid "Force 16 bits per texel"
-msgstr "Erzwinge 16 bits pro Texel"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Nachbearbeitungsfilter für Cell Shading"
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 81106ae7139..e5f44c8efc5 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -66,26 +66,6 @@ msgstr "Permite directivas #extension GLSL en medio de los
shaders"
msgid "Image Quality"
msgstr "Calidad de imagen"
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Profundidad de color de textura"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Preferir profundidad de color del framebuffer"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Preferir 32 bits por texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr "Preferir 16 bits por texel"
-
-#: t_options.h:137
-msgid "Force 16 bits per texel"
-msgstr "Forzar a 16 bits por texel"
-
#: t_options.h:195
msgid "A post-processing filter to cel-shade the output"
msgstr "Un filtro de postprocesamiento para aplicar cel shading a la salida"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index f1a2ce0748e..aa8706cbb1c 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -58,26 +58,6 @@ msgstr ""
msgid "Image Quality"
msgstr "Qualité d'image"
-#: t_options.h:133
-msgid "Texture color depth"
-msgstr "Profondeur de texture"
-
-#: t_options.h:134
-msgid "Prefer frame buffer color depth"
-msgstr "Profondeur de couleur"
-
-#: t_options.h:135
-msgid "Prefer 32 bits per texel"
-msgstr "Préférer 32 bits par texel"
-
-#: t_options.h:136
-msgid "Prefer 16 bits per texel"
-msgstr
[Mesa-dev] [PATCH] radv: add Doom workaround
Cc:
---
src/amd/vulkan/radv_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 33f24b9d302..cc88abb57a8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -480,6 +480,9 @@ radv_handle_per_app_options(struct radv_instance *instance,
*/
instance->perftest_flags |= RADV_PERFTEST_SISCHED;
}
+ } else if (!strcmp(name, "DOOM_VFR")) {
+ /* Work around a Doom VFR game bug */
+ instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
}
}
--
2.17.1
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Re: [Mesa-dev] [PATCH] radv: add Doom workaround
On 15/08/18 22:06, Bas Nieuwenhuizen wrote: On Wed, Aug 15, 2018 at 1:16 PM, Mike Lothian wrote: Do you need the game name here, isn't that set in driconf? There is no driconf for vulkan/radv yet. Reviewed-by: Bas Nieuwenhuizen I assume you tested that it works with the workaround? Yes. I get a black screen without it and I can get to the menu with it. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] egl/android: fix regression in drm_gralloc path
Hi Robert,
Il giorno mer 15 ago 2018 alle ore 09:37 Robert Foss <
robert.f...@collabora.com> ha scritto:
> Hey Mauro,
>
> Thanks for catching this.
>
> On 14/08/2018 22.27, Mauro Rossi wrote:
> > This patch fixes a regression in mesa 18.2 and mesa-dev branches
> > for HAVE_DRM_GRALLOC code path which is causing black screen on Android
> > and prevents boot due to SIGSEGV MAPERR crash related to unproper
> handling
> > of drm_gralloc drm FD in new droid_open_device() path.
> >
> > The problem due to c7bb82136b ("egl/android: Add DRM node probing and
> filtering")
> >
> > ... 3173 3307 D GRALLOC-DRM: drmOpen radeon: 71
> > ... 3173 3307 I GRALLOC-RADEON: detected chipset 0x6841 family 0x31
> (vram size 238MiB, gart size 1021MiB)
> > ... 3173 3307 I GRALLOC-DRM: create radeon for driver radeon
> > ... 3173 3307 W EGL-MAIN: Could not get native buffer FD
> > - beginning of crash
> > ... 3173 3307 F libc: Fatal signal 11 (SIGSEGV), code 1, fault
> addr 0x18 in tid 3307 (RenderThread), pid 3173 (ndroid.systemui)
> > ... 0 0 D : [drm:radeon_crtc_page_flip_target [radeon]]
> flip-ioctl() cur_rbo = 3512328a, new_rbo = 00
> > ... 3420 3420 I crash_dump64: performing dump of process 3173 (target
> tid = 3307)
> > ... 3420 3420 F DEBUG : *** *** *** *** *** *** *** *** *** *** ***
> *** *** *** *** ***
> > ... 3420 3420 F DEBUG : Build fingerprint:
> 'Android-x86/android_x86_64/x86_64:8.1.0/OPM6.171019.030.E1/uten07210645:userdebug/test-keys'
> > ... 3420 3420 F DEBUG : Revision: '0'
> > ... 3420 3420 F DEBUG : ABI: 'x86_64'
> > ... 3420 3420 F DEBUG : pid: 3173, tid: 3307, name: RenderThread
> >>> com.android.systemui <<<
> > ... 3420 3420 F DEBUG : signal 11 (SIGSEGV), code 1 (SEGV_MAPERR),
> fault addr 0x18
> > ... 3420 3420 F DEBUG : Cause: null pointer dereference
> > ... 3420 3420 F DEBUG : rax rbx
> 7c6ac3a3eee0 rcx rdx 0038
> > ... 3420 3420 F DEBUG : rsi rdi
> 7c6ab5bfeaa0
> > ... 3420 3420 F DEBUG : r8 7c6ab04c16e4 r9
> 7c6b4ee6a220 r10 r11 0200
> > ... 3420 3420 F DEBUG : r12 r13
> r14 0001 r15 7c6ab04c1600
> > ... 3420 3420 F DEBUG : cs 0033 ss
> 002b
> > ... 3420 3420 F DEBUG : rip 7c6ab0cee444 rbp
> 7c6ac3ae8400 rsp 7c6ab5bfea80 eflags 00010246
> > ... 3420 3420 F DEBUG :
> > ... 3420 3420 F DEBUG : backtrace:
> > ... 3420 3420 F DEBUG : #00 pc 0056b444
> /system/vendor/lib64/dri/gallium_dri.so (st_update_framebuffer_state+660)
> > ... 3420 3420 F DEBUG : #01 pc 00569d61
> /system/vendor/lib64/dri/gallium_dri.so (st_validate_state+561)
> > ... 3420 3420 F DEBUG : #02 pc 00572374
> /system/vendor/lib64/dri/gallium_dri.so (st_Clear+116)
> > ... 3420 3420 F DEBUG : #03 pc 0004a9c0
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #04 pc 00085cab
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #05 pc 00085f31
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #06 pc 0006e8c1
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #07 pc 0006e3d9
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #08 pc 0006c4e3
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #09 pc 000704c8
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #10 pc 00077fb9
> /android/system/lib64/libhwui.so
> > ... 3420 3420 F DEBUG : #11 pc 000117fa
> /android/system/lib64/libutils.so
> > ... 3420 3420 F DEBUG : #12 pc 000ba193
> /android/system/lib64/libandroid_runtime.so
> > ... 3420 3420 F DEBUG : #13 pc 00079f0b
> /android/system/lib64/libc.so
> > ... 3420 3420 F DEBUG : #14 pc 00028c5d
> /android/system/lib64/libc.so
> > ... 3420 3420 F DEBUG : #15 pc 00027555
> /android/system/lib64/libc.so
> >
> > To avoid the crash the former existing working droid_open_device() is
> restored,
> > renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC
> braces.
> >
> > NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD
> > is not necessary and it is actually causing a redefinition building
> error,
> > because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported
> > by libgralloc_drm which is currently still a dependency.
> >
> > Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation
> > and Androdi GUI booting is fixed with i965, nouveau, radeon.
> >
> > The changes are compatible with gbm_gralloc, I've tested build with hwc
> too.
>
> I would maybe consider shortening the commit message a little bit, or at
>
Re: [Mesa-dev] [PATCH 0/8] Easy OpenGL extensions
Hello Marek, sadly this series didn't apply on top of current git master. Dieter Am 09.08.2018 04:12, schrieb Marek Olšák: Hi, This series adds these extensions: - AMD_gpu_shader_int64 - AMD_multi_draw_indirect - AMD_query_buffer_object - AMD_texture_texture4 - EXT_vertex_attrib_64bit It also exposes these extensions for gallium (radeonsi): - EXT_disjoint_timer_query - KHR_texture_compression_astc_sliced_3d It also allows this in the Compatibility profile: - ARB_post_depth_coverage (not supported by radeonsi) Please review. Thanks, Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv/meta_decompress: fix pointer to integer conversion
On Wed, Aug 15, 2018 at 2:04 PM, Mauro Rossi wrote:
> Hi Bas,
>
> Il giorno mar 14 ago 2018 alle ore 23:10 Bas Nieuwenhuizen
> ha scritto:
>>
>> On Tue, Aug 14, 2018 at 10:48 PM, Mauro Rossi
>> wrote:
>> > (VkShaderModule) cast is added before NULL to avoid following building
>> > error:
>> >
>> > external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error:
>> > incompatible pointer to integer conversion passing 'void *' to parameter
>> > of type 'VkShaderModule' (aka 'unsigned long long')
>> > [-Werror,-Wint-conversion]
>> > VkResult ret = create_pipeline(cmd_buffer->device, NULL,
>> > samples,
>> >^~~~
>> >
>> > prebuilts/clang/host/linux-x86/clang-4053586/lib64/clang/5.0.300080/include/stddef.h:105:16:
>> > note: expanded from macro 'NULL'
>> > # define NULL ((void*)0)
>> >^~
>> > external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32:
>> > note: passing argument to parameter 'vs_module_h' here
>> > VkShaderModule vs_module_h,
>> >^
>> > 1 error generated.
>> >
>> > Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in
>> > shaders.")
>> > Signed-off-by: Mauro Rossi
>> > ---
>> > src/amd/vulkan/radv_meta_decompress.c | 2 +-
>> > 1 file changed, 1 insertion(+), 1 deletion(-)
>> >
>> > diff --git a/src/amd/vulkan/radv_meta_decompress.c
>> > b/src/amd/vulkan/radv_meta_decompress.c
>> > index 41ed7b6d04..183be1fd88 100644
>> > --- a/src/amd/vulkan/radv_meta_decompress.c
>> > +++ b/src/amd/vulkan/radv_meta_decompress.c
>> > @@ -362,7 +362,7 @@ static void radv_process_depth_image_inplace(struct
>> > radv_cmd_buffer *cmd_buffer,
>> > return;
>> >
>> > if (!meta_state->depth_decomp[samples_log2].decompress_pipeline)
>> > {
>> > - VkResult ret = create_pipeline(cmd_buffer->device, NULL,
>> > samples,
>> > + VkResult ret = create_pipeline(cmd_buffer->device,
>> > (VkShaderModule) NULL, samples,
>>
>> Instead of the cast, use VK_NULL_HANDLE.
>
>
> I've applied that change and it is working.
>
> Do you prefer I send a v2 patch version to mesa-dev ML or may I apply to
> gitlab master with your Reviewed-by ?
Sorry for that, yes it is
Reviewed-by: Bas Nieuwenhuizen
with the change.
> Thanks
>
> Mauro
>
>>
>>
>> >
>> > meta_state->depth_decomp[samples_log2].pass,
>> >
>> > meta_state->depth_decomp[samples_log2].p_layout,
>> >
>> > _state->depth_decomp[samples_log2].decompress_pipeline,
>> > --
>> > 2.17.1
>> >
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Re: [Mesa-dev] [PATCH] radv: add Doom workaround
I don't like this... but patch is:
Reviewed-by: Samuel Pitoiset
On 8/15/18 1:12 PM, Timothy Arceri wrote:
Cc:
---
src/amd/vulkan/radv_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 33f24b9d302..cc88abb57a8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -480,6 +480,9 @@ radv_handle_per_app_options(struct radv_instance *instance,
*/
instance->perftest_flags |= RADV_PERFTEST_SISCHED;
}
+ } else if (!strcmp(name, "DOOM_VFR")) {
+ /* Work around a Doom VFR game bug */
+ instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
}
}
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[Mesa-dev] [ANNOUNCE] mesa 18.2.0-rc3
Hello list,
The third release candidate for the Mesa 18.2.0 is now available.
Currently we have:
- 24 queued
- 1 nominated (outstanding)
- and 0 rejected patches
In the current queue we have:
The GLSL compiler has received a correction when hitting an error
condition.
Mesa's state tracker has gotten a patch when checking for ETC2
compatibility.
We are including multiple fixes for the Broadcom, AMD's radv and Intel
drivers while individual fixes for the swr driver and Intel tools.
The EGL driver has received a couple of fixes for the Wayland platform
and another one for the X11. GLX has also received another fix.
From build and integration point of view, we have multiple fixes to
build with autotools and in Android.
Finally, we are also including a fix for Metro 2033 Redux and Metro
Last Light Redux.
Take a look at section "Mesa stable queue" for more information.
Testing reports/general approval
Any testing reports (or general approval of the state of the branch)
will be greatly appreciated.
The plan is to have the fourth release candidate for 18.2.0 next
Wednesday (2018/08/22), around or shortly after 18:00 EEST.
If you have any questions or suggestions - be that about the current
patch queue or otherwise, please go ahead.
Trivial merge conflicts
---
No merge conflicts.
Br,
Andres
Mesa stable queue
-
Nominated (1)
=
Mauro Rossi (1):
egl/android: fix regression in drm_gralloc path (v2)
Queued (24)
===
Adam Jackson (1):
glx: GLX_MESA_multithread_makecurrent is direct-only
Andres Gomez (1):
Update version to 18.2.0-rc3
Bas Nieuwenhuizen (3):
radv: Fix missing Android platform define.
radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.
Emil Velikov (5):
automake: require shared glapi when using DRI based libGL
autotools: error out when using the broken --with-{gl, osmesa}-lib-name
autotools: error out when building with mangling and glvnd
autotools: use correct gl.pc LIBS when using glvnd
swr: don't export swr_create_screen_internal
Eric Anholt (4):
vc4: Respect a sampler view's first_layer field.
vc4: Ignore samplers for finding uniform offsets.
vc4: Fix vc4_fence_server_sync() on pre-syncobj kernels.
egl: Fix leak of X11 pixmaps backing pbuffers in DRI3.
Eric Engestrom (1):
intel/tools: add missing variable initialisation
Gert Wollny (1):
mesa/st: ETC2 now uses R8G8B8A8_SRGB as fallback
Jason Ekstrand (1):
intel: Switch the order of the 2x MSAA sample positions
Juan A. Suarez Romero (2):
wayland/egl: initialize window surface size to window size
wayland/egl: update surface size on window resize
Kenneth Graunke (3):
intel: Fix SIMD16 unaligned payload GRF reads on Gen4-5.
blorp: Don't try to use R32_UNORM for R24_UNORM_X8_TYPELESS rendering.
blorp: Properly handle Z24X8 blits.
Tapani Pälli (1):
glsl: handle error case with ast_post_inc, ast_post_dec
vadym.shovkoplias (1):
drirc: Allow extension midshader for Metro Redux
Rejected (0)
No rejections.
git tag: mesa-18.2.0-rc3
https://mesa.freedesktop.org/archive/mesa-18.2.0-rc3.tar.gz
MD5: e63ad06c07185bfb0bd0d266a4fd79f8 mesa-18.2.0-rc3.tar.gz
SHA1: d3a0d0015579eaf1d64fbb97c105f7063b295506 mesa-18.2.0-rc3.tar.gz
SHA256: 76a6ea3633439f43eac5e81837750f3b39cb8cc6a0e7ce5305296b88c0637e9e
mesa-18.2.0-rc3.tar.gz
SHA512:
d8332255cd3ca030743d0002a923ae40cee08dd51a5231cbb19b27917b65f3b6f788047f5e465b7ba1d08933c9066e410c8b2ca02f78837381a90179c237c366
mesa-18.2.0-rc3.tar.gz
PGP: https://mesa.freedesktop.org/archive/mesa-18.2.0-rc3.tar.gz.sig
https://mesa.freedesktop.org/archive/mesa-18.2.0-rc3.tar.xz
MD5: 0a28b9d1e18973633f46415d99dd667d mesa-18.2.0-rc3.tar.xz
SHA1: 7cc018b6054cf9962eacabf0aabc2d7129854d69 mesa-18.2.0-rc3.tar.xz
SHA256: 5a4cc9a9e4eef016338d708edc1c0265a90ee7bbfc7c2b8a96e3c7320c18f5a5
mesa-18.2.0-rc3.tar.xz
SHA512:
175dbdffdcdf61c7ac0e4e1fae021daba80311fac02074ad6dea208971ab50c68bc43ba8d7b36ecf82b7081c051d301cb562f66785446973b88657d48f7bb663
mesa-18.2.0-rc3.tar.xz
PGP: https://mesa.freedesktop.org/archive/mesa-18.2.0-rc3.tar.xz.sig
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[Mesa-dev] [Bug 107563] [RADV] Broken rendering in Unity demos
https://bugs.freedesktop.org/show_bug.cgi?id=107563 --- Comment #5 from Samuel Pitoiset --- Can you try to record a renderdoc trace that reproduces the issue please? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
On Wed, Aug 15, 2018 at 11:49 AM, Jason Ekstrand wrote:
> On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
> wrote:
>>
>> Reviewed-by: Samuel Pitoiset
>>
>> On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
>> > Behavior wrt firstInstance got changed, and a divisor of 0 has been
>> > disallowed.
>> >
>> > The new version of the ext got published in specification 1.1.81.
>> > ---
>> > src/amd/vulkan/radv_extensions.py | 2 +-
>> > src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
>> > 2 files changed, 5 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/src/amd/vulkan/radv_extensions.py
>> > b/src/amd/vulkan/radv_extensions.py
>> > index a5fbffac33b..d02042e5647 100644
>> > --- a/src/amd/vulkan/radv_extensions.py
>> > +++ b/src/amd/vulkan/radv_extensions.py
>> > @@ -104,7 +104,7 @@ EXTENSIONS = [
>> > Extension('VK_EXT_sampler_filter_minmax', 1,
>> > 'device->rad_info.chip_class >= CIK'),
>> > Extension('VK_EXT_shader_viewport_index_layer', 1, True),
>> > Extension('VK_EXT_shader_stencil_export', 1, True),
>> > -Extension('VK_EXT_vertex_attribute_divisor', 1, True),
>> > +Extension('VK_EXT_vertex_attribute_divisor', 2, True),
>> > Extension('VK_AMD_draw_indirect_count', 1, True),
>> > Extension('VK_AMD_gcn_shader',1, True),
>> > Extension('VK_AMD_rasterization_order', 1,
>> > 'device->has_out_of_order_rast'),
>> > diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
>> > b/src/amd/vulkan/radv_nir_to_llvm.c
>> > index c7d772fa652..d12ef09c9f3 100644
>> > --- a/src/amd/vulkan/radv_nir_to_llvm.c
>> > +++ b/src/amd/vulkan/radv_nir_to_llvm.c
>> > @@ -1984,8 +1984,7 @@ handle_vs_input_decl(struct radv_shader_context
>> > *ctx,
>> > uint32_t divisor =
>> > ctx->options->key.vs.instance_rate_divisors[attrib_index];
>> >
>> > if (divisor) {
>> > - buffer_index =
>> > LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
>> > -
>> > ctx->abi.start_instance, "");
>> > + buffer_index = ctx->abi.instance_id;
>> >
>> > if (divisor != 1) {
>> > buffer_index =
>> > LLVMBuildUDiv(ctx->ac.builder, buffer_index,
>> > @@ -2000,8 +1999,10 @@ handle_vs_input_decl(struct radv_shader_context
>> > *ctx,
>> > MAX2(1,
>> > ctx->shader_info->vs.vgpr_comp_cnt);
>> > }
>> > } else {
>> > - buffer_index = ctx->ac.i32_0;
>> > + unreachable("Invalid vertex attribute
>> > divisor of 0.");
>
>
> You'll want to leave this alone. zero is coming back... Yeah, I know it's
> annoying but I'm really trying to get this settled out as quickly as
> possible. In the mean time, reports are that zero is useful for some DXVK
> apps so it's best to just silently support it rather than breaking stuff.
Is the behavior of zero going to be the same as it was in version 1?
>
>>
>> > }
>> > +
>> > + buffer_index = LLVMBuildAdd(ctx->ac.builder,
>> > ctx->abi.start_instance, buffer_index, "");
>> > } else
>> > buffer_index = LLVMBuildAdd(ctx->ac.builder,
>> > ctx->abi.vertex_id,
>> > ctx->abi.base_vertex,
>> > "");
>> >
>> ___
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>> mesa-dev@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH v4 2/4] gm107/ir: add support for OP_XMAD on GM107+
v4: make the immediate field 16 bits
Signed-off-by: Rhys Perry
---
.../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 65 ++
.../nouveau/codegen/nv50_ir_target_gm107.cpp | 6 +-
.../nouveau/codegen/nv50_ir_target_nvc0.cpp| 1 +
3 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 5e8c22cd54..9138a2717d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -156,6 +156,7 @@ private:
void emitIMUL();
void emitIMAD();
void emitISCADD();
+ void emitXMAD();
void emitIMNMX();
void emitICMP();
void emitISET();
@@ -1893,6 +1894,67 @@ CodeEmitterGM107::emitISCADD()
emitGPR (0x00, insn->def(0));
}
+void
+CodeEmitterGM107::emitXMAD()
+{
+ assert(insn->src(0).getFile() == FILE_GPR);
+
+ bool constbuf = false;
+ bool psl_mrg = true;
+ bool immediate = false;
+ if (insn->src(2).getFile() == FILE_MEMORY_CONST) {
+ assert(insn->src(1).getFile() == FILE_GPR);
+ constbuf = true;
+ psl_mrg = false;
+ emitInsn(0x5100);
+ emitGPR(0x27, insn->src(1));
+ emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(2));
+ } else if (insn->src(1).getFile() == FILE_MEMORY_CONST) {
+ assert(insn->src(2).getFile() == FILE_GPR);
+ constbuf = true;
+ emitInsn(0x4e00);
+ emitCBUF(0x22, -1, 0x14, 16, 2, insn->src(1));
+ emitGPR(0x27, insn->src(2));
+ } else if (insn->src(1).getFile() == FILE_IMMEDIATE) {
+ assert(insn->src(2).getFile() == FILE_GPR);
+ assert(!(insn->subOp & NV50_IR_SUBOP_XMAD_H1(1)));
+ immediate = false;
+ emitInsn(0x3600);
+ emitIMMD(0x14, 16, insn->src(1));
+ emitGPR(0x27, insn->src(2));
+ } else {
+ assert(insn->src(1).getFile() == FILE_GPR);
+ assert(insn->src(2).getFile() == FILE_GPR);
+ emitInsn(0x5b00);
+ emitGPR(0x14, insn->src(1));
+ emitGPR(0x27, insn->src(2));
+ }
+
+ if (psl_mrg)
+ emitField(constbuf ? 0x37 : 0x24, 2, insn->subOp & 0x3);
+
+ unsigned cmode = (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK);
+ cmode >>= NV50_IR_SUBOP_XMAD_CMODE_SHIFT;
+ emitField(0x32, constbuf ? 2 : 3, cmode);
+
+ emitX(constbuf ? 0x36 : 0x26);
+ emitCC(0x2f);
+
+ emitGPR(0x0, insn->def(0));
+ emitGPR(0x8, insn->src(0));
+
+ // source flags
+ if (isSignedType(insn->sType)) {
+ uint16_t h1s = insn->subOp & NV50_IR_SUBOP_XMAD_H1_MASK;
+ emitField(0x30, 2, h1s >> NV50_IR_SUBOP_XMAD_H1_SHIFT);
+ }
+ emitField(0x35, 1, insn->subOp & NV50_IR_SUBOP_XMAD_H1(0) ? 1 : 0);
+ if (!immediate) {
+ bool h1 = insn->subOp & NV50_IR_SUBOP_XMAD_H1(1);
+ emitField(constbuf ? 0x34 : 0x23, 1, h1);
+ }
+}
+
void
CodeEmitterGM107::emitIMNMX()
{
@@ -3267,6 +3329,9 @@ CodeEmitterGM107::emitInstruction(Instruction *i)
case OP_SHLADD:
emitISCADD();
break;
+ case OP_XMAD:
+ emitXMAD();
+ break;
case OP_MIN:
case OP_MAX:
if (isFloatType(insn->dType)) {
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
index 2dd12322a8..de07ad1de8 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
@@ -59,12 +59,15 @@ TargetGM107::isOpSupported(operation op, DataType ty) const
case OP_POW:
case OP_DIV:
case OP_MOD:
- case OP_XMAD:
return false;
case OP_SQRT:
if (ty == TYPE_F64)
return false;
return chipset >= NVISA_GM200_CHIPSET;
+ case OP_XMAD:
+ if (isFloatType(ty))
+ return false;
+ break;
default:
break;
}
@@ -235,6 +238,7 @@ TargetGM107::getLatency(const Instruction *insn) const
case OP_SUB:
case OP_VOTE:
case OP_XOR:
+ case OP_XMAD:
if (insn->dType != TYPE_F64)
return 6;
break;
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
index 8e04069536..60134b445d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp
@@ -162,6 +162,7 @@ static const struct opProperties _initPropsGM107[] = {
{ OP_SUSTP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
{ OP_SUREDB, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
{ OP_SUREDP, 0x0, 0x0, 0x0, 0x0, 0x0, 0x4 },
+ { OP_XMAD,0x0, 0x0, 0x0, 0x0, 0x6, 0x2 },
};
void TargetNVC0::initProps(const struct opProperties *props, int size)
--
2.14.4
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[Mesa-dev] [PATCH v4 0/4] nv50/ir: Improve Performance of Integer Multiplication
Changes in v4: - remove uint16_t(...) in nv50_ir.h - change XMAD immediate size from signed 20 bit to unsigned 16 bit - rework the 4th patch Changes in v3: - stylistic changes - simplify createMulMethod2() - update shader-db statistics - use util_bitcount64 and util_next_power_of_two64 instead of reimplementing them Changes in v2: - rebase - bring back constant folding for multiplication by power-of-twos for nv50 - remove TODO in nv50_ir_target_gm107.cpp - document XMAD's flags - change how XMAD's per-operand flags are represented - move util/bitscan.h stuff into a new patch - stylistic changes This series improve the performance of integer multiplication by removing much usage of the very slow IMAD and IMUL on Maxwell+ and improving multiplication by immediates on Fermi+. The first and second patch add support for the XMAD instruction in codegen The third patch replaces most IMADs and IMULs with a sequence of XMADs on Maxwell+. This is far faster but increases the total instructions in the shader-db by 0.90%, gpr count by 0.10% and local memory by 0.46%. The next patch significantly lowers this number. It replaces many multiplications by immediates with instructions that should be as fast or faster than the generic approach. They are also typically smaller and less register heavy, so they decrease the total instruction count by -0.56% and bring the gpr count and local memory back to normal. This series gives about a ~50% speedup in fragment-heavy scenaries with Dolphin 5.0 on my GTX 1060. All timings were made with interesting looking fifos from Dolphin's bugtracker: Wind Waker: 18 FPS -> 26 FPS at 3x internal resolution Wind Waker: 8 FPS -> 11 FPS at 5x internal resolution Paper Mario?: 26 FPS -> 42 FPS at 5x internal resolution SpongeBob Movie: 19 FPS -> 30 FPS at 5x internal resolution Unigine Heaven and Unigine Valley seems to run the same at low quality with no anti-aliasing and no tessellation. SuperTuxKart and 0 A.D. also show no change. It's possible these patches may break something. Piglit shows no functionality regressions though they should probably be tested for improvements or breakage with actual applications. These patches can also be found on my github: https://github.com/pendingchaos/mesa/tree/nv-xmad-v4 The final changes in shader-db are as follows: total instructions in shared programs : 5768871 -> 5788434 (0.34%) total gprs used in shared programs: 669919 -> 669996 (0.01%) total shared used in shared programs : 548832 -> 548832 (0.00%) total local used in shared programs : 21068 -> 21068 (0.00%) local sharedgpr inst bytes helped 0 0 220 901 901 hurt 0 0 23420252025 Rhys Perry (4): nv50/ir: add preliminary support for OP_XMAD gm107/ir: add support for OP_XMAD on GM107+ nv50/ir: optimize imul/imad to xmads nv50/ir: further optimize multiplication by immediates src/gallium/drivers/nouveau/codegen/nv50_ir.h | 26 .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 65 + .../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 155 ++--- .../drivers/nouveau/codegen/nv50_ir_print.cpp | 19 +++ .../drivers/nouveau/codegen/nv50_ir_target.cpp | 7 +- .../nouveau/codegen/nv50_ir_target_gm107.cpp | 6 +- .../nouveau/codegen/nv50_ir_target_nv50.cpp| 1 + .../nouveau/codegen/nv50_ir_target_nvc0.cpp| 19 +++ 8 files changed, 277 insertions(+), 21 deletions(-) -- 2.14.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v4 1/4] nv50/ir: add preliminary support for OP_XMAD
v4: remove uint16_t(...)
v4: don't allow immediates outside [0,65535] in insnCanLoad()
Signed-off-by: Rhys Perry
Reviewed-by: Karol Herbst
---
src/gallium/drivers/nouveau/codegen/nv50_ir.h | 26 ++
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 18 +--
.../drivers/nouveau/codegen/nv50_ir_print.cpp | 19
.../drivers/nouveau/codegen/nv50_ir_target.cpp | 7 +++---
.../nouveau/codegen/nv50_ir_target_gm107.cpp | 1 +
.../nouveau/codegen/nv50_ir_target_nv50.cpp| 1 +
.../nouveau/codegen/nv50_ir_target_nvc0.cpp| 18 +++
7 files changed, 85 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 0b220cc48d..d5c9570a56 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -58,6 +58,9 @@ enum operation
OP_FMA,
OP_SAD, // abs(src0 - src1) + src2
OP_SHLADD,
+ // extended multiply-add (GM107+), does a lot of things.
+ // see envytools for detailed documentation
+ OP_XMAD,
OP_ABS,
OP_NEG,
OP_NOT,
@@ -256,6 +259,29 @@ enum operation
#define NV50_IR_SUBOP_MINMAX_MED 2
#define NV50_IR_SUBOP_MINMAX_HIGH 3
+// xmad(src0, src1, 0) << 16 + src2
+#define NV50_IR_SUBOP_XMAD_PSL (1 << 0)
+// (xmad(src0, src1, src2) & 0x) | (src1 << 16)
+#define NV50_IR_SUBOP_XMAD_MRG (1 << 1)
+// xmad(src0, src1, src2.lo)
+#define NV50_IR_SUBOP_XMAD_CLO (1 << 2)
+// xmad(src0, src1, src2.hi)
+#define NV50_IR_SUBOP_XMAD_CHI (2 << 2)
+// if both operands to the multiplication are non-zero, subtract 65536 for each
+// negative operand
+#define NV50_IR_SUBOP_XMAD_CSFU (3 << 2)
+// xmad(src0, src1, src2) + src1 << 16
+#define NV50_IR_SUBOP_XMAD_CBCC (4 << 2)
+#define NV50_IR_SUBOP_XMAD_CMODE_SHIFT 2
+#define NV50_IR_SUBOP_XMAD_CMODE_MASK (0x7 << NV50_IR_SUBOP_XMAD_CMODE_SHIFT)
+
+// use the high 16 bits instead of the low 16 bits for the multiplication.
+// if the instruction's sType is signed, sign extend the operand from 16 bits
+// to 32 before multiplication.
+#define NV50_IR_SUBOP_XMAD_H1_SHIFT 5
+#define NV50_IR_SUBOP_XMAD_H1(i) (1 << (NV50_IR_SUBOP_XMAD_H1_SHIFT + (i)))
+#define NV50_IR_SUBOP_XMAD_H1_MASK (0x3 << NV50_IR_SUBOP_XMAD_H1_SHIFT)
+
enum DataType
{
TYPE_NONE,
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 2f7cc206b8..5b4a98d25c 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -191,9 +191,17 @@ void
LoadPropagation::checkSwapSrc01(Instruction *insn)
{
const Target *targ = prog->getTarget();
- if (!targ->getOpInfo(insn).commutative)
- if (insn->op != OP_SET && insn->op != OP_SLCT && insn->op != OP_SUB)
+ if (!targ->getOpInfo(insn).commutative) {
+ if (insn->op != OP_SET && insn->op != OP_SLCT &&
+ insn->op != OP_SUB && insn->op != OP_XMAD)
return;
+ // XMAD is only commutative if both the CBCC and MRG flags are not set.
+ if (insn->op == OP_XMAD &&
+ (insn->subOp & NV50_IR_SUBOP_XMAD_CMODE_MASK) ==
NV50_IR_SUBOP_XMAD_CBCC)
+ return;
+ if (insn->op == OP_XMAD && (insn->subOp & NV50_IR_SUBOP_XMAD_MRG))
+ return;
+ }
if (insn->src(1).getFile() != FILE_GPR)
return;
// This is the special OP_SET used for alphatesting, we can't reverse its
@@ -236,6 +244,12 @@ LoadPropagation::checkSwapSrc01(Instruction *insn)
if (insn->op == OP_SUB) {
insn->src(0).mod = insn->src(0).mod ^ Modifier(NV50_IR_MOD_NEG);
insn->src(1).mod = insn->src(1).mod ^ Modifier(NV50_IR_MOD_NEG);
+ } else
+ if (insn->op == OP_XMAD) {
+ // swap h1 flags
+ uint16_t h1 = (insn->subOp >> 1 & NV50_IR_SUBOP_XMAD_H1(0)) |
+(insn->subOp << 1 & NV50_IR_SUBOP_XMAD_H1(1));
+ insn->subOp = (insn->subOp & ~NV50_IR_SUBOP_XMAD_H1_MASK) | h1;
}
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index ee3506fbae..7eab8b8d70 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -86,6 +86,7 @@ const char *operationStr[OP_LAST + 1] =
"fma",
"sad",
"shladd",
+ "xmad",
"abs",
"neg",
"not",
@@ -240,6 +241,11 @@ static const char *barOpStr[] =
"sync", "arrive", "red and", "red or", "red popc"
};
+static const char *xmadOpCModeStr[] =
+{
+ "clo", "chi", "csfu", "cbcc"
+};
+
static const char *DataTypeStr[] =
{
"-",
@@ -625,6 +631,19 @@ void Instruction::print() const
if (subOp < ARRAY_SIZE(barOpStr))
PRINT("%s ", barOpStr[subOp]);
break;
+ case OP_XMAD: {
+ if (subOp & NV50_IR_SUBOP_XMAD_PSL)
+PRINT("psl ");
+ if
[Mesa-dev] [PATCH v4 3/4] nv50/ir: optimize imul/imad to xmads
This hits the shader-db numbers a good bit, though a few xmads is way
faster than an imul or imad and the cost is mitigated by the next commit,
which optimizes many multiplications by immediates into shorter and less
register heavy instructions than the xmads.
total instructions in shared programs : 5768871 -> 5820882 (0.90%)
total gprs used in shared programs: 669919 -> 670595 (0.10%)
total shared used in shared programs : 548832 -> 548832 (0.00%)
total local used in shared programs : 21068 -> 21164 (0.46%)
local sharedgpr inst bytes
helped 0 0 38 0 0
hurt 1 0 36530763076
Signed-off-by: Rhys Perry
Reviewed-by: Karol Herbst
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 56 ++
.../nouveau/codegen/nv50_ir_target_gm107.cpp | 1 -
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 5b4a98d25c..dc7bf24ba2 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -2301,13 +2301,18 @@ AlgebraicOpt::visit(BasicBlock *bb)
//
=
// ADD(SHL(a, b), c) -> SHLADD(a, b, c)
+// MUL(a, b) -> a few XMADs
+// MAD/FMA(a, b, c) -> a few XMADs
class LateAlgebraicOpt : public Pass
{
private:
virtual bool visit(Instruction *);
void handleADD(Instruction *);
+ void handleMULMAD(Instruction *);
bool tryADDToSHLADD(Instruction *);
+
+ BuildUtil bld;
};
void
@@ -2368,6 +2373,52 @@ LateAlgebraicOpt::tryADDToSHLADD(Instruction *add)
return true;
}
+// MUL(a, b) -> a few XMADs
+// MAD/FMA(a, b, c) -> a few XMADs
+void
+LateAlgebraicOpt::handleMULMAD(Instruction *i)
+{
+ // TODO: handle NV50_IR_SUBOP_MUL_HIGH
+ if (!prog->getTarget()->isOpSupported(OP_XMAD, TYPE_U32))
+ return;
+ if (isFloatType(i->dType) || typeSizeof(i->dType) != 4)
+ return;
+ if (i->subOp || i->usesFlags() || i->flagsDef >= 0)
+ return;
+
+ assert(!i->src(0).mod);
+ assert(!i->src(1).mod);
+ assert(i->op == OP_MUL ? 1 : !i->src(2).mod);
+
+ bld.setPosition(i, false);
+
+ Value *a = i->getSrc(0);
+ Value *b = i->getSrc(1);
+ Value *c = i->op == OP_MUL ? bld.mkImm(0) : i->getSrc(2);
+
+ Value *tmp0 = bld.getSSA();
+ Value *tmp1 = bld.getSSA();
+
+ Instruction *insn = bld.mkOp3(OP_XMAD, TYPE_U32, tmp0, b, a, c);
+ insn->setPredicate(i->cc, i->getPredicate());
+
+ insn = bld.mkOp3(OP_XMAD, TYPE_U32, tmp1, b, a, bld.mkImm(0));
+ insn->setPredicate(i->cc, i->getPredicate());
+ insn->subOp = NV50_IR_SUBOP_XMAD_MRG | NV50_IR_SUBOP_XMAD_H1(1);
+
+ Value *pred = i->getPredicate();
+ i->setPredicate(i->cc, NULL);
+
+ i->op = OP_XMAD;
+ i->setSrc(0, b);
+ i->setSrc(1, tmp1);
+ i->setSrc(2, tmp0);
+ i->subOp = NV50_IR_SUBOP_XMAD_PSL | NV50_IR_SUBOP_XMAD_CBCC;
+ i->subOp |= NV50_IR_SUBOP_XMAD_H1(0) | NV50_IR_SUBOP_XMAD_H1(1);
+
+ i->setPredicate(i->cc, pred);
+}
+
bool
LateAlgebraicOpt::visit(Instruction *i)
{
@@ -2375,6 +2426,11 @@ LateAlgebraicOpt::visit(Instruction *i)
case OP_ADD:
handleADD(i);
break;
+ case OP_MUL:
+ case OP_MAD:
+ case OP_FMA:
+ handleMULMAD(i);
+ break;
default:
break;
}
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
index de07ad1de8..2e2e40770e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_gm107.cpp
@@ -170,7 +170,6 @@ TargetGM107::isBarrierRequired(const Instruction *insn)
const
}
break;
case OPCLASS_ARITH:
- // TODO: IMUL/IMAD require barriers too, use of XMAD instead!
if ((insn->op == OP_MUL || insn->op == OP_MAD) &&
!isFloatType(insn->dType))
return true;
--
2.14.4
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[Mesa-dev] [PATCH v4 4/4] nv50/ir: further optimize multiplication by immediates
Strongly mitigates the harm from the previous commit, which made many
integer multiplications much more heavy on the register and instruction
count.
total instructions in shared programs : 5820882 -> 5788434 (-0.56%)
total gprs used in shared programs: 670595 -> 669996 (-0.09%)
total shared used in shared programs : 548832 -> 548832 (0.00%)
total local used in shared programs : 21164 -> 21068 (-0.45%)
local sharedgpr inst bytes
helped 1 0 38825002500
hurt 0 0 94 11 11
v4: rework createMul() (has a side-effect that mad/fma is optimized to
shl+add on nv50)
Signed-off-by: Rhys Perry
---
.../drivers/nouveau/codegen/nv50_ir_peephole.cpp | 81 ++
1 file changed, 66 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index dc7bf24ba2..d7eb6b503e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -379,6 +379,8 @@ private:
CmpInstruction *findOriginForTestWithZero(Value *);
+ bool createMul(Value *def, Value *a, int32_t b, Value *c);
+
unsigned int foldCount;
BuildUtil bld;
@@ -953,10 +955,65 @@ ConstantFolding::opnd3(Instruction *i, ImmediateValue
)
}
}
+bool
+ConstantFolding::createMul(Value *def, Value *a, int32_t b, Value *c)
+{
+ const Target *target = prog->getTarget();
+ int64_t absB = llabs(b);
+
+ //a * (2^shl) -> a << shl
+ if (b >= 0 && util_is_power_of_two_or_zero64(b)) {
+ int shl = util_logbase2_64(b);
+
+ if (c && target->isOpSupported(OP_SHLADD, TYPE_U32))
+ return bld.mkOp3(OP_SHLADD, TYPE_U32, def, a, bld.mkImm(shl), c);
+
+ Value *res = c ? bld.getSSA() : def;
+ bld.mkOp2(OP_SHL, TYPE_U32, res, a, bld.mkImm(shl));
+ if (c)
+ bld.mkOp2(OP_ADD, TYPE_U32, def, res, c);
+
+ return true;
+ }
+
+ //a * (2^shl + 1) -> a << shl + a
+ //a * -(2^shl + 1) -> -a << shl + a
+ //a * (2^shl - 1) -> a << shl - a
+ //a * -(2^shl - 1) -> -a << shl - a
+ if ((util_is_power_of_two_or_zero64(absB - 1) ||
+util_is_power_of_two_or_zero64(absB + 1)) &&
+ target->isOpSupported(OP_SHLADD, TYPE_U32)) {
+ bool subA = util_is_power_of_two_or_zero64(absB + 1);
+ int shl = subA ? util_logbase2_64(absB + 1) : util_logbase2_64(absB - 1);
+
+ Value *res = c ? bld.getSSA() : def;
+ Instruction *insn = bld.mkOp3(OP_SHLADD, TYPE_U32, res, a,
bld.mkImm(shl), a);
+ if (b < 0)
+ insn->src(0).mod = Modifier(NV50_IR_MOD_NEG);
+ if (subA)
+ insn->src(2).mod = Modifier(NV50_IR_MOD_NEG);
+
+ if (c)
+ bld.mkOp2(OP_ADD, TYPE_U32, def, res, c);
+
+ return true;
+ }
+
+ if (b >= 0 && b <= 0x && target->isOpSupported(OP_XMAD, TYPE_U32)) {
+ Value *tmp = bld.mkOp3v(OP_XMAD, TYPE_U32, bld.getSSA(),
+ a, bld.mkImm(b), c ? c : bld.mkImm(0));
+ bld.mkOp3(OP_XMAD, TYPE_U32, def, a, bld.mkImm(b), tmp)->subOp =
+ NV50_IR_SUBOP_XMAD_PSL | NV50_IR_SUBOP_XMAD_H1(0);
+
+ return true;
+ }
+
+ return false;
+}
+
void
ConstantFolding::opnd(Instruction *i, ImmediateValue , int s)
{
- const Target *target = prog->getTarget();
const int t = !s;
const operation op = i->op;
Instruction *newi = i;
@@ -1040,13 +1097,10 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
, int s)
i->setSrc(s, i->getSrc(t));
i->src(s).mod = i->src(t).mod;
} else
- if (!isFloatType(i->sType) && !imm0.isNegative() && imm0.isPow2()) {
- i->op = OP_SHL;
- imm0.applyLog2();
- i->setSrc(0, i->getSrc(t));
- i->src(0).mod = i->src(t).mod;
- i->setSrc(1, new_ImmediateValue(prog, imm0.reg.data.u32));
- i->src(1).mod = 0;
+ if (!isFloatType(i->dType) && !i->src(t).mod) {
+ bld.setPosition(i, false);
+ if (createMul(i->getDef(0), i->getSrc(t), imm0.reg.data.s32, NULL))
+delete_Instruction(prog, i);
} else
if (i->postFactor && i->sType == TYPE_F32) {
/* Can't emit a postfactor with an immediate, have to fold it in */
@@ -1079,13 +1133,10 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue
, int s)
i->setSrc(2, NULL);
i->op = OP_ADD;
} else
- if (s == 1 && !imm0.isNegative() && imm0.isPow2() &&
- !isFloatType(i->dType) &&
- target->isOpSupported(OP_SHLADD, i->dType) &&
- !i->subOp) {
- i->op = OP_SHLADD;
- imm0.applyLog2();
- i->setSrc(1, new_ImmediateValue(prog, imm0.reg.data.u32));
+ if (!isFloatType(i->dType) && !i->subOp && !i->src(t).mod &&
!i->src(2).mod) {
+ bld.setPosition(i, false);
+ if (createMul(i->getDef(0), i->getSrc(t),
[Mesa-dev] [Bug 107509] corrupted Box in top Right corner in some games
https://bugs.freedesktop.org/show_bug.cgi?id=107509 Michel Dänzer changed: What|Removed |Added Attachment #140998|text/x-log |text/plain mime type|| -- You are receiving this mail because: You are the QA Contact for the bug. You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: Fix missing Android platform define.
Quoting Bas Nieuwenhuizen (2018-08-09 17:27:46) > CC: > --- > src/amd/vulkan/Android.mk | 2 ++ > src/amd/vulkan/Makefile.am | 2 +- > 2 files changed, 3 insertions(+), 1 deletion(-) > > diff --git a/src/amd/vulkan/Android.mk b/src/amd/vulkan/Android.mk > index cee3744f40b..51b03561fa7 100644 > --- a/src/amd/vulkan/Android.mk > +++ b/src/amd/vulkan/Android.mk > @@ -62,6 +62,7 @@ LOCAL_SRC_FILES := \ > $(VULKAN_FILES) > > LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU # instructs LLVM to declare > LLVMInitializeAMDGPU* functions > +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR > > $(call mesa-build-with-llvm) > > @@ -140,6 +141,7 @@ LOCAL_SRC_FILES := \ > $(VULKAN_ANDROID_FILES) > > LOCAL_CFLAGS += -DFORCE_BUILD_AMDGPU # instructs LLVM to declare > LLVMInitializeAMDGPU* functions > +LOCAL_CFLAGS += -DVK_USE_PLATFORM_ANDROID_KHR > > $(call mesa-build-with-llvm) > > diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am > index e7ccc58a28e..e28f032cbee 100644 > --- a/src/amd/vulkan/Makefile.am > +++ b/src/amd/vulkan/Makefile.am > @@ -124,7 +124,7 @@ VULKAN_LIB_DEPS += \ > endif > > if HAVE_PLATFORM_ANDROID > -AM_CPPFLAGS += $(ANDROID_CPPFLAGS) > +AM_CPPFLAGS += $(ANDROID_CPPFLAGS) -DVK_USE_PLATFORM_ANDROID_KHR > AM_CFLAGS += $(ANDROID_CFLAGS) > VULKAN_LIB_DEPS += $(ANDROID_LIBS) > VULKAN_SOURCES += $(VULKAN_ANDROID_FILES) > -- > 2.18.0 > Hi Bas, I went ahead and pulled this into the staging/18.1 branch, we don't have android.mk support for radv in 18.1, so I only pulled in the autotools part. Please let me know if you're happy with that or not. Dylan signature.asc Description: signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: fix memory leaks in radv_load_meta_pipeline()
Reported by Coverity.
Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index ccdcb9ceb0..b8d0a7cfc7 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -263,6 +263,7 @@ radv_load_meta_pipeline(struct radv_device *device)
char path[PATH_MAX + 1];
struct stat st;
void *data = NULL;
+ bool ret = false;
if (!radv_builtin_cache_path(path))
return false;
@@ -278,11 +279,11 @@ radv_load_meta_pipeline(struct radv_device *device)
if(read(fd, data, st.st_size) == -1)
goto fail;
- return radv_pipeline_cache_load(>meta_state.cache, data,
st.st_size);
+ ret = radv_pipeline_cache_load(>meta_state.cache, data,
st.st_size);
fail:
free(data);
close(fd);
- return false;
+ return ret;
}
static void
--
2.18.0
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Re: [Mesa-dev] [PATCH] radv: fix memory leaks in radv_load_meta_pipeline()
Reviewed-by: Bas Nieuwenhuizen
On Wed, Aug 15, 2018 at 3:28 PM, Samuel Pitoiset
wrote:
> Reported by Coverity.
>
> Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.")
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_meta.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
> index ccdcb9ceb0..b8d0a7cfc7 100644
> --- a/src/amd/vulkan/radv_meta.c
> +++ b/src/amd/vulkan/radv_meta.c
> @@ -263,6 +263,7 @@ radv_load_meta_pipeline(struct radv_device *device)
> char path[PATH_MAX + 1];
> struct stat st;
> void *data = NULL;
> + bool ret = false;
>
> if (!radv_builtin_cache_path(path))
> return false;
> @@ -278,11 +279,11 @@ radv_load_meta_pipeline(struct radv_device *device)
> if(read(fd, data, st.st_size) == -1)
> goto fail;
>
> - return radv_pipeline_cache_load(>meta_state.cache, data,
> st.st_size);
> + ret = radv_pipeline_cache_load(>meta_state.cache, data,
> st.st_size);
> fail:
> free(data);
> close(fd);
> - return false;
> + return ret;
> }
>
> static void
> --
> 2.18.0
>
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[Mesa-dev] [PATCH v1] i965/bo/perf: 0-sized-bo allocation log
Added debug-log in case of bo-allocation with 0 size.
Potentially we may not need to allocate such buffers and each
case could be analyzed to improve behaviour.
Signed-off-by: Sergii Romantsov
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..726b266 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -514,6 +514,9 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
* be idle before we can memset. Just disallow that combination.
*/
assert(!(busy && zeroed));
+ if (!size && unlikely(INTEL_DEBUG & DEBUG_PERF))
+ dbg_printf("performance: allocation of 0-sized BO: %s\n", name);
+
/* Round the allocated size up to a power of two number of pages. */
bucket = bucket_for_size(bufmgr, size);
--
2.7.4
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[Mesa-dev] [Bug 107460] radv: OpControlBarrier does not always work correctly (bisected)
https://bugs.freedesktop.org/show_bug.cgi?id=107460 Samuel Pitoiset changed: What|Removed |Added Resolution|--- |FIXED Status|NEW |RESOLVED --- Comment #4 from Samuel Pitoiset --- Should be fixed with https://cgit.freedesktop.org/mesa/mesa/commit/?id=71d5b2fbf83061a1319141d26942771e8c75ff2b -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.
On August 15, 2018 09:28:36 Bas Nieuwenhuizen wrote:
On Wed, Aug 15, 2018 at 11:49 AM, Jason Ekstrand wrote:
On Tue, Aug 14, 2018 at 7:20 AM Samuel Pitoiset
wrote:
Reviewed-by: Samuel Pitoiset
On 7/23/18 4:24 PM, Bas Nieuwenhuizen wrote:
Behavior wrt firstInstance got changed, and a divisor of 0 has been
disallowed.
The new version of the ext got published in specification 1.1.81.
---
src/amd/vulkan/radv_extensions.py | 2 +-
src/amd/vulkan/radv_nir_to_llvm.c | 7 ---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index a5fbffac33b..d02042e5647 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -104,7 +104,7 @@ EXTENSIONS = [
Extension('VK_EXT_sampler_filter_minmax', 1,
'device->rad_info.chip_class >= CIK'),
Extension('VK_EXT_shader_viewport_index_layer', 1, True),
Extension('VK_EXT_shader_stencil_export', 1, True),
-Extension('VK_EXT_vertex_attribute_divisor', 1, True),
+Extension('VK_EXT_vertex_attribute_divisor', 2, True),
Extension('VK_AMD_draw_indirect_count', 1, True),
Extension('VK_AMD_gcn_shader',1, True),
Extension('VK_AMD_rasterization_order', 1,
'device->has_out_of_order_rast'),
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index c7d772fa652..d12ef09c9f3 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1984,8 +1984,7 @@ handle_vs_input_decl(struct radv_shader_context
*ctx,
uint32_t divisor =
ctx->options->key.vs.instance_rate_divisors[attrib_index];
if (divisor) {
- buffer_index =
LLVMBuildAdd(ctx->ac.builder, ctx->abi.instance_id,
-
ctx->abi.start_instance, "");
+ buffer_index = ctx->abi.instance_id;
if (divisor != 1) {
buffer_index =
LLVMBuildUDiv(ctx->ac.builder, buffer_index,
@@ -2000,8 +1999,10 @@ handle_vs_input_decl(struct radv_shader_context
*ctx,
MAX2(1,
ctx->shader_info->vs.vgpr_comp_cnt);
}
} else {
- buffer_index = ctx->ac.i32_0;
+ unreachable("Invalid vertex attribute
divisor of 0.");
You'll want to leave this alone. zero is coming back... Yeah, I know it's
annoying but I'm really trying to get this settled out as quickly as
possible. In the mean time, reports are that zero is useful for some DXVK
apps so it's best to just silently support it rather than breaking stuff.
Is the behavior of zero going to be the same as it was in version 1?
Almost. There base instance will be added in but instance is never
incremented beyond that. Look at Khronos MR 2771.
}
+
+ buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.start_instance, buffer_index, "");
} else
buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.vertex_id,
ctx->abi.base_vertex,
"");
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[Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active
From: Andrii Simiklit When the SVBI Payload Enable is false I guess the register R1.4 which contains the Maximum Streamed Vertex Buffer Index is filled by zero and GS stops to write transform feedback when the transform feedback is not active. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107579 Signed-off-by: Andrii Simiklit --- src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index ea5ad55..0f82500 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -2806,7 +2806,7 @@ genX(upload_gs_state)(struct brw_context *brw) #if GEN_GEN < 7 gs.SOStatisticsEnable = true; if (gs_prog->info.has_transform_feedback_varyings) -gs.SVBIPayloadEnable = true; +gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx); /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled as it * was previously done for gen6. -- 2.7.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] Revert "intel/nir: Call nir_lower_io_to_scalar_early"
On Tue, Aug 14, 2018 at 7:25 PM Timothy Arceri wrote: > On 09/08/18 05:05, Jason Ekstrand wrote: > > Commit 4434591bf56a6b0 caused substantially more URB messages in > > geometry and tessellation shaders. Before we can really enable this > > sort of optimization, We either need some way of combining them back > > together into vectors or we need to do cross-stage vector element > > elimination without splitting everything into scalars. > > You should be calling: > > nir_compact_varyings() after remove_unused_varyings this should do most > of what you want. > Does that turn things back into vectors? The problem we're hitting is not that things aren't compacted, it's that we want to read/write whole vectors at a time as much as possible. Just reverting the patch isn't quite the proper solution because we want to be able to compact things and it would be nice if we could load two variables at a time if they're packed side-by-side in one vec4. However, it does solve the perf regression for now. --Jason ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: disable the auto-waitcnt-before-barrier LLVM option
On 8/15/18 3:33 PM, Bas Nieuwenhuizen wrote:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Aug 15, 2018 at 3:09 PM, Samuel Pitoiset
wrote:
This option allows us to remove additional s_waitcnt instructions
because s_barrier internally does s_waitcnt 0.
Though, apparently there is a problem with LDS accesses that
causes rendering issues with FFXV and DXVK. Disable this
optimization for now (RadeonSI still uses it).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
CC: 18.2
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_llvm_util.c | 3 ++-
src/amd/common/ac_llvm_util.h | 1 +
src/gallium/drivers/radeonsi/si_pipe.c | 1 +
3 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 10e1ca99d4..008a2cfa4e 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -149,7 +149,8 @@ static LLVMTargetMachineRef ac_create_target_machine(enum
radeon_family family,
char features[256];
const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ? "amdgcn-mesa-mesa3d"
: "amdgcn--";
LLVMTargetRef target = ac_get_llvm_target(triple);
- bool barrier_does_waitcnt = family != CHIP_VEGA20;
+ bool barrier_does_waitcnt = tm_options & AC_TM_AUTO_WAITCNT_BEFORE_BARRIER
&&
Can you please do parentheses around the and? I know they're not
strictly necessary but I'd like not to have to
think about precedence too much.
Will do before pushing.
+ family != CHIP_VEGA20;
snprintf(features, sizeof(features),
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index eaf5f21876..e252bed3bb 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -65,6 +65,7 @@ enum ac_target_machine_options {
AC_TM_CHECK_IR = (1 << 5),
AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
AC_TM_CREATE_LOW_OPT = (1 << 7),
+ AC_TM_AUTO_WAITCNT_BEFORE_BARRIER = (1 << 8),
};
enum ac_float_mode {
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 13fcf1f3ae..4327a3f749 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -115,6 +115,7 @@ static void si_init_compiler(struct si_screen *sscreen,
sscreen->info.chip_class <= VI;
enum ac_target_machine_options tm_options =
+ AC_TM_AUTO_WAITCNT_BEFORE_BARRIER |
(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
(sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
(sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK :
0) |
--
2.18.0
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Re: [Mesa-dev] [PATCH] radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS
On 8/15/18 3:34 PM, Bas Nieuwenhuizen wrote: On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset wrote: On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote: On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset wrote: The last parameter of radeon_set_sh_reg_seq() is the number of dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but it was initialized to 0. COMPUTE_RESOURCE_LIMITS is correctly set when generating compute pipelines, so we don't need to initialize it. Note that there we don't set WAVES_PER_SH. Is that intended? Yeah, I don't think that matters and it wasn't set before anyway. Reviewed-by: Bas Nieuwenhuizen Also a radeonsi patch? Why? The same wrong patch was applied to radeonsi initialization, no? No, RadeonSI looks good. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/si_cmd_buffer.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 2337036c67..2cfa7f4c2c 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -88,9 +88,7 @@ si_emit_compute(struct radv_physical_device *physical_device, radeon_emit(cs, 0); radeon_emit(cs, 0); - radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, - S_00B854_WAVES_PER_SH(0x3)); - radeon_emit(cs, 0); + radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */ radeon_emit(cs, S_00B858_SH0_CU_EN(0x) | S_00B858_SH1_CU_EN(0x)); radeon_emit(cs, S_00B85C_SH0_CU_EN(0x) | S_00B85C_SH1_CU_EN(0x)); -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITS
On Wed, Aug 15, 2018 at 2:13 PM, Samuel Pitoiset wrote: > > > On 8/14/18 9:15 PM, Bas Nieuwenhuizen wrote: >> >> On Tue, Aug 14, 2018 at 6:11 PM, Samuel Pitoiset >> wrote: >>> >>> The last parameter of radeon_set_sh_reg_seq() is the number of >>> dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but >>> it was initialized to 0. >>> >>> COMPUTE_RESOURCE_LIMITS is correctly set when generating >>> compute pipelines, so we don't need to initialize it. >> >> >> Note that there we don't set WAVES_PER_SH. Is that intended? > > > Yeah, I don't think that matters and it wasn't set before anyway. > >> >> Reviewed-by: Bas Nieuwenhuizen >> >> Also a radeonsi patch? > > > Why? The same wrong patch was applied to radeonsi initialization, no? > > >> >>> >>> Signed-off-by: Samuel Pitoiset >>> --- >>> src/amd/vulkan/si_cmd_buffer.c | 4 +--- >>> 1 file changed, 1 insertion(+), 3 deletions(-) >>> >>> diff --git a/src/amd/vulkan/si_cmd_buffer.c >>> b/src/amd/vulkan/si_cmd_buffer.c >>> index 2337036c67..2cfa7f4c2c 100644 >>> --- a/src/amd/vulkan/si_cmd_buffer.c >>> +++ b/src/amd/vulkan/si_cmd_buffer.c >>> @@ -88,9 +88,7 @@ si_emit_compute(struct radv_physical_device >>> *physical_device, >>> radeon_emit(cs, 0); >>> radeon_emit(cs, 0); >>> >>> - radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, >>> - S_00B854_WAVES_PER_SH(0x3)); >>> - radeon_emit(cs, 0); >>> + radeon_set_sh_reg_seq(cs, >>> R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); >>> /* R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0 / SE1 */ >>> radeon_emit(cs, S_00B858_SH0_CU_EN(0x) | >>> S_00B858_SH1_CU_EN(0x)); >>> radeon_emit(cs, S_00B85C_SH0_CU_EN(0x) | >>> S_00B85C_SH1_CU_EN(0x)); >>> -- >>> 2.18.0 >>> >>> ___ >>> mesa-dev mailing list >>> mesa-dev@lists.freedesktop.org >>> https://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: Revert divisor = 0 case for vertex attribute extension.
Reviewed-by: Samuel Pitoiset
On 8/15/18 4:30 PM, Bas Nieuwenhuizen wrote:
Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.
Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to version
2."
CC: 18.2
---
src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index bfd8b562e5c..8bf3ae0f150 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2006,7 +2006,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
MAX2(1,
ctx->shader_info->vs.vgpr_comp_cnt);
}
} else {
- unreachable("Invalid vertex attribute divisor of
0.");
+ buffer_index = ctx->ac.i32_0;
}
buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
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Re: [Mesa-dev] [PATCH v3 0/6] support config for third-party DRI driver load
> Pardon for the delay, Qiang Yu Series looks good and is > Reviewed-by: Emil Velikov > > The series has been on the list for a while, Michel seems happy with > it, so I'm inclined to merge this late today/early tomorrow. > Please keep an eye open for any bug reports - just a gut feeling. Thanks Emil, I will. Hope it's OK. Regards, Qiang ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v1] i965: Emitting 3DSTATE_SO_BUFFER of 0-size.
Hello,
that patch is according to remark:
>
> "Additionally, we probably ought to fix the callers to stop allocating 0
> size BOs.
> It looks like most of them come from the 3DSTATE_SO_BUFFER code,
> where one stream has valid transform feedback info, and the other
> 3 are empty. "
And seems additional one: https://patchwork.freedesktop.org/patch/244674/
On Wed, Aug 15, 2018 at 3:21 PM, Sergii Romantsov <
sergii.romant...@gmail.com> wrote:
> Avoided filling of whole structure and bo-allocation if
> size of surface is 0.
>
> Signed-off-by: Sergii Romantsov
> ---
> src/mesa/drivers/dri/i965/genX_state_upload.c | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
> b/src/mesa/drivers/dri/i965/genX_state_upload.c
> index ea5ad55..c051848 100644
> --- a/src/mesa/drivers/dri/i965/genX_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
> @@ -3787,19 +3787,20 @@ genX(upload_3dstate_so_buffers)(struct
> brw_context *brw)
> for (int i = 0; i < 4; i++) {
>struct intel_buffer_object *bufferobj =
> intel_buffer_object(xfb_obj->Buffers[i]);
> + uint32_t start = xfb_obj->Offset[i];
> + uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
> + uint32_t const size = end - start;
>
> - if (!bufferobj) {
> + if (!bufferobj || !size) {
> brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
> sob.SOBufferIndex = i;
> }
> continue;
>}
>
> - uint32_t start = xfb_obj->Offset[i];
>assert(start % 4 == 0);
> - uint32_t end = ALIGN(start + xfb_obj->Size[i], 4);
>struct brw_bo *bo =
> - intel_bufferobj_buffer(brw, bufferobj, start, end - start, true);
> + intel_bufferobj_buffer(brw, bufferobj, start, size, true);
>assert(end <= bo->size);
>
>brw_batch_emit(brw, GENX(3DSTATE_SO_BUFFER), sob) {
> --
> 2.7.4
>
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GlobalLogic Inc.
www.globallogic.com
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Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active
Hi all, This workaround just helps me to avoid the graphical corruption on SNB but I not sure is it good idea. Regards, Andrii. On Wed, Aug 15, 2018 at 6:20 PM, wrote: > From: Andrii Simiklit > > When the SVBI Payload Enable is false I guess the register R1.4 > which contains the Maximum Streamed Vertex Buffer Index is filled by zero > and GS stops to write transform feedback when the transform feedback > is not active. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107579 > Signed-off-by: Andrii Simiklit > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c > b/src/mesa/drivers/dri/i965/genX_state_upload.c > index ea5ad55..0f82500 100644 > --- a/src/mesa/drivers/dri/i965/genX_state_upload.c > +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c > @@ -2806,7 +2806,7 @@ genX(upload_gs_state)(struct brw_context *brw) > #if GEN_GEN < 7 > gs.SOStatisticsEnable = true; > if (gs_prog->info.has_transform_feedback_varyings) > -gs.SVBIPayloadEnable = true; > +gs.SVBIPayloadEnable = _mesa_is_xfb_active_and_unpaused(ctx); > > /* GEN6_GS_SPF_MODE and GEN6_GS_VECTOR_MASK_ENABLE are enabled > as it >* was previously done for gen6. > -- > 2.7.4 > > ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 107509] corrupted Box in top Right corner in some games
https://bugs.freedesktop.org/show_bug.cgi?id=107509 Michel Dänzer changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop |org |.org QA Contact|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop |org |.org Component|Other |Drivers/Gallium/radeonsi --- Comment #4 from Michel Dänzer --- Is it the same using the amdgpu kernel driver instead of radeon? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] radv: Possible demand compilation fix.
Seems that in a single case we use the renderpass before checking
the pipeline, so check the renderpass before we use it.
Fixes: fbcd1673144 "radv: Add on-demand compilation of built-in shaders."
---
src/amd/vulkan/radv_meta_resolve_fs.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 21a5922f5df..af4a6fe7a66 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -463,6 +463,14 @@ void radv_meta_resolve_fragment_image(struct
radv_cmd_buffer *cmd_buffer,
radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
region_count, regions);
+ if
(!device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout])
{
+ VkResult ret = create_resolve_pipeline(device, samples_log2,
radv_fs_key_format_exemplars[fs_key]);
+ if (ret != VK_SUCCESS) {
+ cmd_buffer->record_result = ret;
+ return;
+ }
+ }
+
rp =
device->meta_state.resolve_fragment.rc[samples_log2].render_pass[fs_key][dst_layout];
radv_meta_save(_state, cmd_buffer,
--
2.18.0
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[Mesa-dev] [PATCH] radv: Revert divisor = 0 case for vertex attribute extension.
Seems like DXVK depends on that and it might get reverted
upstream. Since apps are not supposed to use 0 in v2 anyway,
we should be safe implementing the old behavior there.
Fixes: 66e12451ac4 "radv: Update to new VK_EXT_vertex_attribute_divisor to
version 2."
CC: 18.2
---
src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index bfd8b562e5c..8bf3ae0f150 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2006,7 +2006,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
MAX2(1,
ctx->shader_info->vs.vgpr_comp_cnt);
}
} else {
- unreachable("Invalid vertex attribute divisor
of 0.");
+ buffer_index = ctx->ac.i32_0;
}
buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.start_instance, buffer_index, "");
--
2.18.0
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Re: [Mesa-dev] [PATCH v5 1/2] intel/ppgtt: memory address alignment
On 15/08/18 12:23, Sergii Romantsov wrote:
Kernel (for ppgtt) requires memory address to be
aligned to page size (4096).
-v2: added marking that also fixes initial commit 01058a552294.
-v3: numbers replaced by PAGE_SIZE; buffer-object size is aligned
instead of alignment of offsets (Chris Wilson).
-v4: changes related to PAGE_SIZE moved to separate commit
-v5: restored alignment to page-size for 0-size.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106997
Fixes: a363bb2cd0e2 (i965: Allocate VMA in userspace for full-PPGTT systems.)
Fixes: 01058a552294 (i965: Add virtual memory allocator infrastructure to
brw_bufmgr.)
Signed-off-by: Sergii Romantsov
CI seems happy this time :
Reviewed-by: Lionel Landwerlin
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 09d45e3..19e2d14 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -496,7 +496,6 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
uint32_t stride)
{
struct brw_bo *bo;
- unsigned int page_size = getpagesize();
int ret;
struct bo_cache_bucket *bucket;
bool alloc_from_cache;
@@ -522,12 +521,12 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
* allocation up.
*/
if (bucket == NULL) {
- bo_size = size;
- if (bo_size < page_size)
- bo_size = page_size;
+ unsigned int page_size = getpagesize();
+ bo_size = size == 0 ? page_size : ALIGN(size, page_size);
} else {
bo_size = bucket->size;
}
+ assert(bo_size);
mtx_lock(>lock);
/* Get a buffer out of the cache if available */
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[Mesa-dev] [PATCH v2 2/5] meson: use python3 module to find python3
This handy helper is nice for OSes that are not linux or BSD like (mac
and windows) as it knows how to find python3 in odd places.
---
meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 5dc9b45eb42..c8bac35659f 100644
--- a/meson.build
+++ b/meson.build
@@ -697,7 +697,7 @@ if with_platform_haiku
pre_args += '-DHAVE_HAIKU_PLATFORM'
endif
-prog_python = find_program('python3')
+prog_python = import('python3').find_python()
has_mako = run_command(prog_python, '-c', 'import mako; assert
mako.__version__ >= "0.8.0"')
if has_mako.returncode() != 0
error('Python (3.x) mako module >= 0.8.0 required to build mesa.')
--
2.18.0
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[Mesa-dev] [PATCH 1/3] freedreno: Fix warnings
From: "Kristian H. Kristensen"
Signed-off-by: Kristian H. Kristensen
---
src/gallium/drivers/freedreno/a5xx/fd5_compute.c | 2 +-
src/gallium/drivers/freedreno/freedreno_resource.c | 8
src/gallium/drivers/freedreno/ir3/ir3.h| 8 ++--
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c| 2 +-
src/gallium/drivers/freedreno/ir3/ir3_shader.h | 4 +---
5 files changed, 9 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
index 8e2c228e90..66ed7a4af5 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_compute.c
@@ -181,7 +181,7 @@ static void
fd5_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info)
{
struct fd5_compute_stateobj *so = ctx->compute;
- struct ir3_shader_key key = {0};
+ struct ir3_shader_key key = {};
struct ir3_shader_variant *v;
struct fd_ringbuffer *ring = ctx->batch->draw;
unsigned i, nglobal = 0;
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c
b/src/gallium/drivers/freedreno/freedreno_resource.c
index 3fbf50003e..f882cf5a8b 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -211,7 +211,7 @@ fd_try_shadow_resource(struct fd_context *ctx, struct
fd_resource *rsc,
mtx_unlock(>screen->lock);
- struct pipe_blit_info blit = {0};
+ struct pipe_blit_info blit = {};
blit.dst.resource = prsc;
blit.dst.format = prsc->format;
blit.src.resource = pshadow;
@@ -305,7 +305,7 @@ static void
fd_blit_from_staging(struct fd_context *ctx, struct fd_transfer *trans)
{
struct pipe_resource *dst = trans->base.resource;
- struct pipe_blit_info blit = {0};
+ struct pipe_blit_info blit = {};
blit.dst.resource = dst;
blit.dst.format = dst->format;
@@ -325,7 +325,7 @@ static void
fd_blit_to_staging(struct fd_context *ctx, struct fd_transfer *trans)
{
struct pipe_resource *src = trans->base.resource;
- struct pipe_blit_info blit = {0};
+ struct pipe_blit_info blit = {};
blit.src.resource = src;
blit.src.format = src->format;
@@ -372,7 +372,7 @@ flush_resource(struct fd_context *ctx, struct fd_resource
*rsc, unsigned usage)
fd_batch_reference(_batch, rsc->write_batch);
if (usage & PIPE_TRANSFER_WRITE) {
- struct fd_batch *batch, *batches[32] = {0};
+ struct fd_batch *batch, *batches[32] = {};
uint32_t batch_mask;
/* This is a bit awkward, probably a fd_batch_flush_locked()
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h
b/src/gallium/drivers/freedreno/ir3/ir3.h
index 8bac91660b..63215cefc9 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -445,14 +445,12 @@ struct ir3 {
#endif
};
-typedef struct nir_register nir_register;
-
struct ir3_array {
struct list_head node;
unsigned length;
unsigned id;
- nir_register *r;
+ struct nir_register *r;
/* To avoid array write's from getting DCE'd, keep track of the
* most recent write. Any array access depends on the most
@@ -470,13 +468,11 @@ struct ir3_array {
struct ir3_array * ir3_lookup_array(struct ir3 *ir, unsigned id);
-typedef struct nir_block nir_block;
-
struct ir3_block {
struct list_head node;
struct ir3 *shader;
- const nir_block *nblock;
+ const struct nir_block *nblock;
struct list_head instr_list; /* list of ir3_instruction */
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 23d5006352..b41c32d375 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -379,7 +379,7 @@ int main(int argc, char **argv)
while (n < argc) {
char *filename = argv[n];
- char *ext = rindex(filename, '.');
+ char *ext = strrchr(filename, '.');
if (strcmp(ext, ".tgsi") == 0) {
if (num_files != 0)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 507e89c473..288e9fa4e7 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -345,8 +345,6 @@ struct ir3_shader_variant {
struct ir3_shader *shader;
};
-typedef struct nir_shader nir_shader;
-
struct ir3_shader {
enum shader_t type;
@@ -359,7 +357,7 @@ struct ir3_shader {
struct ir3_compiler *compiler;
- nir_shader *nir;
+ struct nir_shader *nir;
struct pipe_stream_output_info stream_output;
struct ir3_shader_variant *variants;
--
[Mesa-dev] [PATCH v2 1/5] meson: Ensure that mako is >= 0.8.0
It's what autotools has required for a long time.
---
meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index 7436164946b..5dc9b45eb42 100644
--- a/meson.build
+++ b/meson.build
@@ -698,9 +698,9 @@ if with_platform_haiku
endif
prog_python = find_program('python3')
-has_mako = run_command(prog_python, '-c', 'import mako')
+has_mako = run_command(prog_python, '-c', 'import mako; assert
mako.__version__ >= "0.8.0"')
if has_mako.returncode() != 0
- error('Python (3.x) mako module required to build mesa.')
+ error('Python (3.x) mako module >= 0.8.0 required to build mesa.')
endif
if cc.get_id() == 'gcc' and cc.version().version_compare('< 4.4.6')
--
2.18.0
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[Mesa-dev] [PATCH v2 5/5] scons: Check for mako 0.8.0
v2: - Use distutils to do the version checking
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107565
---
scons/gallium.py | 13 +
1 file changed, 13 insertions(+)
diff --git a/scons/gallium.py b/scons/gallium.py
index 659da72c1c3..aa7201a9715 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -29,6 +29,7 @@ Frontend-tool for Gallium3D architecture.
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
+from __future__ import print_function
import distutils.version
import os
@@ -677,6 +678,18 @@ def generate(env):
env.PkgCheckModules('XF86VIDMODE', ['xxf86vm'])
env.PkgCheckModules('DRM', ['libdrm >= 2.4.75'])
+if not os.path.exists("src/util/format_srgb.c"):
+print("Checking for Python Mako module (>= 0.8.0)... ", end='')
+try:
+import mako
+except ImportError:
+print("no")
+exit(1)
+if distutils.version.StrictVersion(mako.__version__) <
distutils.version.StrictVersion('0.8.0'):
+print("no")
+exit(1)
+print("yes")
+
if env['x11']:
env.Append(CPPPATH = env['X11_CPPPATH'])
--
2.18.0
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[Mesa-dev] [PATCH v2 3/5] configure: Enforce python 2.7.x
We don't want to support older versions of python 2 anymore, and we
don't support python 3.x in autotools currently.
---
configure.ac | 7 +++
1 file changed, 7 insertions(+)
diff --git a/configure.ac b/configure.ac
index c2155a541b0..78672734d06 100644
--- a/configure.ac
+++ b/configure.ac
@@ -162,6 +162,13 @@ if test -z "$PYTHON2"; then
AC_MSG_ERROR([Python not found - unable to generate sources])
fi
else
+PYTHON_VERSION=`$PYTHON2 --version |& awk '{print $2}'` dnl Yes, python2
prints it's version to stderr
+PYTHON_MAJOR=`echo $PYTHON_VERSION | cut -d . -f 1`
+PYTHON_MINOR=`echo $PYTHON_VERSION | cut -d . -f 2`
+if test $PYTHON_MAJOR -ne 2 -o $PYTHON_MINOR -ne 7; then
+AC_MSG_ERROR([Python version 2.7.x not found - unable to generate
sources])
+fi
+
if test "x$acv_mako_found" = xno; then
if test ! -f "$srcdir/src/mesa/main/format_unpack.c"; then
AC_MSG_ERROR([Python mako module v$PYTHON_MAKO_REQUIRED or higher
not found])
--
2.18.0
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[Mesa-dev] [PATCH v2 4/5] scons: Require python 2.7
less than 2.7 is not supported. v2: - Remove check for python >= 2.0, since we've already enforced 2.7 --- SConstruct | 1 + scons/gallium.py | 4 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/SConstruct b/SConstruct index 6e034fb968f..51dc301a9a8 100644 --- a/SConstruct +++ b/SConstruct @@ -31,6 +31,7 @@ import common # Minimal scons version EnsureSConsVersion(2, 4) +EnsurePythonVersion(2, 7) ### diff --git a/scons/gallium.py b/scons/gallium.py index 92a762a0c1e..659da72c1c3 100755 --- a/scons/gallium.py +++ b/scons/gallium.py @@ -221,10 +221,6 @@ def generate(env): env['suncc'] = env['platform'] == 'sunos' and os.path.basename(env['CC']) == 'cc' env['icc'] = 'icc' == os.path.basename(env['CC']) -if env['msvc'] and env['toolchain'] == 'default' and env['machine'] == 'x86_64': -# MSVC x64 support is broken in earlier versions of scons -env.EnsurePythonVersion(2, 0) - # shortcuts machine = env['machine'] platform = env['platform'] -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radv: disable the auto-waitcnt-before-barrier LLVM option
Reviewed-by: Bas Nieuwenhuizen
On Wed, Aug 15, 2018 at 3:09 PM, Samuel Pitoiset
wrote:
> This option allows us to remove additional s_waitcnt instructions
> because s_barrier internally does s_waitcnt 0.
>
> Though, apparently there is a problem with LDS accesses that
> causes rendering issues with FFXV and DXVK. Disable this
> optimization for now (RadeonSI still uses it).
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107460
> CC: 18.2
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/common/ac_llvm_util.c | 3 ++-
> src/amd/common/ac_llvm_util.h | 1 +
> src/gallium/drivers/radeonsi/si_pipe.c | 1 +
> 3 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
> index 10e1ca99d4..008a2cfa4e 100644
> --- a/src/amd/common/ac_llvm_util.c
> +++ b/src/amd/common/ac_llvm_util.c
> @@ -149,7 +149,8 @@ static LLVMTargetMachineRef ac_create_target_machine(enum
> radeon_family family,
> char features[256];
> const char *triple = (tm_options & AC_TM_SUPPORTS_SPILL) ?
> "amdgcn-mesa-mesa3d" : "amdgcn--";
> LLVMTargetRef target = ac_get_llvm_target(triple);
> - bool barrier_does_waitcnt = family != CHIP_VEGA20;
> + bool barrier_does_waitcnt = tm_options &
> AC_TM_AUTO_WAITCNT_BEFORE_BARRIER &&
Can you please do parentheses around the and? I know they're not
strictly necessary but I'd like not to have to
think about precedence too much.
> + family != CHIP_VEGA20;
>
> snprintf(features, sizeof(features),
>
> "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s%s",
> diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
> index eaf5f21876..e252bed3bb 100644
> --- a/src/amd/common/ac_llvm_util.h
> +++ b/src/amd/common/ac_llvm_util.h
> @@ -65,6 +65,7 @@ enum ac_target_machine_options {
> AC_TM_CHECK_IR = (1 << 5),
> AC_TM_ENABLE_GLOBAL_ISEL = (1 << 6),
> AC_TM_CREATE_LOW_OPT = (1 << 7),
> + AC_TM_AUTO_WAITCNT_BEFORE_BARRIER = (1 << 8),
> };
>
> enum ac_float_mode {
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 13fcf1f3ae..4327a3f749 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -115,6 +115,7 @@ static void si_init_compiler(struct si_screen *sscreen,
>sscreen->info.chip_class <= VI;
>
> enum ac_target_machine_options tm_options =
> + AC_TM_AUTO_WAITCNT_BEFORE_BARRIER |
> (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
> (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL
> : 0) |
> (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK
> : 0) |
> --
> 2.18.0
>
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [Bug 107457] [Tracker] Mesa 18.2 release tracker
https://bugs.freedesktop.org/show_bug.cgi?id=107457 Mark Janes changed: What|Removed |Added Depends on||107359 Referenced Bugs: https://bugs.freedesktop.org/show_bug.cgi?id=107359 [Bug 107359] [Regression] [bisected] [OpenGL CTS] [SKL,BDW] KHR-GL46.texture_barrier*-texels, GTF-GL46.gtf21.GL2FixedTests.buffer_corners.buffer_corners, and GTF-GL46.gtf21.GL2FixedTests.stencil_plane_corners.stencil_plane_corners fail with some configuration -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH v2] anv: add VK_EXT_sampler_filter_minmax support
On August 15, 2018 14:43:08 Lionel Landwerlin
wrote:
Hey there,
Just a few nits below.
Thanks!
-
Lionel
On 15/08/18 18:42, Yunchao He wrote:
This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.
I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*
v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).
---
src/intel/vulkan/anv_device.c | 8
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_formats.c | 6 ++
src/intel/vulkan/genX_state.c | 27 +++
4 files changed, 42 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
break;
}
+ case
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen
>= 9;
I guess you can turn pdevice->info.gen >= 9 into true since the
extension is only available on Gen9.
I think I'd rather keep it. That way, if someone blindly queries, they get
there right value. Also, if it ever becomes core (not that likely), we
already do the right thing on the query.
+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+ }
+
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen
>= 9'),
Extension('VK_EXT_vertex_attribute_divisor', 2, True),
Extension('VK_EXT_post_depth_coverage', 1, 'device->info.gen
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1,
'device->info.gen >= 9'),
]
class VkVersion:
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info
*devinfo,
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
+ if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT |
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info
*devinfo,
if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
+ if (devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..e095cb4cc0 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
[VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
};
+#if GEN_GEN >= 9
+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+ [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+ [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
+ [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
+};
+#endif
+
VkResult genX(CreateSampler)(
VkDevice_device,
const VkSamplerCreateInfo* pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
uint32_t border_color_offset = device->border_colors.offset +
pCreateInfo->borderColor * 64;
+#if GEN_GEN >= 9
+ unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
vk_foreach_struct(ext, pCreateInfo->pNext) {
switch (ext->sType) {
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,16 @@ VkResult genX(CreateSampler)(
sampler->conversion = conversion;
break;
}
+#if GEN_GEN >= 9
+ case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+ struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+ (struct VkSamplerReductionModeCreateInfoEXT *) ext;
You can drop that if below. If you've
[Mesa-dev] [Bug 103078] MATLAB broken with mesa software rendering
https://bugs.freedesktop.org/show_bug.cgi?id=103078 Dylan Baker changed: What|Removed |Added Resolution|--- |NOTOURBUG Status|NEW |RESOLVED --- Comment #15 from Dylan Baker --- It sounds like this was actually a jogl bug, thus not our bug. Please re-open if I've misunderstood. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 83785] Shader branches excluded by uniform values are not optimized out
https://bugs.freedesktop.org/show_bug.cgi?id=83785 Dylan Baker changed: What|Removed |Added Status|NEW |RESOLVED Resolution|--- |NOTABUG --- Comment #4 from Dylan Baker --- This doesn't seem like a real bug, just a lack of optimization. I'm gong to close this. Feel free to re-open if you disagree. -- You are receiving this mail because: You are the assignee for the bug.___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH v3] anv: add VK_EXT_sampler_filter_minmax support
This extension can be supported on SKL+. With this patch,
all corresponding tests (6K+) in CTS can pass. No test fails.
I verified CTS with the command below:
deqp-vk --deqp-case=dEQP-VK.pipeline.sampler.view_type.*reduce*
v2: 1) support all depth formats, not depth-only formats, 2) fix
a wrong indention (Jason).
v3: fix a few nits (Lionel).
---
src/intel/vulkan/anv_device.c | 8
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_formats.c | 6 ++
src/intel/vulkan/genX_state.c | 26 ++
4 files changed, 41 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 04fd6a829e..e45ba4b3af 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1116,6 +1116,14 @@ void anv_GetPhysicalDeviceProperties2(
break;
}
+ case
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
+ VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
+(VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
+ properties->filterMinmaxImageComponentMapping = pdevice->info.gen >=
9;
+ properties->filterMinmaxSingleComponentFormats = true;
+ break;
+ }
+
case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
VkPhysicalDeviceSubgroupProperties *properties = (void *)ext;
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index ea837744b4..e165bd371d 100644
--- a/src/intel/vulkan/anv_extensions.py
+++ b/src/intel/vulkan/anv_extensions.py
@@ -125,6 +125,7 @@ EXTENSIONS = [
Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen
>= 9'),
Extension('VK_EXT_vertex_attribute_divisor', 2, True),
Extension('VK_EXT_post_depth_coverage', 1, 'device->info.gen
>= 9'),
+Extension('VK_EXT_sampler_filter_minmax', 1, 'device->info.gen
>= 9'),
]
class VkVersion:
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 815b320a82..33faf7cc37 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -489,6 +489,9 @@ get_image_format_features(const struct gen_device_info
*devinfo,
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT || devinfo->gen >= 8)
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
+ if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
flags |= VK_FORMAT_FEATURE_BLIT_SRC_BIT |
VK_FORMAT_FEATURE_BLIT_DST_BIT |
VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
@@ -521,6 +524,9 @@ get_image_format_features(const struct gen_device_info
*devinfo,
if (isl_format_supports_sampling(devinfo, plane_format.isl_format)) {
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_BIT;
+ if (devinfo->gen >= 9)
+ flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_MINMAX_BIT_EXT;
+
if (isl_format_supports_filtering(devinfo, plane_format.isl_format))
flags |= VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index b1014d9e79..f075272acd 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -245,6 +245,14 @@ static const uint32_t vk_to_gen_shadow_compare_op[] = {
[VK_COMPARE_OP_ALWAYS] = PREFILTEROPNEVER,
};
+#if GEN_GEN >= 9
+static const uint32_t vk_to_gen_sampler_reduction_mode[] = {
+ [VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT] = STD_FILTER,
+ [VK_SAMPLER_REDUCTION_MODE_MIN_EXT] = MINIMUM,
+ [VK_SAMPLER_REDUCTION_MODE_MAX_EXT] = MAXIMUM,
+};
+#endif
+
VkResult genX(CreateSampler)(
VkDevice_device,
const VkSamplerCreateInfo* pCreateInfo,
@@ -266,6 +274,10 @@ VkResult genX(CreateSampler)(
uint32_t border_color_offset = device->border_colors.offset +
pCreateInfo->borderColor * 64;
+#if GEN_GEN >= 9
+ unsigned sampler_reduction_mode = STD_FILTER;
+#endif
+
vk_foreach_struct(ext, pCreateInfo->pNext) {
switch (ext->sType) {
case VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO: {
@@ -281,6 +293,15 @@ VkResult genX(CreateSampler)(
sampler->conversion = conversion;
break;
}
+#if GEN_GEN >= 9
+ case VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT: {
+ struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
+(struct VkSamplerReductionModeCreateInfoEXT *) ext;
+ sampler_reduction_mode =
+vk_to_gen_sampler_reduction_mode[sampler_reduction->reductionMode];
+ break;
+ }
+#endif
default:
anv_debug_ignored_stype(ext->sType);
break;
@@ -348,6 +369,11 @@ VkResult
Re: [Mesa-dev] [PATCH 2/2] nir: Add a global dead write var removal pass
Disregard this patch. I'm sending a replacement for it.
For the record:
> The pass works by walking through the control flow nodes, and traverse
> the instructions keeping track of the write instructions whose
> destination were not overwritten by other instructions (called "live
> writes"). Reading from the destinations cause the writes to be marked
> as "used". If statements and loops are handled specially to take into
> account the different codepaths. The writes that are not "used" are
> removed.
(...)
> + case nir_cf_node_loop: {
> + nir_loop *loop = nir_cf_node_as_loop(cf_node);
> +
> + /* For tracking used variables in a loop, there are three cases: (a)
> the
> + * body is not entered; (b) the body is executed once; (c) the body is
> + * executed more than once.
> + *
> + * The case (c) is exemplified below:
> + *
> + * c = x
> + * while condition
> + * use(c)
> + * c = y
> + * c = z
> + * use(c)
> + *
> + * All writes to c must be considered used. This is achieved by
> + * performing a second pass in the loop body, with the live write table
> + * produced by a first pass on it.
> + */
> +
> + struct hash_table *loop_live_writes =
> _mesa_hash_table_clone(live_writes, mem_ctx);
> + for (int i = 0; i < 2; i++) {
> + foreach_list_typed_safe(nir_cf_node, cf_node, node, >body)
> +mark_used_writes_in_node(mem_ctx, loop_live_writes, cf_node);
> + }
Doing two iterations here has a bad consequence: the number of times
we execute blocks will blows up, since if there's a loop inside the
loop, we'll execute each block in the inner loop 4 times, and so on.
I've tried other approaches to do this "following the CFG", but for
the case at hand (eliminate dead writes) all them ended up pointing
towards doing the analysis considering the block graph (preds/succs).
So that's what I've done in the new patch.
Thanks,
Caio
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 4/9] nir: Give end_block its own index
Since there's no particular reason for the index to be 0, choose an index that is not used by other block. This is convenient when we store "per-block" data in an array AND look for the successors data (e.g. any kind of backwards data-flow analysis). --- src/compiler/nir/nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c index e12aa5d80f5..1a5cfc27b74 100644 --- a/src/compiler/nir/nir.c +++ b/src/compiler/nir/nir.c @@ -1641,7 +1641,7 @@ nir_index_blocks(nir_function_impl *impl) block->index = index++; } - impl->num_blocks = index; + impl->num_blocks = impl->end_block->index = index; } static bool -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 5/9] nir: Add a local dead write vars removal pass
Instead of doing this as part of the existing (local) copy prop vars
pass. This is an intermediate step before changing both the dead
write and the copy prop vars to act on the whole program instead of on
local blocks. The nature of data we store and the way we iterate is
different enough that would be awkward keeping those together.
---
src/compiler/Makefile.sources | 1 +
src/compiler/nir/meson.build | 1 +
src/compiler/nir/nir.h | 2 +
src/compiler/nir/nir_opt_dead_write_vars.c | 243 +
4 files changed, 247 insertions(+)
create mode 100644 src/compiler/nir/nir_opt_dead_write_vars.c
diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources
index 27a54e0be09..fa93ad08a16 100644
--- a/src/compiler/Makefile.sources
+++ b/src/compiler/Makefile.sources
@@ -274,6 +274,7 @@ NIR_FILES = \
nir/nir_opt_cse.c \
nir/nir_opt_dce.c \
nir/nir_opt_dead_cf.c \
+ nir/nir_opt_dead_write_vars.c \
nir/nir_opt_gcm.c \
nir/nir_opt_global_to_local.c \
nir/nir_opt_if.c \
diff --git a/src/compiler/nir/meson.build b/src/compiler/nir/meson.build
index 8708f9b069c..1c164a548a7 100644
--- a/src/compiler/nir/meson.build
+++ b/src/compiler/nir/meson.build
@@ -158,6 +158,7 @@ files_libnir = files(
'nir_opt_cse.c',
'nir_opt_dce.c',
'nir_opt_dead_cf.c',
+ 'nir_opt_dead_write_vars.c',
'nir_opt_gcm.c',
'nir_opt_global_to_local.c',
'nir_opt_if.c',
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index d0fa693884b..becf6e351c3 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2968,6 +2968,8 @@ bool nir_opt_dce(nir_shader *shader);
bool nir_opt_dead_cf(nir_shader *shader);
+bool nir_opt_dead_write_vars(nir_shader *shader);
+
bool nir_opt_gcm(nir_shader *shader, bool value_number);
bool nir_opt_if(nir_shader *shader);
diff --git a/src/compiler/nir/nir_opt_dead_write_vars.c
b/src/compiler/nir/nir_opt_dead_write_vars.c
new file mode 100644
index 000..822bfa5595d
--- /dev/null
+++ b/src/compiler/nir/nir_opt_dead_write_vars.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright © 2018 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "nir.h"
+#include "nir_builder.h"
+#include "nir_deref.h"
+
+#include "util/u_dynarray.h"
+
+struct state {
+ void *mem_ctx;
+
+ /* Maps nir_deref_instr to a corresponding nir_deref_path. Avoids
+* rebuilding the paths for the same deref. */
+ struct hash_table *paths;
+ void *path_lin_ctx;
+};
+
+static nir_deref_path *
+get_path(struct state *state, nir_deref_instr *deref)
+{
+ struct hash_entry *entry = _mesa_hash_table_search(state->paths, deref);
+ if (!entry) {
+ nir_deref_path *path = linear_zalloc_child(state->path_lin_ctx,
sizeof(nir_deref_path));
+ nir_deref_path_init(path, deref, state->mem_ctx);
+ _mesa_hash_table_insert(state->paths, deref, path);
+ return path;
+ } else {
+ return entry->data;
+ }
+}
+
+/* Entry for unused_writes arrays. */
+struct write_entry {
+ /* If NULL indicates the entry is free to be reused. */
+ nir_intrinsic_instr *intrin;
+ uintptr_t mask;
+ nir_deref_path *path;
+};
+
+static void
+clear_unused_for_modes(struct util_dynarray *unused_writes, nir_variable_mode
modes)
+{
+ util_dynarray_foreach(unused_writes, struct write_entry, entry) {
+ if (!entry->intrin)
+ continue;
+ nir_variable *var = entry->path->path[0]->var;
+ if (var->data.mode & modes)
+ entry->intrin = NULL;
+ }
+}
+
+static void
+clear_unused_for_src(struct util_dynarray *unused_writes, nir_deref_path
*src_path)
+{
+ util_dynarray_foreach(unused_writes, struct write_entry, entry) {
+ if (!entry->intrin)
+ continue;
+ if (nir_compare_deref_paths(src_path, entry->path) &
nir_derefs_may_alias_bit)
+
[Mesa-dev] [PATCH 8/9] freedreno/ir3: Use the new dead write vars pass
--- src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_nir.c index db1d74fdee7..d5f42f2a231 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c @@ -94,6 +94,7 @@ ir3_optimize_loop(nir_shader *s) OPT_V(s, nir_lower_vars_to_ssa); progress |= OPT(s, nir_opt_copy_prop_vars); + progress |= OPT(s, nir_opt_dead_write_vars); progress |= OPT(s, nir_lower_alu_to_scalar); progress |= OPT(s, nir_lower_phis_to_scalar); -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 9/9] nir: Remove handling of dead writes from copy_prop_vars
These are handled by a separate pass now.
---
src/compiler/nir/nir_opt_copy_prop_vars.c | 67 +--
1 file changed, 3 insertions(+), 64 deletions(-)
diff --git a/src/compiler/nir/nir_opt_copy_prop_vars.c
b/src/compiler/nir/nir_opt_copy_prop_vars.c
index 9fecaf0eeec..b6a5b9c2bb4 100644
--- a/src/compiler/nir/nir_opt_copy_prop_vars.c
+++ b/src/compiler/nir/nir_opt_copy_prop_vars.c
@@ -38,10 +38,7 @@
* 1) Copy-propagation on variables that have indirect access. This includes
* propagating from indirect stores into indirect loads.
*
- * 2) Dead code elimination of store_var and copy_var intrinsics based on
- * killed destination values.
- *
- * 3) Removal of redundant load_deref intrinsics. We can't trust regular CSE
+ * 2) Removal of redundant load_deref intrinsics. We can't trust regular CSE
* to do this because it isn't aware of variable writes that may alias the
* value and make the former load invalid.
*
@@ -51,6 +48,8 @@
* rapidly get out of hand. Fortunately, for anything that is only ever
* accessed directly, we get SSA based copy-propagation which is extremely
* powerful so this isn't that great a loss.
+ *
+ * Removal of dead writes to variables is handled by another pass.
*/
struct value {
@@ -66,7 +65,6 @@ struct copy_entry {
nir_instr *store_instr[4];
- unsigned comps_may_be_read;
struct value src;
nir_deref_instr *dst;
@@ -114,44 +112,6 @@ copy_entry_remove(struct copy_prop_var_state *state,
struct copy_entry *entry)
list_add(>link, >copy_free_list);
}
-static void
-remove_dead_writes(struct copy_prop_var_state *state,
- struct copy_entry *entry, unsigned write_mask)
-{
- /* We're overwriting another entry. Some of it's components may not
-* have been read yet and, if that's the case, we may be able to delete
-* some instructions but we have to be careful.
-*/
- unsigned dead_comps = write_mask & ~entry->comps_may_be_read;
-
- for (unsigned mask = dead_comps; mask;) {
- unsigned i = u_bit_scan();
-
- nir_instr *instr = entry->store_instr[i];
-
- /* We may have already deleted it on a previous iteration */
- if (!instr)
- continue;
-
- /* See if this instr is used anywhere that it's not dead */
- bool keep = false;
- for (unsigned j = 0; j < 4; j++) {
- if (entry->store_instr[j] == instr) {
-if (dead_comps & (1 << j)) {
- entry->store_instr[j] = NULL;
-} else {
- keep = true;
-}
- }
- }
-
- if (!keep) {
- nir_instr_remove(instr);
- state->progress = true;
- }
- }
-}
-
static struct copy_entry *
lookup_entry_for_deref(struct copy_prop_var_state *state,
nir_deref_instr *deref,
@@ -165,16 +125,6 @@ lookup_entry_for_deref(struct copy_prop_var_state *state,
return NULL;
}
-static void
-mark_aliased_entries_as_read(struct copy_prop_var_state *state,
- nir_deref_instr *deref, unsigned components)
-{
- list_for_each_entry(struct copy_entry, iter, >copies, link) {
- if (nir_compare_derefs(iter->dst, deref) & nir_derefs_may_alias_bit)
- iter->comps_may_be_read |= components;
- }
-}
-
static struct copy_entry *
get_entry_and_kill_aliases(struct copy_prop_var_state *state,
nir_deref_instr *deref,
@@ -191,11 +141,6 @@ get_entry_and_kill_aliases(struct copy_prop_var_state
*state,
}
nir_deref_compare_result comp = nir_compare_derefs(iter->dst, deref);
- /* This is a store operation. If we completely overwrite some value, we
- * want to delete any dead writes that may be present.
- */
- if (comp & nir_derefs_b_contains_a_bit)
- remove_dead_writes(state, iter, write_mask);
if (comp & nir_derefs_equal_bit) {
assert(entry == NULL);
@@ -231,7 +176,6 @@ store_to_entry(struct copy_prop_var_state *state, struct
copy_entry *entry,
const struct value *value, unsigned write_mask,
nir_instr *store_instr)
{
- entry->comps_may_be_read &= ~write_mask;
if (value->is_ssa) {
entry->src.is_ssa = true;
/* Only overwrite the written components */
@@ -490,9 +434,6 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
case nir_intrinsic_load_deref: {
nir_deref_instr *src = nir_src_as_deref(intrin->src[0]);
- uint8_t comps_read = nir_ssa_def_components_read(>dest.ssa);
- mark_aliased_entries_as_read(state, src, comps_read);
-
struct copy_entry *src_entry =
lookup_entry_for_deref(state, src, nir_derefs_a_contains_b_bit);
struct value value;
@@ -579,8 +520,6 @@ copy_prop_vars_block(struct copy_prop_var_state *state,
continue;
}
- mark_aliased_entries_as_read(state, src, 0xf);
-
struct copy_entry *src_entry =
[Mesa-dev] [PATCH 6/9] nir: Make dead_write_vars pass global
The pass will remove not only writes that are proven to be dead in
block, but also writes that can only be considered dead by looking at
multiple blocks. Such global analysis is necessary to remove dead
writes such as the one marked below:
int total = gl_VertexIndex * 10;
float r = gl_VertexIndex;
for (int i = 0; i < total; i++) {
arr[i] = i; /* DEAD WRITE. */
if ((i % 2) == 0) {
arr[i] = i * 3.0;
} else {
arr[i] = i * 5.0;
}
r = arr[i];
}
out_color = vec4(r,r,r,r);
Without knowing that both sucessor blocks will overwrite the value,
it was not possible to remove the the "arr[i] = i" write.
The local pass was incremented with some extra data collected to allow
a iterative (backward) data-flow analysis to run. The analysis is
used to find out, for each block, what derefs are used after the
block. This information is then used to decide what unused writes in
the end of the block can be removed. In a local-only analysis we
couldn't remove any, because they could be used later.
---
src/compiler/nir/nir_opt_dead_write_vars.c | 546 -
1 file changed, 532 insertions(+), 14 deletions(-)
diff --git a/src/compiler/nir/nir_opt_dead_write_vars.c
b/src/compiler/nir/nir_opt_dead_write_vars.c
index 822bfa5595d..fe72ab784a8 100644
--- a/src/compiler/nir/nir_opt_dead_write_vars.c
+++ b/src/compiler/nir/nir_opt_dead_write_vars.c
@@ -27,6 +27,85 @@
#include "util/u_dynarray.h"
+/**
+ * Elimination of dead writes based on derefs.
+ *
+ * Dead writes are stores and copies that write to a deref, which then gets
+ * another write before it was used (read or sourced for a copy). Those
+ * writes can be removed since they don't affect anything.
+ *
+ * For derefs that refer to a memory area that can be read after the program,
+ * the last write is considered used. The presence of certain instructions
+ * may also cause writes to be considered used, e.g. memory barrier (in this
case
+ * the value must be written as other thread might use it).
+ *
+ * The write mask for store instructions is considered, so it is possible that
+ * a store is removed because of the combination of other stores overwritten
+ * its value.
+ *
+ * The pass works in three steps:
+ *
+ * (1) For each block, perform a local dead write removal. Removing only
+ * writes we are sure are dead, so keeping around the last unused writes
+ * at the end of the block. These last unused will be revisited in (3).
+ *
+ * (2) Perform a data-flow analysis to identify for each block the "uses
+ * before write" of successor blocks. E.g. given the blocks below (block0
+ * precedes block1, that precedes block2)
+ *
+ * block0:block1:block2:
+ * write Aload B load D
+ * write Bwrite Cload E
+ * write Cload C
+ * write Dwrite D
+ * write E
+ * load A
+ *
+ *the goal is know that B and E are "used before write" after block0; D
+ *and E are "used before write" after block1. Note that usage of E
+ *doesn't come from an immediate succesor of block0. The "used before
+ *written" information will decided later what unused writes are removed.
+ *
+ *The data-flow analysis is implemented by starting with per-block sets
+ *and iterate fixing the content in those sets. The nature of the
+ *"fixing" ensures that the sets get stable (i.e. no infinite loops).
+ *Each block gets two sets representing its local information:
+ *
+ *- GEN: the derefs used before write by the block. E.g. GEN(block1) = {B}
+ *- KILL: the derefs overwritten by the block. E.g. KILL(block1) = {C, D}
+ *
+ *And two other sets representing its current state:
+ *
+ *- IN: the derefs used before write for this block and all successors.
+ * E.g. at the end of the analysis, IN(block1) = {B, E}. Note how E is
+ * present but not D.
+ *- OUT: the derefs used before write for the successors of the block.
+ *
+ *In this pass the iteration happens "backwards", so a block uses the
+ *succesor information to improve its own information. The IN and OUT
+ *sets are updated as follows:
+ *
+ *OUT = union IN of all successors
+ *IN = GEN union (OUT minus KILL)
+ *
+ * 3) Remove the last unused writes for each block that are not used by
+ *successor blocks. After the analysis in (2), this information is
+ *available in the OUT set of each block.
+ *
+ * One extra factor in play is that not trivial to decide whether two derefs
+ * are referring to the same storage or not. Currently array indirects are
+ * assumed to alias with each other, i.e. "write A[i]" is considered used by a
+ * later "load A[j]". This logic is mostly handled as part of
+ * nir_compare_deref_paths() function. This prevents us from representing the
[Mesa-dev] [PATCH 0/9] Global dead write vars removal pass
Our code currently only remove dead writes to vars for each block, but doesn't tackle cases that involve multiple blocks. This series will add a pass that use an iterative data-flow analysis to cover those cases. Commit message for patch 6 has a detailed example. I'm working on a subsequent series for adding global capabilities to copy propagation. While those optimizations can be done locally together (as we currently do), the way we iterate the blocks for data-flow analysis is different (dead write uses backward, copy propagation uses forward), so it helps keeping them separate. The motivation for this series (and the upcoming copy propagation) work is to improve our generated code when we move other memory accesses (e.g. SSBOs) to use derefs. Patches 1-4 are small and are worth regardless the series -- I have other series locally that use some of those. So I intend to land them earlier as they get reviewed. Caio Marcelo de Oliveira Filho (9): util/dynarray: add a clone function nir: Export deref comparison functions nir: Skip common instructions when comparing deref paths nir: Give end_block its own index nir: Add a local dead write vars removal pass nir: Make dead_write_vars pass global intel/nir: Use the new dead write vars pass freedreno/ir3: Use the new dead write vars pass nir: Remove handling of dead writes from copy_prop_vars src/compiler/Makefile.sources | 1 + src/compiler/nir/meson.build| 1 + src/compiler/nir/nir.c | 2 +- src/compiler/nir/nir.h | 2 + src/compiler/nir/nir_deref.c| 112 +++ src/compiler/nir/nir_deref.h| 10 + src/compiler/nir/nir_opt_copy_prop_vars.c | 208 +- src/compiler/nir/nir_opt_dead_write_vars.c | 761 src/gallium/drivers/freedreno/ir3/ir3_nir.c | 1 + src/intel/compiler/brw_nir.c| 1 + src/util/u_dynarray.h | 9 + 11 files changed, 913 insertions(+), 195 deletions(-) create mode 100644 src/compiler/nir/nir_opt_dead_write_vars.c -- 2.18.0 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/9] nir: Export deref comparison functions
Reviewed-by: Timothy Arceri
---
src/compiler/nir/nir_deref.c | 109
src/compiler/nir/nir_deref.h | 10 ++
src/compiler/nir/nir_opt_copy_prop_vars.c | 145 ++
3 files changed, 132 insertions(+), 132 deletions(-)
diff --git a/src/compiler/nir/nir_deref.c b/src/compiler/nir/nir_deref.c
index c03acf83597..d013b423a8b 100644
--- a/src/compiler/nir/nir_deref.c
+++ b/src/compiler/nir/nir_deref.c
@@ -270,3 +270,112 @@ nir_fixup_deref_modes(nir_shader *shader)
}
}
}
+
+/** Returns true if the storage referrenced to by deref completely contains
+ * the storage referenced by sub.
+ */
+nir_deref_compare_result
+nir_compare_deref_paths(nir_deref_path *a_path,
+nir_deref_path *b_path)
+{
+ if (a_path->path[0]->var != b_path->path[0]->var)
+ return 0;
+
+ /* Start off assuming they fully compare. We ignore equality for now. In
+* the end, we'll determine that by containment.
+*/
+ nir_deref_compare_result result = nir_derefs_may_alias_bit |
+ nir_derefs_a_contains_b_bit |
+ nir_derefs_b_contains_a_bit;
+
+ nir_deref_instr **a_p = _path->path[1];
+ nir_deref_instr **b_p = _path->path[1];
+ while (*a_p != NULL && *b_p != NULL) {
+ nir_deref_instr *a_tail = *(a_p++);
+ nir_deref_instr *b_tail = *(b_p++);
+
+ switch (a_tail->deref_type) {
+ case nir_deref_type_array:
+ case nir_deref_type_array_wildcard: {
+ assert(b_tail->deref_type == nir_deref_type_array ||
+b_tail->deref_type == nir_deref_type_array_wildcard);
+
+ if (a_tail->deref_type == nir_deref_type_array_wildcard) {
+if (b_tail->deref_type != nir_deref_type_array_wildcard)
+ result &= ~nir_derefs_b_contains_a_bit;
+ } else if (b_tail->deref_type == nir_deref_type_array_wildcard) {
+if (a_tail->deref_type != nir_deref_type_array_wildcard)
+ result &= ~nir_derefs_a_contains_b_bit;
+ } else {
+assert(a_tail->deref_type == nir_deref_type_array &&
+ b_tail->deref_type == nir_deref_type_array);
+assert(a_tail->arr.index.is_ssa && b_tail->arr.index.is_ssa);
+
+nir_const_value *a_index_const =
+ nir_src_as_const_value(a_tail->arr.index);
+nir_const_value *b_index_const =
+ nir_src_as_const_value(b_tail->arr.index);
+if (a_index_const && b_index_const) {
+ /* If they're both direct and have different offsets, they
+* don't even alias much less anything else.
+*/
+ if (a_index_const->u32[0] != b_index_const->u32[0])
+ return 0;
+} else if (a_tail->arr.index.ssa == b_tail->arr.index.ssa) {
+ /* They're the same indirect, continue on */
+} else {
+ /* They're not the same index so we can't prove anything about
+* containment.
+*/
+ result &= ~(nir_derefs_a_contains_b_bit |
nir_derefs_b_contains_a_bit);
+}
+ }
+ break;
+ }
+
+ case nir_deref_type_struct: {
+ /* If they're different struct members, they don't even alias */
+ if (a_tail->strct.index != b_tail->strct.index)
+return 0;
+ break;
+ }
+
+ default:
+ unreachable("Invalid deref type");
+ }
+ }
+
+ /* If a is longer than b, then it can't contain b */
+ if (*a_p != NULL)
+ result &= ~nir_derefs_a_contains_b_bit;
+ if (*b_p != NULL)
+ result &= ~nir_derefs_b_contains_a_bit;
+
+ /* If a contains b and b contains a they must be equal. */
+ if ((result & nir_derefs_a_contains_b_bit) && (result &
nir_derefs_b_contains_a_bit))
+ result |= nir_derefs_equal_bit;
+
+ return result;
+}
+
+nir_deref_compare_result
+nir_compare_derefs(nir_deref_instr *a, nir_deref_instr *b)
+{
+ if (a == b) {
+ return nir_derefs_equal_bit | nir_derefs_may_alias_bit |
+ nir_derefs_a_contains_b_bit | nir_derefs_b_contains_a_bit;
+ }
+
+ nir_deref_path a_path, b_path;
+ nir_deref_path_init(_path, a, NULL);
+ nir_deref_path_init(_path, b, NULL);
+ assert(a_path.path[0]->deref_type == nir_deref_type_var);
+ assert(b_path.path[0]->deref_type == nir_deref_type_var);
+
+ nir_deref_compare_result result = nir_compare_deref_paths(_path, _path);
+
+ nir_deref_path_finish(_path);
+ nir_deref_path_finish(_path);
+
+ return result;
+}
diff --git a/src/compiler/nir/nir_deref.h b/src/compiler/nir/nir_deref.h
index 6f4141aaf82..c61c3f9366f 100644
--- a/src/compiler/nir/nir_deref.h
+++ b/src/compiler/nir/nir_deref.h
@@ -54,6 +54,16 @@ unsigned nir_deref_instr_get_const_offset(nir_deref_instr
*deref,
nir_ssa_def *nir_build_deref_offset(nir_builder *b, nir_deref_instr *deref,
[Mesa-dev] [PATCH 1/9] util/dynarray: add a clone function
---
src/util/u_dynarray.h | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/util/u_dynarray.h b/src/util/u_dynarray.h
index dcbbc06d161..4920fe04b67 100644
--- a/src/util/u_dynarray.h
+++ b/src/util/u_dynarray.h
@@ -102,6 +102,15 @@ util_dynarray_resize(struct util_dynarray *buf, unsigned
newsize)
return p;
}
+static inline void
+util_dynarray_clone(struct util_dynarray *buf, struct util_dynarray *mem_ctx,
+struct util_dynarray *from_buf)
+{
+ util_dynarray_init(buf, mem_ctx);
+ util_dynarray_resize(buf, from_buf->size);
+ memcpy(buf->data, from_buf->data, from_buf->size);
+}
+
static inline void *
util_dynarray_grow(struct util_dynarray *buf, int diff)
{
--
2.18.0
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[Mesa-dev] [PATCH 7/9] intel/nir: Use the new dead write vars pass
---
src/intel/compiler/brw_nir.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index 31ffbe613ec..afc73e58c71 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -543,6 +543,7 @@ brw_nir_optimize(nir_shader *nir, const struct brw_compiler
*compiler,
progress = false;
OPT(nir_lower_vars_to_ssa);
OPT(nir_opt_copy_prop_vars);
+ OPT(nir_opt_dead_write_vars);
if (is_scalar) {
OPT(nir_lower_alu_to_scalar);
--
2.18.0
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[Mesa-dev] [PATCH 3/9] nir: Skip common instructions when comparing deref paths
Deref paths may share the same deref instructions in their chains,
e.g.
ssa_100 = deref_var A
ssa_101 = deref_struct "array_field" of ssa_100
ssa_102 = deref_array "[1]" of ssa_101
ssa_103 = deref_struct "field_a" of ssa_102
ssa_104 = deref_struct "field_a" of ssa_103
when comparing the two last deref instructions, their paths will share
a common sequence ssa_100, ssa_101, ssa_102. This patch skips to next
iteration if the deref instructions are the same. Path[0] (the var)
is still handled specially, so in the case above, only ssa_101 and
ssa_102 will be skipped.
---
src/compiler/nir/nir_deref.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/nir/nir_deref.c b/src/compiler/nir/nir_deref.c
index d013b423a8b..c8851688f9d 100644
--- a/src/compiler/nir/nir_deref.c
+++ b/src/compiler/nir/nir_deref.c
@@ -294,6 +294,9 @@ nir_compare_deref_paths(nir_deref_path *a_path,
nir_deref_instr *a_tail = *(a_p++);
nir_deref_instr *b_tail = *(b_p++);
+ if (a_tail == b_tail)
+ continue;
+
switch (a_tail->deref_type) {
case nir_deref_type_array:
case nir_deref_type_array_wildcard: {
--
2.18.0
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[Mesa-dev] [PATCH 02/21] i965: remove unused no_rast bool
Forcing software fallbacks for i965 hasn't been an option since
5e3c093ff866.
---
src/mesa/drivers/dri/i965/brw_context.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 72be8f2a4d0..c32def7c3d7 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -814,7 +814,6 @@ struct brw_context
* drirc options:
* @{
*/
- bool no_rast;
bool always_flush_batch;
bool always_flush_cache;
bool disable_throttling;
--
2.17.1
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[Mesa-dev] [PATCH 07/21] mesa: remove dri configs unused software-fallback options
These seems to have only been used by DRI1 drivers which were
removed with e4344161bde2.
---
src/util/xmlpool/ca.po | 8
src/util/xmlpool/de.po | 8
src/util/xmlpool/es.po | 8
src/util/xmlpool/fr.po | 8
src/util/xmlpool/nl.po | 8
src/util/xmlpool/sv.po | 8
src/util/xmlpool/t_options.h | 14 --
7 files changed, 62 deletions(-)
diff --git a/src/util/xmlpool/ca.po b/src/util/xmlpool/ca.po
index db74464cafb..36872e2f2ba 100644
--- a/src/util/xmlpool/ca.po
+++ b/src/util/xmlpool/ca.po
@@ -295,14 +295,6 @@ msgstr "Només memòria de targeta (si està disponible)"
msgid "Only GART (AGP/PCIE) memory (if available)"
msgstr "Només memòria GART (AGP/PCIE) (si està disponible)"
-#: t_options.h:309
-msgid "Features that are not hardware-accelerated"
-msgstr "Característiques no accelerades per maquinari"
-
-#: t_options.h:313
-msgid "Enable extension GL_ARB_vertex_program"
-msgstr "Habilita l'extensió GL_ARB_vertex_program"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr "Miscel·lània"
diff --git a/src/util/xmlpool/de.po b/src/util/xmlpool/de.po
index fcd0e843869..57fa6fb4619 100644
--- a/src/util/xmlpool/de.po
+++ b/src/util/xmlpool/de.po
@@ -270,14 +270,6 @@ msgstr "Nur Grafikspeicher (falls verfügbar)"
msgid "Only GART (AGP/PCIE) memory (if available)"
msgstr "Nur GART-Speicher (AGP/PCIE) (falls verfügbar)"
-#: t_options.h:309
-msgid "Features that are not hardware-accelerated"
-msgstr "Funktionalität, die nicht hardwarebeschleunigt ist"
-
-#: t_options.h:313
-msgid "Enable extension GL_ARB_vertex_program"
-msgstr "Erweiterung GL_ARB_vertex_program aktivieren"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/es.po b/src/util/xmlpool/es.po
index 666762cc4b5..68824b61af2 100644
--- a/src/util/xmlpool/es.po
+++ b/src/util/xmlpool/es.po
@@ -279,14 +279,6 @@ msgstr "Solo memoria de tarjeta (si está disponible)"
msgid "Only GART (AGP/PCIE) memory (if available)"
msgstr "Solo memoria GART (AGP/PCIE) (si está disponible)"
-#: t_options.h:309
-msgid "Features that are not hardware-accelerated"
-msgstr "Características no aceleradas por hardware"
-
-#: t_options.h:313
-msgid "Enable extension GL_ARB_vertex_program"
-msgstr "Habilitar la extensión GL_ARB_vertex_program"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr "Misceláneos"
diff --git a/src/util/xmlpool/fr.po b/src/util/xmlpool/fr.po
index 6a1c23263c3..ea5f6812aeb 100644
--- a/src/util/xmlpool/fr.po
+++ b/src/util/xmlpool/fr.po
@@ -266,14 +266,6 @@ msgstr "Utiliser uniquement la mémoire graphique (si
disponible)"
msgid "Only GART (AGP/PCIE) memory (if available)"
msgstr "Utiliser uniquement la mémoire GART (AGP/PCIE) (si disponible)"
-#: t_options.h:309
-msgid "Features that are not hardware-accelerated"
-msgstr "Fonctionnalités ne bénéficiant pas d'une accélération matérielle"
-
-#: t_options.h:313
-msgid "Enable extension GL_ARB_vertex_program"
-msgstr "Activer l'extension GL_ARB_vertex_program"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/nl.po b/src/util/xmlpool/nl.po
index f3576a9cf55..9dc0428ea63 100644
--- a/src/util/xmlpool/nl.po
+++ b/src/util/xmlpool/nl.po
@@ -267,14 +267,6 @@ msgstr "Alleen geheugen op de kaart (als het aanwezig is)"
msgid "Only GART (AGP/PCIE) memory (if available)"
msgstr "Alleen GART (AGP/PCIE) geheugen (als het aanwezig is)"
-#: t_options.h:309
-msgid "Features that are not hardware-accelerated"
-msgstr "Eigenschappen die niet hardwareversneld zijn"
-
-#: t_options.h:313
-msgid "Enable extension GL_ARB_vertex_program"
-msgstr "Zet uitbreiding GL_ARB_vertex_program aan"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/sv.po b/src/util/xmlpool/sv.po
index 05aca5d0a95..d156eba7214 100644
--- a/src/util/xmlpool/sv.po
+++ b/src/util/xmlpool/sv.po
@@ -259,14 +259,6 @@ msgstr "Endast kortminne (om tillgängligt)"
msgid "Only GART (AGP/PCIE) memory (if available)"
msgstr "Endast GART-minne (AGP/PCIE) (om tillgängligt)"
-#: t_options.h:309
-msgid "Features that are not hardware-accelerated"
-msgstr "Funktioner som inte är hårdvaruaccelererade"
-
-#: t_options.h:313
-msgid "Enable extension GL_ARB_vertex_program"
-msgstr "Aktivera tillägget GL_ARB_vertex_program"
-
#: t_options.h:323
msgid "Miscellaneous"
msgstr ""
diff --git a/src/util/xmlpool/t_options.h b/src/util/xmlpool/t_options.h
index f0dc78dd595..ee12f104d76 100644
--- a/src/util/xmlpool/t_options.h
+++ b/src/util/xmlpool/t_options.h
@@ -342,20 +342,6 @@ DRI_CONF_OPT_BEGIN_B(glx_disable_sgi_video_sync, def) \
DRI_CONF_OPT_END
-/**
- * \brief Software-fallback options. To allow using features (like
- * GL_ARB_vertex_program) on GPUs that don't otherwise support the feature.
- */
-#define DRI_CONF_SECTION_SOFTWARE \
-DRI_CONF_SECTION_BEGIN \
-DRI_CONF_DESC(en,gettext("Features that are not hardware-accelerated"))
-
