[PATCH] stmmac: dwmac-ipq806x: fix static checker warning

2015-08-04 Thread Mathieu Olivari 
The patch b1c17215d718: "stmmac: add ipq806x glue layer", leads to the
following static checker warning:

.../stmmac/dwmac-ipq806x.c:314 ipq806x_gmac_probe()
warn: double left shift '1 << (1 << gmac->id)'

The NSS_COMMON_CLK_SRC_CTRL_OFFSET macro is used once as an offset, and
once as a mask, which is a bug indeed. We'll fix it by defining the
offset as the real offset value and computing the mask from it when
required.

Tested on IPQ806x ref designs AP148 & DB149.

Reported-by: Dan Carpenter 
Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
index 333489f..9d89bdb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
@@ -42,7 +42,7 @@
 #define NSS_COMMON_CLK_DIV_MASK0x7f
 
 #define NSS_COMMON_CLK_SRC_CTRL0x14
-#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x)  (1 << x)
+#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x)  (x)
 /* Mode is coded on 1 bit but is different depending on the MAC ID:
  * MAC0: QSGMII=0 RGMII=1
  * MAC1: QSGMII=0 SGMII=0 RGMII=1
@@ -308,7 +308,7 @@ static int ipq806x_gmac_probe(struct platform_device *pdev)
 
/* Configure the clock src according to the mode */
regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
-   val &= ~NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
+   val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
switch (gmac->phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
-- 
2.1.4

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Re: [PATCH 0/7] net: dsa: add QCA AR8xxx switch family support\

2015-05-29 Thread Mathieu Olivari 
On Fri, May 29, 2015 at 12:58:12PM -0700, Florian Fainelli wrote:
> On 29/05/15 11:59, Andrew Lunn wrote:
> > On Fri, May 29, 2015 at 11:49:54AM -0700, Mathieu Olivari wrote:
> >> On Fri, May 29, 2015 at 04:00:01AM +0200, Andrew Lunn wrote:
> >>> FYI:
> >>>
> >>> I have patches which allow DSA to use two cpu interfaces. Seems to
> >>> work on my DIR665 with a Marvell Switch.
> >>>
> >>> I will post the patches as an RFC.
> >>>
> >>>   Andrew
> >>
> >> Does it require the switch CPU ports to support LAG or is it generic
> >> enough to allow switch partitioning?
> > 
> > When using tags, DSA by default partitions the switch. Each user port
> > is separate from other ports. lan4 will not bridge to lan1 unless you
> > either do it in software, or you implement the
> > .port_join_bridge/.port_leave_bridge/.port_stp_update methods of
> > dsa_switch_driver.
> > 
> > What it requires is that for each user port, you can configure what
> > cpu port it should use. Marvell devices have this ability, and at a
> > first look, it seems like SF2 does as well, but i will leave Florian
> > to answer definitively.
> 
> That's right, such configuration happens by using VLAN_CTL in the
> context of SF2, by default only Port  and CPU can talk to each other.
> Bridging ports involving putting them in the same domain, e.g: updating
> the VLAN_CTL bitmask to include all bridge members.

Similar here. That would work for ar8xxx too.

> -- 
> Florian
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Re: [PATCH 0/7] net: dsa: add QCA AR8xxx switch family support\

2015-05-29 Thread Mathieu Olivari 
On Fri, May 29, 2015 at 04:00:01AM +0200, Andrew Lunn wrote:
> FYI:
> 
> I have patches which allow DSA to use two cpu interfaces. Seems to
> work on my DIR665 with a Marvell Switch.
> 
> I will post the patches as an RFC.
> 
>   Andrew

Does it require the switch CPU ports to support LAG or is it generic
enough to allow switch partitioning?

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RE: [PATCH 3/7] net: dsa: ar8xxx: add regmap support

2015-05-29 Thread Mathieu Olivari 
Alternatively, we could have something similar to what happens for the phy
in the wireless subsystems. Wireless PHYs are not registered as net_device
but they can still be listed, queried or configured through netlink.
Just thinking out loud here.

Thanks,
Mathieu

-Original Message-
From: Andrew Lunn [mailto:and...@lunn.ch] 
Sent: Thursday, May 28, 2015 7:44 PM
To: Florian Fainelli
Cc: Mathieu Olivari; robh...@kernel.org; pawel.m...@arm.com;
mark.rutl...@arm.com; ijc+devicet...@hellion.org.uk; ga...@codeaurora.org;
da...@davemloft.net; li...@roeck-us.net; gang.chen.5...@gmail.com;
j...@resnulli.us; lei...@staticky.com; f...@skynet.be;
pavel.nakonec...@skitlab.ru; j...@perches.com; sfel...@gmail.com;
n...@openwrt.org; juh...@openwrt.org; devicet...@vger.kernel.org;
linux-ker...@vger.kernel.org; netdev@vger.kernel.org
Subject: Re: [PATCH 3/7] net: dsa: ar8xxx: add regmap support

> Fair enough, are there other global "things" besides counters that 
> could deserve adding maybe some sort of global/master net_device to 
> help query switch-wide information?

This was discussed a while back. I like the current abstraction, all
interfaces are real interfaces you can send and receive packets over. This
pseudo interface cannot be used for packet transfer, which seems odd.

Having access to registers for debugging, so debugfs seems like the best
option to me.

 Andrew

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[PATCH 6/7] net: dsa: ar8xxx: add support for second xMII interfaces through DT

2015-05-28 Thread Mathieu Olivari 
This patch is adding support for port6 specific options to device tree.
They can be used to setup the second xMII interface, and connect it to
one of the switch port.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/dsa/ar8xxx.c | 50 
 1 file changed, 50 insertions(+)

diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
index 4044614..7559249 100644
--- a/drivers/net/dsa/ar8xxx.c
+++ b/drivers/net/dsa/ar8xxx.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "ar8xxx.h"
 
@@ -260,6 +261,9 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int 
port, int mode)
ar8xxx_write(ds, AR8327_REG_PORT5_PAD_CTRL,
 AR8327_PORT_PAD_RGMII_RX_DELAY_EN);
break;
+   case PHY_INTERFACE_MODE_SGMII:
+   ar8xxx_write(ds, reg, AR8327_PORT_PAD_SGMII_EN);
+   break;
default:
pr_err("xMII mode %d not supported\n", mode);
return -EINVAL;
@@ -268,6 +272,48 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int 
port, int mode)
return 0;
 }
 
+static int ar8xxx_of_setup(struct dsa_switch *ds)
+{
+   struct device_node *dn = ds->pd->of_node;
+   const char *s_phymode;
+   int ret, mode;
+   u32 phy_id, ctrl;
+
+   /* If port6-phy-mode property exists, configure it accordingly */
+   if (!of_property_read_string(dn, "qca,port6-phy-mode", &s_phymode)) {
+   for (mode = 0; mode < PHY_INTERFACE_MODE_MAX; mode++)
+   if (!strcasecmp(s_phymode, phy_modes(mode)))
+   break;
+
+   if (mode == PHY_INTERFACE_MODE_MAX)
+   pr_err("Unknown phy-mode: \"%s\"\n", s_phymode);
+
+   ret = ar8xxx_set_pad_ctrl(ds, 6, mode);
+   if (ret < 0)
+   return ret;
+   }
+
+   /* If a phy ID is specified for PORT6 mac, connect them together */
+   if (!of_property_read_u32(dn, "qca,port6-phy-id", &phy_id)) {
+   ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(6),
+  AR8327_PORT_LOOKUP_MEMBER, BIT(phy_to_port(phy_id)));
+   ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(phy_id)),
+  AR8327_PORT_LOOKUP_MEMBER, BIT(6));
+
+   /* We want the switch to be pass-through and act like a PHY on
+* these ports. So BC/MC/UC & IGMP frames need to be accepted
+*/
+   ctrl = BIT(phy_to_port(phy_id)) | BIT(6);
+   ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL1,
+  ctrl << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
+  ctrl << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
+  ctrl << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
+  ctrl << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
+   }
+
+   return 0;
+}
+
 static int ar8xxx_setup(struct dsa_switch *ds)
 {
struct ar8xxx_priv *priv = ds_to_priv(ds);
@@ -341,6 +387,10 @@ static int ar8xxx_setup(struct dsa_switch *ds)
}
}
 
+   ret = ar8xxx_of_setup(ds);
+   if (ret < 0)
+   return ret;
+
return 0;
 }
 
-- 
2.1.4

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[PATCH 2/7] net: dsa: ar8xxx: add ethtool hw statistics support

2015-05-28 Thread Mathieu Olivari 
MIB counters can now be reported through each switch port by using
"ethtool -S".

Signed-off-by: Mathieu Olivari 
---
 drivers/net/dsa/ar8xxx.c | 106 +++
 drivers/net/dsa/ar8xxx.h |  47 +
 2 files changed, 146 insertions(+), 7 deletions(-)

diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
index 4ce3ffc..2f0fa4d 100644
--- a/drivers/net/dsa/ar8xxx.c
+++ b/drivers/net/dsa/ar8xxx.c
@@ -22,6 +22,55 @@
 
 #include "ar8xxx.h"
 
+#define MIB_DESC(_s, _o, _n)   \
+   {   \
+   .size = (_s),   \
+   .offset = (_o), \
+   .name = (_n),   \
+   }
+
+static const struct ar8xxx_mib_desc ar8327_mib[] = {
+   MIB_DESC(1, 0x00, "RxBroad"),
+   MIB_DESC(1, 0x04, "RxPause"),
+   MIB_DESC(1, 0x08, "RxMulti"),
+   MIB_DESC(1, 0x0c, "RxFcsErr"),
+   MIB_DESC(1, 0x10, "RxAlignErr"),
+   MIB_DESC(1, 0x14, "RxRunt"),
+   MIB_DESC(1, 0x18, "RxFragment"),
+   MIB_DESC(1, 0x1c, "Rx64Byte"),
+   MIB_DESC(1, 0x20, "Rx128Byte"),
+   MIB_DESC(1, 0x24, "Rx256Byte"),
+   MIB_DESC(1, 0x28, "Rx512Byte"),
+   MIB_DESC(1, 0x2c, "Rx1024Byte"),
+   MIB_DESC(1, 0x30, "Rx1518Byte"),
+   MIB_DESC(1, 0x34, "RxMaxByte"),
+   MIB_DESC(1, 0x38, "RxTooLong"),
+   MIB_DESC(2, 0x3c, "RxGoodByte"),
+   MIB_DESC(2, 0x44, "RxBadByte"),
+   MIB_DESC(1, 0x4c, "RxOverFlow"),
+   MIB_DESC(1, 0x50, "Filtered"),
+   MIB_DESC(1, 0x54, "TxBroad"),
+   MIB_DESC(1, 0x58, "TxPause"),
+   MIB_DESC(1, 0x5c, "TxMulti"),
+   MIB_DESC(1, 0x60, "TxUnderRun"),
+   MIB_DESC(1, 0x64, "Tx64Byte"),
+   MIB_DESC(1, 0x68, "Tx128Byte"),
+   MIB_DESC(1, 0x6c, "Tx256Byte"),
+   MIB_DESC(1, 0x70, "Tx512Byte"),
+   MIB_DESC(1, 0x74, "Tx1024Byte"),
+   MIB_DESC(1, 0x78, "Tx1518Byte"),
+   MIB_DESC(1, 0x7c, "TxMaxByte"),
+   MIB_DESC(1, 0x80, "TxOverSize"),
+   MIB_DESC(2, 0x84, "TxByte"),
+   MIB_DESC(1, 0x8c, "TxCollision"),
+   MIB_DESC(1, 0x90, "TxAbortCol"),
+   MIB_DESC(1, 0x94, "TxMultiCol"),
+   MIB_DESC(1, 0x98, "TxSingleCol"),
+   MIB_DESC(1, 0x9c, "TxExcDefer"),
+   MIB_DESC(1, 0xa0, "TxDefer"),
+   MIB_DESC(1, 0xa4, "TxLateCol"),
+};
+
 u32
 ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)
 {
@@ -184,6 +233,10 @@ static int ar8xxx_setup(struct dsa_switch *ds)
if (ret < 0)
return ret;
 
+   /* Enable MIB counters */
+   ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
+   ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
+
/* Disable forwarding by default on all ports */
for (i = 0; i < AR8327_NUM_PORTS; i++)
ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
@@ -228,6 +281,42 @@ ar8xxx_phy_write(struct dsa_switch *ds, int phy, int 
regnum, u16 val)
return mdiobus_write(bus, phy, regnum, val);
 }
 
+static void ar8xxx_get_strings(struct dsa_switch *ds, int phy, uint8_t *data)
+{
+   int i;
+
+   for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
+   strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
+   ETH_GSTRING_LEN);
+   }
+}
+
+static void ar8xxx_get_ethtool_stats(struct dsa_switch *ds, int phy,
+uint64_t *data)
+{
+   const struct ar8xxx_mib_desc *mib;
+   uint32_t reg, i, port;
+   u64 hi;
+
+   port = phy_to_port(phy);
+
+   for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
+   mib = &ar8327_mib[i];
+   reg = AR8327_PORT_MIB_COUNTER(port) + mib->offset;
+
+   data[i] = ar8xxx_read(ds, reg);
+   if (mib->size == 2) {
+   hi = ar8xxx_read(ds, reg + 4);
+   data[i] |= hi << 32;
+   }
+   }
+}
+
+static int ar8xxx_get_sset_count(struct dsa_switch *ds)
+{
+   return ARRAY_SIZE(ar8327_mib);
+}
+
 static void ar8xxx_poll_link(struct dsa_switch *ds)
 {
int i = 0;
@@ -275,13 +364,16 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
 }
 
 static struct dsa_switch_driver ar8xxx_switch_driver = {
-   .tag_protocol   = DSA_TAG_PROTO_NONE,
-   .probe  = ar8xxx_probe,
-   .setup  = ar8xxx_setup,
-   .set_addr   = ar8xxx_set_addr,
-   .poll_link  = ar8xxx_poll_link,
-   .phy_read   = ar8xxx_phy_read,
-   .phy_write  = ar8xxx_phy_write,
+   .tag_protocol

[PATCH 3/7] net: dsa: ar8xxx: add regmap support

2015-05-28 Thread Mathieu Olivari 
All switch registers can now be dumped using regmap/debugfs.

\# cat /sys/kernel/debug/regmap//registers
: 1302
0004: ...
...

Signed-off-by: Mathieu Olivari 
---
 drivers/net/dsa/Kconfig  |  1 +
 drivers/net/dsa/ar8xxx.c | 60 
 drivers/net/dsa/ar8xxx.h |  5 
 3 files changed, 66 insertions(+)

diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 2aae541..17fb296 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -68,6 +68,7 @@ config NET_DSA_BCM_SF2
 config NET_DSA_AR8XXX
tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
depends on NET_DSA
+   select REGMAP
---help---
  This enables support for the Qualcomm Atheros AR8XXX Ethernet
  switch chips.
diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
index 2f0fa4d..327abd4 100644
--- a/drivers/net/dsa/ar8xxx.c
+++ b/drivers/net/dsa/ar8xxx.c
@@ -176,6 +176,57 @@ static char *ar8xxx_probe(struct device *host_dev, int 
sw_addr)
}
 }
 
+static int ar8xxx_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+   struct dsa_switch *ds = (struct dsa_switch *)ctx;
+
+   *val = ar8xxx_read(ds, reg);
+
+   return 0;
+}
+
+static int ar8xxx_regmap_write(void *ctx, uint32_t reg, uint32_t val)
+{
+   struct dsa_switch *ds = (struct dsa_switch *)ctx;
+
+   ar8xxx_write(ds, reg, val);
+
+   return 0;
+}
+
+static const struct regmap_range ar8xxx_readable_ranges[] = {
+   regmap_reg_range(0x, 0x00e4), /* Global control */
+   regmap_reg_range(0x0100, 0x0168), /* EEE control */
+   regmap_reg_range(0x0200, 0x0270), /* Parser control */
+   regmap_reg_range(0x0400, 0x0454), /* ACL */
+   regmap_reg_range(0x0600, 0x0718), /* Lookup */
+   regmap_reg_range(0x0800, 0x0b70), /* QM */
+   regmap_reg_range(0x0C00, 0x0c80), /* PKT */
+   regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
+   regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
+   regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
+   regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
+   regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
+   regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
+   regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
+
+};
+
+static struct regmap_access_table ar8xxx_readable_table = {
+   .yes_ranges = ar8xxx_readable_ranges,
+   .n_yes_ranges = ARRAY_SIZE(ar8xxx_readable_ranges),
+};
+
+struct regmap_config ar8xxx_regmap_config = {
+   .reg_bits = 16,
+   .val_bits = 32,
+   .reg_stride = 4,
+   .max_register = 0x16ac, /* end MIB - Port6 range */
+   .reg_read = ar8xxx_regmap_read,
+   .reg_write = ar8xxx_regmap_write,
+   .rd_table = &ar8xxx_readable_table,
+};
+
 static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int port, int mode)
 {
int reg;
@@ -219,9 +270,17 @@ static int ar8xxx_set_pad_ctrl(struct dsa_switch *ds, int 
port, int mode)
 
 static int ar8xxx_setup(struct dsa_switch *ds)
 {
+   struct ar8xxx_priv *priv = ds_to_priv(ds);
struct net_device *netdev = ds->dst->pd->of_netdev;
int ret, i, phy_mode;
 
+   /* Start by setting up the register mapping */
+   priv->regmap = devm_regmap_init(ds->master_dev, NULL, ds,
+   &ar8xxx_regmap_config);
+
+   if (IS_ERR(priv->regmap))
+   pr_warn("regmap initialization failed");
+
/* Initialize CPU port pad mode (xMII type, delays...) */
phy_mode = of_get_phy_mode(netdev->dev.parent->of_node);
if (phy_mode < 0) {
@@ -365,6 +424,7 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
 
 static struct dsa_switch_driver ar8xxx_switch_driver = {
.tag_protocol   = DSA_TAG_PROTO_NONE,
+   .priv_size  = sizeof(struct ar8xxx_priv),
.probe  = ar8xxx_probe,
.setup  = ar8xxx_setup,
.set_addr   = ar8xxx_set_addr,
diff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h
index 7c7a125..98cc7ed 100644
--- a/drivers/net/dsa/ar8xxx.h
+++ b/drivers/net/dsa/ar8xxx.h
@@ -17,6 +17,11 @@
 #define __AR8XXX_H
 
 #include 
+#include 
+
+struct ar8xxx_priv {
+   struct regmap *regmap;
+};
 
 struct ar8xxx_mib_desc {
unsigned int size;
-- 
2.1.4

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[PATCH 1/7] net: dsa: add new driver for ar8xxx family

2015-05-28 Thread Mathieu Olivari 
This patch contains initial init & registration code for QCA8337. It
will detect a QCA8337 switch, if present and declared in DT/platform.

Each port will be represented through a standalone net_device interface,
as for other DSA switches. CPU can communicate with any of the ports by
setting an IP@ on ethN interface. Ports cannot communicate with each
other just yet.

Link status will be reported through polling, and we don't use any
encapsulation.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/dsa/Kconfig  |   7 ++
 drivers/net/dsa/Makefile |   1 +
 drivers/net/dsa/ar8xxx.c | 303 +++
 drivers/net/dsa/ar8xxx.h |  82 +
 net/dsa/dsa.c|   1 +
 5 files changed, 394 insertions(+)
 create mode 100644 drivers/net/dsa/ar8xxx.c
 create mode 100644 drivers/net/dsa/ar8xxx.h

diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 7ad0a4d..2aae541 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -65,4 +65,11 @@ config NET_DSA_BCM_SF2
  This enables support for the Broadcom Starfighter 2 Ethernet
  switch chips.
 
+config NET_DSA_AR8XXX
+   tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
+   depends on NET_DSA
+   ---help---
+ This enables support for the Qualcomm Atheros AR8XXX Ethernet
+ switch chips.
+
 endmenu
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index e2d51c4..7647687 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -14,3 +14,4 @@ ifdef CONFIG_NET_DSA_MV88E6171
 mv88e6xxx_drv-y += mv88e6171.o
 endif
 obj-$(CONFIG_NET_DSA_BCM_SF2)  += bcm_sf2.o
+obj-$(CONFIG_NET_DSA_AR8XXX)   += ar8xxx.o
diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
new file mode 100644
index 000..4ce3ffc
--- /dev/null
+++ b/drivers/net/dsa/ar8xxx.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2009 Felix Fietkau 
+ * Copyright (C) 2011-2012 Gabor Juhos 
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "ar8xxx.h"
+
+u32
+ar8xxx_mii_read32(struct mii_bus *bus, int phy_id, int regnum)
+{
+   u16 lo, hi;
+
+   lo = bus->read(bus, phy_id, regnum);
+   hi = bus->read(bus, phy_id, regnum + 1);
+
+   return (hi << 16) | lo;
+}
+
+void
+ar8xxx_mii_write32(struct mii_bus *bus, int phy_id, int regnum, u32 val)
+{
+   u16 lo, hi;
+
+   lo = val & 0x;
+   hi = (u16)(val >> 16);
+
+   bus->write(bus, phy_id, regnum, lo);
+   bus->write(bus, phy_id, regnum + 1, hi);
+}
+
+u32 ar8xxx_read(struct dsa_switch *ds, int reg)
+{
+   struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
+   u16 r1, r2, page;
+   u32 val;
+
+   split_addr((u32)reg, &r1, &r2, &page);
+
+   mutex_lock(&bus->mdio_lock);
+
+   bus->write(bus, 0x18, 0, page);
+   wait_for_page_switch();
+   val = ar8xxx_mii_read32(bus, 0x10 | r2, r1);
+
+   mutex_unlock(&bus->mdio_lock);
+
+   return val;
+}
+
+void ar8xxx_write(struct dsa_switch *ds, int reg, u32 val)
+{
+   struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
+   u16 r1, r2, page;
+
+   split_addr((u32)reg, &r1, &r2, &page);
+
+   mutex_lock(&bus->mdio_lock);
+
+   bus->write(bus, 0x18, 0, page);
+   wait_for_page_switch();
+   ar8xxx_mii_write32(bus, 0x10 | r2, r1, val);
+
+   mutex_unlock(&bus->mdio_lock);
+}
+
+u32
+ar8xxx_rmw(struct dsa_switch *ds, int reg, u32 mask, u32 val)
+{
+   struct mii_bus *bus = dsa_host_dev_to_mii_bus(ds->master_dev);
+   u16 r1, r2, page;
+   u32 ret;
+
+   split_addr((u32)reg, &r1, &r2, &page);
+
+   mutex_lock(&bus->mdio_lock);
+
+   bus->write(bus, 0x18, 0, page);
+   wait_for_page_switch();
+
+   ret = ar8xxx_mii_read32(bus, 0x10 | r2, r1);
+   ret &= ~mask;
+   ret |= val;
+   ar8xxx_mii_write32(bus, 0x10 | r2, r1, ret);
+
+   mutex_unlock(&bus->mdio_lock);
+
+   return ret;
+}
+
+static char *ar8xxx_probe(struct device *host_dev, int sw_addr)
+{
+   struct mii_bus *bus = dsa_host_dev_to_mii_bus(host_dev);
+   u32 phy_id;
+
+   if (!bus)
+   return NULL;
+
+   /* sw_addr is irrelevant as the switch occupies the MDIO bus from
+* addresses

[PATCH 7/7] Documentation: devicetree: add ar8xxx binding

2015-05-28 Thread Mathieu Olivari 
Add device-tree binding for ar8xxx switch families.

Signed-off-by: Mathieu Olivari 
---
 .../devicetree/bindings/net/dsa/qca-ar8xxx.txt | 70 ++
 1 file changed, 70 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt

diff --git a/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt 
b/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
new file mode 100644
index 000..f4fd3f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
@@ -0,0 +1,70 @@
+* Qualcomm Atheros AR8xxx switch family
+
+Required properties:
+
+- compatible: should be "qca,ar8xxx"
+- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
+- dsa,ethernet: phandle to the CPU network interface controller, see 
dsa/dsa.txt
+- #size-cells: must be 0
+- #address-cells: must be 2, see dsa/dsa.txt
+
+Subnodes:
+
+The integrated switch subnode should be specified according to the binding
+described in dsa/dsa.txt.
+
+Optional properties:
+
+- qca,port6-phy-mode: if specified, the driver will configure Port 6 in the
+  given phy-mode. See Documentation/devicetree/bindings/net/ethernet.txt for
+  the list of valid phy-mode.
+
+- qca,port6-phy-id: if specified, the driver will connect Port 6 to the PHY
+  given as a parameter. In this case, Port6 and the corresponding PHY will be
+  isolated from the rest of the switch. From a system perspective, they will
+  act as a regular PHY.
+
+Example:
+
+   dsa@0 {
+   compatible = "qca,ar8xxx";
+   #address-cells = <2>;
+   #size-cells = <0>;
+
+   dsa,ethernet = <ðernet0>;
+   dsa,mii-bus = <&mii_bus0>;
+
+   switch@0 {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   reg = <0 0>;/* MDIO address 0, switch 0 in tree */
+
+   qca,port6-phy-mode = "sgmii";
+   qca,port6-phy-id = <4>;
+
+   port@0 {
+   reg = <11>;
+   label = "cpu";
+   };
+
+   port@1 {
+   reg = <0>;
+   label = "lan1";
+   };
+
+   port@2 {
+   reg = <1>;
+   label = "lan2";
+   };
+
+   port@3 {
+   reg = <2>;
+   label = "lan3";
+   };
+
+   port@4 {
+   reg = <3>;
+   label = "lan4";
+   };
+   };
+   };
-- 
2.1.4

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[PATCH 5/7] net: dsa: ar8xxx: enable QCA header support on AR8xxx

2015-05-28 Thread Mathieu Olivari 
This change enable support for the QCA headers in QCA83337 driver.
A 2 bytes header will be added by the switch on every incoming packet
to identify the ingress port, and the DSA tagging code will add a
similar 2 bytes header to control which port is used to send a
particular packet.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/dsa/Kconfig  |  1 +
 drivers/net/dsa/ar8xxx.c | 28 ++--
 drivers/net/dsa/ar8xxx.h | 22 ++
 3 files changed, 49 insertions(+), 2 deletions(-)

diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index 17fb296..fa8b484 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -68,6 +68,7 @@ config NET_DSA_BCM_SF2
 config NET_DSA_AR8XXX
tristate "Qualcomm Atheros AR8XXX Ethernet switch family support"
depends on NET_DSA
+   select NET_DSA_TAG_QCA
select REGMAP
---help---
  This enables support for the Qualcomm Atheros AR8XXX Ethernet
diff --git a/drivers/net/dsa/ar8xxx.c b/drivers/net/dsa/ar8xxx.c
index 327abd4..4044614 100644
--- a/drivers/net/dsa/ar8xxx.c
+++ b/drivers/net/dsa/ar8xxx.c
@@ -292,15 +292,31 @@ static int ar8xxx_setup(struct dsa_switch *ds)
if (ret < 0)
return ret;
 
+   /* Enable CPU Port */
+   ar8xxx_reg_set(ds, AR8327_REG_GLOBAL_FW_CTRL0,
+  AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN);
+
/* Enable MIB counters */
ar8xxx_reg_set(ds, AR8327_REG_MIB, AR8327_MIB_CPU_KEEP);
ar8xxx_write(ds, AR8327_REG_MODULE_EN, AR8327_MODULE_EN_MIB);
 
+   /* Enable QCA header mode on Port 0 */
+   ar8xxx_write(ds, AR8327_REG_PORT_HDR_CTRL(0),
+AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_TX_S |
+AR8327_PORT_HDR_CTRL_ALL << AR8327_PORT_HDR_CTRL_RX_S);
+
/* Disable forwarding by default on all ports */
for (i = 0; i < AR8327_NUM_PORTS; i++)
ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(i),
   AR8327_PORT_LOOKUP_MEMBER, 0);
 
+   /* Forward all unknown frames to CPU port for Linux processing */
+   ar8xxx_write(ds, AR8327_REG_GLOBAL_FW_CTRL1,
+BIT(0) << AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S |
+BIT(0) << AR8327_GLOBAL_FW_CTRL1_BC_DP_S |
+BIT(0) << AR8327_GLOBAL_FW_CTRL1_MC_DP_S |
+BIT(0) << AR8327_GLOBAL_FW_CTRL1_UC_DP_S);
+
/* Setup connection between CPU ports & PHYs */
for (i = 0; i < DSA_MAX_PORTS; i++) {
/* CPU port gets connected to all PHYs in the switch */
@@ -312,8 +328,16 @@ static int ar8xxx_setup(struct dsa_switch *ds)
 
/* Invividual PHYs gets connected to CPU port only */
if (ds->phys_port_mask & BIT(i)) {
-   ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy_to_port(i)),
+   int phy = phy_to_port(i);
+
+   ar8xxx_rmw(ds, AR8327_PORT_LOOKUP_CTRL(phy),
   AR8327_PORT_LOOKUP_MEMBER, BIT(0));
+
+   /* Disable Auto-learning by default so the switch
+* doesn't try to forward the frame to another port
+*/
+   ar8xxx_reg_clear(ds, AR8327_PORT_LOOKUP_CTRL(phy),
+AR8327_PORT_LOOKUP_LEARN);
}
}
 
@@ -423,7 +447,7 @@ static void ar8xxx_poll_link(struct dsa_switch *ds)
 }
 
 static struct dsa_switch_driver ar8xxx_switch_driver = {
-   .tag_protocol   = DSA_TAG_PROTO_NONE,
+   .tag_protocol   = DSA_TAG_PROTO_QCA,
.priv_size  = sizeof(struct ar8xxx_priv),
.probe  = ar8xxx_probe,
.setup  = ar8xxx_setup,
diff --git a/drivers/net/dsa/ar8xxx.h b/drivers/net/dsa/ar8xxx.h
index 98cc7ed..e68b92a 100644
--- a/drivers/net/dsa/ar8xxx.h
+++ b/drivers/net/dsa/ar8xxx.h
@@ -62,6 +62,28 @@ struct ar8xxx_mib_desc {
 #define   AR8XXX_PORT_STATUS_LINK_AUTO BIT(9)
 #define   AR8XXX_PORT_STATUS_LINK_PAUSEBIT(10)
 
+#define AR8327_REG_PORT_HDR_CTRL(_i)   (0x9c + (_i * 4))
+#define   AR8327_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
+#define   AR8327_PORT_HDR_CTRL_RX_S2
+#define   AR8327_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
+#define   AR8327_PORT_HDR_CTRL_TX_S0
+#define   AR8327_PORT_HDR_CTRL_ALL 2
+#define   AR8327_PORT_HDR_CTRL_MGMT1
+#define   AR8327_PORT_HDR_CTRL_NONE0
+
+#define AR8327_REG_GLOBAL_FW_CTRL0 0x620
+#define   AR8327_GLOBAL_FW_CTRL0_CPU_PORT_EN   BIT(10)
+
+#define AR8327_REG_GLOBAL_FW_CTRL1 0x624
+#define   AR8327_GLOBAL_FW_CTRL1_IGMP_DP_MASK  GENMASK(30, 24)
+#define   AR8327_GLOBAL_FW_CTRL1_IGMP_DP_S 24
+#define   AR8327_GLOBAL_FW_CTRL1_BC_DP_MASKGENM

[PATCH 4/7] net: dsa: add QCA tag support

2015-05-28 Thread Mathieu Olivari 
QCA tags are used on QCA ar8xxx switch family. This change adds support
for encap/decap using 2 bytes header mode.

Signed-off-by: Mathieu Olivari 
---
 include/net/dsa.h  |   1 +
 net/dsa/Kconfig|   3 +
 net/dsa/Makefile   |   1 +
 net/dsa/dsa.c  |   5 ++
 net/dsa/dsa_priv.h |   2 +
 net/dsa/slave.c|   5 ++
 net/dsa/tag_qca.c  | 158 +
 7 files changed, 175 insertions(+)
 create mode 100644 net/dsa/tag_qca.c

diff --git a/include/net/dsa.h b/include/net/dsa.h
index fbca63b..64ddf6f 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -26,6 +26,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_TRAILER,
DSA_TAG_PROTO_EDSA,
DSA_TAG_PROTO_BRCM,
+   DSA_TAG_PROTO_QCA,
 };
 
 #define DSA_MAX_SWITCHES   4
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index ff7736f..4f3cce1 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -26,6 +26,9 @@ config NET_DSA_HWMON
  via the hwmon sysfs interface and exposes the onboard sensors.
 
 # tagging formats
+config NET_DSA_TAG_QCA
+   bool
+
 config NET_DSA_TAG_BRCM
bool
 
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index da06ed1..9feb86c 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -3,6 +3,7 @@ obj-$(CONFIG_NET_DSA) += dsa_core.o
 dsa_core-y += dsa.o slave.o
 
 # tagging formats
+dsa_core-$(CONFIG_NET_DSA_TAG_QCA) += tag_qca.o
 dsa_core-$(CONFIG_NET_DSA_TAG_BRCM) += tag_brcm.o
 dsa_core-$(CONFIG_NET_DSA_TAG_DSA) += tag_dsa.o
 dsa_core-$(CONFIG_NET_DSA_TAG_EDSA) += tag_edsa.o
diff --git a/net/dsa/dsa.c b/net/dsa/dsa.c
index fffb9aa..6010a7d 100644
--- a/net/dsa/dsa.c
+++ b/net/dsa/dsa.c
@@ -249,6 +249,11 @@ static int dsa_switch_setup_one(struct dsa_switch *ds, 
struct device *parent)
dst->rcv = brcm_netdev_ops.rcv;
break;
 #endif
+#ifdef CONFIG_NET_DSA_TAG_QCA
+   case DSA_TAG_PROTO_QCA:
+   dst->rcv = qca_netdev_ops.rcv;
+   break;
+#endif
case DSA_TAG_PROTO_NONE:
break;
default:
diff --git a/net/dsa/dsa_priv.h b/net/dsa/dsa_priv.h
index d5f1f9b..350c94b 100644
--- a/net/dsa/dsa_priv.h
+++ b/net/dsa/dsa_priv.h
@@ -74,5 +74,7 @@ extern const struct dsa_device_ops trailer_netdev_ops;
 /* tag_brcm.c */
 extern const struct dsa_device_ops brcm_netdev_ops;
 
+/* tag_qca.c */
+extern const struct dsa_device_ops qca_netdev_ops;
 
 #endif
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index 04ffad3..cd8f552 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -925,6 +925,11 @@ int dsa_slave_create(struct dsa_switch *ds, struct device 
*parent,
p->xmit = brcm_netdev_ops.xmit;
break;
 #endif
+#ifdef CONFIG_NET_DSA_TAG_QCA
+   case DSA_TAG_PROTO_QCA:
+   p->xmit = qca_netdev_ops.xmit;
+   break;
+#endif
default:
p->xmit = dsa_slave_notag_xmit;
break;
diff --git a/net/dsa/tag_qca.c b/net/dsa/tag_qca.c
new file mode 100644
index 000..8f02196
--- /dev/null
+++ b/net/dsa/tag_qca.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include 
+#include "dsa_priv.h"
+
+#define QCA_HDR_LEN2
+#define QCA_HDR_VERSION0x2
+
+#define QCA_HDR_RECV_VERSION_MASK  GENMASK(15, 14)
+#define QCA_HDR_RECV_VERSION_S 14
+#define QCA_HDR_RECV_PRIORITY_MASK GENMASK(13, 11)
+#define QCA_HDR_RECV_PRIORITY_S11
+#define QCA_HDR_RECV_TYPE_MASK GENMASK(10, 6)
+#define QCA_HDR_RECV_TYPE_S6
+#define QCA_HDR_RECV_FRAME_IS_TAGGED   BIT(3)
+#define QCA_HDR_RECV_SOURCE_PORT_MASK  GENMASK(2, 0)
+
+#define QCA_HDR_XMIT_VERSION_MASK  GENMASK(15, 14)
+#define QCA_HDR_XMIT_VERSION_S 14
+#define QCA_HDR_XMIT_PRIORITY_MASK GENMASK(13, 11)
+#define QCA_HDR_XMIT_PRIORITY_S11
+#define QCA_HDR_XMIT_CONTROL_MASK  GENMASK(10, 8)
+#define QCA_HDR_XMIT_CONTROL_S 8
+#define QCA_HDR_XMIT_FROM_CPU  BIT(7)
+#define QCA_HDR_XMIT_DP_BIT_MASK   GENMASK(6, 0)
+
+static inline int reg_to_port(int reg)
+{
+   if (reg < 5)
+   return reg + 1;
+
+   return -1;
+}
+
+static inline int port_to_reg(int port)
+{
+   if (port >= 1 && port <= 6)
+   return port - 1;
+
+   return -1;
+}
+
+static netdev_tx_t qca_tag_xmit(struct sk_buff *skb, struct net_device

[PATCH 0/7] net: dsa: add QCA AR8xxx switch family support

2015-05-28 Thread Mathieu Olivari 
This patch set adds initial support for AR8xxx switches using the DSA
subsystem. It currently supports QCA8337 switch, and can be extended to
other hardware in the same family.

This switch was already discussed in the following thread:
https://www.marc.info/?t=14260141744&r=1&w=2

Below is a typical picture of a QCA8337 used in a standard home gateway
configuration:

+---+   +---+
|   | SGMII |   |
|   eth0+---+   +-- 1000baseT MDI ("WAN")
|wan|   |  7-port   +-- 1000baseT MDI ("LAN1")
|   CPU |   |  ethernet +-- 1000baseT MDI ("LAN2")
|   | RGMII |  switch   +-- 1000baseT MDI ("LAN3")
|   eth1+---+  w/5 PHYs +-- 1000baseT MDI ("LAN4")
|lan|   |   |
+---+   +---+
  |   MDIO |
  \/

The switch is connected to the CPU using 2 xMII interfaces. As DSA only
supports one logical interface to the switch, we split the switch using
device-tree information into 2 parts:
*port 6 (one of the xMII switch port) will be dedicated to one
 particular Ethernet port. From a system perspective, it will be seen as
 a regular PHY.
*port 0 (the other xMII port) will act as the switch master interface

When 2 xMII are used, the switch will therefore be seen as 2 devices: 1
PHY + 1 DSA switch. The configuration of this split is done using driver
specific options in device-tree.

The exact properties are detailed in the Documentation patch below.

Mathieu Olivari (7):
  net: dsa: add new driver for ar8xxx family
  net: dsa: ar8xxx: add ethtool hw statistics support
  net: dsa: ar8xxx: add regmap support
  net: dsa: add QCA tag support
  net: dsa: ar8xxx: enable QCA header support on AR8xxx
  net: dsa: ar8xxx: add support for second xMII interfaces through DT
  Documentation: devicetree: add ar8xxx binding

 .../devicetree/bindings/net/dsa/qca-ar8xxx.txt |  70 +++
 drivers/net/dsa/Kconfig|   9 +
 drivers/net/dsa/Makefile   |   1 +
 drivers/net/dsa/ar8xxx.c   | 530 +
 drivers/net/dsa/ar8xxx.h   | 157 ++
 include/net/dsa.h  |   1 +
 net/dsa/Kconfig|   3 +
 net/dsa/Makefile   |   1 +
 net/dsa/dsa.c  |   6 +
 net/dsa/dsa_priv.h |   2 +
 net/dsa/slave.c|   5 +
 net/dsa/tag_qca.c  | 159 +++
 12 files changed, 944 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/dsa/qca-ar8xxx.txt
 create mode 100644 drivers/net/dsa/ar8xxx.c
 create mode 100644 drivers/net/dsa/ar8xxx.h
 create mode 100644 net/dsa/tag_qca.c

-- 
2.1.4

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[PATCH V2 1/5] clk: qcom: Add support for NSS/GMAC clocks and resets

2015-05-27 Thread Mathieu Olivari 
From: Stephen Boyd 

Add the NSS/GMAC clocks and the TCM clock and NSS resets.

Signed-off-by: Stephen Boyd 
Signed-off-by: Mathieu Olivari 
---
 drivers/clk/qcom/gcc-ipq806x.c   | 594 ++-
 include/dt-bindings/clock/qcom,gcc-ipq806x.h |   2 +
 include/dt-bindings/reset/qcom,gcc-ipq806x.h |  43 ++
 3 files changed, 638 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index a50936a..5639699 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -140,12 +140,47 @@ static struct clk_regmap pll14_vote = {
},
 };
 
+#define NSS_PLL_RATE(f, _l, _m, _n, i) \
+   {  \
+   .freq = f,  \
+   .l = _l, \
+   .m = _m, \
+   .n = _n, \
+   .ibits = i, \
+   }
+
+static struct pll_freq_tbl pll18_freq_tbl[] = {
+   NSS_PLL_RATE(55000, 44, 0, 1, 0x01495625),
+   NSS_PLL_RATE(73300, 58, 16, 25, 0x014b5625),
+};
+
+static struct clk_pll pll18 = {
+   .l_reg = 0x31a4,
+   .m_reg = 0x31a8,
+   .n_reg = 0x31ac,
+   .config_reg = 0x31b4,
+   .mode_reg = 0x31a0,
+   .status_reg = 0x31b8,
+   .status_bit = 16,
+   .post_div_shift = 16,
+   .post_div_width = 1,
+   .freq_tbl = pll18_freq_tbl,
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "pll18",
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .ops = &clk_pll_ops,
+   },
+};
+
 enum {
P_PXO,
P_PLL8,
P_PLL3,
P_PLL0,
P_CXO,
+   P_PLL14,
+   P_PLL18,
 };
 
 static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -197,6 +232,22 @@ static const char *gcc_pxo_pll8_pll0_map[] = {
"pll0_vote",
 };
 
+static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
+   { P_PXO, 0 },
+   { P_PLL8, 4 },
+   { P_PLL0, 2 },
+   { P_PLL14, 5 },
+   { P_PLL18, 1 }
+};
+
+static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = {
+   "pxo",
+   "pll8_vote",
+   "pll0_vote",
+   "pll14",
+   "pll18",
+};
+
 static struct freq_tbl clk_tbl_gsbi_uart[] = {
{  1843200, P_PLL8, 2,  6, 625 },
{  3686400, P_PLL8, 2, 12, 625 },
@@ -2202,6 +2253,472 @@ static struct clk_branch ebi2_aon_clk = {
},
 };
 
+static const struct freq_tbl clk_tbl_gmac[] = {
+   { 13300, P_PLL0, 1,  50, 301 },
+   { 26600, P_PLL0, 1, 127, 382 },
+   { }
+};
+
+static struct clk_dyn_rcg gmac_core1_src = {
+   .ns_reg[0] = 0x3cac,
+   .ns_reg[1] = 0x3cb0,
+   .md_reg[0] = 0x3ca4,
+   .md_reg[1] = 0x3ca8,
+   .bank_reg = 0x3ca0,
+   .mn[0] = {
+   .mnctr_en_bit = 8,
+   .mnctr_reset_bit = 7,
+   .mnctr_mode_shift = 5,
+   .n_val_shift = 16,
+   .m_val_shift = 16,
+   .width = 8,
+   },
+   .mn[1] = {
+   .mnctr_en_bit = 8,
+   .mnctr_reset_bit = 7,
+   .mnctr_mode_shift = 5,
+   .n_val_shift = 16,
+   .m_val_shift = 16,
+   .width = 8,
+   },
+   .s[0] = {
+   .src_sel_shift = 0,
+   .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
+   },
+   .s[1] = {
+   .src_sel_shift = 0,
+   .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
+   },
+   .p[0] = {
+   .pre_div_shift = 3,
+   .pre_div_width = 2,
+   },
+   .p[1] = {
+   .pre_div_shift = 3,
+   .pre_div_width = 2,
+   },
+   .mux_sel_bit = 0,
+   .freq_tbl = clk_tbl_gmac,
+   .clkr = {
+   .enable_reg = 0x3ca0,
+   .enable_mask = BIT(1),
+   .hw.init = &(struct clk_init_data){
+   .name = "gmac_core1_src",
+   .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+   .num_parents = 5,
+   .ops = &clk_dyn_rcg_ops,
+   },
+   },
+};
+
+static struct clk_branch gmac_core1_clk = {
+   .halt_reg = 0x3c20,
+   .halt_bit = 4,
+   .hwcg_reg = 0x3cb4,
+   .hwcg_bit = 6,
+   .clkr = {
+   .enable_reg = 0x3cb4,
+   .enable_mask = BIT(4),
+   .hw.init = &(struct clk_init_data){
+   .name = "gmac_core1_clk",
+   .parent_names = (const char *[]){
+   "gmac_core1_src",
+   },
+   .num_parents = 1,
+   .ops = &clk_branch_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+   },
+};
+
+static struct clk_dyn_rcg gmac_core2_src = {
+

[PATCH V2 2/5] stmmac: add phy-handle support to the platform layer

2015-05-27 Thread Mathieu Olivari 
On stmmac driver, PHY specification in device-tree was done using the
non-standard property "snps,phy-addr". Specifying a PHY on a different
MDIO bus that the one within the stmmac controller doesn't seem to be
possible when device-tree is used.

This change adds support for the phy-handle property, as specified in
Documentation/devicetree/bindings/net/ethernet.txt.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 28 ++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  6 -
 include/linux/stmmac.h |  1 +
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index e4f2739..31c6416 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -52,6 +52,7 @@
 #include "stmmac_ptp.h"
 #include "stmmac.h"
 #include 
+#include 
 
 #define STMMAC_ALIGN(x)L1_CACHE_ALIGN(x)
 
@@ -816,18 +817,25 @@ static int stmmac_init_phy(struct net_device *dev)
priv->speed = 0;
priv->oldduplex = -1;
 
-   if (priv->plat->phy_bus_name)
-   snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
-priv->plat->phy_bus_name, priv->plat->bus_id);
-   else
-   snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
-priv->plat->bus_id);
+   if (priv->plat->phy_node) {
+   phydev = of_phy_connect(dev, priv->plat->phy_node,
+   &stmmac_adjust_link, 0, interface);
+   } else {
+   if (priv->plat->phy_bus_name)
+   snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
+priv->plat->phy_bus_name, priv->plat->bus_id);
+   else
+   snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
+priv->plat->bus_id);
 
-   snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
-priv->plat->phy_addr);
-   pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
+   snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
+priv->plat->phy_addr);
+   pr_debug("stmmac_init_phy:  trying to attach to %s\n",
+phy_id_fmt);
 
-   phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
+   phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
+interface);
+   }
 
if (IS_ERR(phydev)) {
pr_err("%s: Could not attach to PHY\n", dev->name);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 1664c01..8d23155 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "stmmac.h"
 #include "stmmac_platform.h"
@@ -144,13 +145,16 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
/* Default to phy auto-detection */
plat->phy_addr = -1;
 
+   /* If we find a phy-handle property, use it as the PHY */
+   plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0)
dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n");
 
-   if (plat->phy_bus_name)
+   if (plat->phy_node || plat->phy_bus_name)
plat->mdio_bus_data = NULL;
else
plat->mdio_bus_data =
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 7f484a2..c735f5c 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -99,6 +99,7 @@ struct plat_stmmacenet_data {
int phy_addr;
int interface;
struct stmmac_mdio_bus_data *mdio_bus_data;
+   struct device_node *phy_node;
struct stmmac_dma_cfg *dma_cfg;
int clk_csr;
int has_gmac;
-- 
2.1.4

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[PATCH V2 0/5] Add support for QCA IPQ806x Ethernet GMAC controller

2015-05-27 Thread Mathieu Olivari 
This patch set adds support for the integrated Ethernet GMAC controller
on QCA IPQ806x SoC. This controller is based on a Gigabit Synopsys
DesignWare IP, already supported in the stmmac driver located in
drivers/net/ethernet/stmicro/stmmac.

This change is done as a follow-up to the following thread:
*http://www.spinics.net/lists/netdev/msg311265.html
While previous attempt was creating a new driver to drive this controller,
this new post leverages the existing stmmac driver by implementing the
SoC specific glue to it.

Aside from the pure stmmac glue layer, we have a couple of related
patches:
*IPQ806x NSS clock addition is cherry-picked and refreshed from the
 following thread: https://lkml.org/lkml/2014/8/6/390
*phy-handle and fixed-link support are also added in this change set so the
 driver can be fully functional on platforms using device-trees as well as
 ethernet switches.

V2:
 *Fix MODULE_LICENSE to "Dual BSD/GPL" as the dwmac-ipq806x.c is using
  ISC license.

Mathieu Olivari (4):
  stmmac: add phy-handle support to the platform layer
  stmmac: add fixed-link device-tree support
  stmmac: add ipq806x glue layer
  net: stmmac: ipq806x: document device tree bindings

Stephen Boyd (1):
  clk: qcom: Add support for NSS/GMAC clocks and resets

 .../devicetree/bindings/net/ipq806x-dwmac.txt  |  35 ++
 drivers/clk/qcom/gcc-ipq806x.c | 594 -
 drivers/net/ethernet/stmicro/stmmac/Kconfig|  14 +
 drivers/net/ethernet/stmicro/stmmac/Makefile   |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-ipq806x.c| 365 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  30 +-
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  18 +-
 include/dt-bindings/clock/qcom,gcc-ipq806x.h   |   2 +
 include/dt-bindings/reset/qcom,gcc-ipq806x.h   |  43 ++
 include/linux/stmmac.h |   1 +
 10 files changed, 1089 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

-- 
2.1.4

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[PATCH V2 3/5] stmmac: add fixed-link device-tree support

2015-05-27 Thread Mathieu Olivari 
In case DT is used, this change adds the ability to the stmmac driver to
detect a fixed-link PHY, instanciate it, and use it during
phy_connect().

Fixed link PHYs DT usage is described in:
Documentation/devicetree/bindings/net/fixed-link.txt

Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c |  2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 +++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 31c6416..c46178c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -856,7 +856,7 @@ static int stmmac_init_phy(struct net_device *dev)
 * device as well.
 * Note: phydev->phy_id is the result of reading the UID PHY registers.
 */
-   if (phydev->phy_id == 0) {
+   if (!priv->plat->phy_node && phydev->phy_id == 0) {
phy_disconnect(phydev);
return -ENODEV;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8d23155..f3918c7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -148,6 +148,14 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
/* If we find a phy-handle property, use it as the PHY */
plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
 
+   /* If phy-handle is not specified, check if we have a fixed-phy */
+   if (!plat->phy_node && of_phy_is_fixed_link(np)) {
+   if ((of_phy_register_fixed_link(np) < 0))
+   return -ENODEV;
+
+   plat->phy_node = of_node_get(np);
+   }
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
@@ -212,8 +220,10 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
if (of_find_property(np, "snps,pbl", NULL)) {
dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
   GFP_KERNEL);
-   if (!dma_cfg)
+   if (!dma_cfg) {
+   of_node_put(np);
return -ENOMEM;
+   }
plat->dma_cfg = dma_cfg;
of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
dma_cfg->fixed_burst =
-- 
2.1.4

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[PATCH V2 4/5] stmmac: add ipq806x glue layer

2015-05-27 Thread Mathieu Olivari 
The ethernet controller available in IPQ806x is a Synopsys DesignWare
Gigabit MAC IP core, already supported by the stmmac driver.

This glue layer implements some platform specific settings required to
get the controller working on an IPQ806x based platform.

Signed-off-by: Mathieu Olivari 
---

Notes:
v2:
 *fix MODULE_LICENSE to "Dual BSD/GPL" as this file is using ISC license

 drivers/net/ethernet/stmicro/stmmac/Kconfig|  14 +
 drivers/net/ethernet/stmicro/stmmac/Makefile   |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-ipq806x.c| 365 +
 3 files changed, 380 insertions(+)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig 
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 731e045..cec147d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -16,6 +16,7 @@ if STMMAC_ETH
 config STMMAC_PLATFORM
tristate "STMMAC Platform bus support"
depends on STMMAC_ETH
+   select MFD_SYSCON
default y
---help---
  This selects the platform specific bus support for the stmmac driver.
@@ -36,6 +37,19 @@ config DWMAC_GENERIC
  platform specific code to function or is using platform
  data for setup.
 
+config DWMAC_IPQ806X
+   tristate "QCA IPQ806x DWMAC support"
+   default ARCH_QCOM
+   depends on OF
+   select MFD_SYSCON
+   help
+ Support for QCA IPQ806X DWMAC Ethernet.
+
+ This selects the IPQ806x SoC glue layer support for the stmmac
+ device driver. This driver does not use any of the hardware
+ acceleration features available on this SoC. Network devices
+ will behave like standard non-accelerated ethernet interfaces.
+
 config DWMAC_LPC18XX
tristate "NXP LPC18xx/43xx DWMAC support"
default ARCH_LPC18XX
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile 
b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 92e714a..b390161 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -6,6 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o 
ring_mode.o  \
 
 # Ordering matters. Generic driver must be last.
 obj-$(CONFIG_STMMAC_PLATFORM)  += stmmac-platform.o
+obj-$(CONFIG_DWMAC_IPQ806X)+= dwmac-ipq806x.o
 obj-$(CONFIG_DWMAC_LPC18XX)+= dwmac-lpc18xx.o
 obj-$(CONFIG_DWMAC_MESON)  += dwmac-meson.o
 obj-$(CONFIG_DWMAC_ROCKCHIP)   += dwmac-rk.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
new file mode 100644
index 000..7e3129e
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
@@ -0,0 +1,365 @@
+/*
+ * Qualcomm Atheros IPQ806x GMAC glue layer
+ *
+ * Copyright (C) 2015 The Linux Foundation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "stmmac_platform.h"
+
+#define NSS_COMMON_CLK_GATE0x8
+#define NSS_COMMON_CLK_GATE_PTP_EN(x)  BIT(0x10 + x)
+#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
+#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
+#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x)  BIT(0x4 + x)
+#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x)  BIT(0x0 + x)
+
+#define NSS_COMMON_CLK_DIV00xC
+#define NSS_COMMON_CLK_DIV_OFFSET(x)   (x * 8)
+#define NSS_COMMON_CLK_DIV_MASK0x7f
+
+#define NSS_COMMON_CLK_SRC_CTRL0x14
+#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x)  (1 << x)
+/* Mode is coded on 1 bit but is different depending on the MAC ID:
+ * MAC0: QSGMII=0 RGMII=1
+ * MAC1: QSGMII=0 SGMII=0 RGMII=1
+ * MAC2 & MAC3: QSGMII=0 SGMII=1
+ */
+#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x)   1
+#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x)   ((x >= 2) ? 1 : 0)
+
+#define NSS_COMMON_MACSEC_CTL  0x28
+#define NSS_COMMON_MACSEC_CTL_EXT_BYPASS_EN(x) (1 << x)
+
+#define NSS_COMMON_GMA

[PATCH V2 5/5] net: stmmac: ipq806x: document device tree bindings

2015-05-27 Thread Mathieu Olivari 
Add the device tree bindings documentation for the QCA IPQ806x
variant of the Synopsys DesignWare MAC.

Signed-off-by: Mathieu Olivari 
---
 .../devicetree/bindings/net/ipq806x-dwmac.txt  | 35 ++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt

diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt 
b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
new file mode 100644
index 000..6d7ab4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
@@ -0,0 +1,35 @@
+* IPQ806x DWMAC Ethernet controller
+
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file net/stmmac.txt with the following changes.
+
+Required properties:
+
+- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
+ and any applicable more detailed version number
+ described in net/stmmac.txt
+
+- qcom,nss-common: should contain a phandle to a syscon device mapping the
+  nss-common registers.
+
+- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
+  qsgmii-csr registers.
+
+Example:
+
+   gmac: ethernet@3700 {
+   device_type = "network";
+   compatible = "qcom,ipq806x-gmac";
+   reg = <0x3700 0x20>;
+   interrupts = ;
+   interrupt-names = "macirq";
+
+   qcom,nss-common = <&nss_common>;
+   qcom,qsgmii-csr = <&qsgmii_csr>;
+
+   clocks = <&gcc GMAC_CORE1_CLK>;
+   clock-names = "stmmaceth";
+
+   resets = <&gcc GMAC_CORE1_RESET>;
+   reset-names = "stmmaceth";
+   };
-- 
2.1.4

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RE: [PATCH 4/5] stmmac: add ipq806x glue layer

2015-05-27 Thread Mathieu Olivari 
My bad. This is ISC license. MODULE_LICENSE should actually be "Dual BSD/GPL".
Same license is used in other places in the kernel like 
drivers/net/wireless/ath/ath10k/pci.c.
I'll post a v2.
Thanks,
Mathieu

-Original Message-
From: Paul Bolle [mailto:pebo...@tiscali.nl] 
Sent: Wednesday, May 27, 2015 12:04 AM
To: Mathieu Olivari
Cc: robh...@kernel.org; pawel.m...@arm.com; mark.rutl...@arm.com; 
ijc+devicet...@hellion.org.uk; ga...@codeaurora.org; mturque...@linaro.org; 
sb...@codeaurora.org; peppe.cavall...@st.com; agr...@codeaurora.org; 
jo...@codeaurora.org; arch...@codeaurora.org; georgi.dja...@linaro.org; 
w...@the-dreams.de; rna...@codeaurora.org; da...@davemloft.net; 
vbrid...@opensource.altera.com; devicet...@vger.kernel.org; 
linux-ker...@vger.kernel.org; linux-...@vger.kernel.org; netdev@vger.kernel.org
Subject: Re: [PATCH 4/5] stmmac: add ipq806x glue layer

Just a nit: a license mismatch.

On Tue, 2015-05-26 at 12:27 -0700, Mathieu Olivari wrote:
> --- /dev/null
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

> + * Permission to use, copy, modify, and/or distribute this software 
> + for any
> + * purpose with or without fee is hereby granted, provided that the 
> + above
> + * copyright notice and this permission notice appear in all copies.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 
> + WARRANTIES
> + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
> + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE 
> + LIABLE FOR
> + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY 
> + DAMAGES
> + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN 
> + AN
> + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING 
> + OUT OF
> + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

I have no idea which license this is.

> +MODULE_LICENSE("GPL");

But I do know that it's not GPL v2 or later (see include/linux/module.h).


Paul Bolle


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[PATCH 0/5] Add support for QCA IPQ806x Ethernet GMAC controller

2015-05-26 Thread Mathieu Olivari 
This patch set adds support for the integrated Ethernet GMAC controller
on QCA IPQ806x SoC. This controller is based on a Gigabit Synopsys
DesignWare IP, already supported in the stmmac driver located in
drivers/net/ethernet/stmicro/stmmac.

This change is done as a follow-up to the following thread:
*http://www.spinics.net/lists/netdev/msg311265.html
While previous attempt was creating a new driver to drive this controller,
this new post leverages the existing stmmac driver by implementing the
SoC specific glue to it.

Aside from the pure stmmac glue layer, we have a couple of related
patches:
*IPQ806x NSS clock addition is cherry-picked and refreshed from the
 following thread: https://lkml.org/lkml/2014/8/6/390
*phy-handle and fixed-link support are also added in this change set so the
 driver can be fully functional on platforms using device-trees as well as
 ethernet switches.

Mathieu Olivari (4):
  stmmac: add phy-handle support to the platform layer
  stmmac: add fixed-link device-tree support
  stmmac: add ipq806x glue layer
  net: stmmac: ipq806x: document device tree bindings

Stephen Boyd (1):
  clk: qcom: Add support for NSS/GMAC clocks and resets

 .../devicetree/bindings/net/ipq806x-dwmac.txt  |  35 ++
 drivers/clk/qcom/gcc-ipq806x.c | 594 -
 drivers/net/ethernet/stmicro/stmmac/Kconfig|  14 +
 drivers/net/ethernet/stmicro/stmmac/Makefile   |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-ipq806x.c| 365 +
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  |  30 +-
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  18 +-
 include/dt-bindings/clock/qcom,gcc-ipq806x.h   |   2 +
 include/dt-bindings/reset/qcom,gcc-ipq806x.h   |  43 ++
 include/linux/stmmac.h |   1 +
 10 files changed, 1089 insertions(+), 14 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

-- 
2.1.4

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[PATCH 3/5] stmmac: add fixed-link device-tree support

2015-05-26 Thread Mathieu Olivari 
In case DT is used, this change adds the ability to the stmmac driver to
detect a fixed-link PHY, instanciate it, and use it during
phy_connect().

Fixed link PHYs DT usage is described in:
Documentation/devicetree/bindings/net/fixed-link.txt

Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c |  2 +-
 drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 12 +++-
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 31c6416..c46178c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -856,7 +856,7 @@ static int stmmac_init_phy(struct net_device *dev)
 * device as well.
 * Note: phydev->phy_id is the result of reading the UID PHY registers.
 */
-   if (phydev->phy_id == 0) {
+   if (!priv->plat->phy_node && phydev->phy_id == 0) {
phy_disconnect(phydev);
return -ENODEV;
}
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 8d23155..f3918c7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -148,6 +148,14 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
/* If we find a phy-handle property, use it as the PHY */
plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
 
+   /* If phy-handle is not specified, check if we have a fixed-phy */
+   if (!plat->phy_node && of_phy_is_fixed_link(np)) {
+   if ((of_phy_register_fixed_link(np) < 0))
+   return -ENODEV;
+
+   plat->phy_node = of_node_get(np);
+   }
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
@@ -212,8 +220,10 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
if (of_find_property(np, "snps,pbl", NULL)) {
dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*dma_cfg),
   GFP_KERNEL);
-   if (!dma_cfg)
+   if (!dma_cfg) {
+   of_node_put(np);
return -ENOMEM;
+   }
plat->dma_cfg = dma_cfg;
of_property_read_u32(np, "snps,pbl", &dma_cfg->pbl);
dma_cfg->fixed_burst =
-- 
2.1.4

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[PATCH 5/5] net: stmmac: ipq806x: document device tree bindings

2015-05-26 Thread Mathieu Olivari 
Add the device tree bindings documentation for the QCA IPQ806x
variant of the Synopsys DesignWare MAC.

Signed-off-by: Mathieu Olivari 
---
 .../devicetree/bindings/net/ipq806x-dwmac.txt  | 35 ++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt

diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt 
b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
new file mode 100644
index 000..6d7ab4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
@@ -0,0 +1,35 @@
+* IPQ806x DWMAC Ethernet controller
+
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file net/stmmac.txt with the following changes.
+
+Required properties:
+
+- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
+ and any applicable more detailed version number
+ described in net/stmmac.txt
+
+- qcom,nss-common: should contain a phandle to a syscon device mapping the
+  nss-common registers.
+
+- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
+  qsgmii-csr registers.
+
+Example:
+
+   gmac: ethernet@3700 {
+   device_type = "network";
+   compatible = "qcom,ipq806x-gmac";
+   reg = <0x3700 0x20>;
+   interrupts = ;
+   interrupt-names = "macirq";
+
+   qcom,nss-common = <&nss_common>;
+   qcom,qsgmii-csr = <&qsgmii_csr>;
+
+   clocks = <&gcc GMAC_CORE1_CLK>;
+   clock-names = "stmmaceth";
+
+   resets = <&gcc GMAC_CORE1_RESET>;
+   reset-names = "stmmaceth";
+   };
-- 
2.1.4

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[PATCH 1/5] clk: qcom: Add support for NSS/GMAC clocks and resets

2015-05-26 Thread Mathieu Olivari 
From: Stephen Boyd 

Add the NSS/GMAC clocks and the TCM clock and NSS resets.

Signed-off-by: Stephen Boyd 
Signed-off-by: Mathieu Olivari 
---
 drivers/clk/qcom/gcc-ipq806x.c   | 594 ++-
 include/dt-bindings/clock/qcom,gcc-ipq806x.h |   2 +
 include/dt-bindings/reset/qcom,gcc-ipq806x.h |  43 ++
 3 files changed, 638 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index a50936a..5639699 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -140,12 +140,47 @@ static struct clk_regmap pll14_vote = {
},
 };
 
+#define NSS_PLL_RATE(f, _l, _m, _n, i) \
+   {  \
+   .freq = f,  \
+   .l = _l, \
+   .m = _m, \
+   .n = _n, \
+   .ibits = i, \
+   }
+
+static struct pll_freq_tbl pll18_freq_tbl[] = {
+   NSS_PLL_RATE(55000, 44, 0, 1, 0x01495625),
+   NSS_PLL_RATE(73300, 58, 16, 25, 0x014b5625),
+};
+
+static struct clk_pll pll18 = {
+   .l_reg = 0x31a4,
+   .m_reg = 0x31a8,
+   .n_reg = 0x31ac,
+   .config_reg = 0x31b4,
+   .mode_reg = 0x31a0,
+   .status_reg = 0x31b8,
+   .status_bit = 16,
+   .post_div_shift = 16,
+   .post_div_width = 1,
+   .freq_tbl = pll18_freq_tbl,
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "pll18",
+   .parent_names = (const char *[]){ "pxo" },
+   .num_parents = 1,
+   .ops = &clk_pll_ops,
+   },
+};
+
 enum {
P_PXO,
P_PLL8,
P_PLL3,
P_PLL0,
P_CXO,
+   P_PLL14,
+   P_PLL18,
 };
 
 static const struct parent_map gcc_pxo_pll8_map[] = {
@@ -197,6 +232,22 @@ static const char *gcc_pxo_pll8_pll0_map[] = {
"pll0_vote",
 };
 
+static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
+   { P_PXO, 0 },
+   { P_PLL8, 4 },
+   { P_PLL0, 2 },
+   { P_PLL14, 5 },
+   { P_PLL18, 1 }
+};
+
+static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = {
+   "pxo",
+   "pll8_vote",
+   "pll0_vote",
+   "pll14",
+   "pll18",
+};
+
 static struct freq_tbl clk_tbl_gsbi_uart[] = {
{  1843200, P_PLL8, 2,  6, 625 },
{  3686400, P_PLL8, 2, 12, 625 },
@@ -2202,6 +2253,472 @@ static struct clk_branch ebi2_aon_clk = {
},
 };
 
+static const struct freq_tbl clk_tbl_gmac[] = {
+   { 13300, P_PLL0, 1,  50, 301 },
+   { 26600, P_PLL0, 1, 127, 382 },
+   { }
+};
+
+static struct clk_dyn_rcg gmac_core1_src = {
+   .ns_reg[0] = 0x3cac,
+   .ns_reg[1] = 0x3cb0,
+   .md_reg[0] = 0x3ca4,
+   .md_reg[1] = 0x3ca8,
+   .bank_reg = 0x3ca0,
+   .mn[0] = {
+   .mnctr_en_bit = 8,
+   .mnctr_reset_bit = 7,
+   .mnctr_mode_shift = 5,
+   .n_val_shift = 16,
+   .m_val_shift = 16,
+   .width = 8,
+   },
+   .mn[1] = {
+   .mnctr_en_bit = 8,
+   .mnctr_reset_bit = 7,
+   .mnctr_mode_shift = 5,
+   .n_val_shift = 16,
+   .m_val_shift = 16,
+   .width = 8,
+   },
+   .s[0] = {
+   .src_sel_shift = 0,
+   .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
+   },
+   .s[1] = {
+   .src_sel_shift = 0,
+   .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
+   },
+   .p[0] = {
+   .pre_div_shift = 3,
+   .pre_div_width = 2,
+   },
+   .p[1] = {
+   .pre_div_shift = 3,
+   .pre_div_width = 2,
+   },
+   .mux_sel_bit = 0,
+   .freq_tbl = clk_tbl_gmac,
+   .clkr = {
+   .enable_reg = 0x3ca0,
+   .enable_mask = BIT(1),
+   .hw.init = &(struct clk_init_data){
+   .name = "gmac_core1_src",
+   .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
+   .num_parents = 5,
+   .ops = &clk_dyn_rcg_ops,
+   },
+   },
+};
+
+static struct clk_branch gmac_core1_clk = {
+   .halt_reg = 0x3c20,
+   .halt_bit = 4,
+   .hwcg_reg = 0x3cb4,
+   .hwcg_bit = 6,
+   .clkr = {
+   .enable_reg = 0x3cb4,
+   .enable_mask = BIT(4),
+   .hw.init = &(struct clk_init_data){
+   .name = "gmac_core1_clk",
+   .parent_names = (const char *[]){
+   "gmac_core1_src",
+   },
+   .num_parents = 1,
+   .ops = &clk_branch_ops,
+   .flags = CLK_SET_RATE_PARENT,
+   },
+   },
+};
+
+static struct clk_dyn_rcg gmac_core2_src = {
+

[PATCH 4/5] stmmac: add ipq806x glue layer

2015-05-26 Thread Mathieu Olivari 
The ethernet controller available in IPQ806x is a Synopsys DesignWare
Gigabit MAC IP core, already supported by the stmmac driver.

This glue layer implements some platform specific settings required to
get the controller working on an IPQ806x based platform.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/Kconfig|  14 +
 drivers/net/ethernet/stmicro/stmmac/Makefile   |   1 +
 .../net/ethernet/stmicro/stmmac/dwmac-ipq806x.c| 365 +
 3 files changed, 380 insertions(+)
 create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c

diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig 
b/drivers/net/ethernet/stmicro/stmmac/Kconfig
index 731e045..cec147d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
+++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
@@ -16,6 +16,7 @@ if STMMAC_ETH
 config STMMAC_PLATFORM
tristate "STMMAC Platform bus support"
depends on STMMAC_ETH
+   select MFD_SYSCON
default y
---help---
  This selects the platform specific bus support for the stmmac driver.
@@ -36,6 +37,19 @@ config DWMAC_GENERIC
  platform specific code to function or is using platform
  data for setup.
 
+config DWMAC_IPQ806X
+   tristate "QCA IPQ806x DWMAC support"
+   default ARCH_QCOM
+   depends on OF
+   select MFD_SYSCON
+   help
+ Support for QCA IPQ806X DWMAC Ethernet.
+
+ This selects the IPQ806x SoC glue layer support for the stmmac
+ device driver. This driver does not use any of the hardware
+ acceleration features available on this SoC. Network devices
+ will behave like standard non-accelerated ethernet interfaces.
+
 config DWMAC_LPC18XX
tristate "NXP LPC18xx/43xx DWMAC support"
default ARCH_LPC18XX
diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile 
b/drivers/net/ethernet/stmicro/stmmac/Makefile
index 92e714a..b390161 100644
--- a/drivers/net/ethernet/stmicro/stmmac/Makefile
+++ b/drivers/net/ethernet/stmicro/stmmac/Makefile
@@ -6,6 +6,7 @@ stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o 
ring_mode.o  \
 
 # Ordering matters. Generic driver must be last.
 obj-$(CONFIG_STMMAC_PLATFORM)  += stmmac-platform.o
+obj-$(CONFIG_DWMAC_IPQ806X)+= dwmac-ipq806x.o
 obj-$(CONFIG_DWMAC_LPC18XX)+= dwmac-lpc18xx.o
 obj-$(CONFIG_DWMAC_MESON)  += dwmac-meson.o
 obj-$(CONFIG_DWMAC_ROCKCHIP)   += dwmac-rk.o
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c 
b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
new file mode 100644
index 000..577b716
--- /dev/null
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-ipq806x.c
@@ -0,0 +1,365 @@
+/*
+ * Qualcomm Atheros IPQ806x GMAC glue layer
+ *
+ * Copyright (C) 2015 The Linux Foundation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "stmmac_platform.h"
+
+#define NSS_COMMON_CLK_GATE0x8
+#define NSS_COMMON_CLK_GATE_PTP_EN(x)  BIT(0x10 + x)
+#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
+#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
+#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x)  BIT(0x4 + x)
+#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x)  BIT(0x0 + x)
+
+#define NSS_COMMON_CLK_DIV00xC
+#define NSS_COMMON_CLK_DIV_OFFSET(x)   (x * 8)
+#define NSS_COMMON_CLK_DIV_MASK0x7f
+
+#define NSS_COMMON_CLK_SRC_CTRL0x14
+#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x)  (1 << x)
+/* Mode is coded on 1 bit but is different depending on the MAC ID:
+ * MAC0: QSGMII=0 RGMII=1
+ * MAC1: QSGMII=0 SGMII=0 RGMII=1
+ * MAC2 & MAC3: QSGMII=0 SGMII=1
+ */
+#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x)   1
+#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x)   ((x >= 2) ? 1 : 0)
+
+#define NSS_COMMON_MACSEC_CTL  0x28
+#define NSS_COMMON_MACSEC_CTL_EXT_BYPASS_EN(x) (1 << x)
+
+#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
+#define NSS_COMMON_GMAC_CTL_CSYS_REQ   BIT

[PATCH 2/5] stmmac: add phy-handle support to the platform layer

2015-05-26 Thread Mathieu Olivari 
On stmmac driver, PHY specification in device-tree was done using the
non-standard property "snps,phy-addr". Specifying a PHY on a different
MDIO bus that the one within the stmmac controller doesn't seem to be
possible when device-tree is used.

This change adds support for the phy-handle property, as specified in
Documentation/devicetree/bindings/net/ethernet.txt.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c  | 28 ++
 .../net/ethernet/stmicro/stmmac/stmmac_platform.c  |  6 -
 include/linux/stmmac.h |  1 +
 3 files changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index e4f2739..31c6416 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -52,6 +52,7 @@
 #include "stmmac_ptp.h"
 #include "stmmac.h"
 #include 
+#include 
 
 #define STMMAC_ALIGN(x)L1_CACHE_ALIGN(x)
 
@@ -816,18 +817,25 @@ static int stmmac_init_phy(struct net_device *dev)
priv->speed = 0;
priv->oldduplex = -1;
 
-   if (priv->plat->phy_bus_name)
-   snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
-priv->plat->phy_bus_name, priv->plat->bus_id);
-   else
-   snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
-priv->plat->bus_id);
+   if (priv->plat->phy_node) {
+   phydev = of_phy_connect(dev, priv->plat->phy_node,
+   &stmmac_adjust_link, 0, interface);
+   } else {
+   if (priv->plat->phy_bus_name)
+   snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x",
+priv->plat->phy_bus_name, priv->plat->bus_id);
+   else
+   snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x",
+priv->plat->bus_id);
 
-   snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
-priv->plat->phy_addr);
-   pr_debug("stmmac_init_phy:  trying to attach to %s\n", phy_id_fmt);
+   snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
+priv->plat->phy_addr);
+   pr_debug("stmmac_init_phy:  trying to attach to %s\n",
+phy_id_fmt);
 
-   phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, interface);
+   phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link,
+interface);
+   }
 
if (IS_ERR(phydev)) {
pr_err("%s: Could not attach to PHY\n", dev->name);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
index 1664c01..8d23155 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "stmmac.h"
 #include "stmmac_platform.h"
@@ -144,13 +145,16 @@ static int stmmac_probe_config_dt(struct platform_device 
*pdev,
/* Default to phy auto-detection */
plat->phy_addr = -1;
 
+   /* If we find a phy-handle property, use it as the PHY */
+   plat->phy_node = of_parse_phandle(np, "phy-handle", 0);
+
/* "snps,phy-addr" is not a standard property. Mark it as deprecated
 * and warn of its use. Remove this when phy node support is added.
 */
if (of_property_read_u32(np, "snps,phy-addr", &plat->phy_addr) == 0)
dev_warn(&pdev->dev, "snps,phy-addr property is deprecated\n");
 
-   if (plat->phy_bus_name)
+   if (plat->phy_node || plat->phy_bus_name)
plat->mdio_bus_data = NULL;
else
plat->mdio_bus_data =
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index 7f484a2..c735f5c 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -99,6 +99,7 @@ struct plat_stmmacenet_data {
int phy_addr;
int interface;
struct stmmac_mdio_bus_data *mdio_bus_data;
+   struct device_node *phy_node;
struct stmmac_dma_cfg *dma_cfg;
int clk_csr;
int has_gmac;
-- 
2.1.4

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[PATCH] net: stmmac: create one debugfs dir per net-device

2015-05-22 Thread Mathieu Olivari 
stmmac DebugFS entries are currently global to the driver. As a result,
having more than one stmmac device in the system creates the following
error:
* ERROR stmmaceth, debugfs create directory failed
* stmmac_hw_setup: failed debugFS registration

This also results in being able to access the debugfs information for
the first registered device only.

This patch changes the debugfs structure to have one sub-directory per
net-device. Files under "/sys/kernel/debug/stmmaceth" will now show-up
under /sys/kernel/debug/stmmaceth/ethN/.

Signed-off-by: Mathieu Olivari 
---
 drivers/net/ethernet/stmicro/stmmac/stmmac.h  |  6 ++
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 76 ---
 2 files changed, 59 insertions(+), 23 deletions(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h 
b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index 9cbcae2..1f3b33a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -125,6 +125,12 @@ struct stmmac_priv {
int use_riwt;
int irq_wake;
spinlock_t ptp_lock;
+
+#ifdef CONFIG_DEBUG_FS
+   struct dentry *dbgfs_dir;
+   struct dentry *dbgfs_rings_status;
+   struct dentry *dbgfs_dma_cap;
+#endif
 };
 
 int stmmac_mdio_unregister(struct net_device *ndev);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c 
b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index c46178c..a515673 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -119,7 +119,7 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id);
 
 #ifdef CONFIG_DEBUG_FS
 static int stmmac_init_fs(struct net_device *dev);
-static void stmmac_exit_fs(void);
+static void stmmac_exit_fs(struct net_device *dev);
 #endif
 
 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x))
@@ -1922,7 +1922,7 @@ static int stmmac_release(struct net_device *dev)
netif_carrier_off(dev);
 
 #ifdef CONFIG_DEBUG_FS
-   stmmac_exit_fs();
+   stmmac_exit_fs(dev);
 #endif
 
stmmac_release_ptp(priv);
@@ -2514,8 +2514,6 @@ static int stmmac_ioctl(struct net_device *dev, struct 
ifreq *rq, int cmd)
 
 #ifdef CONFIG_DEBUG_FS
 static struct dentry *stmmac_fs_dir;
-static struct dentry *stmmac_rings_status;
-static struct dentry *stmmac_dma_cap;
 
 static void sysfs_display_ring(void *head, int size, int extend_desc,
   struct seq_file *seq)
@@ -2654,36 +2652,39 @@ static const struct file_operations stmmac_dma_cap_fops 
= {
 
 static int stmmac_init_fs(struct net_device *dev)
 {
-   /* Create debugfs entries */
-   stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL);
+   struct stmmac_priv *priv = netdev_priv(dev);
+
+   /* Create per netdev entries */
+   priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir);
 
-   if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) {
-   pr_err("ERROR %s, debugfs create directory failed\n",
-  STMMAC_RESOURCE_NAME);
+   if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) {
+   pr_err("ERROR %s/%s, debugfs create directory failed\n",
+  STMMAC_RESOURCE_NAME, dev->name);
 
return -ENOMEM;
}
 
/* Entry to report DMA RX/TX rings */
-   stmmac_rings_status = debugfs_create_file("descriptors_status",
- S_IRUGO, stmmac_fs_dir, dev,
- &stmmac_rings_status_fops);
+   priv->dbgfs_rings_status =
+   debugfs_create_file("descriptors_status", S_IRUGO,
+   priv->dbgfs_dir, dev,
+   &stmmac_rings_status_fops);
 
-   if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) {
+   if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) {
pr_info("ERROR creating stmmac ring debugfs file\n");
-   debugfs_remove(stmmac_fs_dir);
+   debugfs_remove_recursive(priv->dbgfs_dir);
 
return -ENOMEM;
}
 
/* Entry to report the DMA HW features */
-   stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir,
-dev, &stmmac_dma_cap_fops);
+   priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO,
+   priv->dbgfs_dir,
+   dev, &stmmac_dma_cap_fops);
 
-   if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) {
+   if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) {
pr_info("ERROR creating stmmac MMC debugfs file\n");
-   debugfs_remove(stmmac_rings