Re: [PATCH net] net: qmi_wwan: add support for Cinterion PLS8
On 23/11/17, Bjørn Mork wrote:
> This is also consistent with the Windows drivers. And being a proper
> CDC ECM class function, it should Just Work with the cdc_ether driver.
> Except for the "RmNet" part, which I guess is the reason you want to
> add this device to qmi_wwan. Which is fine, *if* we can be reasonably
> certain that it does support QMI. The description string is a strong
> indication, but it would be even better to know this was tested.
>
> But adding this to qmi_wwan is not enough. You also need to add a
> blacklist entry to cdc_ether. Both should use a device+class match,
> similar to the Novatel entries. This will make the interface numbering
> irrelevant, and will allow a single entry to match both QMI/rmnet
> functions.
I tried the following changes but I still can't get the PLS8 to work
with kernel 4.14. Here some more information what I have and what I did.
The Module is in this Revsion:
Cinterion
PLS8-E REVISION 02.011
A-REVISION 01.010.19
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -779,6 +779,7 @@ static const struct usb_device_id products[] = {
{QMI_FIXED_INTF(0x0b3c, 0xc00a, 6)},/* Olivetti Olicard 160 */
{QMI_FIXED_INTF(0x0b3c, 0xc00b, 4)},/* Olivetti Olicard 500 */
{QMI_FIXED_INTF(0x1e2d, 0x0060, 4)},/* Cinterion PLxx */
+ {QMI_FIXED_INTF(0x1e2d, 0x0061, 3)},/* Cinterion PLS8 */
{QMI_FIXED_INTF(0x1e2d, 0x0053, 4)},/* Cinterion PHxx,PXxx */
{QMI_FIXED_INTF(0x413c, 0x81a2, 8)},/* Dell Wireless 5806 Gobi(TM)
4G LTE Mobile Broadband Card */
{QMI_FIXED_INTF(0x413c, 0x81a3, 8)},/* Dell Wireless 5570 HSPA+
(42Mbps) Mobile Broadband Card */
I tried the value 4 instead of 3. here but both won't work. In my
working old setup with Kernel 3.9.11 the value is 3. and this was the only
change back then.
+++ b/drivers/net/usb/cdc_ether.c
@@ -562,6 +562,7 @@ static void usbnet_cdc_zte_status(struct usbnet *dev,
struct urb *urb)
#define MICROSOFT_VENDOR_ID0x045e
#define UBLOX_VENDOR_ID0x1546
#define TPLINK_VENDOR_ID 0x2357
+#define CINTERION_VENDOR_ID0x1e2d
static const struct usb_device_id products[] = {
/* BLACKLIST !!
@@ -821,6 +822,13 @@ static void usbnet_cdc_zte_status(struct usbnet *dev,
struct urb *urb)
.driver_info = 0,
},
+/* Cinterion PLS8 - handled by qmi_wwan */
+{
+ USB_DEVICE_AND_INTERFACE_INFO(CINTERION_VENDOR_ID, 0x0061,
USB_CLASS_COMM,
+ USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
+ .driver_info = 0,
+},
This change wasn't necessary in my old setup with the PLS8. Can you
explain me why its needed now?
This is the output I get with dmesg.
[ 747.989455] usb 2-1: USB disconnect, device number 11
[ 748.694818] usb 2-1: new high-speed USB device number 12 using ci_hdrc
[ 748.856821] usb 2-1: New USB device found, idVendor=1e2d, idProduct=0061
[ 748.863712] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 748.871112] usb 2-1: Product: LTE Modem
[ 748.875109] usb 2-1: Manufacturer: Cinterion
[ 748.895201] cdc_acm 2-1:1.0: ttyACM0: USB ACM device
[ 748.915099] cdc_acm 2-1:1.2: ttyACM1: USB ACM device
[ 748.933204] cdc_acm 2-1:1.4: ttyACM2: USB ACM device
[ 748.952976] cdc_acm 2-1:1.6: ttyACM3: USB ACM device
Then I try to connect to /dev/ttyACM1 to execute a "ati1" but without
success.
Best Regards,
Oliver
Re: fec driver and two micrel phys
On 29/11/17, Oliver Graute wrote:
> On 28/11/17, Andrew Lunn wrote:
> > On Tue, Nov 28, 2017 at 04:28:15PM +0100, Oliver Graute wrote:
> > > Hello list,
> > >
> > > I try to get two Micrel KSZ8041 Phys working with the fec driver from
> > > Kernel 4.14. But it looks that something with the mii_bus probing is not
> > > working here. I expect the Phys on address 01 and 03. Currently on eth1
> > > I see TX traffic but no RX. On eth0 there is neither nor. (ifconfig)
> > >
> > > [ 51.997034] Micrel KSZ8041 800f.ethernet-1:00: attached PHY driver
> > > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:00, irq=POLL)
> > > [ 52.036719] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
> > > [ 52.621138] Micrel KSZ8041 800f.ethernet-1:01: attached PHY driver
> > > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:01, irq=POLL)
> > > [ 52.649677] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
> > > [ 54.697479] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full -
> > > flow control off
> > > [ 54.721424] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
> > > [ 59.860693] Micrel KSZ8041 800f.ethernet-1:00: attached PHY driver
> > > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:00, irq=POLL)
> > > [ 59.874298] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
> > > [ 59.980688] Micrel KSZ8041 800f.ethernet-1:01: attached PHY driver
> > > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:01, irq=POLL)
> > > [ 59.994289] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
> > > [ 62.025331] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full -
> > > flow control off
> > > [ 62.044588] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
> > >
> > >
> > > On my old setup with an Kernel 4.2 the phys are working. But there I
> > > patched the phy_mask into the old fec code. Because I didn't know how to
> > > do it better by device tree.
> > >
> > > Can someone tell my how to do it right?
> >
> > Hi Oliver
> >
> > Can you show use your device tree? You should be using phy-handle to
> > point to the PHYs on the MDIO bus.
>
> here is my device tree setting (derived from imx28-evk.dts):
>
> {
> phy-mode = "rmii";
> pinctrl-names = "default";
> pinctrl-0 = <_pins_a>;
> phy-reset-gpios = < 13 0>;
> phy-reset-duration = <100>;
> status = "okay";
> };
>
> {
> phy-mode = "rmii";
> pinctrl-names = "default";
> pinctrl-0 = <_pins_a>;
> status = "okay";
> };
>
I got it working with the follwing device tree setup and after reading this
http://lists.infradead.org/pipermail/linux-arm-kernel/2015-January/314706.html
{
phy-mode = "rmii";
phy-handle = <>;
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
phy-reset-gpios = < 13 0>;
phy-reset-duration = <100>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
reg = <1>;
};
ethphy1: ethernet-phy@3 {
reg = <3>;
};
};
};
{
phy-mode = "rmii";
phy-handle = <>;
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
};
Thx for stub me in right direction.
Best regards,
Oliver
Re: fec driver and two micrel phys
On 28/11/17, Andrew Lunn wrote:
> On Tue, Nov 28, 2017 at 04:28:15PM +0100, Oliver Graute wrote:
> > Hello list,
> >
> > I try to get two Micrel KSZ8041 Phys working with the fec driver from
> > Kernel 4.14. But it looks that something with the mii_bus probing is not
> > working here. I expect the Phys on address 01 and 03. Currently on eth1
> > I see TX traffic but no RX. On eth0 there is neither nor. (ifconfig)
> >
> > [ 51.997034] Micrel KSZ8041 800f.ethernet-1:00: attached PHY driver
> > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:00, irq=POLL)
> > [ 52.036719] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
> > [ 52.621138] Micrel KSZ8041 800f.ethernet-1:01: attached PHY driver
> > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:01, irq=POLL)
> > [ 52.649677] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
> > [ 54.697479] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full - flow
> > control off
> > [ 54.721424] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
> > [ 59.860693] Micrel KSZ8041 800f.ethernet-1:00: attached PHY driver
> > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:00, irq=POLL)
> > [ 59.874298] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
> > [ 59.980688] Micrel KSZ8041 800f.ethernet-1:01: attached PHY driver
> > [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:01, irq=POLL)
> > [ 59.994289] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
> > [ 62.025331] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full - flow
> > control off
> > [ 62.044588] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready
> >
> >
> > On my old setup with an Kernel 4.2 the phys are working. But there I
> > patched the phy_mask into the old fec code. Because I didn't know how to
> > do it better by device tree.
> >
> > Can someone tell my how to do it right?
>
> Hi Oliver
>
> Can you show use your device tree? You should be using phy-handle to
> point to the PHYs on the MDIO bus.
here is my device tree setting (derived from imx28-evk.dts):
{
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
phy-reset-gpios = < 13 0>;
phy-reset-duration = <100>;
status = "okay";
};
{
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <_pins_a>;
status = "okay";
};
Best Regards,
Oliver
fec driver and two micrel phys
Hello list, I try to get two Micrel KSZ8041 Phys working with the fec driver from Kernel 4.14. But it looks that something with the mii_bus probing is not working here. I expect the Phys on address 01 and 03. Currently on eth1 I see TX traffic but no RX. On eth0 there is neither nor. (ifconfig) [ 51.997034] Micrel KSZ8041 800f.ethernet-1:00: attached PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:00, irq=POLL) [ 52.036719] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 52.621138] Micrel KSZ8041 800f.ethernet-1:01: attached PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:01, irq=POLL) [ 52.649677] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready [ 54.697479] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off [ 54.721424] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready [ 59.860693] Micrel KSZ8041 800f.ethernet-1:00: attached PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:00, irq=POLL) [ 59.874298] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready [ 59.980688] Micrel KSZ8041 800f.ethernet-1:01: attached PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.ethernet-1:01, irq=POLL) [ 59.994289] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready [ 62.025331] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off [ 62.044588] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready On my old setup with an Kernel 4.2 the phys are working. But there I patched the phy_mask into the old fec code. Because I didn't know how to do it better by device tree. Can someone tell my how to do it right? +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -1909,6 +1909,9 @@ static int fec_enet_mii_probe(struct net_device *ndev) fep->phy_dev = NULL; + //FIXME: Has to come in via DT + fep->mii_bus->phy_mask = 5; [2.857053] fec 800f.ethernet: failed to get phy-reset-gpios: -16 [2.864190] fec 800f.ethernet (unnamed net_device) (uninitialized): Invalid MAC address: 00:00:00:00:00:00 [2.874450] fec 800f.ethernet (unnamed net_device) (uninitialized): Using random MAC address: 4e:7f:b4:28:6d:a5 [2.954844] libphy: fec_enet_mii_bus: probed [2.969254] fec 800f4000.ethernet (unnamed net_device) (uninitialized): Invalid MAC address: 00:00:00:00:00:00 [2.979514] fec 800f4000.ethernet (unnamed net_device) (uninitialized): Using random MAC address: 3a:4a:96:7e:c2:02 [ 41.430276] fec 800f.ethernet eth0: Freescale FEC PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.etherne:01, irq=-1) [ 42.062191] fec 800f4000.ethernet eth1: Freescale FEC PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.etherne:03, irq=-1) [ 43.430622] fec 800f.ethernet eth0: Link is Up - 100Mbps/Full - flow control off [ 48.245927] fec 800f.ethernet eth0: Freescale FEC PHY driver [Micrel KSZ8041] (mii_bus:phy_addr=800f.etherne:01, irq=-1) [ 50.246425] fec 800f.ethernet eth0: Link is Up - 100Mbps/Full - flow control off [ 112.254191] fec 800f.ethernet eth0: Link is Down [ 117.066479] fec 800f4000.ethernet eth1: Link is Up - 100Mbps/Full - flow control off Best Regards, Oliver
Re: [PATCH net] net: qmi_wwan: add support for Cinterion PLS8
On 24/11/17, Reinhard Speyerer wrote: > before posting this problem report > https://developer.gemalto.com/threads/ipv6dualstack-problems-pls8-e-revision-03017 > in the Gemalto developer forum I tested the qmi_wwan/cdc_ether changes > you suggested above and apart from having two working QMI interfaces > the IPv6/dualstack problems observed with AT^SWWAN/cdc_ether were > also gone when using WDSStartNetworkInterface and the QMI interface in > raw IP mode instead. thx for sharing this information. IPv6 with PLS8-E is also a topic on our side Best Regards, Oliver
Re: [PATCH net] net: qmi_wwan: add support for Cinterion PLS8
On 23/11/17, Bjørn Mork wrote:
>
> This is also consistent with the Windows drivers. And being a proper
> CDC ECM class function, it should Just Work with the cdc_ether driver.
> Except for the "RmNet" part, which I guess is the reason you want to
> add this device to qmi_wwan. Which is fine, *if* we can be reasonably
> certain that it does support QMI. The description string is a strong
> indication, but it would be even better to know this was tested.
>
> But adding this to qmi_wwan is not enough. You also need to add a
> blacklist entry to cdc_ether. Both should use a device+class match,
> similar to the Novatel entries. This will make the interface numbering
> irrelevant, and will allow a single entry to match both QMI/rmnet
> functions.
ok I tried it this way:
+++ b/drivers/net/usb/cdc_ether.c
@@ -562,6 +562,7 @@ static void usbnet_cdc_zte_status(struct usbnet *dev,
struct urb *urb)
#define MICROSOFT_VENDOR_ID0x045e
#define UBLOX_VENDOR_ID0x1546
#define TPLINK_VENDOR_ID 0x2357
+#define CINTERION_VENDOR_ID0x1e2d
static const struct usb_device_id products[] = {
/* BLACKLIST !!
@@ -821,6 +822,13 @@ static void usbnet_cdc_zte_status(struct usbnet *dev,
struct urb *urb)
.driver_info = 0,
},
+/* Cinterion PLS8 - handled by qmi_wwan */
+{
+ USB_DEVICE_AND_INTERFACE_INFO(CINTERION_VENDOR_ID, 0x0061,
USB_CLASS_COMM,
+ USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE),
+ .driver_info = 0,
+},
+
/* WHITELIST!!!
*
* CDC Ether uses two interfaces, not necessarily consecutive.
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 720a3a2..93e102e 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -1221,6 +1221,7 @@ static int qmi_wwan_resume(struct usb_interface *intf)
{QMI_FIXED_INTF(0x0b3c, 0xc00a, 6)},/* Olivetti Olicard 160 */
{QMI_FIXED_INTF(0x0b3c, 0xc00b, 4)},/* Olivetti Olicard 500 */
{QMI_FIXED_INTF(0x1e2d, 0x0060, 4)},/* Cinterion PLxx */
+ {QMI_FIXED_INTF(0x1e2d, 0x0061, 3)},/* Cinterion PLS8 LTE */
{QMI_FIXED_INTF(0x1e2d, 0x0053, 4)},/* Cinterion PHxx,PXxx */
{QMI_FIXED_INTF(0x1e2d, 0x0082, 4)},/* Cinterion PHxx,PXxx (2
RmNet) */
{QMI_FIXED_INTF(0x1e2d, 0x0082, 5)},/* Cinterion PHxx,PXxx (2
RmNet) */
but now I'am missing an ttyACM4 interface and the edc_ether registering
is not working anymore.
[ 124.310611] usb 2-1: new high-speed USB device number 2 using ci_hdrc
[ 124.457029] usb 2-1: New USB device found, idVendor=1e2d, idProduct=0061
[ 124.463938] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 124.471307] usb 2-1: Product: LTE Modem
[ 124.475278] usb 2-1: Manufacturer: Cinterion
[ 124.536219] cdc_acm 2-1:1.0: ttyACM0: USB ACM device
[ 124.563155] cdc_acm 2-1:1.2: ttyACM1: USB ACM device
[ 124.589625] cdc_acm 2-1:1.4: ttyACM2: USB ACM device
[ 124.613517] cdc_acm 2-1:1.6: ttyACM3: USB ACM device
in my working old setup with kernel 3.9.11 it looks like this:
[ 129.710622] usb 2-1: new high-speed USB device number 2 using ci_hdrc
[ 129.873985] usb 2-1: New USB device found, idVendor=1e2d, idProduct=0061
[ 129.888573] usb 2-1: New USB device strings: Mfr=1, Product=2, SerialNumber=0
[ 129.902973] usb 2-1: Product: LTE Modem
[ 129.906927] usb 2-1: Manufacturer: Cinterion
[ 129.928389] cdc_acm 2-1:1.0: ttyACM0: USB ACM device
[ 129.959324] cdc_acm 2-1:1.2: ttyACM1: USB ACM device
[ 129.992714] cdc_acm 2-1:1.4: ttyACM2: USB ACM device
[ 130.019416] cdc_acm 2-1:1.6: ttyACM3: USB ACM device
[ 130.045248] cdc_acm 2-1:1.8: This device cannot do calls on its own. It is
not a modem.
[ 130.073929] cdc_acm 2-1:1.8: ttyACM4: USB ACM device
[ 130.100982] cdc_ether 2-1:1.10 usb0: register 'cdc_ether' at
usb-ci_hdrc.1-1, CDC Ethernet Device, de:ad:be:ef:00:00
[ 130.136438] cdc_ether 2-1:1.12 usb1: register 'cdc_ether' at
usb-ci_hdrc.1-1, CDC Ethernet Device, de:ad:be:ef:00:01
Any clue what I'am doing wrong here?
Best regards,
Oliver
Re: [PATCH net] net: qmi_wwan: add support for Cinterion PLS8
On 23/11/17, Bjørn Mork wrote:
> Oliver Graute <oliver.gra...@gmail.com> writes:
>
> > When the PLS8 devices show up with PID 0x0061 they will expose both a
> > QMI port and a WWAN interface.
>
>
> Please remove the indentation.
will do after we clarifed if this patch is really needed
> Are you sure this is correct? The Windows drivers I found for this
> device appear to think all functions use even interface numbers only,
> presumably because of a control+data interface layout?
honestly not. I have this change for some time in use with older kernel
to get this PLS8 module working. Its pop-ups as usb0 network interface and
with 5 /dev/ttyACM interfaces. Its gets an IP address from the provider.
back then I also added this two lines:
+++ V/drivers/usb/serial/option.c 2015-01-26 15:28:09.676671843 +0100
@@ -338,6 +338,7 @@ static void option_instat_callback(struc
#define CINTERION_PRODUCT_PH8 0x0053
#define CINTERION_PRODUCT_AHXX 0x0055
#define CINTERION_PRODUCT_PLXX 0x0060
+#define CINTERION_PRODUCT_PLS8 0x0061
@@ -1251,6 +1252,7 @@ static const struct usb_device_id option
{ USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PLXX),
+ { USB_DEVICE(CINTERION_VENDOR_ID, CINTERION_PRODUCT_PLS8),
> But I don't know anything about this device. Maybe the layout is
> configurable without changing the device ID? Do you have any more
> information you can provide, like for example a verbose lsusb output or
> the relevant part of /sys/kernel/debug/usb/devices?
here the output of lsusb -vvv
Bus 002 Device 002: ID 1e2d:0061
Device Descriptor:
bLength18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass0 (Defined at Interface level)
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize064
idVendor 0x1e2d
idProduct 0x0061
bcdDevice2.32
iManufacturer 1 Cinterion
iProduct2 LTE Modem
iSerial 0
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 497
bNumInterfaces 14
bConfigurationValue 1
iConfiguration 0
bmAttributes 0xe0
Self Powered
Remote Wakeup
MaxPower 20mA
Interface Association:
bLength 8
bDescriptorType11
bFirstInterface 0
bInterfaceCount 2
bFunctionClass 2 Communications
bFunctionSubClass 2 Abstract (modem)
bFunctionProtocol 1 AT-commands (v.25ter)
iFunction 5 CDC Serial
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber0
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 2 Communications
bInterfaceSubClass 2 Abstract (modem)
bInterfaceProtocol 1 AT-commands (v.25ter)
iInterface 3 CDC Abstract Control Model (ACM)
CDC Header:
bcdCDC 1.20
CDC Call Management:
bmCapabilities 0x03
call management
use DataInterface
bDataInterface 1
CDC ACM:
bmCapabilities 0x02
line coding and serial state
CDC Union:
bMasterInterface0
bSlaveInterface 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82 EP 2 IN
bmAttributes3
Transfer TypeInterrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 9
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber1
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass10 CDC Data
bInterfaceSubClass 0 Unused
bInterfaceProtocol 0
iInterface 4 CDC ACM Data
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes2
Transfer TypeBulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 EP 1 OUT
bmAttributes2
Transfer TypeBulk
Synch Type None
Usage Type
[PATCH net] net: qmi_wwan: add support for Cinterion PLS8
When the PLS8 devices show up with PID 0x0061 they will expose both a
QMI port and a WWAN interface.
Signed-off-by: Oliver Graute <oliver.gra...@neuhaus.de>
---
drivers/net/usb/qmi_wwan.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 720a3a2..b7ee59d 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -1221,6 +1221,7 @@ static int qmi_wwan_resume(struct usb_interface *intf)
{QMI_FIXED_INTF(0x0b3c, 0xc00a, 6)},/* Olivetti Olicard 160 */
{QMI_FIXED_INTF(0x0b3c, 0xc00b, 4)},/* Olivetti Olicard 500 */
{QMI_FIXED_INTF(0x1e2d, 0x0060, 4)},/* Cinterion PLxx */
+ {QMI_FIXED_INTF(0x1e2d, 0x0061, 3)},/* Cinterion PLS8 */
{QMI_FIXED_INTF(0x1e2d, 0x0053, 4)},/* Cinterion PHxx,PXxx */
{QMI_FIXED_INTF(0x1e2d, 0x0082, 4)},/* Cinterion PHxx,PXxx (2
RmNet) */
{QMI_FIXED_INTF(0x1e2d, 0x0082, 5)},/* Cinterion PHxx,PXxx (2
RmNet) */
--
1.9.1
Re: Micrel Phy KSZ8031 clock select setting in dts
On 21/06/16, Sascha Hauer wrote:
> On Mon, Jun 20, 2016 at 07:14:06PM +0200, Oliver Graute wrote:
> > On 20/06/16, Andrew Lunn wrote:
> > > > {
> > > > pinctrl-names = "default";
> > > > pinctrl-0 = <_enet1>;
> > > > phy-mode = "rmii";
> > > > micrel,rmii-reference-clock-select-25-mhz;
> > > > clocks,rmii-ref;
> > >
> > > You are adding phy properties, not MAC properties. Please put them in
> > > the phy node.
> >
> > yes, you are right. I fixed this and added the clock like sascha and
> > sergei proposed. (thx to you all)
> >
> > my dts node now looks like this:
> >
> > {
> > pinctrl-names = "default";
> > pinctrl-0 = <_enet1>;
> > phy-mode = "rmii";
> > status = "okay";
> >
> > mdio {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > ethphy0: ethernet-phy@0 {
> > compatible = "micrel,ksz8031";
> > micrel,rmii-reference-clock-select-25-mhz;
> > clocks = <>;
> > clock-names = "rmii-ref";
> > phy-handle = <>;
> > reg = <0>;
> > };
> >
> > };
> >
> > mdc: rmii-ref {
> > #clock-cells = <0>;
> > compatible ="fixed-clock";
> > clock-frequency = <5000>;
> > };
> > };
>
> To make that clear: Which phy do you have: KSZ8031RNL or KSZ8031RNLI?
> The former has 25MHz default input clock whereas the latter has 50MHz
> default input clock.
according the circuit diagram I have KSZ803RNLI.
>
> I assume you have the KSZ8031RNL and use it with 50MHz (so the non
> default case), hence you have to set the KSZPHY_RMII_REF_CLK_SEL bit.
> The "micrel,rmii-reference-clock-select-25-mhz" means "Setting the bit
> selects 25MHz" which is not the case here, so you have to remove the
> property.
ok if I removing the property "micrel,rmii-reference-clock-select-25-mhz"
and removing my changes in micrel.c it now works as well.
> Could it be that your initial setting just did not work because of other
> mistakes, like no correct clock?
yes that was the case. Many thanks for the helpful notes.
Best Regards,
Oliver
Re: Micrel Phy KSZ8031 clock select setting in dts
On 20/06/16, Andrew Lunn wrote:
> > {
> > pinctrl-names = "default";
> > pinctrl-0 = <_enet1>;
> > phy-mode = "rmii";
> > micrel,rmii-reference-clock-select-25-mhz;
> > clocks,rmii-ref;
>
> You are adding phy properties, not MAC properties. Please put them in
> the phy node.
yes, you are right. I fixed this and added the clock like sascha and
sergei proposed. (thx to you all)
my dts node now looks like this:
{
pinctrl-names = "default";
pinctrl-0 = <_enet1>;
phy-mode = "rmii";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "micrel,ksz8031";
micrel,rmii-reference-clock-select-25-mhz;
clocks = <>;
clock-names = "rmii-ref";
phy-handle = <>;
reg = <0>;
};
};
mdc: rmii-ref {
#clock-cells = <0>;
compatible ="fixed-clock";
clock-frequency = <5000>;
};
};
But I also needed to invert the behavior of KSZPHY_RMII_REF_CLK_SEL in
the micrel.c driver to get everything working with my revison of Micrel Phy.
If I understood you right this should not be necessary. So something in
dts is still wrong.
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 7f4e042..198a24f 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -181,10 +181,14 @@ static int kszphy_rmii_clk_sel(struct phy_device *phydev,
bool val)
return ctrl;
}
- if (val)
+ if (val){
+ printk(KERN_DEBUG "if kszphy_rmii_clk_sel val=0x%x \n", val);
ctrl |= KSZPHY_RMII_REF_CLK_SEL;
- else
- ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
+ }
+ else{
+ printk(KERN_DEBUG "else kszphy_rmii_clk_sel val=0x%x \n", val);
+ ctrl |= KSZPHY_RMII_REF_CLK_SEL;
+ }
Best Regards,
Oliver
Re: Micrel Phy KSZ8031 clock select setting in dts
On 20/06/16, Sascha Hauer wrote:
> On Sun, Jun 19, 2016 at 09:29:41PM +0200, Oliver Graute wrote:
> > On 17/06/16, Sergei Shtylyov wrote:
> > > On 06/17/2016 04:04 PM, Oliver Graute wrote:
> > >
> > > >I try to enable a Micrel KSZ8031 in my imx6ul board device tree. But i'am
> > > >struggeling with the setting for KSZPHY_RMII_REF_CLK_SEL BIT(7). In my
> > > >revision of this Micrel KSZ8031 Phy the Bit(7) has to be true. The 0x1f
> > > >register must be 0x8180.
> > > >
> > > >How can I configure this register setting into my DTS?
> > > >
> > > >I already checked Documentation/devicetree/bindings/net/micrel.txt
> > > >
> > > >but i'am not sure if this still up to date. There where some reworks
> > > >after git commit 86dc1342
> > > >
> > > >some other commits related to this Phy clock setting I checked
> > > >
> > > >commit 1fadee0c3
> > > >commit b838b4aced
> > > >
> > > >my non working device tree blob for the phy is:
> > > >
> > > > {
> > > > pinctrl-names = "default";
> > > > pinctrl-0 = <_enet1>;
> > > > phy-mode = "rmii";
> > > > rmmi-ref-clk-sel = <1>;
> > > > phy-handle = <>;
> > > > status = "okay";
> > > >
> > > > mdio {
> > > > #address-cells = <1>;
> > > > #size-cells = <0>;
> > > >
> > > > ethphy0: ethernet-phy@0 {
> > > > compatible = "micrel,ksz8031";
> > > > reg = <0>;
> > > > };
> > > > };
> > > >};
> > > >
> > > >
> > > >some clue how to configure this phy register setting correctly?
> > >
> > >Tried specifying "micrel,rmii-reference-clock-select-25-mhz"
> > > property in the PHY node?
> > >
> >
> > No, I expect my RMII reference clock on 50 MHz. So I thought that
> > rmii-reference-clock-select-25-mhz isn't the right setting for me here.
>
> You misunderstand the meaning of this property. It is not for specifying
> 25MHz. Instead, it's for specifying the polarity of the
> KSZPHY_RMII_REF_CLK_SEL bit.
> Background is that the Micrel Phys come with different default input
> frequencies. Unfortunately Micrel did not change the default value of
> this bit for the different variants, instead they kept the default value
> the same and inverted the meaning for the different variants.
> Sergei is right, you have to set
> micrel,rmii-reference-clock-select-25-mhz.
thx you both for confirming that. Can you tell me also if the clock
statement s fine in my dts?
{
pinctrl-names = "default";
pinctrl-0 = <_enet1>;
phy-mode = "rmii";
micrel,rmii-reference-clock-select-25-mhz;
clocks,rmii-ref;
because the kernel does not pass my printk in the probe function of micrel.c.
clk = devm_clk_get(>dev, "rmii-ref");
/* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
if (!IS_ERR_OR_NULL(clk)) {
printk(KERN_DEBUG "kszphy_probe clk\n");
I checked that CONFIG_HAVE_CLK is enabled.
Best regards,
Oliver
Re: Micrel Phy KSZ8031 clock select setting in dts
On 17/06/16, Sergei Shtylyov wrote:
> On 06/17/2016 04:04 PM, Oliver Graute wrote:
>
> >I try to enable a Micrel KSZ8031 in my imx6ul board device tree. But i'am
> >struggeling with the setting for KSZPHY_RMII_REF_CLK_SEL BIT(7). In my
> >revision of this Micrel KSZ8031 Phy the Bit(7) has to be true. The 0x1f
> >register must be 0x8180.
> >
> >How can I configure this register setting into my DTS?
> >
> >I already checked Documentation/devicetree/bindings/net/micrel.txt
> >
> >but i'am not sure if this still up to date. There where some reworks
> >after git commit 86dc1342
> >
> >some other commits related to this Phy clock setting I checked
> >
> >commit 1fadee0c3
> >commit b838b4aced
> >
> >my non working device tree blob for the phy is:
> >
> > {
> > pinctrl-names = "default";
> > pinctrl-0 = <_enet1>;
> > phy-mode = "rmii";
> > rmmi-ref-clk-sel = <1>;
> > phy-handle = <>;
> > status = "okay";
> >
> > mdio {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
> > ethphy0: ethernet-phy@0 {
> > compatible = "micrel,ksz8031";
> > reg = <0>;
> > };
> > };
> >};
> >
> >
> >some clue how to configure this phy register setting correctly?
>
>Tried specifying "micrel,rmii-reference-clock-select-25-mhz"
> property in the PHY node?
>
No, I expect my RMII reference clock on 50 MHz. So I thought that
rmii-reference-clock-select-25-mhz isn't the right setting for me here.
If I manually set bit 7 in the 0x1f register to true The Phy only works
until the next ifconfig eth0 up/down cycle. After the Phy Reset Bit 7 is
false again and Phy isn't working anymore.
Best Regards,
Oliver
Micrel Phy KSZ8031 clock select setting in dts
Hello,
I try to enable a Micrel KSZ8031 in my imx6ul board device tree. But i'am
struggeling with the setting for KSZPHY_RMII_REF_CLK_SEL BIT(7). In my
revision of this Micrel KSZ8031 Phy the Bit(7) has to be true. The 0x1f
register must be 0x8180.
How can I configure this register setting into my DTS?
I already checked Documentation/devicetree/bindings/net/micrel.txt
but i'am not sure if this still up to date. There where some reworks
after git commit 86dc1342
some other commits related to this Phy clock setting I checked
commit 1fadee0c3
commit b838b4aced
my non working device tree blob for the phy is:
{
pinctrl-names = "default";
pinctrl-0 = <_enet1>;
phy-mode = "rmii";
rmmi-ref-clk-sel = <1>;
phy-handle = <>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "micrel,ksz8031";
reg = <0>;
};
};
};
some clue how to configure this phy register setting correctly?
Best regards,
Oliver
