Re: [PATCH v4 5/7] net: mdio-mux: Add MDIO mux driver for iProc SoCs

2016-06-06 Thread Florian Fainelli 
On 06/06/2016 05:41 AM, Pramod Kumar wrote:
> iProc based SoCs supports the integrated mdio multiplexer which
> has the bus selection as well as mdio transaction generation logic
> inside.
> 
> This multiplexer has child buses for PCIe, SATA, USB and ETH. These
> buses could be internal or external to SOC where PHYs are attached.
> These buses could use C-45 or C-22 mdio transaction.
> 
> Signed-off-by: Pramod Kumar 

Reviewed-by: Florian Fainelli 
-- 
Florian

Re: [PATCH v4 5/7] net: mdio-mux: Add MDIO mux driver for iProc SoCs

2016-06-06 Thread Andrew Lunn 
On Mon, Jun 06, 2016 at 06:11:38PM +0530, Pramod Kumar wrote:
> iProc based SoCs supports the integrated mdio multiplexer which
> has the bus selection as well as mdio transaction generation logic
> inside.
> 
> This multiplexer has child buses for PCIe, SATA, USB and ETH. These
> buses could be internal or external to SOC where PHYs are attached.
> These buses could use C-45 or C-22 mdio transaction.
> 
> Signed-off-by: Pramod Kumar 

Reviewed-by: Andrew Lunn 

 Andrew

[PATCH v4 5/7] net: mdio-mux: Add MDIO mux driver for iProc SoCs

2016-06-06 Thread Pramod Kumar 
iProc based SoCs supports the integrated mdio multiplexer which
has the bus selection as well as mdio transaction generation logic
inside.

This multiplexer has child buses for PCIe, SATA, USB and ETH. These
buses could be internal or external to SOC where PHYs are attached.
These buses could use C-45 or C-22 mdio transaction.

Signed-off-by: Pramod Kumar 
---
 drivers/net/phy/Kconfig  |  11 ++
 drivers/net/phy/Makefile |   1 +
 drivers/net/phy/mdio-mux-bcm-iproc.c | 248 +++
 3 files changed, 260 insertions(+)
 create mode 100644 drivers/net/phy/mdio-mux-bcm-iproc.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 6dad9a9..94c0707 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -254,6 +254,17 @@ config MDIO_BUS_MUX_MMIOREG
 
  Currently, only 8-bit registers are supported.
 
+config MDIO_BUS_MUX_BCM_IPROC
+   tristate "Support for iProc based MDIO bus multiplexers"
+   depends on OF && OF_MDIO && (ARCH_BCM_IPROC || COMPILE_TEST)
+   select MDIO_BUS_MUX
+   default ARCH_BCM_IPROC
+   help
+ This module provides a driver for MDIO bus multiplexers found in
+ iProc based Broadcom SoCs. This multiplexer connects one of several
+ child MDIO bus to a parent bus. Buses could be internal as well as
+ external and selection logic lies inside the same multiplexer.
+
 config MDIO_BCM_UNIMAC
tristate "Broadcom UniMAC MDIO bus controller"
depends on HAS_IOMEM
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index fcdbb92..f5951d5a 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_AMD_PHY) += amd.o
 obj-$(CONFIG_MDIO_BUS_MUX) += mdio-mux.o
 obj-$(CONFIG_MDIO_BUS_MUX_GPIO)+= mdio-mux-gpio.o
 obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
+obj-$(CONFIG_MDIO_BUS_MUX_BCM_IPROC)   += mdio-mux-bcm-iproc.o
 obj-$(CONFIG_MDIO_SUN4I)   += mdio-sun4i.o
 obj-$(CONFIG_MDIO_MOXART)  += mdio-moxart.o
 obj-$(CONFIG_MDIO_BCM_UNIMAC)  += mdio-bcm-unimac.o
diff --git a/drivers/net/phy/mdio-mux-bcm-iproc.c 
b/drivers/net/phy/mdio-mux-bcm-iproc.c
new file mode 100644
index 000..0a04125
--- /dev/null
+++ b/drivers/net/phy/mdio-mux-bcm-iproc.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright 2016 Broadcom
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, version 2, as
+ * published by the Free Software Foundation (the "GPL").
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License version 2 (GPLv2) for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * version 2 (GPLv2) along with this source code.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define MDIO_PARAM_OFFSET  0x00
+#define MDIO_PARAM_MIIM_CYCLE  29
+#define MDIO_PARAM_INTERNAL_SEL25
+#define MDIO_PARAM_BUS_ID  22
+#define MDIO_PARAM_C45_SEL 21
+#define MDIO_PARAM_PHY_ID  16
+#define MDIO_PARAM_PHY_DATA0
+
+#define MDIO_READ_OFFSET   0x04
+#define MDIO_READ_DATA_MASK0x
+#define MDIO_ADDR_OFFSET   0x08
+
+#define MDIO_CTRL_OFFSET   0x0C
+#define MDIO_CTRL_WRITE_OP 0x1
+#define MDIO_CTRL_READ_OP  0x2
+
+#define MDIO_STAT_OFFSET   0x10
+#define MDIO_STAT_DONE 1
+
+#define BUS_MAX_ADDR   32
+#define EXT_BUS_START_ADDR 16
+
+struct iproc_mdiomux_desc {
+   void *mux_handle;
+   void __iomem *base;
+   struct device *dev;
+   struct mii_bus *mii_bus;
+};
+
+static int iproc_mdio_wait_for_idle(void __iomem *base, bool result)
+{
+   unsigned int timeout = 1000; /* loop for 1s */
+   u32 val;
+
+   do {
+   val = readl(base + MDIO_STAT_OFFSET);
+   if ((val & MDIO_STAT_DONE) == result)
+   return 0;
+
+   usleep_range(1000, 2000);
+   } while (timeout--);
+
+   return -ETIMEDOUT;
+}
+
+/* start_miim_ops- Program and start MDIO transaction over mdio bus.
+ * @base: Base address
+ * @phyid: phyid of the selected bus.
+ * @reg: register offset to be read/written.
+ * @val :0 if read op else value to be written in @reg;
+ * @op: Operation that need to be carried out.
+ *  MDIO_CTRL_READ_OP: Read transaction.
+ *  MDIO_CTRL_WRITE_OP: Write transaction.
+ *
+ * Return value: Successful Read operation returns read reg values and write
+ *  operation returns 0. Failure operation returns negative error code.
+ */
+static int start_miim_ops(void __iomem