[Nouveau] [Bug 95044] [NVA0] [Reclocking] GPU doesn't relax memory clocks

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95044

--- Comment #6 from debianlinuxe...@gmail.com ---
Created attachment 123159
  --> https://bugs.freedesktop.org/attachment.cgi?id=123159=edit
MMIO trace log file

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[Nouveau] [Bug 95044] [NVA0] [Reclocking] GPU doesn't relax memory clocks

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=95044

--- Comment #5 from debianlinuxe...@gmail.com ---
As karolherbst pointed on the #nouveau irc channel, I patched my distro kernel
sources with this patch : 

https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/arch/x86/mm/kmmio.c?id=cfa52c0cfa4d727aa3e457bf29aeff296c528a08

Build with the same options as current kernel.

It did the trick.

I finally was able to do the mmiotrace test.

The test consisted in running the bare X server with only the nvidia-settings
application.

Forced Maximum Performance level.

At reach then forced adaptive.

At reach then exited both application and X.

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Re: [Nouveau] [PATCH mesa v2 3/3] nouveau: codegen: LOAD: Take src swizzle into account

[Hans de Goede]

Hi,

On 22-04-16 10:37, Marek Olšák wrote:

On Fri, Apr 22, 2016 at 9:23 AM, Hans de Goede  wrote:

Hi,

On 22-04-16 09:08, Marek Olšák wrote:


On Thu, Apr 21, 2016 at 7:04 PM, Ilia Mirkin  wrote:


[+radeon folk]

Marek, Nicolai, Bas - please have a look at the doc change and let us
know if you think this will cause a problem for radeon.

Hans is solving the issue that he wants to swizzle the data loaded
from the image/buffer/whatever before sticking it into the dst
register.



Is this something st/mesa needs or just nouveau? If just nouveau needs
it, I don't see a point in updating the TGSI spec, since nouveau can
just add the swizzle when translating from TGSI.



This is something which the llvm tgsi backend needs, which we plan to
use to add opencl support to nouveau.

 From the commit msg:

"The llvm TGSI backend uses pointers in registers and does things like:

LOAD TEMP[0].y, MEMORY[0], TEMP[0]

Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be
loaded instead.

This commit adds support for a swizzle suffix for the 1st source
operand, which allows using:

LOAD TEMP[0].y, MEMORY[0]., TEMP[0]

And actually getting the desired behavior"


If radeonsi needs no changes and st/mesa doesn't change behavior, it's OK.


Since radeonsi does not use llvm generated tgsi, it should not need any
changes, and these patches do not touch st/mesa.

Regards,

Hans
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Re: [Nouveau] [PATCH mesa v2 3/3] nouveau: codegen: LOAD: Take src swizzle into account

[Marek Olšák]

On Fri, Apr 22, 2016 at 9:23 AM, Hans de Goede  wrote:
> Hi,
>
> On 22-04-16 09:08, Marek Olšák wrote:
>>
>> On Thu, Apr 21, 2016 at 7:04 PM, Ilia Mirkin  wrote:
>>>
>>> [+radeon folk]
>>>
>>> Marek, Nicolai, Bas - please have a look at the doc change and let us
>>> know if you think this will cause a problem for radeon.
>>>
>>> Hans is solving the issue that he wants to swizzle the data loaded
>>> from the image/buffer/whatever before sticking it into the dst
>>> register.
>>
>>
>> Is this something st/mesa needs or just nouveau? If just nouveau needs
>> it, I don't see a point in updating the TGSI spec, since nouveau can
>> just add the swizzle when translating from TGSI.
>
>
> This is something which the llvm tgsi backend needs, which we plan to
> use to add opencl support to nouveau.
>
> From the commit msg:
>
> "The llvm TGSI backend uses pointers in registers and does things like:
>
> LOAD TEMP[0].y, MEMORY[0], TEMP[0]
>
> Expecting the data at address TEMP[0].x to get loaded to
> TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be
> loaded instead.
>
> This commit adds support for a swizzle suffix for the 1st source
> operand, which allows using:
>
> LOAD TEMP[0].y, MEMORY[0]., TEMP[0]
>
> And actually getting the desired behavior"

If radeonsi needs no changes and st/mesa doesn't change behavior, it's OK.

Marek
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Re: [Nouveau] GM108GLM?

[Pierre Moreau]

Hello,

A patch was merged yesterday to recognise GM108 (see
https://github.com/skeggsb/nouveau/commit/3da1f2a19e5e8dc8d68a4400d9cca01c64ecd59e).
I guess it will make it into 4.7.

Pierre

On 12:14 PM - Apr 18 2016, Sune Mølgaard wrote:
> Is there anything I can do in this regard?
> 
> /smo
> 
> On 2016-03-31 23:12, Pierre Moreau wrote:
> > Oh, hum, GM108 is NV118 and not NV108 which is Gk208… My bad!
> > 
> > SMF from the bug report seemed to have some working setup, and since he 
> > didn't
> > pinged back, I guess it's working nicely. But some more checking might 
> > still be
> > needed?
> > 
> > On 04:59 PM - Mar 31 2016, Ilia Mirkin wrote:
> >> Actually GM108 is not one of the recognized chips. Someone needs to go
> >> through and check that its goldens didn't change. Nobody's done that.
> >>
> >> See https://bugs.freedesktop.org/show_bug.cgi?id=89558
> >>
> >> On Thu, Mar 31, 2016 at 4:57 PM, Pierre Moreau  
> >> wrote:
> >>> Hello,
> >>>
> >>> Acceleration support for GM107 was merged in kernel 4.1, and modesetting
> >>> support was added to 3.15. Which kernel version did you try? The GM108 
> >>> chipset
> >>> seems to be recognised since at least 2015/08/20.
> >>>
> >>> Regards,
> >>>
> >>> Pierre Moreau
> >>>
> >>>
> >>> On 02:55 PM - Mar 29 2016, Sune Mølgaard wrote:
>  Hiya,
> 
>  Is there any change for Quadro K620M support at some point in time, and
>  what can I do to help, apart from the info below?
> 
>  Best regards,
> 
>  Sune Mølgaard
> 
>  dmesg |grep -i nouveau
>  [1.164919] nouveau :08:00.0: unknown chipset (1183a0a2)
>  [1.164943] nouveau: probe of :08:00.0 failed with error -12
> 
>  lspci|grep -i nvidi
>  08:00.0 3D controller: NVIDIA Corporation GM108GLM [Quadro K620M] (rev 
>  a2)
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> 




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Re: [Nouveau] [PATCH mesa v2 3/3] nouveau: codegen: LOAD: Take src swizzle into account

[Hans de Goede]

Hi,

On 22-04-16 09:08, Marek Olšák wrote:

On Thu, Apr 21, 2016 at 7:04 PM, Ilia Mirkin  wrote:

[+radeon folk]

Marek, Nicolai, Bas - please have a look at the doc change and let us
know if you think this will cause a problem for radeon.

Hans is solving the issue that he wants to swizzle the data loaded
from the image/buffer/whatever before sticking it into the dst
register.


Is this something st/mesa needs or just nouveau? If just nouveau needs
it, I don't see a point in updating the TGSI spec, since nouveau can
just add the swizzle when translating from TGSI.


This is something which the llvm tgsi backend needs, which we plan to
use to add opencl support to nouveau.

From the commit msg:

"The llvm TGSI backend uses pointers in registers and does things like:

LOAD TEMP[0].y, MEMORY[0], TEMP[0]

Expecting the data at address TEMP[0].x to get loaded to
TEMP[0].y. But this will cause the data at TEMP[0].x + 4 to be
loaded instead.

This commit adds support for a swizzle suffix for the 1st source
operand, which allows using:

LOAD TEMP[0].y, MEMORY[0]., TEMP[0]

And actually getting the desired behavior"

Regards,

Hans
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[Nouveau] [Bug 94990] Latest 4.6rc4 kernel, no booting on gtx970

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=94990

--- Comment #16 from Alexandre Courbot  ---
Hi,

Your latest comments seem to indicate that the issue is not related to firmware
- it just happens to manifest itself at this stage as well when firmware is
loaded.

2 things to try:

1) Can you try loading Nouveau with the "config=NvForcePost=1" option? Adding
"nouveau.config=NvForcePost=1" to your kernel command line should do it.

2) Can I get a full log of you booting with the /lib/firmware directory
removed, or can you confirm that when you can see Nouveau complaining about the
firmware when you boot in this configuration?

Thanks!

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