Re: [Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
On 10/27/2016 07:28 PM, Ilia Mirkin wrote:
On Thu, Oct 27, 2016 at 1:19 PM, Samuel Pitoiset
wrote:
Are you sure this refactoring doesn't break anything?
Few comments inline.
On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin
---
src/nvc0_accel.c | 11 ++
src/nvc0_accel.h | 56 ++
src/nvc0_exa.c | 23 ---
src/nvc0_xv.c| 67
+++-
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+
*/
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ }
}
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 607e97b..959f67f 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -7,6 +7,7 @@
#include "hwdefs/nvc0_m2mf.xml.h"
#include "hwdefs/nv50_defs.xml.h"
#include "hwdefs/nv50_texture.h"
+#include "hwdefs/gm107_texture.xml.h"
#include "hwdefs/nv_3ddefs.xml.h"
/* subchannel assignments, compatible with kepler's fixed layout */
@@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct
nouveau_bo *bo,
}
}
+static __inline__ void
+PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned
offset,
+unsigned width, unsigned height, unsigned pitch, unsigned format)
+{
+ if (push->client->device->chipset < 0x110) {
+ unsigned tic2 = 0xd0001000;
+ if (pitch == 0)
+ tic2 |= 0x4000;
+ else
+ tic2 |= 0x0005c000;
+ PUSH_DATA(push, format);
+ PUSH_DATA(push, bo->offset + offset);
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ (bo->config.nvc0.tile_mode << 18) |
+ tic2);
+ PUSH_DATA(push, 0x0030);
+ PUSH_DATA(push, 0x8000 | width);
+ PUSH_DATA(push, 0x0001 | height);
+ PUSH_DATA(push, 0x0300);
+ PUSH_DATA(push, 0x);
+ } else {
+ unsigned tile_mode = bo->config.nvc0.tile_mode;
+ PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) <<
1));
+ PUSH_DATA(push, bo->offset + offset);
+ if (pitch == 0) {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+
GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ ((tile_mode & 0x007)) |
+ ((tile_mode & 0x070) >> (4 - 3)) |
+ ((tile_mode & 0x700) >> (8 - 6)));
+ PUSH_DATA(push,
GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
+ GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
+ ((height - 1) & 0x));
+ PUSH_DATA(push,
GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
+
GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
+ PUSH_DATA(push, 0x);
+ } else {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+
GM107_TIC2_2_HEADER_VERSION_PITCH);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push,
GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+
GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
(height - 1));
+ PUSH_DATA(push, 0x0);
+ PUSH_DATA(push, 0x0);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0
Re: [Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
On Thu, Oct 27, 2016 at 1:19 PM, Samuel Pitoiset
wrote:
> Are you sure this refactoring doesn't break anything?
>
> Few comments inline.
>
>
> On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
>>
>> This flips GM10x to using the updated format, which is what I tested
>> with. However GM20x and GP10x also use this TIC format.
>>
>> Signed-off-by: Ilia Mirkin
>> ---
>> src/nvc0_accel.c | 11 ++
>> src/nvc0_accel.h | 56 ++
>> src/nvc0_exa.c | 23 ---
>> src/nvc0_xv.c| 67
>> +++-
>> 4 files changed, 93 insertions(+), 64 deletions(-)
>>
>> diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
>> index 0682806..8da5051 100644
>> --- a/src/nvc0_accel.c
>> +++ b/src/nvc0_accel.c
>> @@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
>> PUSH_DATA (push, (bo->offset + MISC_OFFSET));
>> PUSH_DATA (push, 1);
>> + } else {
>> + /* Use new TIC format. Not strictly necessary for GM20x+
>> */
>> + IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
>> + if (pNv->dev->chipset >= 0x120) {
>> + /* Use center sample locations. */
>> + BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
>> + PUSH_DATA (push, 0x);
>> + PUSH_DATA (push, 0x);
>> + PUSH_DATA (push, 0x);
>> + PUSH_DATA (push, 0x);
>> + }
>> }
>>
>> BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
>> diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
>> index 607e97b..959f67f 100644
>> --- a/src/nvc0_accel.h
>> +++ b/src/nvc0_accel.h
>> @@ -7,6 +7,7 @@
>> #include "hwdefs/nvc0_m2mf.xml.h"
>> #include "hwdefs/nv50_defs.xml.h"
>> #include "hwdefs/nv50_texture.h"
>> +#include "hwdefs/gm107_texture.xml.h"
>> #include "hwdefs/nv_3ddefs.xml.h"
>>
>> /* subchannel assignments, compatible with kepler's fixed layout */
>> @@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct
>> nouveau_bo *bo,
>> }
>> }
>>
>> +static __inline__ void
>> +PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned
>> offset,
>> +unsigned width, unsigned height, unsigned pitch, unsigned format)
>> +{
>> + if (push->client->device->chipset < 0x110) {
>> + unsigned tic2 = 0xd0001000;
>> + if (pitch == 0)
>> + tic2 |= 0x4000;
>> + else
>> + tic2 |= 0x0005c000;
>> + PUSH_DATA(push, format);
>> + PUSH_DATA(push, bo->offset + offset);
>> + PUSH_DATA(push, ((bo->offset + offset) >> 32) |
>> + (bo->config.nvc0.tile_mode << 18) |
>> + tic2);
>> + PUSH_DATA(push, 0x0030);
>> + PUSH_DATA(push, 0x8000 | width);
>> + PUSH_DATA(push, 0x0001 | height);
>> + PUSH_DATA(push, 0x0300);
>> + PUSH_DATA(push, 0x);
>> + } else {
>> + unsigned tile_mode = bo->config.nvc0.tile_mode;
>> + PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) <<
>> 1));
>> + PUSH_DATA(push, bo->offset + offset);
>> + if (pitch == 0) {
>> + PUSH_DATA(push, ((bo->offset + offset) >> 32) |
>> +
>> GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
>> + PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
>> + ((tile_mode & 0x007)) |
>> + ((tile_mode & 0x070) >> (4 - 3)) |
>> + ((tile_mode & 0x700) >> (8 - 6)));
>> + PUSH_DATA(push,
>> GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
>> + GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
>> + GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
>> + (width - 1));
>> + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
>> + ((height - 1) & 0x));
>> + PUSH_DATA(push,
>> GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO |
>> +
>> GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
>> + PUSH_DATA(push, 0x);
>> + } else {
>> + PUSH_DATA(push, ((bo->offset + offset) >> 32) |
>> +
>> GM107_TIC2_2_HEADER_VERSION_PITCH);
>> + PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
>> + (pitch >> 5));
>> + PUSH_DATA(push,
>> GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
>> +
>> GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
>> + (widt
Re: [Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
Are you sure this refactoring doesn't break anything?
Few comments inline.
On 10/27/2016 04:02 PM, Ilia Mirkin wrote:
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin
---
src/nvc0_accel.c | 11 ++
src/nvc0_accel.h | 56 ++
src/nvc0_exa.c | 23 ---
src/nvc0_xv.c| 67 +++-
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ }
}
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 607e97b..959f67f 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -7,6 +7,7 @@
#include "hwdefs/nvc0_m2mf.xml.h"
#include "hwdefs/nv50_defs.xml.h"
#include "hwdefs/nv50_texture.h"
+#include "hwdefs/gm107_texture.xml.h"
#include "hwdefs/nv_3ddefs.xml.h"
/* subchannel assignments, compatible with kepler's fixed layout */
@@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo
*bo,
}
}
+static __inline__ void
+PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset,
+unsigned width, unsigned height, unsigned pitch, unsigned format)
+{
+ if (push->client->device->chipset < 0x110) {
+ unsigned tic2 = 0xd0001000;
+ if (pitch == 0)
+ tic2 |= 0x4000;
+ else
+ tic2 |= 0x0005c000;
+ PUSH_DATA(push, format);
+ PUSH_DATA(push, bo->offset + offset);
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ (bo->config.nvc0.tile_mode << 18) |
+ tic2);
+ PUSH_DATA(push, 0x0030);
+ PUSH_DATA(push, 0x8000 | width);
+ PUSH_DATA(push, 0x0001 | height);
+ PUSH_DATA(push, 0x0300);
+ PUSH_DATA(push, 0x);
+ } else {
+ unsigned tile_mode = bo->config.nvc0.tile_mode;
+ PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1));
+ PUSH_DATA(push, bo->offset + offset);
+ if (pitch == 0) {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ ((tile_mode & 0x007)) |
+ ((tile_mode & 0x070) >> (4 - 3)) |
+ ((tile_mode & 0x700) >> (8 - 6)));
+ PUSH_DATA(push,
GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
+ GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
+ ((height - 1) & 0x));
+ PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO
|
+
GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
+ PUSH_DATA(push, 0x);
+ } else {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_PITCH);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
(height - 1));
+ PUSH_DATA(push, 0x0);
+ PUSH_DATA(push, 0x0);
+ }
+ }
+}
+
#endif
[Nouveau] [PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
This flips GM10x to using the updated format, which is what I tested
with. However GM20x and GP10x also use this TIC format.
Signed-off-by: Ilia Mirkin
---
src/nvc0_accel.c | 11 ++
src/nvc0_accel.h | 56 ++
src/nvc0_exa.c | 23 ---
src/nvc0_xv.c| 67 +++-
4 files changed, 93 insertions(+), 64 deletions(-)
diff --git a/src/nvc0_accel.c b/src/nvc0_accel.c
index 0682806..8da5051 100644
--- a/src/nvc0_accel.c
+++ b/src/nvc0_accel.c
@@ -322,6 +322,17 @@ NVAccelInit3D_NVC0(ScrnInfoPtr pScrn)
PUSH_DATA (push, (bo->offset + MISC_OFFSET) >> 32);
PUSH_DATA (push, (bo->offset + MISC_OFFSET));
PUSH_DATA (push, 1);
+ } else {
+ /* Use new TIC format. Not strictly necessary for GM20x+ */
+ IMMED_NVC0(push, SUBC_3D(0x0f10), 1);
+ if (pNv->dev->chipset >= 0x120) {
+ /* Use center sample locations. */
+ BEGIN_NVC0(push, SUBC_3D(0x11e0), 4);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ PUSH_DATA (push, 0x);
+ }
}
BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
diff --git a/src/nvc0_accel.h b/src/nvc0_accel.h
index 607e97b..959f67f 100644
--- a/src/nvc0_accel.h
+++ b/src/nvc0_accel.h
@@ -7,6 +7,7 @@
#include "hwdefs/nvc0_m2mf.xml.h"
#include "hwdefs/nv50_defs.xml.h"
#include "hwdefs/nv50_texture.h"
+#include "hwdefs/gm107_texture.xml.h"
#include "hwdefs/nv_3ddefs.xml.h"
/* subchannel assignments, compatible with kepler's fixed layout */
@@ -108,4 +109,59 @@ PUSH_DATAu(struct nouveau_pushbuf *push, struct nouveau_bo
*bo,
}
}
+static __inline__ void
+PUSH_TIC(struct nouveau_pushbuf *push, struct nouveau_bo *bo, unsigned offset,
+unsigned width, unsigned height, unsigned pitch, unsigned format)
+{
+ if (push->client->device->chipset < 0x110) {
+ unsigned tic2 = 0xd0001000;
+ if (pitch == 0)
+ tic2 |= 0x4000;
+ else
+ tic2 |= 0x0005c000;
+ PUSH_DATA(push, format);
+ PUSH_DATA(push, bo->offset + offset);
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ (bo->config.nvc0.tile_mode << 18) |
+ tic2);
+ PUSH_DATA(push, 0x0030);
+ PUSH_DATA(push, 0x8000 | width);
+ PUSH_DATA(push, 0x0001 | height);
+ PUSH_DATA(push, 0x0300);
+ PUSH_DATA(push, 0x);
+ } else {
+ unsigned tile_mode = bo->config.nvc0.tile_mode;
+ PUSH_DATA(push, (format & 0x3f) | ((format & ~0x3f) << 1));
+ PUSH_DATA(push, bo->offset + offset);
+ if (pitch == 0) {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ ((tile_mode & 0x007)) |
+ ((tile_mode & 0x070) >> (4 - 3)) |
+ ((tile_mode & 0x700) >> (8 - 6)));
+ PUSH_DATA(push,
GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V |
+ GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
+ ((height - 1) & 0x));
+ PUSH_DATA(push, GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO
|
+
GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE);
+ PUSH_DATA(push, 0x);
+ } else {
+ PUSH_DATA(push, ((bo->offset + offset) >> 32) |
+ GM107_TIC2_2_HEADER_VERSION_PITCH);
+ PUSH_DATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
(height - 1));
+ PUSH_DATA(push, 0x0);
+ PUSH_DATA(push, 0x0);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index a53dfe6..017a7da 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@
