Re: [Openipmi-developer] [PATCH v2 3/3] bindings: ipmi: Add binding for Aspeed SSIF BMC driver
On 02/04/2021 00:09, Rob Herring wrote: On Tue, Mar 30, 2021 at 09:10:29PM +0700, Quan Nguyen wrote: Add device tree binding document for the Aspeed SSIF BMC driver. Signed-off-by: Quan Nguyen --- .../bindings/ipmi/aspeed-ssif-bmc.txt | 18 ++ 1 file changed, 18 insertions(+) create mode 100644 Documentation/devicetree/bindings/ipmi/aspeed-ssif-bmc.txt Same comment as you ignored on v1. Dear Rob, I really did not mean to do that. What happen is that there was a compilation error complaint by kernel robot test on my v1. So I tried to send my v2 to fix that issue asap. Unfortunately, your reply on my v1 arrived just right after I hit "git send-email" to send out my v2. For this comment, I'll switch to use yaml file in next version. - Quan ___ Openipmi-developer mailing list Openipmi-developer@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openipmi-developer
[Openipmi-developer] Re [PATCH v2 21/21] ipmi: kcs_bmc_aspeed: Optionally apply status address
On Fri, Mar 19, 2021 at 01:27:52AM CDT, Andrew Jeffery wrote:
>Some Aspeed KCS devices can derive the status register address from the
>address of the data register. As such, the address of the status
>register can be implicit in the configuration if desired. On the other
>hand, sometimes address schemes might be requested that are incompatible
>with the default addressing scheme. Allow these requests where possible
>if the devicetree specifies the status register address.
>
>Signed-off-by: Andrew Jeffery
>---
> drivers/char/ipmi/kcs_bmc_aspeed.c | 113 +
> 1 file changed, 81 insertions(+), 32 deletions(-)
>
>diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c
>b/drivers/char/ipmi/kcs_bmc_aspeed.c
>index 7334b1f51dcc..98789b837690 100644
>--- a/drivers/char/ipmi/kcs_bmc_aspeed.c
>+++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
>@@ -83,6 +83,8 @@
> #define LPC_STR2 0x040
> #define LPC_STR3 0x044
> #define LPC_HICRB0x100
>+#define LPC_HICRB_EN16LADR2 BIT(5)
>+#define LPC_HICRB_EN16LADR1 BIT(4)
> #define LPC_HICRB_IBFIE4 BIT(1)
> #define LPC_HICRB_LPC4E BIT(0)
> #define LPC_HICRC0x104
>@@ -96,6 +98,11 @@
> #define LPC_IDR4 0x114
> #define LPC_ODR4 0x118
> #define LPC_STR4 0x11C
>+#define LPC_LSADR120x120
>+#define LPC_LSADR12_LSADR2_MASK GENMASK(31, 16)
>+#define LPC_LSADR12_LSADR2_SHIFT 16
>+#define LPC_LSADR12_LSADR1_MASK GENMASK(15, 0)
>+#define LPC_LSADR12_LSADR1_SHIFT 0
>
> #define OBE_POLL_PERIOD(HZ / 2)
>
>@@ -123,7 +130,7 @@ struct aspeed_kcs_bmc {
>
> struct aspeed_kcs_of_ops {
> int (*get_channel)(struct platform_device *pdev);
>- int (*get_io_address)(struct platform_device *pdev);
>+ int (*get_io_address)(struct platform_device *pdev, u32 addrs[2]);
> };
>
> static inline struct aspeed_kcs_bmc *to_aspeed_kcs_bmc(struct kcs_bmc_device
> *kcs_bmc)
>@@ -217,38 +224,64 @@ static void aspeed_kcs_updateb(struct kcs_bmc_device
>*kcs_bmc, u32 reg, u8 mask,
> * C. KCS4
> *D / C : CA4h / CA5h
> */
>-static void aspeed_kcs_set_address(struct kcs_bmc_device *kcs_bmc, u16 addr)
>+static int aspeed_kcs_set_address(struct kcs_bmc_device *kcs_bmc, u32
>addrs[2], int nr_addrs)
> {
> struct aspeed_kcs_bmc *priv = to_aspeed_kcs_bmc(kcs_bmc);
>
>- switch (kcs_bmc->channel) {
>+ if (WARN_ON(nr_addrs < 1 || nr_addrs > 2))
>+ return -EINVAL;
>+
>+ switch (priv->kcs_bmc.channel) {
> case 1:
>- regmap_update_bits(priv->map, LPC_HICR4,
>- LPC_HICR4_LADR12AS, 0);
>- regmap_write(priv->map, LPC_LADR12H, addr >> 8);
>- regmap_write(priv->map, LPC_LADR12L, addr & 0xFF);
>+ regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS, 0);
>+ regmap_write(priv->map, LPC_LADR12H, addrs[0] >> 8);
>+ regmap_write(priv->map, LPC_LADR12L, addrs[0] & 0xFF);
>+ if (nr_addrs == 2) {
>+ regmap_update_bits(priv->map, LPC_LSADR12,
>LPC_LSADR12_LSADR1_MASK,
>+ addrs[1] <<
>LPC_LSADR12_LSADR1_SHIFT);
>+
>+ regmap_update_bits(priv->map, LPC_HICRB,
>LPC_HICRB_EN16LADR1,
>+ LPC_HICRB_EN16LADR1);
>+ }
> break;
>
> case 2:
>- regmap_update_bits(priv->map, LPC_HICR4,
>- LPC_HICR4_LADR12AS, LPC_HICR4_LADR12AS);
>- regmap_write(priv->map, LPC_LADR12H, addr >> 8);
>- regmap_write(priv->map, LPC_LADR12L, addr & 0xFF);
>+ regmap_update_bits(priv->map, LPC_HICR4, LPC_HICR4_LADR12AS,
>LPC_HICR4_LADR12AS);
>+ regmap_write(priv->map, LPC_LADR12H, addrs[0] >> 8);
>+ regmap_write(priv->map, LPC_LADR12L, addrs[0] & 0xFF);
>+ if (nr_addrs == 2) {
>+ regmap_update_bits(priv->map, LPC_LSADR12,
>LPC_LSADR12_LSADR2_MASK,
>+ addrs[1] <<
>LPC_LSADR12_LSADR2_SHIFT);
>+
>+ regmap_update_bits(priv->map, LPC_HICRB,
>LPC_HICRB_EN16LADR2,
>+ LPC_HICRB_EN16LADR2);
>+ }
> break;
>
> case 3:
>- regmap_write(priv->map, LPC_LADR3H, addr >> 8);
>- regmap_write(priv->map, LPC_LADR3L, addr & 0xFF);
>+ if (nr_addrs == 2) {
>+ dev_err(priv->kcs_bmc.dev,
>+ "Channel 3 only supports inferred status IO
>address\n");
>+ return -EINVAL;
>+ }
>+
>+ regmap_write(priv->map, LPC_LADR3H, addrs[0] >> 8);
>+ regmap_write(priv->map, LPC_LADR3L, addrs[0] & 0xFF);
> break;
>
> case 4:
>- regmap_write(priv->map,
Re: [Openipmi-developer] [PATCH v2 3/3] bindings: ipmi: Add binding for Aspeed SSIF BMC driver
On Tue, Mar 30, 2021 at 09:10:29PM +0700, Quan Nguyen wrote: > Add device tree binding document for the Aspeed SSIF BMC driver. > > Signed-off-by: Quan Nguyen > --- > .../bindings/ipmi/aspeed-ssif-bmc.txt | 18 ++ > 1 file changed, 18 insertions(+) > create mode 100644 Documentation/devicetree/bindings/ipmi/aspeed-ssif-bmc.txt Same comment as you ignored on v1. ___ Openipmi-developer mailing list Openipmi-developer@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openipmi-developer
Re: [Openipmi-developer] [EXTERNAL] [PATCH v2 19/21] ipmi: kcs_bmc_aspeed: Implement KCS SerIRQ configuration
On Fri, Mar 19, 2021 at 01:27:50AM CDT, Andrew Jeffery wrote:
>Apply the SerIRQ ID and level/sense behaviours from the devicetree if
>provided.
>
>Signed-off-by: Andrew Jeffery
>---
> drivers/char/ipmi/kcs_bmc_aspeed.c | 179 -
> 1 file changed, 177 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/char/ipmi/kcs_bmc_aspeed.c
>b/drivers/char/ipmi/kcs_bmc_aspeed.c
>index 271845eb2e26..3782aef4eb73 100644
>--- a/drivers/char/ipmi/kcs_bmc_aspeed.c
>+++ b/drivers/char/ipmi/kcs_bmc_aspeed.c
>@@ -9,6 +9,7 @@
> #include
> #include
> #include
>+#include
> #include
> #include
> #include
>@@ -28,6 +29,22 @@
>
> #define KCS_CHANNEL_MAX 4
>
>+/*
>+ * Field class descriptions
>+ *
>+ * LPCyE Enable LPC channel y
>+ * IBFIEy Input Buffer Full IRQ Enable for LPC channel y
>+ * IRQxEy Assert SerIRQ x for LPC channel y (Deprecated, use IDyIRQX,
>IRQXEy)
>+ * IDyIRQXUse the specified 4-bit SerIRQ for LPC channel y
>+ * SELyIRQX SerIRQ polarity for LPC channel y (low: 0, high: 1)
>+ * IRQXEy Assert the SerIRQ specified in IDyIRQX for LPC channel y
>+ */
>+
>+#define LPC_TYIRQX_LOW 0b00
>+#define LPC_TYIRQX_HIGH 0b01
>+#define LPC_TYIRQX_RSVD 0b10
>+#define LPC_TYIRQX_RISING0b11
>+
> #define LPC_HICR00x000
> #define LPC_HICR0_LPC3E BIT(7)
> #define LPC_HICR0_LPC2E BIT(6)
>@@ -39,6 +56,19 @@
> #define LPC_HICR40x010
> #define LPC_HICR4_LADR12AS BIT(7)
> #define LPC_HICR4_KCSENBLBIT(2)
>+#define LPC_SIRQCR00x070
>+/* IRQ{12,1}E1 are deprecated as of AST2600 A3 but necessary for prior chips
>*/
>+#define LPC_SIRQCR0_IRQ12E1BIT(1)
>+#define LPC_SIRQCR0_IRQ1E1 BIT(0)
>+#define LPC_HICR5 0x080
>+#define LPC_HICR5_ID3IRQX_MASK GENMASK(23, 20)
>+#define LPC_HICR5_ID3IRQX_SHIFT 20
>+#define LPC_HICR5_ID2IRQX_MASK GENMASK(19, 16)
>+#define LPC_HICR5_ID2IRQX_SHIFT 16
>+#define LPC_HICR5_SEL3IRQX BIT(15)
>+#define LPC_HICR5_IRQXE3 BIT(14)
>+#define LPC_HICR5_SEL2IRQX BIT(13)
>+#define LPC_HICR5_IRQXE2 BIT(12)
> #define LPC_LADR3H 0x014
> #define LPC_LADR3L 0x018
> #define LPC_LADR12H 0x01C
>@@ -55,6 +85,13 @@
> #define LPC_HICRB0x100
> #define LPC_HICRB_IBFIF4 BIT(1)
> #define LPC_HICRB_LPC4E BIT(0)
>+#define LPC_HICRC0x104
>+#define LPC_HICRC_ID4IRQX_MASK GENMASK(7, 4)
>+#define LPC_HICRC_ID4IRQX_SHIFT 4
>+#define LPC_HICRC_TY4IRQX_MASK GENMASK(3, 2)
>+#define LPC_HICRC_TY4IRQX_SHIFT 2
>+#define LPC_HICRC_OBF4_AUTO_CLR BIT(1)
>+#define LPC_HICRC_IRQXE4 BIT(0)
> #define LPC_LADR40x110
> #define LPC_IDR4 0x114
> #define LPC_ODR4 0x118
>@@ -62,11 +99,21 @@
>
> #define OBE_POLL_PERIOD(HZ / 2)
>
>+enum aspeed_kcs_irq_mode {
>+ aspeed_kcs_irq_none,
>+ aspeed_kcs_irq_serirq,
>+};
>+
> struct aspeed_kcs_bmc {
> struct kcs_bmc_device kcs_bmc;
>
> struct regmap *map;
>
>+ struct {
>+ enum aspeed_kcs_irq_mode mode;
>+ int id;
>+ } upstream_irq;
>+
> struct {
> spinlock_t lock;
> bool remove;
>@@ -103,6 +150,49 @@ static void aspeed_kcs_outb(struct kcs_bmc_device
>*kcs_bmc, u32 reg, u8 data)
>
> rc = regmap_write(priv->map, reg, data);
> WARN(rc != 0, "regmap_write() failed: %d\n", rc);
>+
>+ /* Trigger the upstream IRQ on ODR writes, if enabled */
>+
>+ switch (reg) {
>+ case LPC_ODR1:
>+ case LPC_ODR2:
>+ case LPC_ODR3:
>+ case LPC_ODR4:
>+ break;
>+ default:
>+ return;
>+ }
>+
>+ if (priv->upstream_irq.mode != aspeed_kcs_irq_serirq)
>+ return;
>+
>+ switch (kcs_bmc->channel) {
>+ case 1:
>+ switch (priv->upstream_irq.id) {
>+ case 12:
>+ regmap_update_bits(priv->map, LPC_SIRQCR0,
>LPC_SIRQCR0_IRQ12E1,
>+ LPC_SIRQCR0_IRQ12E1);
>+ break;
>+ case 1:
>+ regmap_update_bits(priv->map, LPC_SIRQCR0,
>LPC_SIRQCR0_IRQ1E1,
>+ LPC_SIRQCR0_IRQ1E1);
>+ break;
>+ default:
>+ break;
>+ }
>+ break;
>+ case 2:
>+ regmap_update_bits(priv->map, LPC_HICR5, LPC_HICR5_IRQXE2,
>LPC_HICR5_IRQXE2);
>+ break;
>+ case 3:
>+ regmap_update_bits(priv->map, LPC_HICR5, LPC_HICR5_IRQXE3,
>LPC_HICR5_IRQXE3);
>+ break;
>+ case 4:
>+ regmap_update_bits(priv->map, LPC_HICRC, LPC_HICRC_IRQXE4,
>LPC_HICRC_IRQXE4);
>+ break;
>+ default:
>+ break;
>+ }
> }
>
> static void
Re: [Openipmi-developer] [PATCH v2 00/21] ipmi: Allow raw access to KCS devices
On Fri, Mar 19, 2021 at 01:19:30AM CDT, Andrew Jeffery wrote: >Hello, > >This series is a bit of a mix of things, but its primary purpose is to >expose BMC KCS IPMI devices to userspace in a way that enables userspace >to talk to host firmware using protocols that are not IPMI. > >v1 can be found here: > >https://lore.kernel.org/openbmc/20210219142523.3464540-1-and...@aj.id.au/ > >Changes in v2 include: > >* A rebase onto v5.12-rc2 >* Incorporation of off-list feedback on SerIRQ configuration from > Chiawei >* Further validation on hardware for ASPEED KCS devices 2, 3 and 4 >* Lifting the existing single-open constraint of the IPMI chardev >* Fixes addressing Rob's feedback on the conversion of the ASPEED KCS > binding to dt-schema >* Fixes addressing Rob's feedback on the new aspeed,lpc-interrupts > property definition for the ASPEED KCS binding > >A new chardev device is added whose implementation exposes the Input >Data Register (IDR), Output Data Register (ODR) and Status Register >(STR) via read() and write(), and implements poll() for event >monitoring. > >The existing /dev/ipmi-kcs* chardev interface exposes the KCS devices in >a way which encoded the IPMI protocol in its behaviour. However, as >LPC[0] KCS devices give us bi-directional interrupts between the host >and a BMC with both a data and status byte, they are useful for purposes >beyond IPMI. > >As a concrete example, libmctp[1] implements a vendor-defined MCTP[2] >binding using a combination of LPC Firmware cycles for bulk data >transfer and a KCS device via LPC IO cycles for out-of-band protocol >control messages[3]. This gives a throughput improvement over the >standard KCS binding[4] while continuing to exploit the ease of setup of >the LPC bus for early boot firmware on the host processor. > >The series takes a bit of a winding path to achieve its aim: > >1. It begins with patches 1-5 put together by Chia-Wei, which I've >rebased on v5.12-rc2. These fix the ASPEED LPC bindings and other >non-KCS LPC-related ASPEED device drivers in a way that enables the >SerIRQ patches at the end of the series. With Joel's review I'm hoping >these 5 can go through the aspeed tree, and that the rest can go through >the IPMI tree. > >2. Next, patches 6-13 fairly heavily refactor the KCS support in the >IPMI part of the tree, re-architecting things such that it's possible to >support multiple chardev implementations sitting on top of the ASPEED >and Nuvoton device drivers. However, the KCS code didn't really have >great separation of concerns as it stood, so even if we disregard the >multiple-chardev support I think the cleanups are worthwhile. > >3. Patch 14 adds some interrupt management capabilities to the KCS >device drivers in preparation for patch 16, which introduces the new >"raw" KCS device interface. I'm not stoked about the device name/path, >so if people are looking to bikeshed something then feel free to lay >into that. > >4. The remaining patches switch the ASPEED KCS devicetree binding to >dt-schema, add a new interrupt property to describe the SerIRQ behaviour >of the device and finally clean up Serial IRQ support in the ASPEED KCS >driver. > >Rob: The dt-binding patches still come before the relevant driver >changes, I tried to keep the two close together in the series, hence the >bindings changes not being patches 1 and 2. > >I've exercised the series under qemu with the rainier-bmc machine plus >additional patches for KCS support[5]. I've also substituted this series in >place of a hacky out-of-tree driver that we've been using for the >libmctp stack and successfully booted the host processor under our >internal full-platform simulation tools for a Rainier system. > >Note that this work touches the Nuvoton driver as well as ASPEED's, but >I don't have the capability to test those changes or the IPMI chardev >path. Tested-by tags would be much appreciated if you can exercise one >or both. > >Please review! > >Andrew > After rebasing the series onto the OpenBMC dev-5.10 kernel (with only a tiny conflict for the addition of the ast2600 entry in ast_kcs_bmc_match) and enabling CONFIG_IPMI_KCS_BMC_CDEV_IPMI, my e3c246d4i system booted healthily and handled some basic ipmitool operations as expected. Tested-by: Zev Weiss Zev ___ Openipmi-developer mailing list Openipmi-developer@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/openipmi-developer
