Re: [OpenWrt-Devel] [PATCH] 802.1Q VLAN support for Infineon ADM6996 switch chip
On 10/01/11 20:32, David Goodenough wrote: Perhaps I should restate my question, that is unclear. Are there any register values or other way programatically to tell which of the ADM6996 chips is being used as the PHY on a particular system? ADM6996F and ADM6996M are very different. The M is programmed through the MDIO interface that is also used by regular Ethernet PHYs. It occupies the whole address space, though. Normally, there is 5 bits adressing a particular PHY and 5 bits addressing a register in that PHY. The ADM6996M has a 10-bit register address, which is split between the normal two 5-bit addresses. The M has two chip identifier registers, Chip Identifier 0 and Chip Identifier 1, at addresses 0xA0 and 0xA1 respectively. The lowest four bits of identifier 0 are a version number; 0x3 in the datasheet. The higher bits are a product code, 0x102. Chip Identifier 1 reads back as 0x0007. The ADM6996F and ADM6996L are accessed through an SPI interface, it seems, the same bus where the serial config EEPROM is located. I'm not 100% sure of the protocol used to access the switch chip from the CPU, the datasheet isn't very definitive on this, and I do not have equipment with that chip. But the chips don't seem to have an MDIO interface, so that's a very obvious identifying difference. Anyway, at register address 0 the F and L have a Chip Identifier Register. The lowest 4 bits is a version number. The whole register is specified as 0x00071010 for both F and L (!). The M is obviously more advanced that the F and L. Programmatically, the F and L might even be the same. But the difference between the M on the one side and F and L on the other is very large. The only thing they seem to have in common is the chip name. So I'm sorry, but the driver I wrote will not work even one bit for the F and L chips. Peter. -- I use the GNU Privacy Guard (GnuPG) in combination with Enigmail. You can send me encrypted mail if you want some privacy. My key is available at http://wwwhome.cs.utwente.nl/~lebbing/pubkey.txt (new, larger key created on Nov 12, 2009) ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH] 802.1Q VLAN support for Infineon ADM6996 switch chip
On 11/01/11 12:49, Peter Lebbing wrote: The ADM6996F and ADM6996L are accessed through an SPI interface, it seems, the same bus where the serial config EEPROM is located. I'm not 100% sure of the protocol used to access the switch chip from the CPU, the datasheet isn't very definitive on this, and I do not have equipment with that chip. Scratch that. The specification of the management bus comes after the register description in the datasheet, not before :). I just noticed that. It *is* a sort of MDIO, sorry about that. But they send 32 bits of data instead of the regular 16 of MDIO. Anyway, identification of the F and L chips is at PHY address 0, register 0, and is 0x00071010 as I said. But because they send 32 databits instead of 16, I'm not sure what you would actually see if you just search the MDIO bus from your MAC. Still, it's completely different from the chip ID of the ADM6996M. Peter. -- I use the GNU Privacy Guard (GnuPG) in combination with Enigmail. You can send me encrypted mail if you want some privacy. My key is available at http://wwwhome.cs.utwente.nl/~lebbing/pubkey.txt (new, larger key created on Nov 12, 2009) ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] [PATCH] 802.1Q VLAN support for Infineon ADM6996 switch chip
On Tuesday 11 January 2011, Peter Lebbing wrote: On 11/01/11 12:49, Peter Lebbing wrote: The ADM6996F and ADM6996L are accessed through an SPI interface, it seems, the same bus where the serial config EEPROM is located. I'm not 100% sure of the protocol used to access the switch chip from the CPU, the datasheet isn't very definitive on this, and I do not have equipment with that chip. Scratch that. The specification of the management bus comes after the register description in the datasheet, not before :). I just noticed that. It *is* a sort of MDIO, sorry about that. But they send 32 bits of data instead of the regular 16 of MDIO. Anyway, identification of the F and L chips is at PHY address 0, register 0, and is 0x00071010 as I said. But because they send 32 databits instead of 16, I'm not sure what you would actually see if you just search the MDIO bus from your MAC. Still, it's completely different from the chip ID of the ADM6996M. Peter. OK, so does your code check to see if this is an M, or do we need to add that? Do you think we should have two different drivers, one for the M the other for the F and L, or can we interweave the code? David ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] CyaSSL Support
Hi, We just wanted to remind the OpenWrt community that we support the OpenWrt project and that we offer free technical support for CyaSSL to open source community projects. We have just recently released CyaSSL 1.8.0 which offers several new features including increased portability through the os_settings.h file and the new C Standard Library Abstraction layer, lower memory use through configurable input/output buffer sizes and less dynamic memory use, x509 v3 signed certificate generation, and a complete manual. If you have any support questions, feel free to post to our support forums (http://www.yassl.com/forums) or email us at supp...@yassl.com. Thanks, Chris Conlon www.yassl.com ch...@yassl.com +1 406 209 0601 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] r24920 and others: ath9k: DMA failed to stop in 10 ms
I have seen this message emited by the resulting OpenWRT package for my Atheros AP83 based system. I had been using a snapshot of OpenWRT from March 2010, which did not have this problem. However for any of the kernels I have tried, 2.6.32.27, 2.6.36, 2.6.37, all have this error message. In addition, when I use Station mode and associate two devices that are running OpenWRT, I get incredibly flaky iperf numbers, with packet losses going up to 10% on a 10 mbs stream. Whereas when I use a non-OpenWRT station, with an OpenWRT AP, I get almost no loss on the 10 mbs stream, and can get up to 30-40 mbs with 'some loss'. So, the question is, what has happened since last March with the linux ath9k driver support? John Clark. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] r24920 and others: ath9k: DMA failed to stop in 10 ms
On Tue, Jan 11, 2011 at 1:35 PM, John Clark jcl...@metricsystems.comwrote: I have seen this message emited by the resulting OpenWRT package for my Atheros AP83 based system. I had been using a snapshot of OpenWRT from March 2010, which did not have this problem. However for any of the kernels I have tried, 2.6.32.27, 2.6.36, 2.6.37, all have this error message. In addition, when I use Station mode and associate two devices that are running OpenWRT, I get incredibly flaky iperf numbers, with packet losses going up to 10% on a 10 mbs stream. Whereas when I use a non-OpenWRT station, with an OpenWRT AP, I get almost no loss on the 10 mbs stream, and can get up to 30-40 mbs with 'some loss'. So, the question is, what has happened since last March with the linux ath9k driver support? What's the exact error? I've see something similar in my dmesg: ath: Failed to stop TX DMA in 100 msec after killing last frame However, I get great performance regardless. Able to pull 150 mbit/s actual in a 2x2 MIMO configuration. -JR ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [OpenWrt-Devel] r24920 and others: ath9k: DMA failed to stop in 10 ms
I would agree, lately, I am seeing a bunch of these in my logs: ath: Failed to stop TX DMA in 100 msec after killing last frame but my 802.11n 40MHz performance has been the best its been in 6 months ;-) On Tue, 11 Jan 2011 16:35:10 -0600, J. Ryan Earl o...@jryanearl.us wrote: On Tue, Jan 11, 2011 at 1:35 PM, John Clark jcl...@metricsystems.comwrote: I have seen this message emited by the resulting OpenWRT package for my Atheros AP83 based system. I had been using a snapshot of OpenWRT from March 2010, which did not have this problem. However for any of the kernels I have tried, 2.6.32.27, 2.6.36, 2.6.37, all have this error message. In addition, when I use Station mode and associate two devices that are running OpenWRT, I get incredibly flaky iperf numbers, with packet losses going up to 10% on a 10 mbs stream. Whereas when I use a non-OpenWRT station, with an OpenWRT AP, I get almost no loss on the 10 mbs stream, and can get up to 30-40 mbs with 'some loss'. So, the question is, what has happened since last March with the linux ath9k driver support? What's the exact error? I've see something similar in my dmesg: ath: Failed to stop TX DMA in 100 msec after killing last frame However, I get great performance regardless. Able to pull 150 mbit/s actual in a 2x2 MIMO configuration. -JR ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[OpenWrt-Devel] ADSL on BCM6358
Hi all, I have a pair of AGPF and they are based on BCM6358. Do you know if there is any effort to support the DSL subsystem on them? I found this http://www.neufbox4.org/forum/viewtopic.php?id=1260 but looks dead Thanks S. ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
