Re: [PATCH] realtek: make Netgear GS108T v3 u-boot env partition writable
Hi, Op vrijdag 17 juni 2022 om 09:54:56 +02:00:00 schreef Bjørn Mork : Sander Vanheule writes: On Thu, 2022-06-16 at 22:28 +0200, Stijn Segers wrote: Signed-off-by: Stijn Segers You need to add at least one line describing why this change is needed; now you only have a commit title. Just mentioning that you want to be able to modify the u-boot-env from userspace should be enough. Could even use the real usecase example from the forum as body. Then we have that documented here as well. Bjørn Thank you both, clearly my gitiquette is not up to snuff :^). Sent in a v2, also changed the title since it applies to a shared DTSI. Cheers Stijn ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[PATCH v2] realtek: make Netgear GS1xx u-boot env partition writable
Make the u-boot environment partition for the NETGEAR
GS108T v3 and GS110TPP writable (they share a DTS), so
the values can be manipulated from userspace.
See https://forum.openwrt.org/t/57875/1567 for a real
world example.
Signed-off-by: Stijn Segers
---
target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi
b/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi
index 7eccfcb5a2..fd44543bb4 100644
--- a/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi
+++ b/target/linux/realtek/dts-5.10/rtl8380_netgear_gigabit_1xx.dtsi
@@ -24,7 +24,6 @@
partition@e {
label = "u-boot-env";
reg = <0x00e 0x001>;
- read-only;
};
partition@f {
--
2.36.1
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[sdwalker/sdwalker.github.io] 48869b: This week's update
The sender domain has a DMARC Reject/Quarantine policy which disallows sending mailing list messages using the original "From" header. To mitigate this problem, the original message has been wrapped automatically by the mailing list software.--- Begin Message --- Branch: refs/heads/master Home: https://github.com/sdwalker/sdwalker.github.io Commit: 48869b8a6561d2cb64417904860cc88439b995dc https://github.com/sdwalker/sdwalker.github.io/commit/48869b8a6561d2cb64417904860cc88439b995dc Author: Stephen Walker Date: 2022-06-19 (Sun, 19 Jun 2022) Changed paths: M uscan/index-19.07.html M uscan/index-21.02.html M uscan/index.html Log Message: --- This week's update --- End Message --- ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[PATCH] realtek: fix gcc-12 build with -Werror=array-compare
Removing this gcc-12 error:
arch/mips/rtl838x/setup.c:64:30: error: comparison between two arrays
[-Werror=array-compare]
64 | else if (__dtb_start != __dtb_end)
Signed-off-by: Bjørn Mork
---
Kind of stupid
But this is how similar fallout has been fixed in mainline AFAICS. For
example commit ca831f29f8f2 ("mm: page_alloc: fix building error on
-Werror=array-compare")
target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c
b/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c
index 55419c7b0b7a..18c477eb0fe7 100644
--- a/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c
+++ b/target/linux/realtek/files-5.10/arch/mips/rtl838x/setup.c
@@ -61,7 +61,7 @@ void __init plat_mem_setup(void)
if (fw_passed_dtb) /* UHI interface */
dtb = (void *)fw_passed_dtb;
- else if (__dtb_start != __dtb_end)
+ else if (&__dtb_start[0] != &__dtb_end[0])
dtb = (void *)__dtb_start;
else
panic("no dtb found");
--
2.30.2
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Re: [PATCH v2 1/4] realtek: correct egress frame priority assignment
On 19/06/2022 13:46, Sander Vanheule wrote: Priority values passed to the egress (TX) frame header initialiser are invalid when smaller than 0, and should not be assigned to the frame. Queue assignment is then left to the switch core logic. Current code for RTL83xx forces the passed priority value to be positive, by always masking it to the lower bits, resulting in the priority always being set and enabled. RTL93xx code doesn't even check the value and unconditionally assigns the (32 bit) value to the (5 bit) QID field without masking. Fix priority assignment by only setting the AS_QID/AS_PRI flag when a valid value is passed, and properly mask the value to not overflow the QID/PRI field. For RTL839x, also assign the priority to the right part of the frame header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36 and 37-39. The means they should be assigned to the third 16 bit value, containing bits 32-47. Perfect! Best Birger ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[PATCH v2 2/4] realtek: correct egress frame port verification
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1.
Refactor the code to only generate egress frame CPU headers when a valid
destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
argument's type to 'unsigned int', since only positive values are valid.
This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.
Reported-by: Arınç ÜNAL
Reported-by: Birger Koblitz
Signed-off-by: Sander Vanheule
---
.../drivers/net/ethernet/rtl838x_eth.c| 74 +--
.../drivers/net/ethernet/rtl838x_eth.h| 2 +-
2 files changed, 37 insertions(+), 39 deletions(-)
diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index 586a390ba90d..170fc9247bdf 100644
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -92,47 +92,43 @@ struct notify_b {
u32 reserved2[8];
};
-static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
+static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
int prio)
{
- if (dest_port > 0) {
- // cpu_tag[0] is reserved on the RTL83XX SoCs
- h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0:
L2LEARNING on
- h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM
settings below
- h->cpu_tag[3] = 0x;
- h->cpu_tag[4] = BIT(dest_port) >> 16;
- h->cpu_tag[5] = BIT(dest_port) & 0x;
+ // cpu_tag[0] is reserved on the RTL83XX SoCs
+ h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
+ h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings
below
+ h->cpu_tag[3] = 0x;
+ h->cpu_tag[4] = BIT(dest_port) >> 16;
+ h->cpu_tag[5] = BIT(dest_port) & 0x;
- /* Set internal priority (PRI) and enable (AS_PRI) */
- if (prio >= 0)
- h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
- }
+ /* Set internal priority (PRI) and enable (AS_PRI) */
+ if (prio >= 0)
+ h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
}
-static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
+static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
int prio)
{
- if (dest_port > 0) {
- // cpu_tag[0] is reserved on the RTL83XX SoCs
- h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
- h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] =
0;
- // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
- if (dest_port >= 32) {
- dest_port -= 32;
- h->cpu_tag[2] = BIT(dest_port) >> 16;
- h->cpu_tag[3] = BIT(dest_port) & 0x;
- } else {
- h->cpu_tag[4] = BIT(dest_port) >> 16;
- h->cpu_tag[5] = BIT(dest_port) & 0x;
- }
- h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
- h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
-
- /* Set internal priority (PRI) and enable (AS_PRI) */
- if (prio >= 0)
- h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
+ // cpu_tag[0] is reserved on the RTL83XX SoCs
+ h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
+ h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
+ // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
+ if (dest_port >= 32) {
+ dest_port -= 32;
+ h->cpu_tag[2] = BIT(dest_port) >> 16;
+ h->cpu_tag[3] = BIT(dest_port) & 0x;
+ } else {
+ h->cpu_tag[4] = BIT(dest_port) >> 16;
+ h->cpu_tag[5] = BIT(dest_port) & 0x;
}
+ h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
+ h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
+
+ /* Set internal priority (PRI) and enable (AS_PRI) */
+ if (prio >= 0)
+ h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
}
-static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
+static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
int prio)
{
h->cpu_tag[0] = 0x8000; // CPU tag marker
h->cpu_tag[1] = h->cpu_tag[2] = 0;
@@ -147,7 +143,7 @@ static void rtl930x_create_tx_header(struct p_hdr *h, int
dest_port, int prio)
h->cpu_tag[2] = (BIT(5) |
[PATCH v2 4/4] realtek: fix egress L2 learning on rtl839x
The flag to enable L2 address learning on egress frames is in bits 40,
with bit 0 being the leftmost bit of the header. This corresponds to
BIT(7) in the third 16-bit value of the header.
Correctly set L2LEARNING by fixing the off-by-one error.
Fixes: 9eab76c84e31 ("realtek: Improve TX CPU-Tag usage")
Signed-off-by: Sander Vanheule
---
.../realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index 5fa156935798..26e573c3fec5 100644
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -110,7 +110,7 @@ static void rtl839x_create_tx_header(struct p_hdr *h,
unsigned int dest_port, in
{
// cpu_tag[0] is reserved on the RTL83XX SoCs
h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
- h->cpu_tag[2] = BIT(4); /* AS_DPM flag */
+ h->cpu_tag[2] = BIT(7) | BIT(4); /* L2LEARNING and AS_DPM flags */
h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
// h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
if (dest_port >= 32) {
@@ -121,7 +121,6 @@ static void rtl839x_create_tx_header(struct p_hdr *h,
unsigned int dest_port, in
h->cpu_tag[4] = BIT(dest_port) >> 16;
h->cpu_tag[5] = BIT(dest_port) & 0x;
}
- h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
/* Set internal priority (PRI) and enable (AS_PRI) */
if (prio >= 0)
--
2.36.1
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[PATCH v2 1/4] realtek: correct egress frame priority assignment
Priority values passed to the egress (TX) frame header initialiser are
invalid when smaller than 0, and should not be assigned to the frame.
Queue assignment is then left to the switch core logic.
Current code for RTL83xx forces the passed priority value to be
positive, by always masking it to the lower bits, resulting in the
priority always being set and enabled. RTL93xx code doesn't even check
the value and unconditionally assigns the (32 bit) value to the (5 bit)
QID field without masking.
Fix priority assignment by only setting the AS_QID/AS_PRI flag when a
valid value is passed, and properly mask the value to not overflow the
QID/PRI field.
For RTL839x, also assign the priority to the right part of the frame
header. Counting from the leftmost bit, AS_PRI and PRI are in bits 36
and 37-39. The means they should be assigned to the third 16 bit value,
containing bits 32-47.
Signed-off-by: Sander Vanheule
---
.../drivers/net/ethernet/rtl838x_eth.c| 26 ++-
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index cf6aabc6142f..586a390ba90d 100644
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -94,8 +94,6 @@ struct notify_b {
static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
- prio &= 0x7;
-
if (dest_port > 0) {
// cpu_tag[0] is reserved on the RTL83XX SoCs
h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0:
L2LEARNING on
@@ -103,16 +101,15 @@ static void rtl838x_create_tx_header(struct p_hdr *h, int
dest_port, int prio)
h->cpu_tag[3] = 0x;
h->cpu_tag[4] = BIT(dest_port) >> 16;
h->cpu_tag[5] = BIT(dest_port) & 0x;
- // Set internal priority and AS_PRIO
+
+ /* Set internal priority (PRI) and enable (AS_PRI) */
if (prio >= 0)
- h->cpu_tag[2] |= (prio | 0x8) << 12;
+ h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
}
}
static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
- prio &= 0x7;
-
if (dest_port > 0) {
// cpu_tag[0] is reserved on the RTL83XX SoCs
h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
@@ -128,9 +125,10 @@ static void rtl839x_create_tx_header(struct p_hdr *h, int
dest_port, int prio)
}
h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
- // Set internal priority and AS_PRIO
+
+ /* Set internal priority (PRI) and enable (AS_PRI) */
if (prio >= 0)
- h->cpu_tag[1] |= prio | BIT(3);
+ h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 8;
}
}
@@ -138,21 +136,21 @@ static void rtl930x_create_tx_header(struct p_hdr *h, int
dest_port, int prio)
{
h->cpu_tag[0] = 0x8000; // CPU tag marker
h->cpu_tag[1] = h->cpu_tag[2] = 0;
- if (prio >= 0)
- h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority
Queue
h->cpu_tag[3] = 0;
h->cpu_tag[4] = 0;
h->cpu_tag[5] = 0;
h->cpu_tag[6] = BIT(dest_port) >> 16;
h->cpu_tag[7] = BIT(dest_port) & 0x;
+
+ /* Enable (AS_QID) and set priority queue (QID) */
+ if (prio >= 0)
+ h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
}
static void rtl931x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
{
h->cpu_tag[0] = 0x8000; // CPU tag marker
h->cpu_tag[1] = h->cpu_tag[2] = 0;
- if (prio >= 0)
- h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority
Queue
h->cpu_tag[3] = 0;
h->cpu_tag[4] = h->cpu_tag[5] = h->cpu_tag[6] = h->cpu_tag[7] = 0;
if (dest_port >= 32) {
@@ -163,6 +161,10 @@ static void rtl931x_create_tx_header(struct p_hdr *h, int
dest_port, int prio)
h->cpu_tag[6] = BIT(dest_port) >> 16;
h->cpu_tag[7] = BIT(dest_port) & 0x;
}
+
+ /* Enable (AS_QID) and set priority queue (QID) */
+ if (prio >= 0)
+ h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8;
}
static void rtl93xx_header_vlan_set(struct p_hdr *h, int vlan)
--
2.36.1
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[PATCH v2 3/4] realtek: fix port mask on rtl839x
The flags to enable the outgoing port mask is in bits 43, with bit 0
being the leftmost bit of the header. This corresponds to BIT(4) in the
third 16-bit value of the header.
Correctly set AS_DPM by fixing the off-by-one error.
Fixes: 9eab76c84e31 ("realtek: Improve TX CPU-Tag usage")
Signed-off-by: Sander Vanheule
---
.../realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index 170fc9247bdf..5fa156935798 100644
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -110,7 +110,8 @@ static void rtl839x_create_tx_header(struct p_hdr *h,
unsigned int dest_port, in
{
// cpu_tag[0] is reserved on the RTL83XX SoCs
h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
- h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
+ h->cpu_tag[2] = BIT(4); /* AS_DPM flag */
+ h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
// h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
if (dest_port >= 32) {
dest_port -= 32;
@@ -120,7 +121,6 @@ static void rtl839x_create_tx_header(struct p_hdr *h,
unsigned int dest_port, in
h->cpu_tag[4] = BIT(dest_port) >> 16;
h->cpu_tag[5] = BIT(dest_port) & 0x;
}
- h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
/* Set internal priority (PRI) and enable (AS_PRI) */
--
2.36.1
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[PATCH v2 0/4] realtek: egress frame header fixes
These patches contains a few code improvements and fixes for erroneous bitfield assignments. Currently only compile tested, so until I can test these patches, please let me know how this changes behaviour on the affected platforms. Sander Vanheule (4): realtek: correct egress frame priority assignment realtek: correct egress frame port verification realtek: fix port mask on rtl839x realtek: fix egress L2 learning on rtl839x .../drivers/net/ethernet/rtl838x_eth.c| 87 +-- .../drivers/net/ethernet/rtl838x_eth.h| 2 +- 2 files changed, 44 insertions(+), 45 deletions(-) -- 2.36.1 ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [PATCH] realtek: correct egress frame port verification
Hi Birger, On Sun, 2022-06-19 at 11:40 +0200, Birger Koblitz wrote: > Hi, > > On 19.06.22 10:56, Sander Vanheule wrote: > > > - h->cpu_tag[1] = h->cpu_tag[2] = 0; > > - if (prio >= 0) > > - h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set > > Priority Queue > > + h->cpu_tag[1] = 0; > > + /* Enable (AS_QID) and set Priority Queue (QID) */ > > + h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8; > You are removing the possibility to let the SoC choose a Queue on its own > based on congestion, > if you always enable AS_QID. There was a reason that there were negative > Queue-ID values, which > denoted allowing the SoC to choose, i.e. AS_QID was not set. I changed the code this way because prio was always positive, or made so by masking out the upper bits (rtl8380/rtl8390). The passed value (sk_buff::priority >> 1) positive (unsigned) too. There should be no change in behaviour with this patch. Currently preparing a second version (series) of these changes, which I will send shortly. Please let me know how this changes (hopefully improves) behaviour on the affected platforms, as I won't have time to test this in the next days. Best, Sander ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
Re: [PATCH] realtek: correct egress frame port verification
The sender domain has a DMARC Reject/Quarantine policy which disallows
sending mailing list messages using the original "From" header.
To mitigate this problem, the original message has been wrapped
automatically by the mailing list software.--- Begin Message ---
On 19.06.2022 11:56, Sander Vanheule wrote:
> Destination switch ports for outgoing frame can range from 0 to
> CPU_PORT-1, and frame priorities should also always be positive.
>
> Refactor the code to only generate egress frame CPU headers when the a
> valid destination port number is available, and make the code a bit more
> consistent between different switch generations. Change the dest_port
> and prio argument types from 'int' to 'unsigned int', since only
> positive values are valid.
>
> This fixes the issue where egress frames on switch port 0 did not
> receive a VLAN tag, because they are sent out without a CPU header.
> Also fixes a potential issue with invalid (negative) egress port numbers
> on RTL93xx switches.
>
> Reported-by: Arınç ÜNAL
> Reported-by: Birger Koblitz
> Signed-off-by: Sander Vanheule
Thanks for doing this!
Acked-by: Arınç ÜNAL
> ---
> .../drivers/net/ethernet/rtl838x_eth.c| 86 +--
> .../drivers/net/ethernet/rtl838x_eth.h| 2 +-
> 2 files changed, 40 insertions(+), 48 deletions(-)
>
> diff --git
> a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
> b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
> index cf6aabc6142f..241a5787f820 100644
> --- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
> +++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
> @@ -92,54 +92,44 @@ struct notify_b {
> u32 reserved2[8];
> };
>
> -static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int
> prio)
> +static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int
> dest_port, unsigned int prio)
> {
> - prio &= 0x7;
> -
> - if (dest_port > 0) {
> - // cpu_tag[0] is reserved on the RTL83XX SoCs
> - h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0:
> L2LEARNING on
> - h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM
> settings below
> - h->cpu_tag[3] = 0x;
> - h->cpu_tag[4] = BIT(dest_port) >> 16;
> - h->cpu_tag[5] = BIT(dest_port) & 0x;
> - // Set internal priority and AS_PRIO
> - if (prio >= 0)
> - h->cpu_tag[2] |= (prio | 0x8) << 12;
> - }
> + // cpu_tag[0] is reserved on the RTL83XX SoCs
> + h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
> + h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings
> below
> + h->cpu_tag[3] = 0x;
> + h->cpu_tag[4] = BIT(dest_port) >> 16;
> + h->cpu_tag[5] = BIT(dest_port) & 0x;
> + // Set internal priority and AS_PRIO
> + h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
> }
>
> -static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int
> prio)
> +static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int
> dest_port, unsigned int prio)
> {
> - prio &= 0x7;
> -
> - if (dest_port > 0) {
> - // cpu_tag[0] is reserved on the RTL83XX SoCs
> - h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
> - h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] =
> 0;
> - // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
> - if (dest_port >= 32) {
> - dest_port -= 32;
> - h->cpu_tag[2] = BIT(dest_port) >> 16;
> - h->cpu_tag[3] = BIT(dest_port) & 0x;
> - } else {
> - h->cpu_tag[4] = BIT(dest_port) >> 16;
> - h->cpu_tag[5] = BIT(dest_port) & 0x;
> - }
> - h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
> - h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
> - // Set internal priority and AS_PRIO
> - if (prio >= 0)
> - h->cpu_tag[1] |= prio | BIT(3);
> + // cpu_tag[0] is reserved on the RTL83XX SoCs
> + h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
> + h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
> + // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
> + if (dest_port >= 32) {
> + dest_port -= 32;
> + h->cpu_tag[2] = BIT(dest_port) >> 16;
> + h->cpu_tag[3] = BIT(dest_port) & 0x;
> + } else {
> + h->cpu_tag[4] = BIT(dest_port) >> 16;
> + h->cpu_tag[5] = BIT(dest_port) & 0x;
> }
> + h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
> + h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
> + // Set internal priority and AS_PRIO
> + h->cpu_tag[1]
Re: [PATCH] realtek: correct egress frame port verification
Hi, On 19.06.22 10:56, Sander Vanheule wrote: > - h->cpu_tag[1] = h->cpu_tag[2] = 0; > - if (prio >= 0) > - h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority > Queue > + h->cpu_tag[1] = 0; > + /* Enable (AS_QID) and set Priority Queue (QID) */ > + h->cpu_tag[2] = (BIT(5) | (prio & 0x1f)) << 8; You are removing the possibility to let the SoC choose a Queue on its own based on congestion, if you always enable AS_QID. There was a reason that there were negative Queue-ID values, which denoted allowing the SoC to choose, i.e. AS_QID was not set. Cheers, Birger ___ openwrt-devel mailing list openwrt-devel@lists.openwrt.org https://lists.openwrt.org/mailman/listinfo/openwrt-devel
[PATCH] realtek: correct egress frame port verification
Destination switch ports for outgoing frame can range from 0 to
CPU_PORT-1, and frame priorities should also always be positive.
Refactor the code to only generate egress frame CPU headers when the a
valid destination port number is available, and make the code a bit more
consistent between different switch generations. Change the dest_port
and prio argument types from 'int' to 'unsigned int', since only
positive values are valid.
This fixes the issue where egress frames on switch port 0 did not
receive a VLAN tag, because they are sent out without a CPU header.
Also fixes a potential issue with invalid (negative) egress port numbers
on RTL93xx switches.
Reported-by: Arınç ÜNAL
Reported-by: Birger Koblitz
Signed-off-by: Sander Vanheule
---
.../drivers/net/ethernet/rtl838x_eth.c| 86 +--
.../drivers/net/ethernet/rtl838x_eth.h| 2 +-
2 files changed, 40 insertions(+), 48 deletions(-)
diff --git a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
index cf6aabc6142f..241a5787f820 100644
--- a/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
+++ b/target/linux/realtek/files-5.10/drivers/net/ethernet/rtl838x_eth.c
@@ -92,54 +92,44 @@ struct notify_b {
u32 reserved2[8];
};
-static void rtl838x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
+static void rtl838x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
unsigned int prio)
{
- prio &= 0x7;
-
- if (dest_port > 0) {
- // cpu_tag[0] is reserved on the RTL83XX SoCs
- h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0:
L2LEARNING on
- h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM
settings below
- h->cpu_tag[3] = 0x;
- h->cpu_tag[4] = BIT(dest_port) >> 16;
- h->cpu_tag[5] = BIT(dest_port) & 0x;
- // Set internal priority and AS_PRIO
- if (prio >= 0)
- h->cpu_tag[2] |= (prio | 0x8) << 12;
- }
+ // cpu_tag[0] is reserved on the RTL83XX SoCs
+ h->cpu_tag[1] = 0x0401; // BIT 10: RTL8380_CPU_TAG, BIT0: L2LEARNING on
+ h->cpu_tag[2] = 0x0200; // Set only AS_DPM, to enable DPM settings
below
+ h->cpu_tag[3] = 0x;
+ h->cpu_tag[4] = BIT(dest_port) >> 16;
+ h->cpu_tag[5] = BIT(dest_port) & 0x;
+ // Set internal priority and AS_PRIO
+ h->cpu_tag[2] |= ((prio & 0x7) | BIT(3)) << 12;
}
-static void rtl839x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
+static void rtl839x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
unsigned int prio)
{
- prio &= 0x7;
-
- if (dest_port > 0) {
- // cpu_tag[0] is reserved on the RTL83XX SoCs
- h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
- h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] =
0;
- // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
- if (dest_port >= 32) {
- dest_port -= 32;
- h->cpu_tag[2] = BIT(dest_port) >> 16;
- h->cpu_tag[3] = BIT(dest_port) & 0x;
- } else {
- h->cpu_tag[4] = BIT(dest_port) >> 16;
- h->cpu_tag[5] = BIT(dest_port) & 0x;
- }
- h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
- h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
- // Set internal priority and AS_PRIO
- if (prio >= 0)
- h->cpu_tag[1] |= prio | BIT(3);
+ // cpu_tag[0] is reserved on the RTL83XX SoCs
+ h->cpu_tag[1] = 0x0100; // RTL8390_CPU_TAG marker
+ h->cpu_tag[2] = h->cpu_tag[3] = h->cpu_tag[4] = h->cpu_tag[5] = 0;
+ // h->cpu_tag[1] |= BIT(1) | BIT(0); // Bypass filter 1/2
+ if (dest_port >= 32) {
+ dest_port -= 32;
+ h->cpu_tag[2] = BIT(dest_port) >> 16;
+ h->cpu_tag[3] = BIT(dest_port) & 0x;
+ } else {
+ h->cpu_tag[4] = BIT(dest_port) >> 16;
+ h->cpu_tag[5] = BIT(dest_port) & 0x;
}
+ h->cpu_tag[2] |= BIT(5); // Enable destination port mask use
+ h->cpu_tag[2] |= BIT(8); // Enable L2 Learning
+ // Set internal priority and AS_PRIO
+ h->cpu_tag[1] |= (prio & 0x7) | BIT(3);
}
-static void rtl930x_create_tx_header(struct p_hdr *h, int dest_port, int prio)
+static void rtl930x_create_tx_header(struct p_hdr *h, unsigned int dest_port,
unsigned int prio)
{
h->cpu_tag[0] = 0x8000; // CPU tag marker
- h->cpu_tag[1] = h->cpu_tag[2] = 0;
- if (prio >= 0)
- h->cpu_tag[2] = BIT(13) | prio << 8; // Enable and set Priority
Queue
+ h->cpu_tag[1] = 0;
+ /* Enable
