On Wed, Mar 18, 2015 at 8:50 AM, Rafał Miłecki wrote:
> Signed-off-by: Rafał Miłecki
> ---
> .../generic/files/drivers/net/phy/b53/b53_regs.h | 26
> ++
> 1 file changed, 26 insertions(+)
>
> diff --git a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
> b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
> index 4899cc4..6d71493 100644
> --- a/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
> +++ b/target/linux/generic/files/drivers/net/phy/b53/b53_regs.h
> @@ -50,6 +50,9 @@
> /* Jumbo Frame Registers */
> #define B53_JUMBO_PAGE 0x40
>
> +/* CFP Configuration Registers Page */
> +#define B53_CFP_PAGE 0xa1
> +
> /*
> * Control Page registers
> */
> @@ -99,6 +102,20 @@
> #define B53_MC_FLOOD_MASK 0x34
> #define B53_IPMC_FLOOD_MASK0x36
>
> +/* On BCM5301X we can override ports 0-5 and 7 as well */
> +/* For port 8 still use B53_PORT_OVERRIDE_CTRL */
> +#define B53_GMII_PORT_OVERRIDE_CTRL(i) (0x58 + i)
These are also present on BCM63XX integrated switch chips as well as
531XX switch chips, so probably common to all devices with xMII
interfaces on ports 0~7. Please always include the register width in
the comment.
There's also a second set of registers at 0x60~0x67 for setting up
RGMII timing, but might be not needed for 5301X.
> +#define GMII_PORT_OVERRIDE_LINK BIT(0)
> +#define GMII_PORT_OVERRIDE_FULL_DUPLEX BIT(1) /* 0 = Half Duplex */
> +#define GMII_PORT_OVERRIDE_SPEED_S 2
> +#define GMII_PORT_OVERRIDE_SPEED_10M (0 << PORT_OVERRIDE_SPEED_S)
> +#define GMII_PORT_OVERRIDE_SPEED_100M(1 <<
> PORT_OVERRIDE_SPEED_S)
> +#define GMII_PORT_OVERRIDE_SPEED_1000M (2 << PORT_OVERRIDE_SPEED_S)
> +#define GMII_PORT_OVERRIDE_RX_FLOW BIT(4)
> +#define GMII_PORT_OVERRIDE_TX_FLOW BIT(5)
> +#define GMII_PORT_OVERRIDE_ENBIT(6) /* Use the
> register contents */
> +#define GMII_PORT_OVERRIDE_SPEED_2000M BIT(7) /* Requires setting
> 1000M */
If space allows, maybe add "BCM5301X only" or so.
> +
> /* Software reset register (8 bit) */
> #define B53_SOFTRESET 0x79
>
> @@ -156,6 +173,9 @@
> #define GC_FRM_MGMT_PORT_04 0x00
> #define GC_FRM_MGMT_PORT_MII 0x80
>
> +#define B53_BRCM_HDR 0x03
> +#define BRCM_HDR_EN BIT(0)
> +
> /* Device ID register (8 or 32 bit) */
> #define B53_DEVICE_ID 0x30
>
> @@ -310,4 +330,10 @@
> #define JMS_MIN_SIZE 1518
> #define JMS_MAX_SIZE 9724
>
> +/*
> + * CFP Configuration Page Registers
> + */
> +
> +#define B53_CFP_CTRL 0x00
Please add info about the register width, so it's easier to verify
accesses use the correct read/write function.
> +
> #endif /* !__B53_REGS_H */
> --
> 1.8.4.5
Jonas
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