Re: [OpenWrt-Devel] [PATCH 2/3] ARM: dts: Att Vitesse G5e switch to the Gemini SQ201

[Geert Uytterhoeven]

Hi Linus,

On Wed, Jul 4, 2018 at 9:21 PM Linus Walleij  wrote:
> This adds the Vitesse G5e ethernet switch to the Square
> One Itian SQ201 router device tree.
>
> Signed-off-by: Linus Walleij 

Thanks for your patch!

> --- a/arch/arm/boot/dts/gemini-sq201.dts
> +++ b/arch/arm/boot/dts/gemini-sq201.dts
> @@ -20,7 +20,7 @@
> };
>
> chosen {
> -   bootargs = "console=ttyS0,115200n8";
> +   bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw 
> rootwait";
> stdout-path = 
> };

The above hunk looks unrelated.

Gr{oetje,eeting}s,

Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

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[OpenWrt-Devel] [PATCH 2/3] ARM: dts: Att Vitesse G5e switch to the Gemini SQ201

[Linus Walleij]

This adds the Vitesse G5e ethernet switch to the Square
One Itian SQ201 router device tree.

Signed-off-by: Linus Walleij 
---
 arch/arm/boot/dts/gemini-sq201.dts | 75 +-
 1 file changed, 73 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/gemini-sq201.dts 
b/arch/arm/boot/dts/gemini-sq201.dts
index 2706b86e06f1..830c167012a0 100644
--- a/arch/arm/boot/dts/gemini-sq201.dts
+++ b/arch/arm/boot/dts/gemini-sq201.dts
@@ -20,7 +20,7 @@
};
 
chosen {
-   bootargs = "console=ttyS0,115200n8";
+   bootargs = "console=ttyS0,115200n8 root=/dev/sda1 rw rootwait";
stdout-path = 
};
 
@@ -70,6 +70,61 @@
};
};
 
+   spi {
+   compatible = "spi-gpio";
+   #address-cells = <1>;
+   #size-cells = <0>;
+   /* Check pin collisions */
+   gpio-sck = < 28 GPIO_ACTIVE_HIGH>;
+   gpio-miso = < 30 GPIO_ACTIVE_HIGH>;
+   gpio-mosi = < 29 GPIO_ACTIVE_HIGH>;
+   cs-gpios = < 31 GPIO_ACTIVE_HIGH>;
+   num-chipselects = <1>;
+
+   switch@0 {
+   compatible = "vitesse,vsc7395";
+   reg = <0>;
+   /* Specified for 2.5 MHz or below */
+   spi-max-frequency = <250>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   label = "lan1";
+   };
+   port@1 {
+   reg = <1>;
+   label = "lan2";
+   };
+   port@2 {
+   reg = <2>;
+   label = "lan3";
+   };
+   port@3 {
+   reg = <3>;
+   label = "lan4";
+   };
+   vsc: port@6 {
+   reg = <6>;
+   label = "cpu";
+   ethernet = <>;
+   phy-mode = "rgmii";
+   fixed-link {
+   speed = <1000>;
+   full-duplex;
+   pause;
+   };
+   };
+   };
+   };
+   };
+
+
soc {
flash@3000 {
/*
@@ -135,6 +190,16 @@
"gpio0kgrp";
};
};
+   /*
+* gpio0dgrp cover lines used by the SPI
+* to the Vitesse G5x chip.
+*/
+   gpio1_default_pins: pinctrl-gpio1 {
+   mux {
+   function = "gpio1";
+   groups = "gpio1dgrp";
+   };
+   };
pinctrl-gmii {
mux {
function = "gmii";
@@ -205,6 +270,11 @@
pinctrl-0 = <_default_pins>;
};
 
+   gpio1: gpio@4e00 {
+   pinctrl-names = "default";
+   pinctrl-0 = <_default_pins>;
+   };
+
pci@5000 {
status = "okay";
interrupt-map-mask = <0xf800 0 0 7>;
@@ -235,7 +305,8 @@
phy-handle = <>;
};
ethernet-port@1 {
-   /* Used for the Vitesse G5 chip, add later */
+   phy-mode = "rgmii";
+   phy-handle = <>;
};
};
 
-- 
2.17.1


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