The PINS conntrolled by the SPI bits in the GPIO_MODE register is always
7 and not 8 for nand mode.
Signed-off-by: Sven Eckelmann <s...@open-mesh.com>
---
v2:
- split into multiple patches
.../linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
index f08ecb032623..7c29fbeedb35 100644
--- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
+++ b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
@@ -593,7 +593,7 @@ Signed-off-by: John Crispin <blo...@openwrt.org>
+static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii", 0, 22, 12) };
+static struct rt2880_pmx_func spi_grp[] = {
+ FUNC("spi", 0, 34, 7),
-+ FUNC("nand", 2, 34, 8),
++ FUNC("nand", 2, 34, 7),
+};
+static struct rt2880_pmx_func sdhci_grp[] = {
+ FUNC("sdhci", 0, 41, 8),
--
2.5.0
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