On 10.12.21 12:13, Denis K wrote:
Thomas Hühn wrote:
We have 5 Mikrotik 912UAG in our Freifunk Network and just build and updated
them today with latest tunk .. we moved vom ar71xx to ath79 successfully,
so far so good .. thx for your upstream work!
The only thing that is not working: we can not get your 2nd wifi card in the
mPCIe port up and running. Only the USB Port is working. We have tried
several things to switch from USB to mPCIe .. without success:
* change the dts file ar9342_mikrotik_routerboard-912uag-2hpnd.dts in
the gpio-export section to have usb_power output = 0 and pcie_power = 1
mPCIe port is powered with 3,3V (measured on in 2 & 4) but mPCIe WiFi
cards (ath9k - mikrotik) are not detected, tried to rescan the PCI bus
as well
* change on a running 912UAG i the /sys/class/gpio/power_usb
../power-pcie/values ... not WiFi Card detection
* compare the running und working mPCIe port ar71xx image on the router ...
found out there is gpio52 used, but different latch setup .. our good
gues was that GPIO20 could be responsible for the usb switch for the mPCIe
port .. add gpio20 to the export folder and set it to 1.. but no WiFi card
detection
Who has some troubleshooting tips for how to disable the usb port and enable
the mPCIe port?
I've done some tests with RB912UAG-2HPnD and R11e-5HacT.
It seems that you need to set power-pcie gpio before pci controller
driver starts. Since it doesn't support hotplug or rescan (I suppose).
gpio-export starts after, so I've used this temporarily hack in ssr
node in dts (gpio-hog):
ssr: ssr@1 {
compatible = "fairchild,74hc595";
gpio-controller;
#gpio-cells = <2>;
registers-number = <1>;
reg = <1>;
spi-max-frequency = <5000>;
power_pcie {
gpio-hog;
gpios = <7 0>;
output-high;
};
power_usb {
gpio-hog;
gpios = <6 0>;
output-low;
};
};
root@OpenWrt:~# lspci
00:00.0 Class 0280: 168c:003c
This workaround works, but it is better to make pci rescan working.
power_usb and power_pcie gpio lines are on the Serial Shift Register (ssr).
It seems that RouterBoot left both =1. But SSR while init set them =0. Then
the PCI controller (arch/mips/pci-ar724x) starts... and says: "PCIe link is
down", remembers this in the internal link_up field and never re-check
AR724x_PCI_RESET_LINK_UP register bit. When link_up is false, pci read/write
handlers always return error. When I patched it to actually check link status
before reading, I had kernel panic with Device bus error when trying to read
Vendor ID from config register (see "MIPS: pci-ar724x: avoid data bus error
due to a missing PCIe module" Gabor Juhos patch). It seems that we need to
somehow reinit the PCI host controller.
Does anyone have any ideas?
Regards, Denis
Checking ar71xx code shows that this same issue is avoided
by simply putting the PCI init function at the bottom of the complete hw
init sequence function.
So this workaround is fine for me as it's way better
to have working PCI today (and basically mimicing behaviour as done in
ar71xx)
than no PCI at all out of "principle".
Let's use evolution here iso revolution. :-)
Regards,
Koen
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