Re: [PATCH v5 00/13] Instantiate VT82xx functions in host device
Am 16. September 2022 14:36:05 UTC schrieb "Philippe Mathieu-Daudé" : >On 12/9/22 21:50, Bernhard Beschow wrote: >> Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow >> : > >>> Testing done: >>> >>> * `qemu-system-ppc -machine pegasos2 -rtc base=localtime -device >>> ati-vga,guest_hwcursor=true,romfile="" -cdrom morphos-3.17.iso -kernel >>> morphos-3.17/boot.img` >>> >>> Boots successfully and it is possible to open games and tools. >>> >>> >>> >>> * I was unable to test the fuloong2e board even before this series since it >>> seems to be unfinished [1]. >>> >>> A buildroot-baked kernel [2] booted but doesn't find its root partition, >>> though the issues could be in the buildroot receipt I created. >>> >>> >>> >>> [1] https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2 >>> >>> [2] https://github.com/shentok/buildroot/commits/fuloong2e >>> >> >> Copying from v2 (just found it in my spam folder :/): >> Series: >> Reviewed-by: Philippe Mathieu-Daudé >> >> Review seems complete, thanks to all who participated! Now we just need >> someone to queue this series. >> >> Best regards, >> Bernhard > >Excellent cleanup! Series queued to mips-next. Great! Can't wait for it to land.
Re: [PATCH 10/11] hw/sd/sdhci: Implement Freescale eSDHC device model
Am 16. September 2022 15:15:03 UTC schrieb Bin Meng :
>On Thu, Sep 15, 2022 at 11:30 PM Bernhard Beschow wrote:
>>
>> Will allow e500 boards to access SD cards using just their own devices.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> hw/sd/sdhci.c | 147 +-
>> include/hw/sd/sdhci.h | 3 +
>> 2 files changed, 149 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
>> index 7a5996caad..09285ccfa1 100644
>> --- a/hw/sd/sdhci.c
>> +++ b/hw/sd/sdhci.c
>> @@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s)
>> s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
>> sdhci_data_transfer, s);
>>
>> s->io_ops = &sdhci_mmio_ops;
>> +s->io_registers_map_size = SDHC_REGISTERS_MAP_SIZE;
>> }
>>
>> void sdhci_uninitfn(SDHCIState *s)
>> @@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
>> s->fifo_buffer = g_malloc0(s->buf_maxsz);
>>
>> memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
>> - SDHC_REGISTERS_MAP_SIZE);
>> + s->io_registers_map_size);
>> }
>>
>> void sdhci_common_unrealize(SDHCIState *s)
>> @@ -1575,6 +1576,149 @@ static const TypeInfo sdhci_bus_info = {
>> .class_init = sdhci_bus_class_init,
>> };
>>
>> +/* --- qdev Freescale eSDHC --- */
>> +
>> +/* Host Controller Capabilities Register 2 */
>> +#define ESDHC_CAPABILITIES_10x114
>> +
>> +/* Control Register for DMA transfer */
>> +#define ESDHC_DMA_SYSCTL0x40c
>> +#define ESDHC_PERIPHERAL_CLK_SEL0x0008
>> +#define ESDHC_FLUSH_ASYNC_FIFO 0x0004
>> +#define ESDHC_DMA_SNOOP 0x0040
>
>It looks the above 3 bit fields are not used?
Yes, possibly. I'll check for more unused stuff.
>> +
>> +#define ESDHC_REGISTERS_MAP_SIZE0x410
>> +
>> +static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size)
>> +{
>> +uint64_t ret;
>> +
>> +if (size != 4) {
>> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
>> + " wrong size\n", size, offset);
>> +return 0;
>> +}
>> +
>> +if (offset & 0x3) {
>> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
>> + " unaligned\n", size, offset);
>> +return 0;
>> +}
>> +
>> +switch (offset) {
>> +case SDHC_SYSAD:
>> +case SDHC_BLKSIZE:
>> +case SDHC_ARGUMENT:
>> +case SDHC_TRNMOD:
>> +case SDHC_RSPREG0:
>> +case SDHC_RSPREG1:
>> +case SDHC_RSPREG2:
>> +case SDHC_RSPREG3:
>> +case SDHC_BDATA:
>> +case SDHC_PRNSTS:
>> +case SDHC_HOSTCTL:
>> +case SDHC_CLKCON:
>> +case SDHC_NORINTSTS:
>> +case SDHC_NORINTSTSEN:
>> +case SDHC_NORINTSIGEN:
>> +case SDHC_ACMD12ERRSTS:
>> +case SDHC_CAPAB:
>> +case SDHC_SLOT_INT_STATUS:
>> +ret = sdhci_read(opaque, offset, size);
>> +break;
>> +
>> +case ESDHC_DMA_SYSCTL:
>> +case 0x44:
>
>Can we define a macro for this offset?
Sure. Not sure why I didn't.
>> +ret = 0;
>> +qemu_log_mask(LOG_UNIMP, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
>> + " not implemented\n", size, offset);
>> +break;
>> +
>> +default:
>> +ret = 0;
>> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
>> + " unknown offset\n", size, offset);
>> +break;
>> +}
>> +
>> +return ret;
>> +}
>> +
>> +static void esdhci_write(void *opaque, hwaddr offset, uint64_t val,
>> + unsigned size)
>> +{
>> +if (size != 4) {
>> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
>> + " <- 0x%08lx wrong size\n", size, offset, val);
>> +return;
>> +}
>> +
>> +if (offset & 0x3) {
>> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
>> + " <- 0x%08lx unaligned\n", size, offset, val);
>> +return;
>> +}
>> +
>> +switch (offset) {
>> +case SDHC_SYSAD:
>> +case SDHC_BLKSIZE:
>> +case SDHC_ARGUMENT:
>> +case SDHC_TRNMOD:
>> +case SDHC_BDATA:
>> +case SDHC_HOSTCTL:
>> +case SDHC_CLKCON:
>> +case SDHC_NORINTSTS:
>> +case SDHC_NORINTSTSEN:
>> +case SDHC_NORINTSIGEN:
>> +case SDHC_FEAER:
>> +sdhci_write(opaque, offset, val, size);
>> +break;
>> +
>> +case ESDHC_DMA_SYSCTL:
>> +case 0x44:
>
>ditto
Ack.
Best regards,
Bernhard
>
>> +qemu_log_mask(LOG_UNIMP, "ESDHC wr_%ub @0x%02" HWADDR_PRIx " <-
>> 0x%08lx "
>> + "not implemented\n", size, offset, val);
>> +break;
>> +
>> +default:
>> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
>> + " <- 0x%08lx unknown offset\n", size, offset, val);
>> +break;
>> +}
>> +}
>> +
>> +static const MemoryRegionOps esdhc_mmi
Re: [PATCH 04/11] hw/ppc/mpc8544ds: Add platform bus
Am 16. September 2022 06:15:53 UTC schrieb Bin Meng : >On Thu, Sep 15, 2022 at 11:29 PM Bernhard Beschow wrote: >> >> Models the real device more closely. > >Please describe the source (e.g.: I assume it's MPC8544DS board manual >or something like that?) that describe such memory map for the >platform bus. > >Is this the eLBC bus range that includes the NOR flash device? Good point. My numbers come from a different board. I'll fix them according to the mpc8544ds.dts in the Linux tree. This will leave an eLBC memory window of just 8MB while my proprietary load needs 64MB. My proprietary load doesn't seem to have 64 bit physical memory support so I can't use e500plat either. Any suggestions? Best regards, Bernhard > >> >> Signed-off-by: Bernhard Beschow >> --- >> hw/ppc/mpc8544ds.c | 6 ++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/hw/ppc/mpc8544ds.c b/hw/ppc/mpc8544ds.c >> index 81177505f0..cd6cd04bef 100644 >> --- a/hw/ppc/mpc8544ds.c >> +++ b/hw/ppc/mpc8544ds.c >> @@ -14,6 +14,7 @@ >> #include "sysemu/device_tree.h" >> #include "hw/ppc/openpic.h" >> #include "qemu/error-report.h" >> +#include "qemu/units.h" >> #include "cpu.h" >> >> static void mpc8544ds_fixup_devtree(void *fdt) >> @@ -45,6 +46,11 @@ static void e500plat_machine_class_init(ObjectClass *oc, >> void *data) >> pmc->pci_nr_slots = 2; >> pmc->fixup_devtree = mpc8544ds_fixup_devtree; >> pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; >> +pmc->has_platform_bus = true; >> +pmc->platform_bus_base = 0xEC00ULL; >> +pmc->platform_bus_size = 128 * MiB; >> +pmc->platform_bus_first_irq = 5; >> +pmc->platform_bus_num_irqs = 10; >> pmc->ccsrbar_base = 0xE000ULL; >> pmc->pci_mmio_base = 0xC000ULL; >> pmc->pci_mmio_bus_base = 0xC000ULL; >> -- > >Regards, >Bin
Re: [PATCH 09/11] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
Am 16. September 2022 10:07:28 UTC schrieb Bin Meng :
>On Thu, Sep 15, 2022 at 11:42 PM Bernhard Beschow wrote:
>>
>> The device model's functions start with "usdhc_", so rename the defines
>> accordingly for consistency.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> hw/sd/sdhci.c | 68 +--
>> 1 file changed, 34 insertions(+), 34 deletions(-)
>>
>> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
>> index 6da5e2c781..7a5996caad 100644
>> --- a/hw/sd/sdhci.c
>> +++ b/hw/sd/sdhci.c
>> @@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = {
>>
>> /* --- qdev i.MX eSDHC --- */
>>
>> -#define ESDHC_MIX_CTRL 0x48
>> +#define USDHC_MIX_CTRL 0x48
>>
>> -#define ESDHC_VENDOR_SPEC 0xc0
>> -#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8)
>> +#define USDHC_VENDOR_SPEC 0xc0
>> +#define USDHC_IMX_FRC_SDCLK_ON (1 << 8)
>>
>> -#define ESDHC_DLL_CTRL 0x60
>> +#define USDHC_DLL_CTRL 0x60
>>
>> -#define ESDHC_TUNING_CTRL 0xcc
>> -#define ESDHC_TUNE_CTRL_STATUS 0x68
>> -#define ESDHC_WTMK_LVL 0x44
>> +#define USDHC_TUNING_CTRL 0xcc
>> +#define USDHC_TUNE_CTRL_STATUS 0x68
>> +#define USDHC_WTMK_LVL 0x44
>>
>> /* Undocumented register used by guests working around erratum ERR004536 */
>> -#define ESDHC_UNDOCUMENTED_REG270x6c
>> +#define USDHC_UNDOCUMENTED_REG270x6c
>>
>> -#define ESDHC_CTRL_4BITBUS (0x1 << 1)
>> -#define ESDHC_CTRL_8BITBUS (0x2 << 1)
>> +#define USDHC_CTRL_4BITBUS (0x1 << 1)
>> +#define USDHC_CTRL_8BITBUS (0x2 << 1)
>>
>> -#define ESDHC_PRNSTS_SDSTB (1 << 3)
>> +#define USDHC_PRNSTS_SDSTB (1 << 3)
>>
>> static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
>> {
>> @@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr
>> offset, unsigned size)
>> hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
>>
>> if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
>> -hostctl1 |= ESDHC_CTRL_8BITBUS;
>> +hostctl1 |= USDHC_CTRL_8BITBUS;
>> }
>>
>> if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
>> -hostctl1 |= ESDHC_CTRL_4BITBUS;
>> +hostctl1 |= USDHC_CTRL_4BITBUS;
>> }
>>
>> ret = hostctl1;
>> @@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr
>> offset, unsigned size)
>>
>> case SDHC_PRNSTS:
>> /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
>> -ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
>> +ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
>> if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
>> -ret |= ESDHC_PRNSTS_SDSTB;
>> +ret |= USDHC_PRNSTS_SDSTB;
>> }
>> break;
>>
>> -case ESDHC_VENDOR_SPEC:
>> +case USDHC_VENDOR_SPEC:
>> ret = s->vendor_spec;
>> break;
>> -case ESDHC_DLL_CTRL:
>> -case ESDHC_TUNE_CTRL_STATUS:
>> -case ESDHC_UNDOCUMENTED_REG27:
>> -case ESDHC_TUNING_CTRL:
>> -case ESDHC_MIX_CTRL:
>> -case ESDHC_WTMK_LVL:
>> +case USDHC_DLL_CTRL:
>> +case USDHC_TUNE_CTRL_STATUS:
>> +case USDHC_UNDOCUMENTED_REG27:
>> +case USDHC_TUNING_CTRL:
>> +case USDHC_MIX_CTRL:
>> +case USDHC_WTMK_LVL:
>> ret = 0;
>> break;
>> }
>> @@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t
>> val, unsigned size)
>> uint32_t value = (uint32_t)val;
>>
>> switch (offset) {
>> -case ESDHC_DLL_CTRL:
>> -case ESDHC_TUNE_CTRL_STATUS:
>> -case ESDHC_UNDOCUMENTED_REG27:
>> -case ESDHC_TUNING_CTRL:
>> -case ESDHC_WTMK_LVL:
>> +case USDHC_DLL_CTRL:
>> +case USDHC_TUNE_CTRL_STATUS:
>> +case USDHC_UNDOCUMENTED_REG27:
>> +case USDHC_TUNING_CTRL:
>> +case USDHC_WTMK_LVL:
>> break;
>>
>> -case ESDHC_VENDOR_SPEC:
>> +case USDHC_VENDOR_SPEC:
>> s->vendor_spec = value;
>> switch (s->vendor) {
>> case SDHCI_VENDOR_IMX:
>> -if (value & ESDHC_IMX_FRC_SDCLK_ON) {
>> +if (value & USDHC_IMX_FRC_SDCLK_ON) {
>> s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
>> } else {
>> s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
>> @@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t
>> val, unsigned size)
>> * Second, split "Data Transfer Width" from bits 2 and 1 in to
>> * bits 5 and 1
>> */
>> -if (value & ESDHC_CTRL_8BITBUS) {
>> +if (value & USDHC_CTRL_8BITBUS) {
>> hostctl1 |= SDHC_CTRL_8BITBUS;
>> }
>>
>> -if (value & ESDHC_CTRL_4BITBUS) {
>> -hostctl1 |= ESDHC_CTRL_4BITBUS;
>> +if (value & USDHC_CTRL_4BITBUS) {
>> +
Re: [PATCH 07/11] hw/ppc/e500: Implement pflash handling
Am 16. September 2022 15:00:06 UTC schrieb Bin Meng :
>On Thu, Sep 15, 2022 at 11:36 PM Bernhard Beschow wrote:
>>
>> Allows e500 boards to have their root file system reside on flash using
>> only builtin devices.
>>
>> Note that the flash memory area is only created when a -pflash argument is
>> given, and that the size is determined by the given file. The idea is to
>> put users into control.
>>
>> Signed-off-by: Bernhard Beschow
>> ---
>> docs/system/ppc/ppce500.rst | 12 +
>> hw/ppc/Kconfig | 1 +
>> hw/ppc/e500.c | 54 +
>> 3 files changed, 67 insertions(+)
>>
>> diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
>> index ba6bcb7314..c3f55c6f3d 100644
>> --- a/docs/system/ppc/ppce500.rst
>> +++ b/docs/system/ppc/ppce500.rst
>> @@ -119,6 +119,18 @@ To boot the 32-bit Linux kernel:
>>-initrd /path/to/rootfs.cpio \
>>-append "root=/dev/ram"
>>
>> +Rather than using a root file system on ram disk, it is possible to have it
>> on
>> +emulated flash. Given an ext2 image whose size must be a power of two, it
>> can
>> +be used as follows:
>> +
>> +.. code-block:: bash
>> +
>> + $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
>
>qemu-system-ppc{64|32}
Will fix.
>> + -display none -serial stdio \
>> + -kernel vmlinux \
>> + -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
>> + -append "rootwait root=/dev/mtdblock0"
>> +
>> Running U-Boot
>> --
>>
>> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
>> index 791fe78a50..769a1ead1c 100644
>> --- a/hw/ppc/Kconfig
>> +++ b/hw/ppc/Kconfig
>> @@ -126,6 +126,7 @@ config E500
>> select ETSEC
>> select GPIO_MPC8XXX
>> select OPENPIC
>> +select PFLASH_CFI01
>> select PLATFORM_BUS
>> select PPCE500_PCI
>> select SERIAL
>> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
>> index 864b6f3d92..7843a4e04b 100644
>> --- a/hw/ppc/e500.c
>> +++ b/hw/ppc/e500.c
>> @@ -23,8 +23,10 @@
>> #include "e500-ccsr.h"
>> #include "net/net.h"
>> #include "qemu/config-file.h"
>> +#include "hw/block/flash.h"
>> #include "hw/char/serial.h"
>> #include "hw/pci/pci.h"
>> +#include "sysemu/block-backend-io.h"
>> #include "sysemu/sysemu.h"
>> #include "sysemu/kvm.h"
>> #include "sysemu/reset.h"
>> @@ -267,6 +269,34 @@ static void sysbus_device_create_devtree(SysBusDevice
>> *sbdev, void *opaque)
>> }
>> }
>>
>> +static void create_devtree_flash(SysBusDevice *sbdev,
>> + PlatformDevtreeData *data)
>> +{
>> +char *name;
>
>Use g_autofree
Yes, good idea.
>> +uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
>> + "num-blocks",
>> + &error_fatal);
>> +uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
>> + "sector-length",
>> + &error_fatal);
>> +uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
>> + "width",
>> + &error_fatal);
>> +hwaddr flashbase = 0;
>> +hwaddr flashsize = num_blocks * sector_length;
>> +void *fdt = data->fdt;
>> +
>> +name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
>> +qemu_fdt_add_subnode(fdt, name);
>> +qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1);
>> +qemu_fdt_setprop_cell(fdt, name, "#size-cells", 1);
>
>#address-cells and #size-cells are not needed.
Will remove.
>> +qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
>> +qemu_fdt_setprop_sized_cells(fdt, name, "reg",
>> + 1, flashbase, 1, flashsize);
>> +qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
>> +g_free(name);
>> +}
>> +
>> static void platform_bus_create_devtree(PPCE500MachineState *pms,
>> void *fdt, const char *mpic)
>> {
>> @@ -276,6 +306,8 @@ static void
>> platform_bus_create_devtree(PPCE500MachineState *pms,
>> uint64_t addr = pmc->platform_bus_base;
>> uint64_t size = pmc->platform_bus_size;
>> int irq_start = pmc->platform_bus_first_irq;
>> +SysBusDevice *sbdev;
>> +bool ambiguous;
>>
>> /* Create a /platform node that we can put all devices into */
>>
>> @@ -302,6 +334,13 @@ static void
>> platform_bus_create_devtree(PPCE500MachineState *pms,
>> /* Loop through all dynamic sysbus devices and create nodes for them */
>> foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
>>
>> +sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
>> +&ambiguous));
>
>Can this be moved into sysbus_device_create_devtree(), and use the
>same l
Re: [PATCH 11/11] hw/ppc/e500: Add Freescale eSDHC to e500 boards
On Fri, Sep 16, 2022 at 5:26 PM Bin Meng wrote:
> On Thu, Sep 15, 2022 at 11:30 PM Bernhard Beschow
> wrote:
> >
> > Adds missing functionality to emulated e500 SOCs which increases the
> > chance of given "real" firmware images to access SD cards.
>
> By "firmware" do you mean U-Boot?
>
No, I mean a proprietary flash blob including partitions for the kernel,
root fs, U-Boot, etc.
>
> > Signed-off-by: Bernhard Beschow
> > ---
> > docs/system/ppc/ppce500.rst | 13 +
> > hw/ppc/Kconfig | 1 +
> > hw/ppc/e500.c | 32
> > 3 files changed, 46 insertions(+)
> >
> > diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
> > index c3f55c6f3d..50b199c8f3 100644
> > --- a/docs/system/ppc/ppce500.rst
> > +++ b/docs/system/ppc/ppce500.rst
> > @@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices:
> > * Power-off functionality via one GPIO pin
> > * 1 Freescale MPC8xxx PCI host controller
> > * VirtIO devices via PCI bus
> > +* 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
> > * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
> >
> > Hardware configuration information
> > @@ -131,6 +132,18 @@ be used as follows:
> >-drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
> >-append "rootwait root=/dev/mtdblock0"
> >
> > +Alternatively, the root file system can also reside on an emulated SD
> card
> > +whose size must again be a power of two:
> > +
> > +.. code-block:: bash
> > +
> > + $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
>
> qemu-system-ppc{64|32}
>
Will fix.
> > + -display none -serial stdio \
> > + -kernel vmlinux \
> > + -device sd-card,drive=mydrive \
> > + -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \
> > + -append "rootwait root=/dev/mmcblk0"
> > +
> > Running U-Boot
> > --
> >
> > diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> > index 769a1ead1c..6e31f568ba 100644
> > --- a/hw/ppc/Kconfig
> > +++ b/hw/ppc/Kconfig
> > @@ -129,6 +129,7 @@ config E500
> > select PFLASH_CFI01
> > select PLATFORM_BUS
> > select PPCE500_PCI
> > +select SDHCI
> > select SERIAL
> > select MPC_I2C
> > select FDT_PPC
> > diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> > index 7843a4e04b..87a03fd4a9 100644
> > --- a/hw/ppc/e500.c
> > +++ b/hw/ppc/e500.c
> > @@ -48,6 +48,7 @@
> > #include "hw/net/fsl_etsec/etsec.h"
> > #include "hw/i2c/i2c.h"
> > #include "hw/irq.h"
> > +#include "hw/sd/sdhci.h"
> >
> > #define EPAPR_MAGIC(0x45504150)
> > #define DTC_LOAD_PAD 0x180
> > @@ -66,11 +67,14 @@
> > #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
> > #define MPC8544_PCI_REGS_OFFSET0x8000ULL
> > #define MPC8544_PCI_REGS_SIZE 0x1000ULL
> > +#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
> > +#define MPC85XX_ESDHC_REGS_SIZE0x1000ULL
> > #define MPC8544_UTIL_OFFSET0xeULL
> > #define MPC8XXX_GPIO_OFFSET0x000FF000ULL
> > #define MPC8544_I2C_REGS_OFFSET0x3000ULL
> > #define MPC8XXX_GPIO_IRQ 47
> > #define MPC8544_I2C_IRQ43
> > +#define MPC85XX_ESDHC_IRQ 72
> > #define RTC_REGS_OFFSET0x68
> >
> > #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
> > @@ -203,6 +207,25 @@ static void dt_i2c_create(void *fdt, const char
> *soc, const char *mpic,
> > g_free(i2c);
> > }
> >
> > +static void dt_sdhc_create(void *fdt, const char *parent, const char
> *mpic)
> > +{
> > +hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
> > +hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
> > +int irq = MPC85XX_ESDHC_IRQ;
> > +char *name;
> > +
> > +name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
> > +qemu_fdt_add_subnode(fdt, name);
> > +/* qemu_fdt_setprop_cells(fdt, name, "voltage-ranges", 3300, 3300);
> */
>
> Drop it if it is useless
>
> > +qemu_fdt_setprop_cells(fdt, name, "clock-frequency", 16700);
>
> Is this an arbitrary frequency?
>
I'll drop both since the eSDHC works also without the frequency line.
> +qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
> > +qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
> > +qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
> > +qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
> > +qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
> > +qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
> > +g_free(name);
> > +}
> >
> > typedef struct PlatformDevtreeData {
> > void *fdt;
> > @@ -556,6 +579,8 @@ static int
> ppce500_load_device_tree(PPCE500MachineState *pms,
> >
> > dt_rtc_create(fdt, "i2c", "rtc");
> >
> > +/* sdhc */
> > +dt_sdhc_create(fdt, soc, mpic);
> >
> > gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
> > MPC8544_UTIL_OFFSET);
> > @@ -996,6 +1021,13 @@ voi
Re: [PATCH 00/11] ppc/e500: Add support for two types of flash, cleanup
On Fri, Sep 16, 2022 at 5:27 PM Bin Meng wrote: > Hi Bernhard, > Hi Bin, > On Thu, Sep 15, 2022 at 11:25 PM Bernhard Beschow > wrote: > > > > This series adds support for -pflash and direct SD card access to the > > PPC e500 boards. The idea is to increase compatibility with "real" > firmware > > images where only the bare minimum of drivers is compiled in. > > > > The series is structured as follows: > > > > Patches 1-3 perform some general cleanup which paves the way for the > rest of > > the series. > > > > Patches 4-7 add -pflash handling where memory-mapped flash can be added > on > > user's behalf. That is, the flash memory region is only added if the > -pflash > > argument is supplied. Note that the cfi01 device model becomes stricter > in > > checking the size of the emulated flash space. > > > > Patches 8-11 add a new device model - the Freescale eSDHC - to the e500 > > boards which was missing so far. > > > > User documentation is also added as the new features become available. > > > > Tesing done: > > * `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append > > "console=ttyS0 rootwait root=/dev/mtdblock0 nokaslr" -drive > > if=pflash,file=rootfs.ext2,format=raw` > > * `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append > > "console=ttyS0 rootwait root=/dev/mmcblk0" -device sd-card,drive=mydrive > -drive > > id=mydrive,if=none,file=rootfs.ext2,format=raw` > > Thanks for the patches! > My obligation! > Did you get a chance to test the U-Boot image to work with pflash and > eSDHC? > No, unfortunately not. Testing U-Boot would involve familiarizing myself with it first which will probably come at some point. Right now, however, my focus is on running a proprietary firmware flash image. Best regards, Bernhard > > > > The load was created using latest Buildroot with `make > > qemu_ppc_e500mc_defconfig` where the rootfs was configured to be of ext2 > type. > > In both cases it was possible to log in and explore the root file system. > > > > Regards, > Bin >
Re: [PATCH 00/11] ppc/e500: Add support for two types of flash, cleanup
Hi Bernhard, On Thu, Sep 15, 2022 at 11:25 PM Bernhard Beschow wrote: > > This series adds support for -pflash and direct SD card access to the > PPC e500 boards. The idea is to increase compatibility with "real" firmware > images where only the bare minimum of drivers is compiled in. > > The series is structured as follows: > > Patches 1-3 perform some general cleanup which paves the way for the rest of > the series. > > Patches 4-7 add -pflash handling where memory-mapped flash can be added on > user's behalf. That is, the flash memory region is only added if the -pflash > argument is supplied. Note that the cfi01 device model becomes stricter in > checking the size of the emulated flash space. > > Patches 8-11 add a new device model - the Freescale eSDHC - to the e500 > boards which was missing so far. > > User documentation is also added as the new features become available. > > Tesing done: > * `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append > "console=ttyS0 rootwait root=/dev/mtdblock0 nokaslr" -drive > if=pflash,file=rootfs.ext2,format=raw` > * `qemu-system-ppc -M ppce500 -cpu e500mc -m 256 -kernel uImage -append > "console=ttyS0 rootwait root=/dev/mmcblk0" -device sd-card,drive=mydrive > -drive > id=mydrive,if=none,file=rootfs.ext2,format=raw` Thanks for the patches! Did you get a chance to test the U-Boot image to work with pflash and eSDHC? > > The load was created using latest Buildroot with `make > qemu_ppc_e500mc_defconfig` where the rootfs was configured to be of ext2 type. > In both cases it was possible to log in and explore the root file system. > Regards, Bin
Re: [PATCH 11/11] hw/ppc/e500: Add Freescale eSDHC to e500 boards
On Thu, Sep 15, 2022 at 11:30 PM Bernhard Beschow wrote:
>
> Adds missing functionality to emulated e500 SOCs which increases the
> chance of given "real" firmware images to access SD cards.
By "firmware" do you mean U-Boot?
>
> Signed-off-by: Bernhard Beschow
> ---
> docs/system/ppc/ppce500.rst | 13 +
> hw/ppc/Kconfig | 1 +
> hw/ppc/e500.c | 32
> 3 files changed, 46 insertions(+)
>
> diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
> index c3f55c6f3d..50b199c8f3 100644
> --- a/docs/system/ppc/ppce500.rst
> +++ b/docs/system/ppc/ppce500.rst
> @@ -19,6 +19,7 @@ The ``ppce500`` machine supports the following devices:
> * Power-off functionality via one GPIO pin
> * 1 Freescale MPC8xxx PCI host controller
> * VirtIO devices via PCI bus
> +* 1 Freescale Enhanced Secure Digital Host controller (eSDHC)
> * 1 Freescale Enhanced Triple Speed Ethernet controller (eTSEC)
>
> Hardware configuration information
> @@ -131,6 +132,18 @@ be used as follows:
>-drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
>-append "rootwait root=/dev/mtdblock0"
>
> +Alternatively, the root file system can also reside on an emulated SD card
> +whose size must again be a power of two:
> +
> +.. code-block:: bash
> +
> + $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
qemu-system-ppc{64|32}
> + -display none -serial stdio \
> + -kernel vmlinux \
> + -device sd-card,drive=mydrive \
> + -drive id=mydrive,if=none,file=/path/to/rootfs.ext2,format=raw \
> + -append "rootwait root=/dev/mmcblk0"
> +
> Running U-Boot
> --
>
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index 769a1ead1c..6e31f568ba 100644
> --- a/hw/ppc/Kconfig
> +++ b/hw/ppc/Kconfig
> @@ -129,6 +129,7 @@ config E500
> select PFLASH_CFI01
> select PLATFORM_BUS
> select PPCE500_PCI
> +select SDHCI
> select SERIAL
> select MPC_I2C
> select FDT_PPC
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 7843a4e04b..87a03fd4a9 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -48,6 +48,7 @@
> #include "hw/net/fsl_etsec/etsec.h"
> #include "hw/i2c/i2c.h"
> #include "hw/irq.h"
> +#include "hw/sd/sdhci.h"
>
> #define EPAPR_MAGIC(0x45504150)
> #define DTC_LOAD_PAD 0x180
> @@ -66,11 +67,14 @@
> #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
> #define MPC8544_PCI_REGS_OFFSET0x8000ULL
> #define MPC8544_PCI_REGS_SIZE 0x1000ULL
> +#define MPC85XX_ESDHC_REGS_OFFSET 0x2e000ULL
> +#define MPC85XX_ESDHC_REGS_SIZE0x1000ULL
> #define MPC8544_UTIL_OFFSET0xeULL
> #define MPC8XXX_GPIO_OFFSET0x000FF000ULL
> #define MPC8544_I2C_REGS_OFFSET0x3000ULL
> #define MPC8XXX_GPIO_IRQ 47
> #define MPC8544_I2C_IRQ43
> +#define MPC85XX_ESDHC_IRQ 72
> #define RTC_REGS_OFFSET0x68
>
> #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000)
> @@ -203,6 +207,25 @@ static void dt_i2c_create(void *fdt, const char *soc,
> const char *mpic,
> g_free(i2c);
> }
>
> +static void dt_sdhc_create(void *fdt, const char *parent, const char *mpic)
> +{
> +hwaddr mmio = MPC85XX_ESDHC_REGS_OFFSET;
> +hwaddr size = MPC85XX_ESDHC_REGS_SIZE;
> +int irq = MPC85XX_ESDHC_IRQ;
> +char *name;
> +
> +name = g_strdup_printf("%s/sdhc@%" PRIx64, parent, mmio);
> +qemu_fdt_add_subnode(fdt, name);
> +/* qemu_fdt_setprop_cells(fdt, name, "voltage-ranges", 3300, 3300); */
Drop it if it is useless
> +qemu_fdt_setprop_cells(fdt, name, "clock-frequency", 16700);
Is this an arbitrary frequency?
> +qemu_fdt_setprop(fdt, name, "sdhci,auto-cmd12", NULL, 0);
> +qemu_fdt_setprop_phandle(fdt, name, "interrupt-parent", mpic);
> +qemu_fdt_setprop_cells(fdt, name, "bus-width", 4);
> +qemu_fdt_setprop_cells(fdt, name, "interrupts", irq, 0x2);
> +qemu_fdt_setprop_cells(fdt, name, "reg", mmio, size);
> +qemu_fdt_setprop_string(fdt, name, "compatible", "fsl,esdhc");
> +g_free(name);
> +}
>
> typedef struct PlatformDevtreeData {
> void *fdt;
> @@ -556,6 +579,8 @@ static int ppce500_load_device_tree(PPCE500MachineState
> *pms,
>
> dt_rtc_create(fdt, "i2c", "rtc");
>
> +/* sdhc */
> +dt_sdhc_create(fdt, soc, mpic);
>
> gutil = g_strdup_printf("%s/global-utilities@%llx", soc,
> MPC8544_UTIL_OFFSET);
> @@ -996,6 +1021,13 @@ void ppce500_init(MachineState *machine)
> i2c_slave_create_simple(i2c, "ds1338", RTC_REGS_OFFSET);
>
>
nits: use one line for the separation
> +/* eSDHC */
> +dev = qdev_new(TYPE_FSL_ESDHC);
> +s = SYS_BUS_DEVICE(dev);
> +sysbus_realize_and_unref(s, &error_fatal);
> +sysbus_mmio_map(s, 0, pmc->ccsrbar_base + MPC85XX_ESDHC_REGS_OFFSET);
> +sysbus_connect_irq(s, 0, qdev_get_gpio_in(mpicdev, MPC85XX_ESDHC_IRQ));
> +
> /* General Utility device */
>
Re: [PATCH 10/11] hw/sd/sdhci: Implement Freescale eSDHC device model
On Thu, Sep 15, 2022 at 11:30 PM Bernhard Beschow wrote:
>
> Will allow e500 boards to access SD cards using just their own devices.
>
> Signed-off-by: Bernhard Beschow
> ---
> hw/sd/sdhci.c | 147 +-
> include/hw/sd/sdhci.h | 3 +
> 2 files changed, 149 insertions(+), 1 deletion(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 7a5996caad..09285ccfa1 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1369,6 +1369,7 @@ void sdhci_initfn(SDHCIState *s)
> s->transfer_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> sdhci_data_transfer, s);
>
> s->io_ops = &sdhci_mmio_ops;
> +s->io_registers_map_size = SDHC_REGISTERS_MAP_SIZE;
> }
>
> void sdhci_uninitfn(SDHCIState *s)
> @@ -1392,7 +1393,7 @@ void sdhci_common_realize(SDHCIState *s, Error **errp)
> s->fifo_buffer = g_malloc0(s->buf_maxsz);
>
> memory_region_init_io(&s->iomem, OBJECT(s), s->io_ops, s, "sdhci",
> - SDHC_REGISTERS_MAP_SIZE);
> + s->io_registers_map_size);
> }
>
> void sdhci_common_unrealize(SDHCIState *s)
> @@ -1575,6 +1576,149 @@ static const TypeInfo sdhci_bus_info = {
> .class_init = sdhci_bus_class_init,
> };
>
> +/* --- qdev Freescale eSDHC --- */
> +
> +/* Host Controller Capabilities Register 2 */
> +#define ESDHC_CAPABILITIES_10x114
> +
> +/* Control Register for DMA transfer */
> +#define ESDHC_DMA_SYSCTL0x40c
> +#define ESDHC_PERIPHERAL_CLK_SEL0x0008
> +#define ESDHC_FLUSH_ASYNC_FIFO 0x0004
> +#define ESDHC_DMA_SNOOP 0x0040
It looks the above 3 bit fields are not used?
> +
> +#define ESDHC_REGISTERS_MAP_SIZE0x410
> +
> +static uint64_t esdhci_read(void *opaque, hwaddr offset, unsigned size)
> +{
> +uint64_t ret;
> +
> +if (size != 4) {
> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
> + " wrong size\n", size, offset);
> +return 0;
> +}
> +
> +if (offset & 0x3) {
> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
> + " unaligned\n", size, offset);
> +return 0;
> +}
> +
> +switch (offset) {
> +case SDHC_SYSAD:
> +case SDHC_BLKSIZE:
> +case SDHC_ARGUMENT:
> +case SDHC_TRNMOD:
> +case SDHC_RSPREG0:
> +case SDHC_RSPREG1:
> +case SDHC_RSPREG2:
> +case SDHC_RSPREG3:
> +case SDHC_BDATA:
> +case SDHC_PRNSTS:
> +case SDHC_HOSTCTL:
> +case SDHC_CLKCON:
> +case SDHC_NORINTSTS:
> +case SDHC_NORINTSTSEN:
> +case SDHC_NORINTSIGEN:
> +case SDHC_ACMD12ERRSTS:
> +case SDHC_CAPAB:
> +case SDHC_SLOT_INT_STATUS:
> +ret = sdhci_read(opaque, offset, size);
> +break;
> +
> +case ESDHC_DMA_SYSCTL:
> +case 0x44:
Can we define a macro for this offset?
> +ret = 0;
> +qemu_log_mask(LOG_UNIMP, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
> + " not implemented\n", size, offset);
> +break;
> +
> +default:
> +ret = 0;
> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC rd_%ub @0x%02" HWADDR_PRIx
> + " unknown offset\n", size, offset);
> +break;
> +}
> +
> +return ret;
> +}
> +
> +static void esdhci_write(void *opaque, hwaddr offset, uint64_t val,
> + unsigned size)
> +{
> +if (size != 4) {
> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
> + " <- 0x%08lx wrong size\n", size, offset, val);
> +return;
> +}
> +
> +if (offset & 0x3) {
> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
> + " <- 0x%08lx unaligned\n", size, offset, val);
> +return;
> +}
> +
> +switch (offset) {
> +case SDHC_SYSAD:
> +case SDHC_BLKSIZE:
> +case SDHC_ARGUMENT:
> +case SDHC_TRNMOD:
> +case SDHC_BDATA:
> +case SDHC_HOSTCTL:
> +case SDHC_CLKCON:
> +case SDHC_NORINTSTS:
> +case SDHC_NORINTSTSEN:
> +case SDHC_NORINTSIGEN:
> +case SDHC_FEAER:
> +sdhci_write(opaque, offset, val, size);
> +break;
> +
> +case ESDHC_DMA_SYSCTL:
> +case 0x44:
ditto
> +qemu_log_mask(LOG_UNIMP, "ESDHC wr_%ub @0x%02" HWADDR_PRIx " <-
> 0x%08lx "
> + "not implemented\n", size, offset, val);
> +break;
> +
> +default:
> +qemu_log_mask(LOG_GUEST_ERROR, "ESDHC wr_%ub @0x%02" HWADDR_PRIx
> + " <- 0x%08lx unknown offset\n", size, offset, val);
> +break;
> +}
> +}
> +
> +static const MemoryRegionOps esdhc_mmio_ops = {
> +.read = esdhci_read,
> +.write = esdhci_write,
> +.valid = {
> +.min_access_size = 1,
> +.max_access_size = 4,
> +.unaligned = false
> +},
> +.endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +static void esdhci_init(Object *obj)
> +{
> +DeviceState *dev = DEVICE(
Re: [PATCH 07/11] hw/ppc/e500: Implement pflash handling
On Thu, Sep 15, 2022 at 11:36 PM Bernhard Beschow wrote:
>
> Allows e500 boards to have their root file system reside on flash using
> only builtin devices.
>
> Note that the flash memory area is only created when a -pflash argument is
> given, and that the size is determined by the given file. The idea is to
> put users into control.
>
> Signed-off-by: Bernhard Beschow
> ---
> docs/system/ppc/ppce500.rst | 12 +
> hw/ppc/Kconfig | 1 +
> hw/ppc/e500.c | 54 +
> 3 files changed, 67 insertions(+)
>
> diff --git a/docs/system/ppc/ppce500.rst b/docs/system/ppc/ppce500.rst
> index ba6bcb7314..c3f55c6f3d 100644
> --- a/docs/system/ppc/ppce500.rst
> +++ b/docs/system/ppc/ppce500.rst
> @@ -119,6 +119,18 @@ To boot the 32-bit Linux kernel:
>-initrd /path/to/rootfs.cpio \
>-append "root=/dev/ram"
>
> +Rather than using a root file system on ram disk, it is possible to have it
> on
> +emulated flash. Given an ext2 image whose size must be a power of two, it can
> +be used as follows:
> +
> +.. code-block:: bash
> +
> + $ qemu-system-ppc64 -M ppce500 -cpu e500mc -smp 4 -m 2G \
qemu-system-ppc{64|32}
> + -display none -serial stdio \
> + -kernel vmlinux \
> + -drive if=pflash,file=/path/to/rootfs.ext2,format=raw \
> + -append "rootwait root=/dev/mtdblock0"
> +
> Running U-Boot
> --
>
> diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig
> index 791fe78a50..769a1ead1c 100644
> --- a/hw/ppc/Kconfig
> +++ b/hw/ppc/Kconfig
> @@ -126,6 +126,7 @@ config E500
> select ETSEC
> select GPIO_MPC8XXX
> select OPENPIC
> +select PFLASH_CFI01
> select PLATFORM_BUS
> select PPCE500_PCI
> select SERIAL
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 864b6f3d92..7843a4e04b 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -23,8 +23,10 @@
> #include "e500-ccsr.h"
> #include "net/net.h"
> #include "qemu/config-file.h"
> +#include "hw/block/flash.h"
> #include "hw/char/serial.h"
> #include "hw/pci/pci.h"
> +#include "sysemu/block-backend-io.h"
> #include "sysemu/sysemu.h"
> #include "sysemu/kvm.h"
> #include "sysemu/reset.h"
> @@ -267,6 +269,34 @@ static void sysbus_device_create_devtree(SysBusDevice
> *sbdev, void *opaque)
> }
> }
>
> +static void create_devtree_flash(SysBusDevice *sbdev,
> + PlatformDevtreeData *data)
> +{
> +char *name;
Use g_autofree
> +uint64_t num_blocks = object_property_get_uint(OBJECT(sbdev),
> + "num-blocks",
> + &error_fatal);
> +uint64_t sector_length = object_property_get_uint(OBJECT(sbdev),
> + "sector-length",
> + &error_fatal);
> +uint64_t bank_width = object_property_get_uint(OBJECT(sbdev),
> + "width",
> + &error_fatal);
> +hwaddr flashbase = 0;
> +hwaddr flashsize = num_blocks * sector_length;
> +void *fdt = data->fdt;
> +
> +name = g_strdup_printf("%s/nor@%" PRIx64, data->node, flashbase);
> +qemu_fdt_add_subnode(fdt, name);
> +qemu_fdt_setprop_cell(fdt, name, "#address-cells", 1);
> +qemu_fdt_setprop_cell(fdt, name, "#size-cells", 1);
#address-cells and #size-cells are not needed.
> +qemu_fdt_setprop_string(fdt, name, "compatible", "cfi-flash");
> +qemu_fdt_setprop_sized_cells(fdt, name, "reg",
> + 1, flashbase, 1, flashsize);
> +qemu_fdt_setprop_cell(fdt, name, "bank-width", bank_width);
> +g_free(name);
> +}
> +
> static void platform_bus_create_devtree(PPCE500MachineState *pms,
> void *fdt, const char *mpic)
> {
> @@ -276,6 +306,8 @@ static void
> platform_bus_create_devtree(PPCE500MachineState *pms,
> uint64_t addr = pmc->platform_bus_base;
> uint64_t size = pmc->platform_bus_size;
> int irq_start = pmc->platform_bus_first_irq;
> +SysBusDevice *sbdev;
> +bool ambiguous;
>
> /* Create a /platform node that we can put all devices into */
>
> @@ -302,6 +334,13 @@ static void
> platform_bus_create_devtree(PPCE500MachineState *pms,
> /* Loop through all dynamic sysbus devices and create nodes for them */
> foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
>
> +sbdev = SYS_BUS_DEVICE(object_resolve_path_type("", TYPE_PFLASH_CFI01,
> +&ambiguous));
Can this be moved into sysbus_device_create_devtree(), and use the
same logic as the eTSEC device?
> +if (sbdev) {
> +assert(!ambiguous);
> +create_devtree_flash(sbdev, &data);
> +}
> +
> g_free(node);
> }
>
> @@ -856,6 +895,7 @@ void ppce500_init(MachineState *machine)
Re: [PATCH v5 13/13] hw/isa/vt82c686: Create rtc-time alias in boards instead
On 1/9/22 13:41, Bernhard Beschow wrote:
According to good QOM practice, an object should only deal with objects
of its own sub tree. Having devices create an alias on the machine
object doesn't respect this good practice. To resolve this, create the
alias in the machine's code.
Signed-off-by: Bernhard Beschow
---
hw/isa/vt82c686.c | 2 --
hw/mips/fuloong2e.c | 4
hw/ppc/pegasos2.c | 4
3 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 48cd4d0036..3f9bd0c04d 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -632,8 +632,6 @@ static void via_isa_realize(PCIDevice *d, Error **errp)
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
return;
}
-object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(&s->rtc),
- "date");
isa_connect_gpio_out(ISA_DEVICE(&s->rtc), 0, s->rtc.isairq);
for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) {
diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c
index 3c46215616..b478483706 100644
--- a/hw/mips/fuloong2e.c
+++ b/hw/mips/fuloong2e.c
@@ -295,6 +295,10 @@ static void mips_fuloong2e_init(MachineState *machine)
pci_dev = pci_create_simple_multifunction(pci_bus,
PCI_DEVFN(FULOONG2E_VIA_SLOT,
0),
true, TYPE_VT82C686B_ISA);
+object_property_add_alias(OBJECT(machine), "rtc-time",
+ object_resolve_path_component(OBJECT(pci_dev),
+"rtc"),
+ "date");
Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH v5 00/13] Instantiate VT82xx functions in host device
On 12/9/22 21:50, Bernhard Beschow wrote: Am 1. September 2022 11:41:14 UTC schrieb Bernhard Beschow : Testing done: * `qemu-system-ppc -machine pegasos2 -rtc base=localtime -device ati-vga,guest_hwcursor=true,romfile="" -cdrom morphos-3.17.iso -kernel morphos-3.17/boot.img` Boots successfully and it is possible to open games and tools. * I was unable to test the fuloong2e board even before this series since it seems to be unfinished [1]. A buildroot-baked kernel [2] booted but doesn't find its root partition, though the issues could be in the buildroot receipt I created. [1] https://osdn.net/projects/qmiga/wiki/SubprojectPegasos2 [2] https://github.com/shentok/buildroot/commits/fuloong2e Copying from v2 (just found it in my spam folder :/): Series: Reviewed-by: Philippe Mathieu-Daudé Review seems complete, thanks to all who participated! Now we just need someone to queue this series. Best regards, Bernhard Excellent cleanup! Series queued to mips-next.
Re: [PATCH v5 11/13] hw/mips/fuloong2e: Inline vt82c686b_southbridge_init() and remove it
On 1/9/22 13:41, Bernhard Beschow wrote: The previous patches moved most of this function into the via-isa device model such that it has become fairly trivial. So inline it for simplicity. Suggested-by: BALATON Zoltan Signed-off-by: Bernhard Beschow --- hw/mips/fuloong2e.c | 28 ++-- 1 file changed, 10 insertions(+), 18 deletions(-) Reviewed-by: Philippe Mathieu-Daudé
Re: [PATCH 09/11] hw/sd/sdhci: Rename ESDHC_* defines to USDHC_*
On Thu, Sep 15, 2022 at 11:42 PM Bernhard Beschow wrote:
>
> The device model's functions start with "usdhc_", so rename the defines
> accordingly for consistency.
>
> Signed-off-by: Bernhard Beschow
> ---
> hw/sd/sdhci.c | 68 +--
> 1 file changed, 34 insertions(+), 34 deletions(-)
>
> diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
> index 6da5e2c781..7a5996caad 100644
> --- a/hw/sd/sdhci.c
> +++ b/hw/sd/sdhci.c
> @@ -1577,24 +1577,24 @@ static const TypeInfo sdhci_bus_info = {
>
> /* --- qdev i.MX eSDHC --- */
>
> -#define ESDHC_MIX_CTRL 0x48
> +#define USDHC_MIX_CTRL 0x48
>
> -#define ESDHC_VENDOR_SPEC 0xc0
> -#define ESDHC_IMX_FRC_SDCLK_ON (1 << 8)
> +#define USDHC_VENDOR_SPEC 0xc0
> +#define USDHC_IMX_FRC_SDCLK_ON (1 << 8)
>
> -#define ESDHC_DLL_CTRL 0x60
> +#define USDHC_DLL_CTRL 0x60
>
> -#define ESDHC_TUNING_CTRL 0xcc
> -#define ESDHC_TUNE_CTRL_STATUS 0x68
> -#define ESDHC_WTMK_LVL 0x44
> +#define USDHC_TUNING_CTRL 0xcc
> +#define USDHC_TUNE_CTRL_STATUS 0x68
> +#define USDHC_WTMK_LVL 0x44
>
> /* Undocumented register used by guests working around erratum ERR004536 */
> -#define ESDHC_UNDOCUMENTED_REG270x6c
> +#define USDHC_UNDOCUMENTED_REG270x6c
>
> -#define ESDHC_CTRL_4BITBUS (0x1 << 1)
> -#define ESDHC_CTRL_8BITBUS (0x2 << 1)
> +#define USDHC_CTRL_4BITBUS (0x1 << 1)
> +#define USDHC_CTRL_8BITBUS (0x2 << 1)
>
> -#define ESDHC_PRNSTS_SDSTB (1 << 3)
> +#define USDHC_PRNSTS_SDSTB (1 << 3)
>
> static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size)
> {
> @@ -1615,11 +1615,11 @@ static uint64_t usdhc_read(void *opaque, hwaddr
> offset, unsigned size)
> hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3);
>
> if (s->hostctl1 & SDHC_CTRL_8BITBUS) {
> -hostctl1 |= ESDHC_CTRL_8BITBUS;
> +hostctl1 |= USDHC_CTRL_8BITBUS;
> }
>
> if (s->hostctl1 & SDHC_CTRL_4BITBUS) {
> -hostctl1 |= ESDHC_CTRL_4BITBUS;
> +hostctl1 |= USDHC_CTRL_4BITBUS;
> }
>
> ret = hostctl1;
> @@ -1630,21 +1630,21 @@ static uint64_t usdhc_read(void *opaque, hwaddr
> offset, unsigned size)
>
> case SDHC_PRNSTS:
> /* Add SDSTB (SD Clock Stable) bit to PRNSTS */
> -ret = sdhci_read(opaque, offset, size) & ~ESDHC_PRNSTS_SDSTB;
> +ret = sdhci_read(opaque, offset, size) & ~USDHC_PRNSTS_SDSTB;
> if (s->clkcon & SDHC_CLOCK_INT_STABLE) {
> -ret |= ESDHC_PRNSTS_SDSTB;
> +ret |= USDHC_PRNSTS_SDSTB;
> }
> break;
>
> -case ESDHC_VENDOR_SPEC:
> +case USDHC_VENDOR_SPEC:
> ret = s->vendor_spec;
> break;
> -case ESDHC_DLL_CTRL:
> -case ESDHC_TUNE_CTRL_STATUS:
> -case ESDHC_UNDOCUMENTED_REG27:
> -case ESDHC_TUNING_CTRL:
> -case ESDHC_MIX_CTRL:
> -case ESDHC_WTMK_LVL:
> +case USDHC_DLL_CTRL:
> +case USDHC_TUNE_CTRL_STATUS:
> +case USDHC_UNDOCUMENTED_REG27:
> +case USDHC_TUNING_CTRL:
> +case USDHC_MIX_CTRL:
> +case USDHC_WTMK_LVL:
> ret = 0;
> break;
> }
> @@ -1660,18 +1660,18 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t
> val, unsigned size)
> uint32_t value = (uint32_t)val;
>
> switch (offset) {
> -case ESDHC_DLL_CTRL:
> -case ESDHC_TUNE_CTRL_STATUS:
> -case ESDHC_UNDOCUMENTED_REG27:
> -case ESDHC_TUNING_CTRL:
> -case ESDHC_WTMK_LVL:
> +case USDHC_DLL_CTRL:
> +case USDHC_TUNE_CTRL_STATUS:
> +case USDHC_UNDOCUMENTED_REG27:
> +case USDHC_TUNING_CTRL:
> +case USDHC_WTMK_LVL:
> break;
>
> -case ESDHC_VENDOR_SPEC:
> +case USDHC_VENDOR_SPEC:
> s->vendor_spec = value;
> switch (s->vendor) {
> case SDHCI_VENDOR_IMX:
> -if (value & ESDHC_IMX_FRC_SDCLK_ON) {
> +if (value & USDHC_IMX_FRC_SDCLK_ON) {
> s->prnsts &= ~SDHC_IMX_CLOCK_GATE_OFF;
> } else {
> s->prnsts |= SDHC_IMX_CLOCK_GATE_OFF;
> @@ -1740,12 +1740,12 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t
> val, unsigned size)
> * Second, split "Data Transfer Width" from bits 2 and 1 in to
> * bits 5 and 1
> */
> -if (value & ESDHC_CTRL_8BITBUS) {
> +if (value & USDHC_CTRL_8BITBUS) {
> hostctl1 |= SDHC_CTRL_8BITBUS;
> }
>
> -if (value & ESDHC_CTRL_4BITBUS) {
> -hostctl1 |= ESDHC_CTRL_4BITBUS;
> +if (value & USDHC_CTRL_4BITBUS) {
> +hostctl1 |= USDHC_CTRL_4BITBUS;
> }
>
> /*
> @@ -1768,11 +1768,11 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t
> val, unsigned size)
> sdhci_write
Re: [PATCH 08/11] hw/sd/sdhci-internal: Unexport ESDHC defines
On Thu, Sep 15, 2022 at 11:39 PM Bernhard Beschow wrote: > > These defines aren't used outside of sdhci.c, so can be defined there. > > Signed-off-by: Bernhard Beschow > --- > hw/sd/sdhci-internal.h | 20 > hw/sd/sdhci.c | 19 +++ > 2 files changed, 19 insertions(+), 20 deletions(-) > Reviewed-by: Bin Meng
Re: [PATCH 00/27] qapi: Elide redundant has_FOO in generated C
On 9/15/22 23:42, Markus Armbruster wrote: In QAPI, absent optional members are distinct from any present value. We thus represent an optional schema member FOO as two C members: a FOO with the member's type, and a bool has_FOO. Likewise for function arguments. However, the has_FOO is actually redundant for a pointer-valued FOO, which can be null only when has_FOO is false, i.e. has_FOO == !!FOO. Except for arrays, where we a null FOO can also be a present empty array. The redundant has_FOO are a nuisance to work with. Improve the generator to elide them. PATCH 01+02 are trivial documentation cleanups. PATCH 03 tweaks an example in documentation so it'll show the change. PATCH 04 improves the code generator, but nerfs the change for the schema modules where handwritten code needs to be updated. PATCH 05-26 un-nerfs in reviewable chunks. Their commit messages refer back to PATCH 04 for an explanation of the transformation. Please read that first. Note that these patches combine the mechanical transformation with obvious, local follow-up simplifications. If you want them separate for easier review, let me know. [..] 98 files changed, 456 insertions(+), 674 deletions(-) Good stats! -- Best regards, Vladimir
Re: [PATCH 12/27] qapi job: Elide redundant has_FOO in generated C
On 9/15/22 23:43, Markus Armbruster wrote: The has_FOO for pointer-valued FOO are redundant, except for arrays. They are also a nuisance to work with. Recent commit "qapi: Start to elide redundant has_FOO in generated C" provided the means to elide them step by step. This is the step for qapi/job.json. Said commit explains the transformation in more detail. The invariant violations mentioned there do not occur here. Cc: John Snow Cc: Vladimir Sementsov-Ogievskiy Cc:qemu-block@nongnu.org Signed-off-by: Markus Armbruster Reviewed-by: Vladimir Sementsov-Ogievskiy -- Best regards, Vladimir
