Add CLI options for user specified
- PCI vendor, device, subsystem vendor and subsystem IDs
- IEEE-OUI ID
e.g. PCI IDs to be specified as follows:
-device
nvme,id_vendor=0xABCD,id_device=0xA0B0,id_subsys_vendor=0xEF00,id_subsys=0xEF01
IEEE-OUI ID (Identify Controller bytes 75:73) is to be
specified in LE format.
(e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD, Byte[75]=0xAB).
Signed-off-by: Saif Abrar
---
hw/nvme/nvme.h | 5 +
hw/nvme/ctrl.c | 44
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/hw/nvme/nvme.h b/hw/nvme/nvme.h
index bed8191bd5..6e19a479d1 100644
--- a/hw/nvme/nvme.h
+++ b/hw/nvme/nvme.h
@@ -537,6 +537,11 @@ typedef struct NvmeParams {
uint8_t sriov_max_vq_per_vf;
uint8_t sriov_max_vi_per_vf;
bool msix_exclusive_bar;
+uint16_t id_vendor;
+uint16_t id_device;
+uint16_t id_subsys_vendor;
+uint16_t id_subsys;
+uint32_t ieee_oui;
} NvmeParams;
typedef struct NvmeCtrl {
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 127c3d2383..35aeb48e0b 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -8050,8 +8050,9 @@ out:
static void nvme_init_sriov(NvmeCtrl *n, PCIDevice *pci_dev, uint16_t offset)
{
-uint16_t vf_dev_id = n->params.use_intel_id ?
- PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME;
+uint16_t vf_dev_id = n->params.id_device ? n->params.id_device :
+(n->params.use_intel_id ?
+ PCI_DEVICE_ID_INTEL_NVME : PCI_DEVICE_ID_REDHAT_NVME);
NvmePriCtrlCap *cap = >pri_ctrl_cap;
uint64_t bar_size = nvme_mbar_size(le16_to_cpu(cap->vqfrsm),
le16_to_cpu(cap->vifrsm),
@@ -8098,7 +8099,13 @@ static bool nvme_init_pci(NvmeCtrl *n, PCIDevice
*pci_dev, Error **errp)
pci_conf[PCI_INTERRUPT_PIN] = 1;
pci_config_set_prog_interface(pci_conf, 0x2);
-if (n->params.use_intel_id) {
+if (n->params.id_vendor) {
+pci_config_set_vendor_id(pci_conf, n->params.id_vendor);
+pci_config_set_device_id(pci_conf, n->params.id_device);
+pci_set_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID,
+
n->params.id_subsys_vendor);
+pci_set_word(pci_conf + PCI_SUBSYSTEM_ID, n->params.id_subsys);
+} else if (n->params.use_intel_id) {
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_NVME);
} else {
@@ -8206,7 +8213,11 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice
*pci_dev)
id->rab = 6;
-if (n->params.use_intel_id) {
+if (n->params.ieee_oui) {
+id->ieee[0] = extract32(n->params.ieee_oui, 0, 8);
+id->ieee[1] = extract32(n->params.ieee_oui, 8, 8);
+id->ieee[2] = extract32(n->params.ieee_oui, 16, 8);
+} else if (n->params.use_intel_id) {
id->ieee[0] = 0xb3;
id->ieee[1] = 0x02;
id->ieee[2] = 0x00;
@@ -8419,6 +8430,24 @@ static void nvme_exit(PCIDevice *pci_dev)
memory_region_del_subregion(>bar0, >iomem);
}
+static void nvme_prop_ieee_set(Object *obj, Visitor *v, const char *name,
+void *opaque, Error **errp)
+{
+Property *prop = opaque;
+uint32_t *val = object_field_prop_ptr(obj, prop);
+if (!visit_type_uint32(v, name, val, errp)) {
+return;
+}
+}
+
+static const PropertyInfo nvme_prop_ieee = {
+.name = "uint32",
+.description = "IEEE OUI: Identify Controller bytes 75:73\
+ in LE format. (e.g. ieee_oui=0xABCDEF => Byte[73]=0xEF, Byte[74]=0xCD,\
+ Byte[75]=0xAB)",
+.set = nvme_prop_ieee_set,
+};
+
static Property nvme_props[] = {
DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf),
DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND,
@@ -8451,6 +8480,13 @@ static Property nvme_props[] = {
params.sriov_max_vq_per_vf, 0),
DEFINE_PROP_BOOL("msix-exclusive-bar", NvmeCtrl, params.msix_exclusive_bar,
false),
+DEFINE_PROP_UINT16("id_vendor", NvmeCtrl, params.id_vendor, 0),
+DEFINE_PROP_UINT16("id_device", NvmeCtrl, params.id_device, 0),
+DEFINE_PROP_UINT16("id_subsys_vendor", NvmeCtrl,
+params.id_subsys_vendor,
0),
+DEFINE_PROP_UINT16("id_subsys", NvmeCtrl, params.id_subsys, 0),
+DEFINE_PROP("ieee_oui", NvmeCtrl, params.ieee_oui, nvme_prop_ieee,
+
uint32_t),
DEFINE_PROP_END_OF_LIST(),
};
--
2.39.3
